Storage device, electronic device and method for controlling a storage device

Abstract

A storage system (1), which is an example of a storage device according to an embodiment of the present disclosure, comprises a magnetoresistive element (120) having a magnetization direction that is variable between a first state and a second state by applying a voltage, a selector element (110) connected to the magnetoresistive element (120), and a write circuit (70), which is an example of a write unit that changes a write voltage applied to the magnetoresistive element (120) between a first write voltage to change the magnetization direction of the magnetoresistive element (120) to the first state and a second write voltage to change the magnetization direction of the magnetoresistive element (120) to the second state.

Description

Technical area

[0001] The present disclosure relates to a storage device, an electronic device, and a storage device control method. background

[0002] A magnetoresistive random access memory (MRAM) using a magnetoresistive element as a storage element maintains a state by the magnetization state of a ferromagnetic material and, accordingly, exhibits non-volatility, retaining recorded data even if a power supply is turned off. A basic structure of the magnetoresistive element is a sandwich structure in which a non-magnetic thin film made of an insulator is sandwiched between two magnetic layers made of magnetic thin films. This structure is called a magnetic tunnel junction (MTJ). Since a film thickness of the non-magnetic thin film is very thin, such as approximately a few nm, a tunnel current flows when a voltage is applied to both ends of the element.The magnitude of the tunneling current depends on the relative angle of magnetization between the two magnetic layers. This is called the tunnel magnetoresistance (TMR) effect.

[0003] In MRAM, the magnetization of one magnetic layer (fixed magnetization layer) of the two magnetic layers is fixed, and the magnetization of the other magnetic layer (storage layer) is controlled by an external field. A state in which the magnetization of the fixed magnetization layer and the magnetization of the storage layer are parallel to each other is called state 0, and a state in which the magnetization of the fixed magnetization layer and the magnetization of the storage layer are antiparallel to each other is called state 1. In this way, the state ("0" or "1") is stored in a non-volatile manner by rewriting the parallel or antiparallel state of the magnetization.Regarding the external field used to control the magnetization direction, a current magnetic field generated by causing a current to flow to external wiring, a method utilizing the spin transfer torque (STT) effect by causing a current to flow directly to the MTJ, a method utilizing voltage-controlled magnetic anisotropy (VCMA), and the like are used. The TMR effect is used to read the state.

[0004] A currently established MRAM is STT-MRAM, which can be reduced in size and power consumption compared to a case using a current magnetic field. On the other hand, attention has been drawn to voltage-controlled (VC) MRAM using VCMA because writing can be performed at high speed and with low power consumption. A voltage-write scheme using VCMA, disclosed in Patent Literature 1, implements bidirectional writing by applying an ultrafast pulse voltage in a unipolar manner (applying the voltage only in one direction).

[0005] In the conventional voltage write scheme, a bidirectional write operation is performed with a unipolar voltage. When no voltage is applied to an MTJ, the magnetization of a storage layer is oriented in a direction (z-direction) perpendicular to a film surface due to perpendicular magnetic anisotropy (a property that magnetization is likely to be oriented in the direction perpendicular to the film surface). Similarly, the magnetization of a fixed layer is oriented in the z-direction due to perpendicular magnetic anisotropy. Here, both the magnetization of the storage layer and the magnetization of the fixed layer are assumed to be in a +z direction, i.e., in a parallel state, and the 0 state is written.Furthermore, it is assumed that an external magnetic field is applied in a +x direction among in-plane directions (an x direction and a y direction). When a voltage is applied to the MTJ, the perpendicular magnetic anisotropy of the storage layer due to an electric field generated near an interface between a non-magnetic layer and the storage layer disappears, and the property that the magnetization is likely to be oriented in the direction perpendicular to the film surface disappears. As a result, the magnetization of the storage layer begins to move toward the x direction, where magnetic energy due to the external magnetic field is minimized, and begins a so-called precessional motion, gradually moving toward the +x direction while circling in a yz plane, instead of a simple change in a straight line from the +z direction to the +x direction.There is a moment in the process of precessional motion in the yz plane when the magnetization of the storage layer, initially oriented in the +z direction, is essentially oriented in a -z direction. If the voltage applied to the MTJ is set to zero at this time, the perpendicular magnetic anisotropy of the storage layer returns to its original state, and the magnetization is likely oriented in the direction perpendicular to the film surface, so that the magnetization of the storage layer is fixed in the -z direction. That is, state 1, in which the magnetization of the storage layer and the magnetization of the fixed layer become antiparallel from state 0, is written by applying a pulsed voltage.A similar phenomenon occurs when the magnetization of the storage layer is initially oriented in the -z direction, and bidirectional writing can be implemented by applying a unipolar pulse voltage. Citation listPatent literature

[0006] Patent Literature 1: JP 2018-092696 A Brief descriptionTechnical problem

[0007] However, the previously described write scheme is a so-called toggle write scheme, in which a change from state 0 to state 1 and a change from state 1 to state 0 can be made by applying a pulse voltage of the same magnitude to the MTJ. For this reason, if, for example, state 1 is to be written into an already existing state 1, state 0 is erroneously written. To avoid such erroneous writing, it is necessary to read an initial state before writing. For example, if state 1 is to be written, the already written initial state is read. If the initial state is state 0, then writing is performed to set state 1. On the other hand, if the initial state is state 1, no writing is performed. Erroneous writing can be prevented by performing the initial reading in this way.However, a read time generally requires 10 ns or longer, and power is consumed during read time. This hinders the high-speed, low-power characteristics of VC-MRAM.

[0008] Therefore, the present disclosure provides a storage device, an electronic device, and a storage device control method that enable high-speed, low-power writing. Solution to the problem

[0009] A storage device according to the embodiment of the present disclosure includes: a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application; a selection element connected to the magnetoresistive element; and a write unit that switchably applies a first write voltage for setting the magnetization direction of the magnetoresistive element to the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element to the second state to the magnetoresistive element.

[0010] An electronic device according to the embodiment of the present disclosure includes a storage device that stores data, the storage device including: a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application; a selection element connected to the magnetoresistive element; and a write unit that switchably applies a first write voltage for setting the magnetization direction of the magnetoresistive element to the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element to the second state to the magnetoresistive element.

[0011] A storage device control method according to the embodiment of the present disclosure includes: switchably applying, to a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application, a first write voltage for setting the magnetization direction of the magnetoresistive element to the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element to the second state. Short description of the drawings Fig. 1 is a diagram illustrating a first configuration example of a storage system according to an embodiment of the present disclosure. Fig. 2 is a diagram illustrating a second configuration example of the storage system according to the embodiment of the present disclosure. Fig. 3 is a diagram illustrating a first configuration example of a memory cell according to the embodiment of the present disclosure. Fig. 4 is a diagram illustrating a second configuration example of the memory cell according to the embodiment of the present disclosure. Fig. 5 is a diagram illustrating a first configuration example of a magnetoresistive element according to the embodiment of the present disclosure. Fig. 6 is a diagram illustrating a second configuration example of the magnetoresistive element according to the embodiment of the present disclosure. Fig. 7 is a diagram schematically illustrating the memory cell according to the embodiment of the present disclosure. Fig. 8 is a view illustrating a first relationship between a voltage and a current applied to the memory cell according to the embodiment of the present disclosure. Fig. 9 is a view illustrating a second relationship between the voltage and current applied to the memory cell according to the embodiment of the present disclosure. Fig. 10 is a view for describing a bit line voltage in a first example of simulation results according to the embodiment of the present disclosure. Fig. 11 is a view for describing a word line voltage in the first example of the simulation results according to the embodiment of the present disclosure. Fig. 12 is a view for describing the first example of the simulation results according to the embodiment of the present disclosure. Fig. 13 is a view for describing a bit line voltage in a second example of the simulation results according to the embodiment of the present disclosure. Fig. 14 is a view for describing a word line voltage in the second example of the simulation results according to the embodiment of the present disclosure. Fig. 15 is a view for describing the second example of the simulation results according to the embodiment of the present disclosure. Fig. 16 is a view illustrating a first example of a processing procedure of write processing according to the embodiment of the present disclosure. Fig. 17 is a view illustrating a second example of the processing procedure of the write processing according to the embodiment of the present disclosure. Fig. 18 is a view illustrating a third example of the processing procedure of the write processing according to the embodiment of the present disclosure. Fig. 19 is a view illustrating a fourth example of the processing procedure of the write processing according to the embodiment of the present disclosure. Fig. 20 is a view for describing a first example of a continuous writing method according to the embodiment of the present disclosure. Fig. 21 is a view for describing a second example of the continuous writing method according to the embodiment of the present disclosure. Fig. 22 is a view for describing a third example of the simulation results according to the embodiment of the present disclosure. Fig. 23 is a view for describing a fourth example of the simulation results according to the embodiment of the present disclosure. Fig. 24 is a view for describing a first example of a writing method of the magnetoresistive element according to the embodiment of the present disclosure. Fig. 25 is a view for describing a fifth example of the simulation results according to the embodiment of the present disclosure. Fig. 26 is a view for describing a sixth example of the simulation results according to the embodiment of the present disclosure. Fig. 27 is a view for describing a seventh example of the simulation results according to the embodiment of the present disclosure. Fig. 28 is a view for describing an eighth example of the simulation results according to the embodiment of the present disclosure. Fig. 29 is a view illustrating a first example of a write pulse shape according to the embodiment of the present disclosure. Fig. 30 is a view illustrating a second example of the write pulse shape according to the embodiment of the present disclosure. Fig. 31 is a view illustrating a third example of the write pulse shape according to the embodiment of the present disclosure. Fig. 32 is a view illustrating a fourth example of the write pulse shape according to the embodiment of the present disclosure. Fig. 33 is a view illustrating a fifth example of the write pulse shape according to the embodiment of the present disclosure. Fig. 34 is a diagram illustrating a first configuration example of a write pulse generation circuit according to the embodiment of the present disclosure. Fig. 35 is a view for describing an operation example of the write pulse generation circuit in the first configuration example according to the embodiment of the present disclosure. Fig. 36 is a view for describing an operation example of the write pulse generation circuit in the first configuration example according to the embodiment of the present disclosure. Fig. 37 is a diagram illustrating a second configuration example of the write pulse generation circuit according to the embodiment of the present disclosure. Fig. 38 is a view for describing a second example of the writing method of the magnetoresistive element according to the embodiment of the present disclosure. Fig. 39 is a view illustrating a sixth example of the write pulse shape according to the embodiment of the present disclosure. Fig. 40 is a view for describing a ninth example of the simulation results according to the embodiment of the present disclosure. Fig. 41 is a view for describing a tenth example of the simulation results according to the embodiment of the present disclosure. Fig. 42 is a view for describing a first example of restriction of the write pulse shape according to the embodiment of the present disclosure. Fig. 43 is a view illustrating a seventh example of the write pulse shape according to the embodiment of the present disclosure. Fig. 44 is a view for describing a third example of the writing method of the magnetoresistive element according to the embodiment of the present disclosure. Fig. 45 is a view for describing an eleventh example of the simulation results according to the embodiment of the present disclosure. Fig. 46 is a view for describing a twelfth example of the simulation results according to the embodiment of the present disclosure. Fig. 47 is a view for describing a second example of the restriction of the write pulse shape according to the embodiment of the present disclosure. Fig. 48 is a view for describing a third example of the restriction of the write pulse shape according to the embodiment of the present disclosure. Fig. 49 is a view illustrating an eighth example of the write pulse shape according to the embodiment of the present disclosure. Fig. 50 is a view for describing a fourth example of the restriction of the write pulse shape according to the embodiment of the present disclosure. Fig. 51 is a view for describing a fifth example of the write pulse shape restriction according to the embodiment of the present disclosure. Fig. 52 is a view for describing a sixth example of the write pulse shape restriction according to the embodiment of the present disclosure. Fig. 53 is a view illustrating a ninth example of the write pulse shape according to the embodiment of the present disclosure. Fig. 54 is a view for describing a seventh example of the write pulse shape restriction according to the embodiment of the present disclosure. Fig. 55 is a view for describing an eighth example of the write pulse shape restriction according to the embodiment of the present disclosure. Fig. 56 is a view for describing a ninth example of the write pulse shape restriction according to the embodiment of the present disclosure. Fig. 57 is a view for describing a tenth example of the restriction of the write pulse shape according to the embodiment of the present disclosure. Fig. 58 is a view illustrating a fifth example of the processing procedure of the write processing according to the embodiment of the present disclosure. Fig. 59 is a view for describing a first example of a writing method using initial writing according to the embodiment of the present disclosure. Fig. 60 is a view for describing a second example of the writing method using initial writing according to the embodiment of the present disclosure. Fig. 61 is a view for describing a thirteenth example of the simulation results according to the embodiment of the present disclosure. Fig. 62 is a view for describing a fourteenth example of the simulation results according to the embodiment of the present disclosure. Fig. 63 is a diagram illustrating an example of a schematic configuration of an imaging apparatus. Fig. 64 is a diagram illustrating an example of a schematic configuration of a distance measuring device. Fig. 65 is a view illustrating an example of an appearance of a gaming facility. Fig. 66 is a diagram illustrating an example of a schematic configuration of the game device. Description of embodiments

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that devices, means, methods, and the like according to the present disclosure are not limited to the embodiments, and various numerical values, materials, and the like according to the embodiments are examples. Furthermore, the same parts in the following embodiments are denoted by basically the same reference numerals, and a repetitive description thereof will be omitted.

[0013] One or more embodiments (including examples and modifications) described below can be implemented independently. However, at least some of the several embodiments described below can be appropriately implemented in combination with at least some other embodiments. The several embodiments may include novel features that are different from one another. Therefore, the several embodiments may contribute to achieving different goals or solutions to problems, and may each exhibit different effects. It is noted that the effects of the respective embodiments are merely examples and are not limited, and additional effects may be present.

[0014] Furthermore, the drawings referred to in the following description are drawings for promoting the description and understanding of an embodiment of the present disclosure, and shapes, dimensions, ratios, and the like illustrated in the drawings sometimes differ from actual ones for the sake of clarity. Furthermore, an element and the like illustrated in the drawings can be appropriately modified in design in consideration of the following description and known techniques. Furthermore, in the following description, a vertical direction of a laminate structure of the element and the like corresponds to a relative direction in a case where a surface of a substrate on which the element is provided faces upward, and it sometimes differs from the vertical direction according to an actual gravitational acceleration.

[0015] Note that terms such as "perpendicular direction" (a direction perpendicular to a film surface or a lamination direction of the laminate structure) and "in-plane direction" (a direction parallel to the film surface or a direction perpendicular to the lamination direction of the laminate structure) are sometimes used for convenience when describing a magnetization direction (magnetic moment) or magnetic anisotropy. However, these terms do not necessarily mean the exact magnetization directions. For example, a term such as "the magnetization direction is the perpendicular direction" or "having perpendicular magnetic anisotropy" means a state in which magnetization in the perpendicular direction is stronger than magnetization in the in-plane direction.Similarly, for example, an expression such as “the magnetization direction is the in-plane direction” or “with an in-plane magnetic anisotropy” means a state in which magnetization in the in-plane direction is stronger than magnetization in the perpendicular direction.

[0016] Here, the present inventors developed a compact model, described in Verilog-A language, of an MTJ with the VCMA effect that can be incorporated into a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator, and invented a non-switching write scheme as a result of research through SPICE simulation using this MTJ model. In the non-switching write scheme of the present disclosure, for example, in a memory cell in which a cell transistor and the MTJ are connected in series, voltages of different magnitudes are applied to the memory cell between the case of writing state 1 and the case of writing state 0.In this case, the voltage applied to the memory cell is divided by the cell transistor and the MTJ, and the voltage divided and applied to the MTJ changes depending on a state that has already been written to the MTJ. As a result, it is possible to prevent erroneous writing from occurring when State 1 is to be written in a state where State 1 has been written and when State 0 is to be written in a state where State 0 has been written. Therefore, in the non-switching write scheme of the present disclosure, it is unnecessary to read an initial state before writing, whereas in the switching write scheme of the related art, it is necessary to read the initial state before writing. Therefore, it is possible to reduce a read time and power consumption required at the time of initial reading.The non-switching write scheme of the present disclosure will be described in detail later.

[0017] The present disclosure will be described in the following order of points. 1. Embodiment 1-1. Storage system configuration example 1-2. Memory cell configuration example 1-3. Configuration example of the magnetoresistive element 1-4. Writing scheme using a rectangular pulse 1-5. Simulation result 1-6. Write processing 1-7. Writing scheme using a non-rectangular pulse 1-8. Write pulse generation circuit 1-9. Writing scheme using a long rectangular pulse 1-10. Writing scheme using a long gradient pulse 1-11. Writing scheme using a sawtooth pulse 1-12. Writing scheme using initial writing 1-13. Function and effect 2. Other embodiments 3. Configuration example of an electronic device 3-1. Imaging device 3-2. Distance measuring device 3-3. Gaming setup 4. Appendix <1. Embodiment><1-1. Storage System Configuration Example>

[0018] A configuration example of a storage system 1 according to the present embodiment will be described with reference to Fig. 1 described. Fig. Figure 1 is a diagram illustrating the configuration example of the storage system 1 according to the present embodiment. The storage system 1 is an example of a storage device that retains information using a magnetization direction of a magnetic material.

[0019] As in Fig. 1, the storage system 1 according to the present embodiment includes an interface unit 2, a storage control unit 3, and a storage array 4.

[0020] The interface unit 2 exchanges (e.g., performs transmission and reception of) signals with a host system or the like using the storage system 1.

[0021] The storage control unit 3 exchanges data with the host system or the like to control the storage array 4. The storage control unit 3 receives a command from the host system or the like and controls the writing and reading of data based on the received command. For example, the storage control unit 3 issues commands and addresses for writing and reading, and data to be written to the storage array 4. Furthermore, the storage control unit 3 issues the read command and then receives read data from the storage array 4.

[0022] The memory array 4 stores data. The memory array 4 includes a memory cell array 10, a word line address decoder 20, a word line control circuit 30, a bit line address decoder 40, a bit line control circuit 50, a sense amplifier 60, a write circuit 70, a read circuit 80, and a voltage generation circuit 90. The write circuit 70 functions as a write unit.

[0023] The memory cell array 10 is configured by arranging memory cells 100, each storing data, in a two-dimensional matrix. The memory cell 100 includes a selection element 110 and a magnetoresistive element 120. For example, a magnetoresistive element such as an MTJ can be used as the magnetoresistive element 120. The selection element 110 is an element connected to one end of the magnetoresistive element 120 and controls the application of a voltage to the magnetoresistive element 120. For example, an n-channel MOS transistor can be used as the selection element 110.

[0024] A word line 11 (WL) and a bit line 12 (BL), which transmit a control signal, are connected to the memory cell 100. A source line 13 (SL), which transmits a signal from the magnetoresistive element 120, is further arranged in the memory cell 100. In the memory cell array 10, a plurality of the word lines 11 are wired to extend in the row direction, and a plurality of the bit lines 12 and a plurality of the source lines 13 are wired to extend in the column direction.

[0025] The word line address decoder 20 selects the word line 11 of the memory cell array 10 based on the control signal from the memory control unit 3.

[0026] The word line control circuit 30 outputs the control signal to the word line 11 selected by the word line address decoder 20.

[0027] The bit line address decoder 40 selects the bit line 12 of the memory cell array 10 based on the control signal from the memory control unit 3.

[0028] The bit line control circuit 50 outputs the control signal to the bit line 12, which is selected by the bit line address decoder 40.

[0029] The sense amplifier 60 reads data by detecting a current flowing through the memory cell 100 at the time of reading. The read data is output to the memory control unit 3.

[0030] The write circuit 70 is a circuit that performs writing with respect to the memory cell 100 at an intersection of the selected word line 11 and the selected bit line 12. The write circuit 70 performs writing to the magnetoresistive element 120 via the selection element 110 of the memory cell 100.

[0031] The read circuit 80 is a circuit that performs reading with respect to the memory cell 100 at an intersection of the selected word line 11 and the selected bit line 12. The read circuit 80 performs reading on the magnetoresistive element 120 via the selection element 110 of the memory cell 100.

[0032] The voltage generation circuit 90 is a circuit that generates a voltage to be applied at the time of writing and reading the memory cell 100.

[0033] Here, reading can be performed by applying a predetermined read voltage to the magnetoresistive element 120 of the memory cell 100 and detecting a current flowing through the memory cell 100, although details of writing with respect to the memory cell 100 will be described later. Note that the read voltage is preferably a voltage with a polarity different from that of a write voltage.

[0034] Next, another configuration example of the storage system 1 according to the present embodiment will be described with reference to Fig. 2 described. Fig. Figure 2 is a diagram illustrating another configuration example of the storage system 1 according to the embodiment of the present disclosure. The storage system 1 is also an example of the storage device that retains information using the magnetization direction of the magnetic material.

[0035] As in Fig. 2, two bit line control circuits 50 are arranged above and below the memory cell array 10, which differs from Fig. 1. As a result, for example, the bit line control circuit 50 arranged on the upper side can control the even-numbered bit lines 12, and the bit line control circuit 50 arranged on the lower side can control the odd-numbered bit lines 12. The other functions are similar to those of the bit line control circuit 50 arranged on the lower side. Fig. 1 illustrated storage system 1. <1-2. Memory cell configuration example>

[0036] Configuration examples of the memory cell 100 according to the present embodiment will be described with reference to Fig. 3 and Fig. 4 described. Fig. 3 and Fig. 4 are diagrams each illustrating the configuration example of the memory cell 100 according to the present embodiment. Each drawing is a schematic diagram illustrating the configuration example of the memory cell 100. It is noted that the memory cell 100 includes the selection element 110 and the magnetoresistive element 120 as described above. In the examples of Fig. 3 and Fig. 4, the selection element 110 and the magnetoresistive element 120 are connected in series, and the selection element 110 has a drain (drain terminal), a source (source terminal), and a gate (gate terminal).

[0037] As in Fig. As illustrated in Figure 3, the magnetoresistive element 120 of the memory cell 100 is connected to a wiring 101 via a contact layer 103 and is connected to the selection element 110 via a contact layer 104. The selection element 110 has its drain connected to the contact layer 104 and its source connected to the source line 13 (SL). Furthermore, the gate of the selection element 110 is connected to the word line 11 (WL). Note that the contact layer 103 is connected to the wiring 101, which represents the bit line 12 (BL). When an overvoltage is applied to the word line 11 (WL), the selection element 110 is activated, and a voltage can be applied to the magnetoresistive element 120.

[0038] As in Fig. As illustrated in Figure 4, the magnetoresistive element 120 of the memory cell 100 is connected to a wiring 102 via the contact layer 104 and is connected to the selection element 110 via the contact layer 103. The selection element 110 has its drain connected to the bit line 12 (BL) and its source connected to the contact layer 103. Furthermore, the gate of the selection element 110 is connected to the word line 11 (WL). Note that the contact layer 104 is connected to the wiring 102, which represents the source line 13 (SL). When an overvoltage is applied to the word line 11 (WL), the selection element 110 is activated, and a voltage can be applied to the magnetoresistive element 120.

[0039] As previously described, the word line 11 (WL) is connected to the word line control circuit 30 (see Fig. 1 and Fig. 2). The bit line 12 (BL) is connected to the bit line control circuit 50 (see Fig. 1 and Fig. 2). The source line 13 (SL) is connected to the sense amplifier 60 (see Fig. 1 and Fig. 2). A voltage for writing or reading can be applied to the magnetoresistive element 120 by applying a voltage between the bit line 12 (BL) and the source line 13 (SL) and applying the on-voltage to activate the select element 110 to the word line 11 (WL). <1-3. Configuration example of the magnetoresistive element>

[0040] Configuration examples of the magnetoresistive element 120 according to the present embodiment will be described with reference to Fig. 5 and Fig. 6 described. Fig. 5 and Fig. 6 are views each illustrating the configuration example of the magnetoresistive element 120 according to the present embodiment. Each drawing is a cross-sectional view illustrating the configuration example of the magnetoresistive element 120.

[0041] As in Fig. 5 and Fig. 6, the magnetoresistive element 120 includes a base layer 121, a fixed magnetization layer 122, a tunnel barrier layer 123, a storage layer 124, and a cap layer 125. The magnetoresistive element 120, which is shown in Fig. 5 is configured by sequentially laminating the base layer 121, the fixed magnetization layer 122, the tunnel barrier layer 123, the storage layer 124, and the cap layer 125. On the other hand, the magnetoresistive element 120 shown in Fig. 6, by sequentially laminating the base layer 121, the storage layer 124, the tunnel barrier layer 123, the fixed magnetization layer 122 and the cap layer 125.

[0042] As the base layer 121, for example, a layer formed of a noble metal such as Cr, Ta, Ru, Au, Ag, Cu, Al, Ti, V, Mo, Zr, Hf, Re, W, Pt, Pd, Ir, or Rh, or a transition metal element, or a laminate structure thereof, can be used. Furthermore, the base layer 121 can also be made of a conductive nitride such as TiN. For example, the base layer 121 is configured using a film for controlling a crystal orientation of the fixed magnetization layer 122 and improving adhesion strength to a lower electrode.

[0043] The fixed magnetization layer 122 is a layer with magnetic anisotropy and a fixed magnetization direction. The fixed magnetization layer 122 may be made of, for example, CoFeB, a CoFeC alloy, a NiFeB alloy, a NiFeC alloy, or the like. Further, the fixed magnetization layer 122 may have a laminated ferri-pin structure in which multiple ferromagnetic layers are laminated with a non-magnetic layer in between. Co, CoFe, CoFeB, or the like may be used as a material of the ferromagnetic layer constituting the fixed magnetization layer with the laminated ferri-pin structure. Further, Ru, Re, Ir, Os, or the like may be used as a material of the non-magnetic layer.

[0044] Furthermore, the fixed magnetization layer 122 can be configured such that the orientation of the magnetization is fixed by utilizing an antiferromagnetic coupling between an antiferromagnetic layer and a ferromagnetic layer. Examples of a material of the antiferromagnetic layer can include magnetic materials such as an FeMn alloy, a PtMn alloy, a PtCrMn alloy, a NiMn alloy, an IrMn alloy, NiO, and Fe2O3. Furthermore, a non-magnetic element such as Ag, Cu, Au, Al, Si, Bi, Ta, B, C, O, N, Pd, Pt, Zr, Hf, Ir, W, Mo, or Nb can be added to these magnetic materials.

[0045] The tunnel barrier layer 123 is disposed adjacent to the storage layer 124 to be described later and applies an electric field to the storage layer 124 to impart the stress-controlled magnetic anisotropy effect. The tunnel barrier layer 123 may be made of an oxide of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba, or a nitride of at least one element selected from the group consisting of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, and Ba. Furthermore, it may also be configured using an insulator such as MgF2, CaF, SrTiO2, AlLaO3, or AlNO, a dielectric, and a semiconductor. It is also possible to have a structure in which these layers are laminated. Note that the thickness of the tunnel barrier layer 123 is preferably 0.6 nm or more.

[0046] The storage layer 124 is a layer with magnetic anisotropy and a variable magnetization direction. Furthermore, the storage layer 124 is a layer with the VCMA effect. A state in which the magnetization direction of the storage layer 124 and the magnetization direction of the fixed magnetization layer 122 are identical, and a state in which the magnetization direction of the storage layer 124 and the magnetization direction of the fixed magnetization layer 122 are different, are referred to as a parallel state and an antiparallel state, respectively. The magnetoresistive element 120 is in a low-resistance state in the parallel state and is in a high-resistance state in the antiparallel state. The magnetization direction of the storage layer 124 can be changed by applying a voltage to the magnetoresistive element 120, as described above.

[0047] Furthermore, the storage layer 124 may be made of cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), Fe, iron boride (FeB), or the like. Furthermore, it is also possible to use a configuration including a transition metal (Hf, Ta, W, Re, Ir, Pt, Au, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Ti, V, Cr, Mn, Ni, or Cu) or the like. A nitride or an oxide may also be included. Furthermore, iridium (Ir) or osmium (Os) may be used as a material that induces a proximity magnetic moment in the magnetic material. Note that a heavy metal may also be added to the storage layer 124 to enhance the stress-controlled magnetic anisotropy effect. A thickness of the storage layer 124 is preferably 3.0 nm or less.

[0048] Furthermore, the storage layer 124 may have a laminate structure in which a plurality of ferromagnetic layers are laminated with a non-magnetic layer in between. At this time, two ferromagnetic layers adjacent to each other with the non-magnetic layer in between may be exchange-coupled. The non-magnetic layer may be made of Mg, Al, Ti, Si, Zn, Zr, Hf, Ta, Bi, Cr, Ga, La, Gd, Sr, Ba, W, Re, Ir, Pt, Au, Nb, Mo, Ru, Rh, Pd, Ag, V, Mn, Ni, Cu, or the like.

[0049] The cap layer 125 is a layer that prevents diffusion of a metal from a wiring element. The cap layer 125 may be made of a metal such as Cr, Ta, Ru, Au, Ag, Cu, Al, Ti, V, Mo, Zr, Hf, Re, W, Pt, Pd, Ir, or Rh. Further, the cap layer 125 may be configured using a layer formed of an alloy containing it or a transition metal. Further, the cap layer 125 may also be configured by laminating them. Further, the cap layer 125 may also be made of a conductive nitride such as TiN.

[0050] The various layers described above can be produced by, for example, a physical vapor deposition (PVD) process, exemplified by a sputtering process, an ion beam deposition process, and a vacuum vapor deposition process, and a chemical vapor deposition (CVD) process, exemplified by an atomic layer deposition (ALD) process. Furthermore, patterning of these layers can be performed by a reactive ion etching (RIE) process or an ion thinning process. It is preferable to form the various layers consecutively in a vacuum device, and it is preferable to perform patterning thereafter. <1-4. Writing scheme using a rectangular pulse>

[0051] A writing scheme using a rectangular pulse according to the present embodiment will be described with reference to Fig. 7 to 9 described.

[0052] Fig. 7 is a diagram schematically illustrating the memory cell 100. In an example from Fig. 7, the magnetoresistive element 120 is an MTJ (MTJ element), and the selection element 110 is an n-channel MOS transistor. As described above, it is possible to cause a current to flow through the memory cell 100 by applying voltages to the bit line 12 (BL), the source line 13 (SL), and the word line 11 (WL) connected by the memory cell 100.

[0053] Here, a bit line voltage of bit line 12 (BL) is given by V BL is a source line voltage of the source line 13 (SL) by V SL and is a word line voltage of the word line 11 (WL) by V WL Furthermore, an MTJ voltage applied to the MTJ is denoted by V MTJIt is necessary to set the magnetic anisotropy of the storage layer 124 to zero by applying a voltage (write voltage) to the MTJ to perform writing using the VCMA effect. The MTJ voltage V MTJ , when the magnetic anisotropy of the storage layer 124 becomes zero, V c0 Since the MTJ voltage V MTJ from the bit line voltage V BL , the source line voltage V SL and the word line voltage V WL depends, it is necessary to adjust these voltages so that the MTJ voltage V MTJ to V c0 becomes.

[0054] Fig. Figure 8 is a view showing a relationship between the MTJ voltage V MTJand a current flowing through the memory cell 100. Here, a curve C1 represents an MTJ current in state 0, and a curve C2 represents an MTJ current in state 1. Since a resistance value in state 0 is smaller than a resistance value in state 1, the MTJ current in state 0 is greater than the MTJ current in state 1 at the same MTJ voltage. Furthermore, a curve C3 represents a transistor current when writing state 1, and a curve C4 represents a transistor current when writing state 0. Here, the source line voltage is V SL set to ground, the word line voltage V WL different values ​​between writing state 0 and writing state 1 and has the bit line voltage V BL the same value between writing state 0 and writing state 1.

[0055] As from Fig. As can be seen in Figure 7, the voltage V MTJ, which is applied to the MTJ by applying a voltage to the memory cell 100, at intersection points of the curves C1 to C4, since the MTJ current and the transistor current have the same value. In particular, if state 1 is to be written to state 0, a voltage indicated by an intersection point A of the curve C1 and the curve C3 is applied to the MTJ. If state 1 is to be written to state 1, a voltage indicated by an intersection point B of the curve C2 and the curve C3 is applied to the MTJ. If state 0 is to be written to state 1, a voltage indicated by an intersection point C of the curve C2 and the curve C4 is applied to the MTJ. If state 0 is to be written to state 0, a voltage indicated by an intersection point D of the curve C1 and the curve C4 is applied to the MTJ. It is noted that the voltages at the intersection points A and C are related to the voltage V c0at which the magnetic anisotropy of the storage layer 124 becomes zero. In contrast, the word line voltage V WL adjusted so that the voltages at the intersection points A and C are equal to the voltage V c0 Then, the adjusted voltage has different values ​​between writing state 0 and writing state 1, as can be understood from the fact that curve C3 and curve C4 are different. It is understood that the MTJ voltage V MTJ equal to V c0 by applying the voltage adjusted in this way to the memory cell 100 if state 1 is to be written to state 0 and if state 0 is to be written to state 1, so that the magnetic anisotropy of the storage layer 124 becomes zero and the writing of the opposite state is performed.

[0056] On the other hand, if state 1 is to be written to state 1, the voltage at intersection point B will be greater than V c0 , and the magnetic anisotropy of the storage layer 124 becomes negative. At this time, the magnetization of the storage layer 124 cannot perform a desired precessional movement and remains in state 1 after a pulse voltage is applied. That is, unlike toggle writing, there is no erroneous change to state 0. Furthermore, if state 0 is to be written to state 0, the voltage at the intersection point D becomes smaller than V c0, and the magnetic anisotropy of the storage layer 124 remains positive. At this time, the magnetization of the storage layer 124 does not undergo precessional motion and remains in state 0 after the pulse voltage is applied. That is, unlike toggle writing, there is no erroneous change to state 1. As described above, it should be understood that state 0 and state 1 can be written in a non-toggle manner regardless of the initial state.

[0057] Since the anisotropy at each of the intersection points A and C is zero, precessional writing is possible here. When a magnetization state changes due to precessional motion, an operating point changes from A to B or from C to D. At intersection point B, an in-plane magnetization film is formed, and accordingly, writing is not possible due to precessional motion around a perpendicular axis. At intersection point D, a perpendicular magnetization film is formed, and accordingly, precessional motion does not occur, and writing is not possible. Note that writing is not limited to precessional motion and can, for example, be a Langer pulse scheme.

[0058] Fig. 9 is a view showing a relationship between the MTJ voltage V MTJ and the current flowing through the memory cell 100. Here, curve C1 and curve C2 are the same MTJ currents as those in Fig. 8. Furthermore, a curve C5 represents a transistor current in the case of writing state 1 and a curve C6 represents a transistor current in the case of writing state 0. Here, the source line voltage V SL set to ground, the word line voltage V WL the same value between the case of writing state 0 and the case of writing state 1 and has the bit line voltage V BL different values ​​between the case of writing state 0 and the case of writing state 1.

[0059] As from Fig. As can be seen in Figure 7, the voltage V MTJ, which is applied to the MTJ by applying a voltage to the memory cell 100, at intersections of the curve C1, the curve C2, the curve C5, and the curve C6, since the MTJ current and the transistor current have the same value. Specifically, if state 1 is to be written to state 0, a voltage indicated by an intersection point A of the curve C1 and the curve C5 is applied to the MTJ. If state 1 is to be written to state 1, a voltage indicated by an intersection point B of the curve C2 and the curve C5 is applied to the MTJ. If state 0 is to be written to state 1, a voltage indicated by an intersection point C of the curve C2 and the curve C6 is applied to the MTJ. If state 0 is to be written to state 0, a voltage indicated by an intersection point D of the curve C1 and the curve C6 is applied to the MTJ.The stresses from intersection A to intersection D are in the same relationship as those in . Fig. 8 and the bit line voltage V BL is adjusted so that the voltages at the intersection point A and the intersection point C are equal to the voltage V c0 Then, the adjusted voltage has different values ​​between writing state 0 and writing state 1, as can be understood from the fact that curve C5 and curve C6 are different. According to the same discussion as that in Fig. 8, state 0 and state 1 can be written in a non-switching manner, independent of the initial state, as described previously. <1-5. Simulation results>

[0060] Simulation results according to the present embodiment will be described with reference to Fig. 10 to 15 described.

[0061] In Fig. 10 to 12 is the source line voltage V SL placed on mass, as in Fig. 8, Fig. Fig. 10 is a view illustrating that the bit line voltage V BL has the same value between the case of writing state 0 and the case of writing state 1, Fig. Fig. 11 is a view illustrating that the word line voltage V WL has different values ​​between the case of writing state 0 and the case of writing state 1, and Fig. 12 is a view showing simulation results of magnetization motion under conditions of Fig. 10 and Fig. 11 illustrates.

[0062] The respective drawings, which are arranged in a grid of 2 × 2 in Fig. 10 to 12 correspond to the intersection point A to the intersection point D, which are arranged in Fig. 8. That is, the upper row corresponds to the case of writing state 1, the lower row corresponds to the case of writing state 0, the left column corresponds to a case where the initial state is 0, and the right column corresponds to a case where the initial state is state 1. Furthermore, in each drawing, the horizontal axis represents time, the vertical axis represents Fig. 10 the bit line voltage V BL , in Fig. 11 the word line voltage V WL and in Fig. 12 each axial component of the magnetization of the storage layer 124. In Fig. 10, a constant voltage of V1 is used as the bit line voltage V BL created jointly between writing state 1 in the upper row and writing state 0 in the lower row. In Fig. 11, different voltages with a pulse of 1 ns, i.e. V2 when writing state 1 in the upper row and V3 when writing state 0 in the lower row, are used as the word line voltage V WL created.

[0063] The magnetization movement when applying such voltages is in Fig. 12. In a case indicated by A, where state 1 is to be written when the initial state is state 0, a z-component of the magnetization is +1 before the application of a pulse voltage, but is -1 after the application of the pulse, and it is understood that a state change occurs. Similarly, in a case indicated by C, where state 0 is to be written when the initial state is state 1, the z-component of the magnetization is -1 before the application of the pulse voltage, but is +1 after the application of the pulse, and it is understood that a state change occurs.On the other hand, in cases indicated by B and D where the initial state and a state to be written are the same, magnetization motion is observed during pulse application, but it is understood that the sign of the z-component of the magnetization does not change before and after the pulse voltage is applied, and writing is not performed. Thus, it is understood that non-switching writing can be performed regardless of the initial state by applying different voltages between writing state 0 and writing state 1.

[0064] In Fig. 13 to 15 is the source line voltage V SL placed on mass, as in Fig. 9, Fig. Fig. 13 is a view illustrating that the bit line voltage V BL has different values ​​between the case of writing state 0 and the case of writing state 1, Fig. Fig. 14 is a view illustrating that the word line voltage V WL has the same value between the case of writing state 0 and the case of writing state 1, and Fig. 15 is a view showing simulation results of magnetization motion under conditions of Fig. 13 and Fig. 14 illustrates.

[0065] The respective drawings, which are arranged in a grid of 2 × 2 in Fig. 13 to 15 correspond to the intersection point A to the intersection point D, which are arranged in Fig. 9. That is, the upper row corresponds to the case of writing state 1, the lower row corresponds to the case of writing state 0, the left column corresponds to a case where the initial state is 0, and the right column corresponds to a case where the initial state is state 1. Furthermore, in each drawing, the horizontal axis represents time, the vertical axis represents Fig. 13 the bit line voltage V BL , in Fig. 14 the word line voltage V WL and in Fig. 15 each axial component of the magnetization of the storage layer 124. In Fig. 13, different constant voltages, i.e. V4 when writing state 1 in the upper row and V5 when writing state 0 in the lower row, are used as the bit line voltage V BL created. In Fig. 14, a common voltage V6 with a pulse of 1 ns is used as the word line voltage VWL when writing state 1 in the upper row and when writing state 0 in the lower row. The magnetization movement when applying such voltages is Fig. 15. The non-switching writing is performed by applying different voltages between the writing of state 0 and the writing of state 1 regardless of the initial state, which is the Fig. 12, although details are different.

[0066] It is noted that in Fig. 10 to 15 the bit line voltage V BL is a constant voltage and the word line voltage V WL is a pulse voltage, but in contrast, the bit line voltage V BL be a pulse voltage and can be the word line voltage V WL be a constant voltage. Furthermore, both the bit line voltage V BLas well as the word line voltage V WL Pulse voltages. At this time, a rise or fall of a pulse voltage between the bit line voltage V BL and the word line voltage V WL may not match or do not necessarily match. Furthermore, although a pulse width of 1 ns is used, this is only an example, and any pulse width can be used as long as the writing can be performed correctly. <1-6. Write processing>

[0067] A write processing according to the present embodiment will be described with reference to Fig. 16 to 21 described.

[0068] Fig. 16 is a view illustrating a first example of a processing procedure of the write processing according to the present embodiment. The drawing is a flowchart illustrating an example of write processing (step S100) in the storage system 1. As shown in Fig. As illustrated in Figure 16, the write circuit 70 performs writing (step S101). Through the above processing, writing can be performed.

[0069] Fig. Fig. 17 is a diagram illustrating a second example of the processing procedure of the write processing according to the present embodiment. The drawing is a flowchart illustrating an example of write processing (step S110) in the storage system 1. As shown in Fig. As illustrated in Fig. 17, first, a counter C held in the memory control unit 3 is set to zero (step S111). Next, one is added to the counter C held in the memory control unit 3 (step S112). Next, the write circuit 70 performs writing (step S101). Thereafter, the memory control unit 3 determines whether a value of the counter C matches a number N of continuous writes determined in advance (step S113). As a result, if the number N of continuous writes matches (Yes in step S113), the processing is terminated. On the other hand, if the number N of continuous writes does not match (No in step S113) in step S113, the processing of step S112 is performed again. Through the above processing, continuous writing can be performed.

[0070] Fig. Fig. 18 is a diagram illustrating a third example of the processing procedure of the write processing according to the present embodiment. The drawing is a flowchart illustrating an example of write processing (step S120) in the storage system 1. As shown in Fig. 18, first the Fig. 17 is performed (step S110). Next, the read circuit 80 performs verification of reading from the target memory cell 100 (step S102). Next, it is determined whether data read by the memory control unit 3 matches write data (step S103). As a result, if the write data matches (Yes in step S103), the processing is terminated. On the other hand, if the write data does not match (No in step S103), the processing of step S110 is performed again in step S103. Through the above processing, continuous writing with a verification function can be performed.

[0071] Fig. Fig. 19 is a diagram illustrating a fourth example of the processing procedure of the write processing according to the present embodiment. The drawing is a flowchart illustrating an example of write processing (step S130) in the storage system 1. As shown in Fig. 19, the read circuit 80 first performs initial reading from the target memory cell 100 (step S131). Next, it is determined whether data read by the memory control unit 3 matches write data (step S103). Consequently, if the write data matches (Yes in step S103), the processing is terminated. On the other hand, if the write data does not match (No in step S103), the Fig. 17 is performed (step S110). Next, the read circuit 80 performs read verification (step S102). Thereafter, the processing of step S103 is performed again. Through the above processing, it is possible to perform continuous writing with a verification function that includes initial reading.

[0072] Fig. 20 and Fig. 21 are views for describing a continuous writing method according to the present embodiment. Each drawing illustrates a variation of a method for applying a pulse voltage in the manner shown in Fig. 17 illustrated continuous writing processing. In Fig. 20, the pulse width of the pulse voltage is different for each write (t1 < t2 < t3). On the other hand, in Fig. 21, a voltage value (amplitude) of the pulse voltage varies with each write (V1 < V2 < V3). Since the optimal write pulse width and voltage may vary among the magnetoresistive elements 120 in the memory cell array 10, it is possible to reduce a write error rate by performing multiple writes with different pulse widths and voltages.

[0073] It is noted that three impulses in the examples from Fig. 20 and Fig. 21 can be applied, but the number of pulse applications is arbitrary. Furthermore, not only one of the pulse width and the voltage value (amplitude) of the pulse voltage, but also both of them can be different for each write. Furthermore, the pulse voltage is desirably a pulse voltage with a pulse width of 0.1 ns or more and 20 ns or less. Precessional motion occurs reliably if the pulse width is 0.1 ns or more; the precessional motion converges (stabilizes) if the pulse width is 20 ns or less; however, the precessional motion ends when the magnetization is completely oriented in one direction of an external magnetic field if the pulse width exceeds 20 ns. <1-7. Writing scheme using a non-rectangular pulse>

[0074] A writing scheme using a non-rectangular pulse according to the present embodiment will be described with reference to Fig. 22 to 33 described.

[0075] In the above description, one form of a write pulse is a rectangular pulse, as in Fig. 11. The term "square-wave" means that a voltage of the write pulse is essentially constant. Simulation results of a magnetization movement when the rectangular pulse is used are shown in Fig. 22 and Fig. 23. For comparison, Fig. 22 the case of MTJ alone and illustrates Fig. 23 illustrates the case of the memory cell 100 of the present embodiment. The upper row illustrates a voltage, the middle row illustrates an energy K of a perpendicular magnetic anisotropy, and the lower row illustrates a magnetization. In the MTJ of Fig. 22 the voltage V c0 directly to the MTJ. In the memory cell 100 of Fig. 23, the word line voltage V WLadjusted so that the voltage V c0 is applied to the MTJ. In both cases, the previously described voltages are applied continuously from a time of 0 ns to a relaxation time of 1 ns.

[0076] In Fig. 22, K = 0 is maintained since the MTJ voltage V MTJ is fixed. As a result, the magnetization movement, illustrated in the lower row, is an ideal precessional movement in a spiral form with a constant cycle. On the other hand, in the memory cell 100 of Fig. 23 the word line voltage V WL fixed, but the MTJ voltage V MTJ a value obtained by dividing the bit line voltage by the MTJ and the selection element 110, and is accordingly not constant.

[0077] In particular, the MTJ voltage V MTJ entangled with the magnetization movement, as shown by a dashed line in the upper row Fig. 23. Since the magnetization is in state 0 at time 0 ns, as assumed, V c0 applied to the MTJ. However, the magnetization deviates from state 0 as soon as the magnetization movement begins. A resistance value R of the MTJ depends on a perpendicular component of the magnetization of the storage layer 124. An intersection point of an MTJ current, which is determined by the resistance value, and a transistor current becomes a new operating point. This state is indicated by an arrow A1 in Fig. 24. The MTJ current moves between state 0 and state 1 according to the magnetization motion, and the operating point moves between A and B.

[0078] The time dependence of K is shown in the middle row from Fig. 23. Although K = 0 at the start of the voltage application, the MTJ voltage becomes higher than V due to an increase in resistance c0Since the perpendicular magnetic anisotropy is neither zero nor constant, but assumes a negative value, the storage layer 124 forms an in-plane magnetization layer. Since not only an external magnetic field but also an effective magnetic field that attracts the magnetization within the plane is acting, the Fig. 23, the magnetization motion illustrated is not the ideal precessional motion in the spiral form, but is distorted. In the magnetization motion in the lower row from Fig. 22, a z-component of the magnetization has a minimum value of about 1.9 ns. The absolute value of this is 0.93. In the magnetization movement in the lower row from Fig. 23, the z-component of the magnetization has a minimum value of approximately 1.4 ns. Its absolute value is 0.54. When the absolute value of the minimum is closer to one, writing can be performed more stably if the voltage application is stopped at that time. For this reason, the writing stability tends to decrease when writing using memory cell 100 compared to writing using the MTJ alone.

[0079] In order to eliminate such instability of writing, it is possible to use a voltage pulse having a non-rectangular shape in writing according to the present embodiment. Fig. Figure 24 illustrates a concept of this. With the rectangular pulse, there is a problem that the MTJ voltage increases and the perpendicular magnetic anisotropy is not zero when the operating point moves from A to B. Therefore, the operating point is then moved from A to C. Accordingly, the MTJ voltage remains at V even during the magnetization movement. c0 and the vertical magnetic anisotropy is also kept at zero.

[0080] Fig. 25 and Fig. 26 illustrate simulation results of writing state 1. The initial state is state 0 in Fig. 25 and the initial state is state 1 in Fig. 26. The MTJ voltage in the upper row from Fig. 25 is essentially constant, and K in the middle row is essentially zero. As a result, the ideal precessional motion is achieved. In the lower row, the absolute value of the z-component of the magnetization at 1.9 ns, when the voltage pulse ends, is 0.79. Since the value is 0.54 when the rectangular pulse is used, it is understood that the writing stability is improved. Furthermore, in Fig. 26, no magnetization reversal occurs. This means that non-switching slicing can be implemented as in the case of the rectangular pulse.

[0081] Similarly, simulation results of writing state 0 to Fig. 27 and Fig. 28. The initial state is state 0 in Fig. 27 and the initial state is state 1 in Fig. 28. The MTJ voltage in the upper row from Fig. 28 is essentially constant, and K in the middle row is essentially zero. As a result, the ideal precessional motion is achieved. In the lower row, the absolute value of the z-component of the magnetization at 1.7 ns, when the voltage pulse ends, is 0.99, and it is understood that the writing stability is improved. Furthermore, in Fig. 27, no magnetization reversal occurs. This means that non-switching slicing can be implemented as in the case of the rectangular pulse.

[0082] Fig. Figures 29 to 33 are views each illustrating an example of a non-rectangular pulse shape. It is noted that Fig. 29 to 33 illustrate the case of writing state 1. In the case of writing state 0, a voltage increases with time. In Fig. 29, a voltage waveform depends linearly on time. In Fig. 30 a tension form protrudes downwards. In Fig. 31, a tension form stands out upwards. In each of Fig. 32 and Fig. 33, a voltage waveform is formed into a non-square pulse including several rectangular pulses. The above Fig. 29 to 33 illustrate the examples of the shape of the non-rectangular pulse and the shape is not limited to this.

[0083] Here, in each of Fig. 29 to 33, a pulse waveform has a shape in which the amplitude changes from zero to a desired amplitude value, gradually decreases from the desired amplitude value to the other amplitude value, and changes from the other amplitude value to zero. This pulse waveform has the shape that decreases linearly, curvilinearly, or stepwise from the desired amplitude value to the other amplitude value. This shape corresponds to the case of writing from state 1, and in the case of writing from state 0, a pulse waveform has a shape that increases linearly, curvilinearly, or stepwise from one desired amplitude value to another amplitude value. <1-8. Write pulse generation circuit>

[0084] Write pulse generating circuits 200 and 210 according to the present embodiment will be described with reference to Fig. 34 to 37. Each of the write pulse generation circuits 200 and 210 generates a write pulse (pulse voltage). The write pulse generation circuit 200 and / or 210 is included, for example, in the write circuit 70.

[0085] Fig. 34 is a diagram illustrating a configuration example of the write pulse generating circuit 200. As shown in Fig. 34, the write pulse generation circuit 200 includes a CR circuit 202, a transfer gate 203, and a negative feedback amplifier circuit using an operational amplifier 204. The transfer gate 203 controls conduction and interruption between an output 206 of the CR circuit 202 and a non-inverting input 207 of the operational amplifier 204.

[0086] Fig. 35 and Fig. 36 are views each showing an example of operation of the Fig. 34 illustrate the write pulse generation circuit 200. In Fig. 35, a rising square wave voltage is input to an input terminal 201 of the write pulse generating circuit 200. A square wave signal input to the input terminal 201 has a waveform with a smooth rise time through the CR circuit 202. The transfer gate 203 allows conduction between the output 206 of the CR circuit 202 and the non-inverting input 207 of the operational amplifier 204 only from a time 2031 to a time 2032. The negative feedback amplifier circuit outputs a signal corresponding to a difference between a signal input to a non-inverting input terminal and a negative feedback signal input to an inverting input terminal as the write pulse from an output terminal 205.

[0087] In Fig. 36, a falling square wave voltage is input to the input end 201 of the write pulse generating circuit 200. A square wave signal input to the input end 201 has a waveform with a smooth fall time through the CR circuit 202. The transfer gate 203 allows conduction between the output 206 of the CR circuit 202 and the non-inverting input 207 of the operational amplifier 204 only from a time 2031 to a time 2032. The negative feedback amplifier circuit outputs a signal corresponding to a difference between a signal input to the non-inverting input terminal and a negative feedback signal input to the inverting input terminal as the write pulse from the output terminal 205.

[0088] Fig. 37 is a diagram illustrating another configuration example of the write pulse generating circuit 210. As shown in Fig. As illustrated in Figure 37, the write pulse generation circuit 210 includes a waveform memory 211 and a D / A conversion circuit 212. This write generation circuit 210 generates the write pulse using the waveform memory 211 and the D / A conversion circuit 212.

[0089] The waveform memory 211 stores waveform data of the write pulse. The waveform data of the write pulse includes multiple N-bit words of time series data, whose output level can be selected in 2N steps as one word. N ports for reading are provided in the waveform memory 211, and these N ports are each connected to N input ends of the D / A conversion circuit 212.

[0090] The D / A conversion circuit 212 inputs the waveform data of the write pulse from the waveform memory 211 for each N-bit data (one word), converts the data into an analog signal, and outputs the analog signal as the write pulse. The D / A conversion circuit 212 can be configured using, for example, an R2R network circuit or the like.

[0091] Since such write pulse generation circuits 200 and 210 are used, a write pulse waveform with a high degree of freedom can be obtained, and the write pulse of each of the above embodiments can be easily obtained with a high degree of freedom. It is noted that in the example of Fig. 37 the number N of bits of a word is set to “3”, so that the output level can be determined among 23 levels, but this number is not specifically limited. <1-9. Writing scheme using a long rectangular pulse>

[0092] A writing scheme using a long rectangular pulse according to the present embodiment will be described with reference to Fig. 38 to 42 described.

[0093] As described above, non-switching writing can be performed by applying a rectangular or non-rectangular pulse to the memory cell 100. However, it is desirable to control the pulse width of the rectangular or non-rectangular pulse with high precision in order to write to a desired state. For example, unless the pulse width of the rectangular or non-rectangular pulse is controlled with high precision, there are concerns that the precessional movement of the magnetization will continue beyond half a turn and return to a state before writing.

[0094] Meanwhile, when writing using the memory cell 100 according to the present embodiment shown in Fig. 7, it is clear from the simulation results that it is unnecessary to control the pulse width of the rectangular pulse only for writing state 0. Fig. 38 illustrates a concept of this. As in Fig. As illustrated in Figure 38, the operating point moves from C to D, as indicated by an arrow A3 in the case of writing from state 0. Then, the MTJ voltage decreases, the perpendicular magnetic anisotropy becomes positive, and the precessional motion automatically stops. This means that it is unnecessary to limit the pulse width of the write pulse to, for example, 1.6 ns. Such a pulse, which only needs to be a certain time (for example, 1 ns) or more without any limitation on the pulse width, is called a "long pulse." Furthermore, the operating point is at D when the initial state is state 0. At this time, the perpendicular magnetic anisotropy remains positive, and accordingly, the precessional motion does not occur. This means that no state change occurs no matter how long the write pulse is applied.

[0095] As an example of such a write pulse, a long rectangular pulse is used. As shown in Fig. As illustrated in Figure 39, a long rectangular pulse shape is a shape in which an end voltage of a rectangular pulse is maintained as it is without being set to zero. Specifically, the long rectangular pulse shape is a shape in which the amplitude changes from zero to a desired amplitude value, and the desired amplitude value is maintained until the end of a pulse waveform.

[0096] Fig. 40 and Fig. 41 illustrate simulation results of writing state 0. The initial state is state 0 in Fig. 40 and the initial state is state 1 in Fig. 41. Since K in the middle row consists of Fig. 40 is positive from beginning to end, no magnetization reversal occurs. K in the middle row from Fig. 41 is essentially zero at the beginning of the voltage application, but increases when a state change occurs due to the precessional motion, becoming a positive value. After state 0 is written as a result, the precessional motion stops automatically. This means that writing state 0 can be implemented in a non-switching manner by applying the long rectangular pulse.

[0097] Note that when writing state 0 using the long rectangular pulse, there is no limitation on the pulse width of the write pulse, but there is a limitation on the pulse amplitude. The bit line voltage V BL and the word line voltage V WL the in Fig. 7 were varied by a grid, and a simulation similar to that in Fig. 40 and Fig. 41 was carried out to determine combinations of the bit line voltage V BLand the word line voltage V WL to obtain keys that allow writing in a non-switching manner. Fig. Figure 42 illustrates the results. A black stripe-shaped part is a part that shows the combinations of the bit line voltage V BL and the word line voltage V WL that enable non-shift writing. As can be seen from Fig. As can be seen in Figure 42, a region of the part is narrow, and its width is only about 60 mV at the maximum. This means that the pulse amplitude of the write pulse must be controlled to this extent. An embodiment in which non-switching writing can be expanded will be described in <1-11> below. <1-10. Writing scheme using a long gradient pulse>

[0098] A writing scheme using a long gradient pulse according to the present embodiment will be described with reference to Fig. 43 to 48 described.

[0099] Fig. Figure 43 is a view illustrating an example of a shape of the long gradient pulse. It is noted that Fig. 43 illustrates the case of writing state 1. That is, the shape of the long gradient pulse is a shape in which a final voltage of the Fig. 29 is maintained as it is without being set to zero. Specifically, the shape of the long gradient pulse is a shape in which the amplitude changes from zero to a desired amplitude value (first amplitude value), gradually decreases from the desired amplitude value to the next desired amplitude value (second amplitude value), and maintains the next desired amplitude value until the end of a pulse waveform.

[0100] It is noted that Fig. 43 illustrates the example of the shape of the long gradient pulse and the shape is not limited to this. For example, the shape may also be a shape in which a final voltage of the Fig. 30 to 33 is maintained as it is without being set to zero. That is, the shape of the long gradient pulse is a shape in which the amplitude gradually decreases from a desired amplitude value linearly, curvilinearly, or stepwise to the next desired amplitude value. This shape corresponds to the case of writing state 1, and in the case of writing state 0, a shape of the long gradient pulse is a shape in which the amplitude gradually increases from a desired amplitude value linearly, curvilinearly, or stepwise to the next desired amplitude value.

[0101] If the Fig. 43 is used when writing state 1, a limitation on a pulse width is removed. Fig. Figure 44 illustrates one concept. The operating point is moved from A not to C, but further to E by extending the slope of a non-rectangular pulse. Then, at the operating point E, the MTJ voltage decreases, the perpendicular magnetic anisotropy becomes positive, and the precessional motion automatically stops. This means that it is unnecessary to limit the pulse width of the write pulse to, for example, 1.6 ns.

[0102] Fig. 45 and Fig. 46 illustrate simulation results of writing state 1. The initial state is state 0 in Fig. 45 and the initial state is state 1 in Fig. 46. ​​K in the middle row from Fig. 45 is essentially zero at the beginning of the voltage application, but increases when a state change occurs due to the precessional movement, becoming a positive value. After state 1 is written as a result, the precessional movement stops automatically. K in the middle row. Fig. 46 is negative at the beginning of a voltage application, and a desired precessional movement cannot be performed. Afterward, K exceeds zero and becomes a positive value as the MTJ voltage decreases, and the magnetization movement stops. This means that writing to state 1 can be implemented in a non-switching manner by applying the long gradient pulse.

[0103] A constraint on the shape of the long gradient pulse was simulated as in the previously described writing scheme using the long rectangular pulse from <1-9>. The shape of the long gradient pulse includes a start voltage V1, an end voltage V2, and a slope width t1, which is Fig. 43. Among them, the starting voltage V1 was set to a voltage value at which the perpendicular magnetic anisotropy energy K for state 0 becomes zero. The remaining final voltage V2 and tilt width t1 were varied by a grid. Note that there are a case where the bit line BL is used and a case where the word line WL is used when a voltage pulse is applied to the memory cell 100. Since the bit line BL is used here, simulation results using the final voltage V2 as the bit line voltage V BL2 in Fig. 47 and Fig. 48. A black stripe-shaped part in Fig. 47 is an area where writing of state 1 is successful regardless of the initial state, and a black stripe-shaped part in Fig. 48 is an area where writing state 1 is only successful if the initial state is state 0.

[0104] As from Fig. 47 and Fig. 48, it is understood that the slope width t1 at which writing is successful is wider when the bit line voltage V BL2 the slope is lower. Then it is understood that a case where the bit line voltage V BL2 is zero, is most desirable. A pulse shape at this time is a “sawtooth pulse of the falling type”, which Fig. 49. A writing scheme using a sawtooth pulse is described in <1-11> below. If Fig. 47 and Fig. 48, furthermore, the area in which writing is successful is wider when the initial state is restricted to state 0. For this reason, when the initial state is state 1, it is possible to use a scheme of writing state 0 before writing state 1 and then writing state 1. This scheme is described in <1-12> below. <1-11. Writing scheme using a sawtooth pulse>

[0105] The writing scheme using the sawtooth pulse according to the present embodiment will be described with reference to Fig. 49 to 57.

[0106] Fig. Figure 49 is a view illustrating an example of a shape of the falling-type sawtooth pulse. The shape of the falling-type sawtooth pulse is a shape in which the final voltage of the Fig. 29 is set to zero. In particular, the shape of the decay-type sawtooth pulse is a shape in which the amplitude changes from zero to a desired amplitude value and gradually decreases from the desired amplitude value to zero. It is noted that Fig. 49 illustrates the example of the shape of the sawtooth pulse of the falling type and the shape is not limited to this. For example, the shape can also be a shape in which the final voltage of the Fig. 30 to 33 is set to zero. That is, the shape of the decay-type sawtooth pulse is one in which the amplitude changes from zero to a desired amplitude value, and the amplitude gradually decreases from the desired amplitude value to zero in a linear, curvilinear, or stepwise manner.

[0107] A constraint on the shape of the falling-type sawtooth pulse was simulated as in the previously described writing scheme using the long gradient pulse from <1-10>. The shape of the falling-type sawtooth pulse includes a starting voltage V and a decay width t2, which is Fig. 49. The starting voltage V and fall width t2 were varied by a grid. Note that there is a case where the bit line BL is used and a case where the word line WL is used when a voltage pulse is applied to the memory cell 100. Since the bit line BL is used here, simulation results using the starting voltage V as the bit line voltage V BL in Fig. 50. A black stripe-shaped part in Fig. 50 is a region where writing from state 0 is successful regardless of the initial state. It is understood that the bit line voltage V BL , which enables non-switching writing, exists when the fall width is 2 ns or more. For example, when the fall width t2 is 10 ns, a width of the bit line voltage V BL about 90 mV. Since the width of the bit line voltage V BL in the case of Fig. 42 is 60 mV, it is understood that an operating margin of 1.5 times is obtained.

[0108] Furthermore, simulation results in the case of writing state 1 in Fig. 51 and Fig. 52. A black stripe-shaped part in Fig. 51 is an area where writing of state 1 is successful regardless of the initial state, and a black stripe-shaped part in Fig. 52 is an area where writing state 1 is only successful if the initial state is state 0. If Fig. 51 and Fig. 52, the area where writing is successful is wider when the initial state is limited to "0." For this reason, when the initial state is state 1, it is possible to use a scheme of writing state 0 before writing state 1 and then writing state 1. This scheme is described in <1-12> below.

[0109] Fig. Figure 53 is a view illustrating an example of a shape of a rising-type sawtooth pulse. That is, the shape of the rising-type sawtooth pulse is a shape obtained by inverting the Fig. 49. In particular, the shape of the rising-type sawtooth pulse is a shape in which the amplitude gradually increases from zero to a desired amplitude value and changes from the desired amplitude value to zero. It is noted that Fig. 53 illustrates the example of the shape of the rising type sawtooth pulse and the shape is not limited to this. For example, the shape may also be a shape in which the waveform in one of Fig. 30 to 33 is inverted along the time axis, and a starting voltage is set to zero. That is, the shape of the rising-type sawtooth pulse is one in which the amplitude gradually increases from zero linearly, curvilinearly, or stepwise to a desired amplitude value, and changes from the desired amplitude value to zero.

[0110] In the same way as before, a constraint on the shape of the rising-type sawtooth pulse was simulated. The shape of the rising-type sawtooth pulse includes a final voltage V and a rise width t3, which are Fig. 53. The final voltage V and rise width t3 were varied by a grid. Note that there is a case where the bit line BL is used and a case where the word line WL is used when a voltage pulse is applied to the memory cell 100. Since the bit line BL is used here, simulation results using the final voltage V as the bit line voltage V BL in Fig. 54. A black stripe-shaped part in Fig. 54 is a region where writing from state 0 is successful regardless of the initial state. It is understood that the bit line voltage V BL, which enables non-switching writing, exists when the rise width is 2 ns or more. For example, when the fall width is 10 ns, a width of the bit line voltage V BL about 220 mV. Since the width of the bit line voltage V BL in the case of Fig. 42 is 60 mV, it is understood that an operating margin of 3.7 times is obtained.

[0111] Furthermore, simulation results in the case of writing state 1 in Fig. 55 and Fig. 56. A black stripe-shaped part in Fig. 55 is an area where writing of state 1 is successful regardless of the initial state, and a black stripe-shaped part in Fig. 56 is an area where writing state 1 is only successful if the initial state is state 0. If Fig. 55 and Fig. 56, the area where writing is successful is wider when the initial state is limited to "0." For this reason, when the initial state is state 1, it is possible to use the scheme of writing state 0 before writing state 1 and then writing state 1. This scheme is described in <1-12> below.

[0112] It is noted that a triangular sawtooth pulse (triangle pulse), as in Fig. 57 illustrates that, in addition to the falling-type sawtooth pulse and the rising-type sawtooth pulse, a triangular sawtooth pulse can be used as the sawtooth pulse. Specifically, one form of the triangular sawtooth pulse is a form in which the amplitude gradually increases from zero to a desired amplitude value and gradually decreases from the desired amplitude value to zero, as shown in Fig. 57. In the example from Fig. 57, the shape of the triangular sawtooth pulse is one in which the amplitude gradually increases linearly from zero to a desired amplitude value and gradually decreases linearly from the desired amplitude value to zero. The shape of the triangular sawtooth pulse is not specifically limited and may, for example, be one in which the amplitude gradually increases curvilinearly or stepwise from zero, or gradually decreases curvilinearly or stepwise from a desired amplitude value. Furthermore, the shape of the triangular sawtooth pulse can be determined by appropriately changing the rise width t3 and the fall width t2. <1-12. Writing scheme using initial writing>

[0113] A writing scheme using initial writing according to the present embodiment will be described with reference to Fig. 58 to 62 described.

[0114] Fig. Fig. 58 is a view illustrating an example of a processing procedure of a write processing of the write scheme using the initial write according to the present embodiment. This drawing is an example of writing (step S101) performed by the write circuit 70 in the write processing (step S100) in the storage system 1 shown in Fig. 16. First, the memory control unit 3 determines whether a state to be written is state 0 (step S141). As a result, if the state to be written is state 0 (Yes in step S141), the write circuit 70 writes state 0 (step S142), and the processing ends. On the other hand, if the state to be written is state 1 in step S141 (No in step S141), the write circuit 70 writes state 0 (step S143). Thereafter, the write circuit 70 writes state 1 (step S144), and the processing ends.

[0115] Fig. 59 and Fig. 60 are views for describing the writing scheme using the initial writing according to the present embodiment. Each drawing illustrates a variation of a method for applying a pulse voltage in the Fig. 58 illustrated writing scheme using the initial writing. In Fig. 59, the writing of state 0 and the writing of state 1 are independent of each other. On the other hand, in Fig. 60 writing state 0 and writing state 1 continuously. That is, a shape of a write pulse is a shape obtained by connecting a pulse shape for writing state 0 and a pulse shape for writing state 1.

[0116] Fig. 61 and Fig. 62 illustrate simulation results of the write scheme using the initial write according to the present embodiment. The state to be written is shown in Fig. 61 State 0 (state 0 is to be written) and the state to be written is in Fig. 62 State 1 (state 1 is to be written). For examples from Fig. 61 and Fig. 62, a long rectangular pulse is used to write state 0 and a sawtooth pulse of the falling type is used to write state 1. Furthermore, in the example from Fig. 62 writing state 0 and writing state 1 continuously, as in Fig. 60 illustrates. Fig. 61 illustrates the independent writing of state 0 and is accordingly similar to the results in Fig. 40 and Fig. 41 similar. In Fig. 62, the falling-type sawtooth pulse is continuously applied after writing state 0 using the long rectangular pulse. That is, multiple pulses with different pulse waveforms are continuous. When the initial state is state 0, there is no state change in the case of writing state 0. After that, state 1 is written by applying the falling-type sawtooth pulse. On the other hand, when the initial state is state 1, state 0 is written in the case of writing state 0. After that, state 1 is written by applying the falling-type sawtooth pulse. Since writing state 1 with respect to state 1 is avoided in this way, a writing margin increases.

[0117] It is noted that the write pulses used in the respective write schemes from the previously described write scheme using the long gradient pulse in <1-10> to the previously described write scheme using the initial write in <1-12> can be generated by using each of the write pulse generation circuits 200 and 210 illustrated in <1-8> and described previously alone or in combination. <1-13. Function and Effect>

[0118] As described above, according to the embodiment, the memory system 1 functioning as the storage device includes: the magnetoresistive element 120 whose magnetization direction is variable between a first state (e.g., state 1) and a second state (e.g., state 0) by voltage application; the selection element 110 connected to the magnetoresistive element 120; and the write unit (e.g., the write circuit 70) switchably applying a first write voltage (e.g., the MTJ voltage V MTJ ) for setting the magnetization direction of the magnetoresistive element 120 to the first state and a second write voltage (for example, the MTJ voltage V MTJ) to the magnetoresistive element 120 to set the magnetization direction of the magnetoresistive element 120 to the second state. As a result, it is possible to perform non-switching writing, which does not require reading an initial state before writing. As a result, the reading time and power consumption required at the time of initial reading can be reduced, and high-speed, low-power writing can be implemented.

[0119] Furthermore, the writing unit may apply a pulse voltage as the first writing voltage and / or the second writing voltage to the magnetoresistive element 120. As a result, high-speed, low-power writing can be reliably implemented.

[0120] Furthermore, the writing unit can continuously repeat the application of the pulse voltage to the magnetoresistive element 120. As a result, a write error rate can be reduced.

[0121] Furthermore, the pulse width or amplitude of the pulse voltage can be different for each pulse voltage application. As a result, the write error rate can be reliably reduced.

[0122] Furthermore, the writing unit can read a state of the magnetization direction of the magnetoresistive element 120 after applying the pulse voltage (for example, after continuously repeating the application of the pulse voltage) and reapply the pulse voltage if the read state is not a desired state (for example, continuously repeating the application of the pulse voltage). As a result, the write error rate can be reliably reduced.

[0123] Furthermore, the pulse voltage may desirably be a pulse voltage with a pulse width of 0.1 ns or more and 20 ns or less. As a result, the write error rate can be reliably reduced.

[0124] Furthermore, a pulse waveform of the pulse voltage used as the first write voltage can be different from a pulse waveform of the pulse voltage used as the second write voltage. As a result, it is possible to improve writing stability (for example, reduce the write error rate).

[0125] Furthermore, a pulse waveform of the pulse voltage may have a shape in which the amplitude changes from zero to a first amplitude value, and the first amplitude value is maintained until the end of the pulse waveform. As a result, it is possible to reliably improve the stability of writing.

[0126] Furthermore, the pulse waveform of the pulse voltage can have a non-rectangular shape. As a result, it is possible to reliably improve the stability of writing.

[0127] Furthermore, the non-rectangular pulse waveform may have a first shape in which the amplitude changes from zero to a first amplitude value, gradually decreases or increases from the first amplitude value to a second amplitude value, and changes from the second amplitude value to zero. As a result, it is possible to reliably improve the stability of writing.

[0128] Furthermore, the non-rectangular pulse waveform may have a shape that decreases or increases linearly, curvilinearly, or stepwise from the first amplitude value to the second amplitude value with the first shape described above. As a result, it is possible to reliably improve the stability of writing.

[0129] Furthermore, the non-rectangular pulse waveform may have a second shape in which the amplitude changes from zero to a first amplitude value, gradually decreases or increases from the first amplitude value to a second amplitude value, and the second amplitude value is maintained until the end of the pulse waveform. As a result, it is possible to reliably improve the stability of writing.

[0130] Furthermore, the non-rectangular pulse waveform may have a shape that decreases or increases linearly, curvilinearly, or stepwise from the first amplitude value to the second amplitude value with the second shape described above. As a result, it is possible to reliably improve the stability of writing.

[0131] Furthermore, the non-rectangular pulse waveform may have a third shape in which the amplitude changes from zero to a first amplitude value and gradually decreases from the first amplitude value to zero. As a result, it is possible to reliably improve the stability of writing.

[0132] Furthermore, the non-rectangular pulse waveform may have a shape that decreases linearly, curvilinearly, or stepwise from the first amplitude value to zero with the third shape described above. As a result, it is possible to reliably improve the stability of writing.

[0133] Furthermore, the non-rectangular pulse waveform may have a fourth shape in which the amplitude gradually increases from zero to the first amplitude value and changes from the first amplitude value to zero. As a result, it is possible to reliably improve the stability of writing.

[0134] Furthermore, the non-rectangular pulse waveform may have a shape in which the amplitude increases linearly, curvilinearly, or stepwise from zero to the first amplitude value with the fourth shape described above. As a result, it is possible to reliably improve the stability of writing.

[0135] Furthermore, the non-rectangular pulse waveform may have a fifth shape in which the amplitude gradually increases from zero to the first amplitude value and gradually decreases from the first amplitude value to zero. As a result, it is possible to reliably improve the stability of writing.

[0136] Furthermore, the non-rectangular pulse waveform may have a shape in which the amplitude increases linearly, curvilinearly, or stepwise from zero to the first amplitude value and decreases linearly, curvilinearly, or stepwise from the first amplitude value to zero with the fifth shape described above. As a result, it is possible to reliably improve the stability of writing.

[0137] Furthermore, the writing unit may apply the first write voltage when the magnetization direction of the magnetoresistive element 120 is set to the first state, and apply the second write voltage after applying the first write voltage when the magnetization direction of the magnetoresistive element 120 is set to the second state. As a result, a write margin increases, and accordingly, it is possible to reliably improve the stability of writing.

[0138] Furthermore, the selection element 110 may have a drain terminal, a source terminal, and a gate terminal, one terminal of two terminals of the magnetoresistive element 120 may be connected to the bit line 12, the other terminal may be connected to the drain terminal, the source terminal may be connected to the source line 13, and the gate terminal may be connected to the word line 11 (see Fig. 3). With such an initial configuration, high-speed, low-power writing can also be implemented.

[0139] Furthermore, the selection element 110 may have a drain terminal, a source terminal, and a gate terminal, one terminal of two terminals of the magnetoresistive element 120 may be connected to the source line 13, the other terminal may be connected to the source terminal, the drain terminal may be connected to the bit line 12, and the gate terminal may be connected to the word line 11 (see Fig. 4). With such a configuration, high-speed, low-power writing can also be implemented.

[0140] Furthermore, in the first configuration or the second configuration described above, the writing unit may apply a first voltage (for example, GND) to the source line 13, a second voltage (for example, V1 in Fig. 10) to the bit line 12 or the word line 11, a first pulse voltage (for example V2 in Fig. 11) to the word line 11 or the bit line 12 to apply the first write voltage to the magnetoresistive element 120 if the magnetization direction of the magnetoresistive element 120 is set to the first state, and a second pulse voltage (for example, V3 in Fig. 11) to the word line 11 or the bit line 12 to apply the second write voltage to the magnetoresistive element 120 if the magnetization direction of the magnetoresistive element 120 is set to the second state. As a result, high-speed, low-power writing can be reliably implemented.

[0141] Furthermore, the first pulse voltage can be higher than the second pulse voltage. As a result, high-speed, low-power writing can be implemented more reliably.

[0142] Furthermore, in the first configuration or the second configuration described above, the writing unit may apply a third voltage (for example, GND) to the source line 13, a third pulse voltage (for example, V6 in Fig. 14) to the word line 11 or the bit line 12, a fourth voltage (for example V4 in Fig. 13) to the bit line 12 or the word line 11 to apply the first write voltage to the magnetoresistive element 120 if the magnetization direction of the magnetoresistive element 120 is set to the first state, and a fifth voltage (for example, V5 in Fig. 13) to the bit line 12 or the word line 11 to apply the second write voltage to the magnetoresistive element 120 if the magnetization direction of the magnetoresistive element 120 is set to the second state. As a result, high-speed, low-power writing can be reliably implemented.

[0143] Furthermore, the fourth voltage can be higher than the fifth voltage. As a result, writing can be implemented more reliably at high speed and low power consumption. <2. Other embodiments>

[0144] The configurations according to the above embodiment can be implemented in various different forms besides the previously described embodiment. For example, the configurations are not limited to the previously described examples and can have various modes. Furthermore, for example, the configurations, processing procedures, specific names, and information, including various types of data and parameters, illustrated in the above document and drawings can be arbitrarily changed unless otherwise specified.

[0145] Furthermore, each component of each illustrated device is a functional concept and does not necessarily have to be physically configured as illustrated. That is, the specific form of distribution / integration of each device is not limited to those illustrated in the drawings, and all or part of them may be functionally or physically distributed / integrated into any units according to different loads or usage situations.

[0146] For example, the MTJ according to any of the above embodiments and modifications thereof may be used as the magnetoresistive element 120, and a storage device such as a hard disk drive (HDD) may be configured as the storage device. <3. Configuration example of an electronic device>

[0147] As an electronic device to which the storage system 1 according to the above embodiment (including modifications) is applied, an imaging device 300, a distance measuring device 400 and a game device 900 are described with reference to Fig. 63 to 66. For example, each of the imaging device 300, the distance measuring device 400, and the gaming device 900 uses the storage system 1 according to each of the above embodiments as a memory. Examples of the memory include a flash memory and the like. <3-1. Imaging device>

[0148] The imaging apparatus 300 to which the storage system 1 according to the above embodiment is applied will be described with reference to Fig. 63 described. Fig. 63 is a diagram illustrating an example of a schematic configuration of the imaging device 300. The imaging device 300 is an example of the electronic device to which the storage system 1 according to the present embodiment is applied. Examples of the imaging device 300 include electronic devices such as a digital still camera, a video camera, a smartphone with an imaging function, and a mobile phone.

[0149] As in Fig. 63, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element 303, a control circuit (drive circuit) 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 can capture a still image and a moving image.

[0150] The optical system 301 includes one or more lenses. The optical system 301 guides light (incident light) from a subject to the imaging element 303 and forms an image on a light-receiving surface of the imaging element 303.

[0151] The shutter device 302 is arranged between the optical system 301 and the imaging element 303. The shutter device 302 controls a light irradiation period and a light shielding period with respect to the imaging element 303 according to the control of the control circuit 304.

[0152] The imaging element 303 accumulates signal charges for a certain period according to light formed on the light-receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the imaging element 303 are transferred according to a drive signal (timing signal) provided by the control circuit 304.

[0153] The control circuit 304 outputs the drive signal for controlling a transfer operation of the imaging element 303 and a shutter operation of the shutter device 302 to drive the imaging element 303 and the shutter device 302.

[0154] The signal processing circuit 305 performs various types of signal processing on the signal charges output from the imaging element 303. An image (image data) obtained by performing signal processing by the signal processing circuit 305 is supplied to the monitor 306 and also supplied to the memory 307.

[0155] The monitor 306 displays a moving image or a still image captured by the imaging element 303 based on the image data provided by the signal processing circuit 305. For example, a panel-type display device such as a liquid crystal panel or an organic electroluminescence (EL) panel is used as the monitor 306.

[0156] The memory 307 stores the image data provided by the signal processing circuit 305, that is, image data of the moving image or the still image captured by the imaging element 303. The memory 307 corresponds to the storage device 1 according to the above embodiment.

[0157] Also in the imaging device 300 configured in this manner, high-speed and low-power writing can be implemented by using the previously described memory system 1 as the memory 307. <3-2. Distance measuring device>

[0158] The distance measuring device 400 to which the storage system 1 according to the above embodiment is applied will be described with reference to Fig. 64 described. Fig. 64 is a diagram illustrating an example of a schematic configuration of the distance measuring device 400. The distance measuring device 400 is an example of the electronic device to which the storage system 1 according to the present embodiment is applied.

[0159] As in Fig. 64, the distance measuring device (distance image sensor) 400 includes a light source unit 401, an optical system 402, a solid-state imaging device (imaging element) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. The distance measuring device 400 can acquire a distance image according to a distance to a subject by projecting light from the light source unit 401 toward the subject and receiving light (modulated light or pulsed light) reflected from a surface of the subject.

[0160] The light source unit 401 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source or a laser diode array in which laser diodes are lined up in a line is used as the light source unit 401. Note that the laser diode array is supported by a predetermined driving unit (not illustrated) and is scanned in a direction perpendicular to the array direction of the laser diodes.

[0161] The optical system 402 includes one or more lenses. The optical system 402 guides light (incident light) from the subject to the solid-state imaging device 403 to form an image on a light-receiving surface (sensor unit) of the solid-state imaging device 403.

[0162] The solid-state imaging device 403 stores signal charges according to the light of the image formed on the light-receiving surface via the optical system 402. A distance signal indicating the distance obtained from a light-receiving signal (APD OUT) output from the solid-state imaging device 403 is supplied to the signal processing circuit 405. For example, a solid-state imaging element such as an image sensor is used as the solid-state imaging device 403.

[0163] The control circuit 404 outputs a drive signal (control signal) for controlling operations of the light source unit 401, the solid-state imaging device 403, and the like to drive the light source unit 401, the solid-state imaging device 403, and the like.

[0164] The signal processing circuit 405 performs various types of signal processing on the distance signal provided from the solid-state imaging device 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, and the like) to construct the distance image based on the distance signal. An image (image data) obtained by performing the signal processing by the signal processing circuit 405 is supplied to the monitor 406 and also supplied to the memory 407.

[0165] The monitor 406 displays the distance image captured by the imaging element 303 based on the image data provided by the signal processing circuit 405. For example, a panel-type display device such as a liquid crystal panel or an organic EL panel is used as the monitor 406.

[0166] The memory 407 stores the image data provided by the signal processing circuit 405, that is, the image data of the distance image captured by the imaging element 303. The memory 407 corresponds to the storage system 1 according to the above embodiment.

[0167] Also in the distance measuring device 400 configured in this manner, high-speed and low-power writing can be implemented by using the previously described memory system 1 as the memory 407. <3-3. Gaming device>

[0168] The game device 900 to which the storage system 1 according to the above embodiment is applied will be described with reference to Fig. 65 and Fig. 66 described. Fig. 65 is a perspective view (external perspective view) illustrating an example of the schematic configuration of the game device 900.

[0169] Fig. 66 is a block diagram illustrating an example of the schematic configuration of the game device 900. The game device 900 is an example of the electronic device to which the storage system 1 according to the present embodiment is applied.

[0170] As in Fig. 65, for example, the game device 900 has an appearance in which each component is arranged inside and outside an outer casing 901 formed in a horizontally long flat shape.

[0171] On the front surface of the outer casing 901, a display panel 902 is provided at the center thereof in the longitudinal direction. Further, operation buttons 903 and operation buttons 904 are provided on the left and right sides of the display panel 902, respectively, spaced apart from each other in the circumferential direction. An operation button 905 is provided at a lower end of the front surface of the outer casing 901. The operation buttons 903, 904, and 905 function as direction buttons, designation buttons, or the like, and are used to select menu items displayed on the display panel 902, for game progress, or the like.

[0172] On the upper surface of the outer casing 901, a connection terminal 906 for connecting an external device, a power supply terminal 907, a light receiving window 908 for performing infrared communication with the external device, and the like are provided.

[0173] As in Fig. As illustrated in Figure 66, the gaming device 900 includes an arithmetic processing unit 910 including a central processing unit (CPU), a storage unit 920 that stores various types of information, and a controller 930 that controls each configuration of the gaming device 900. Power is supplied to the arithmetic processing unit 910 and the controller 930 from, for example, a battery (not illustrated) or the like.

[0174] The arithmetic processing unit 910 generates a menu screen for allowing a user to set various types of information or select an application. Furthermore, the arithmetic processing unit 910 executes the application selected by the user.

[0175] The storage unit 920 stores various types of information set by the user. The storage unit 920 corresponds to the storage system 1 according to the above embodiment.

[0176] The controller 930 includes an input receiving unit 931, a communication processing unit 933, and a power controller 935. The input receiving unit 931 detects, for example, the states of the operation buttons 903, 904, and 905. Furthermore, the communication processing unit 933 performs communication processing with an external device. The power controller 935 controls the power supplied to each unit of the gaming device 900.

[0177] Also in the game device 900 configured in this manner, high-speed and low-power writing can be implemented by using the above-described memory system 1 as the game device 920.

[0178] It is noted that the memory system 1 according to each of the above-described embodiments can be mounted on the same semiconductor chip together with a semiconductor circuit constituting an arithmetic device or the like to constitute a semiconductor device (System-on-a-Chip: SoC).

[0179] Furthermore, the storage system 1 according to the above embodiment can be mounted on various electronic devices on which a memory (storage unit) can be mounted, as described above. For example, the storage system 1 can be mounted on various electronic devices, such as a notebook personal computer (PC), a mobile device (e.g., a smartphone, a tablet PC, or the like), a personal digital assistant (PDA), a wearable device, and a music device, in addition to the imaging device 300 and the game device 900. For example, the storage system 1 is used as various memories such as storage. <4. Appendix>

[0180] It is noted that the present technology may also have the following configurations. (1) A storage device comprising: a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application; a selection element connected to the magnetoresistive element; and a write unit that switchably applies a first write voltage for setting the magnetization direction of the magnetoresistive element to the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element to the second state to the magnetoresistive element. (2) The storage device according to (1), wherein the writing unit applies a pulse voltage as the first writing voltage and / or the second writing voltage to the magnetoresistive element. (3) The storage device according to (2), wherein the writing unit continuously repeats the application of the pulse voltage to the magnetoresistive element. (4) The storage device according to (3), wherein a pulse width or an amplitude of the pulse voltage is different for each application of the pulse voltage. (5) The storage device according to any one of (2) to (4), wherein the writing unit reads a state of the magnetization direction of the magnetoresistive element after applying the pulse voltage and applies the pulse voltage again if the read state is not a desired state. (6) The storage device according to any one of (2) to (5), wherein the pulse voltage is a pulse voltage with a pulse width of 0.1 ns or more and 20 ns or less. (7) The storage device according to any one of (2) to (6), wherein a pulse waveform of the pulse voltage used as the first write voltage is different from a pulse waveform of the pulse voltage used as the second write voltage. (8) The storage device according to any one of (2) to (7), wherein a pulse waveform of the pulse voltage has a shape in which an amplitude changes from zero to a first amplitude value and the first amplitude value is maintained until an end of the pulse waveform. (9) The storage device according to any one of (2) to (7), wherein a pulse waveform of the pulse voltage has a non-rectangular shape. (10) The storage device according to (9), wherein the pulse waveform of the pulse voltage has a shape in which an amplitude changes from zero to a first amplitude value, gradually decreases or increases from the first amplitude value to a second amplitude value, and changes from the second amplitude value to zero. (11) The storage device according to (10), wherein the pulse waveform of the pulse voltage has a shape that decreases or increases linearly, curvilinearly, or stepwise from the first amplitude value to the second amplitude value. (12) The storage device according to (9), wherein the pulse waveform of the pulse voltage has a shape in which an amplitude changes from zero to a first amplitude value, gradually decreases or increases from the first amplitude value to a second amplitude value, and the second amplitude value is maintained until an end of the pulse waveform. (13) The storage device according to (12), wherein the pulse waveform of the pulse voltage has a shape that decreases or increases linearly, curvilinearly, or stepwise from the first amplitude value to the second amplitude value. (14) The storage device according to (9), wherein the pulse waveform of the pulse voltage has a shape in which an amplitude changes from zero to a first amplitude value and gradually decreases from the first amplitude value to zero. (15) The storage device according to (14), wherein the pulse waveform of the pulse voltage has a shape that decreases linearly, curvilinearly or stepwise from the first amplitude value to zero. (16) The storage device according to (9), wherein the pulse waveform of the pulse voltage has a shape in which an amplitude gradually increases from zero to a first amplitude value and changes from the first amplitude value to zero. (17) The storage device according to (16), wherein the pulse waveform of the pulse voltage has a shape in which the amplitude increases linearly, curvilinearly or stepwise from zero to the first amplitude value. (18) The storage device according to (9), wherein the pulse waveform of the pulse voltage has a shape in which an amplitude gradually increases from zero to a first amplitude value and gradually decreases from the first amplitude value to zero. (19) The storage device according to (18), wherein the pulse waveform of the pulse voltage has a shape in which the amplitude increases linearly, curvilinearly or stepwise from zero to the first amplitude value and decreases linearly, curvilinearly or stepwise from the first amplitude value to zero. (20) The storage device according to any one of (1) to (19), wherein the writing unit applies the first write voltage when the magnetization direction of the magnetoresistive element is set to the first state, and applies the first write voltage and then applies the second write voltage when the magnetization direction of the magnetoresistive element is set to the second state. (21) The storage device according to any one of (1) to (20), wherein the selection element has a drain terminal, a source terminal and a gate terminal, one of two terminals of the magnetoresistive element is connected to a bit line and another terminal is connected to the drain terminal, the source terminal is connected to a source line, and the gate terminal is connected to a word line. (22) The storage device according to any one of (1) to (20), wherein the selection element has a drain terminal, a source terminal and a gate terminal, one terminal of two terminals of the magnetoresistive element is connected to a source line and another terminal is connected to the source terminal, the drain terminal is connected to a bit line, and the gate terminal is connected to a word line. (23) The storage device according to (21), wherein the write unit applies a first voltage to the source line, applies a second voltage to the bit line or the word line, applies a first pulse voltage to the word line or the bit line to apply the first write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the first state, and applies a second pulse voltage to the word line or the bit line to apply the second write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the second state. (24) The storage device according to (22), wherein the write unit applies a first voltage to the source line, applies a second voltage to the bit line or the word line, applies a first pulse voltage to the word line or the bit line to apply the first write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the first state, and applies a second pulse voltage to the word line or the bit line to apply the second write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the second state. (25) The storage device according to (23) or (24), wherein the first pulse voltage is higher than the second pulse voltage. (26) The storage device according to (21), wherein the write unit applies a third voltage to the source line, applies a third pulse voltage to the word line or the bit line, applies a fourth voltage to the bit line or the word line to apply the first write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the first state, and applies a fifth voltage to the bit line or the word line to apply the second write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the second state. (27) The storage device according to (22), wherein the write unit applies a third voltage to the source line, applies a third pulse voltage to the word line or the bit line, applies a fourth voltage to the bit line or the word line to apply the first write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the first state, and applies a fifth voltage to the bit line or the word line to apply the second write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the second state. (28) The storage device according to (26) or (27), wherein the fourth voltage is higher than the fifth voltage. (29) Electronic device comprising: a storage device that stores data, wherein the storage device includes: a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application; a selection element connected to the magnetoresistive element; and a write unit that switchably applies a first write voltage for setting the magnetization direction of the magnetoresistive element to the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element to the second state to the magnetoresistive element. (30) A storage device control method comprising: switchable application, to a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application, of a first write voltage for setting the magnetization direction of the magnetoresistive element in the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element in the second state. (31) An electronic device incorporating the storage device according to any one of (1) to (28). (32) A storage device control method for controlling the storage device according to any one of (1) to (28). List of reference symbols 1 storage system 2 interface unit 3 Storage control unit 4 Storage array 10 memory cell array 11 Wording 12 bit line 13 Source line 20 word line address decoders 30 Word line control circuit 40 bit line address decoders 50 Bit line control circuit 60 detection amplifiers 70 write circuit 80 reading circuit 90 Voltage generation circuit 100 memory cells 101 Wiring 102 Wiring 103 Contact layer 104 Contact layer 110 Selection element 120 Magnetoresistive element 121 Base layer 122 Fixed magnetization layer 123 Tunnel barrier layer 124 Storage layer 125 top layer 200 write pulse generation circuit 201 End of input 202 CR circuit 203 Transfer Gate 204 operational amplifiers 205 Output connector 206 Exit 207 Non-inverting input 210 Write pulse generation circuit 211 waveform memories 212 D / A conversion circuit 300 imaging device 307 storage 400 Distance measuring device 407 memory 900 gaming facilities 920 storage unit QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2018-092696 A

[0006]

Claims

[1] Storage device comprising: a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application; a selection element connected to the magnetoresistive element; and a write unit that switchably applies a first write voltage for setting the magnetization direction of the magnetoresistive element to the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element to the second state to the magnetoresistive element. [2] The storage device according to claim 1, wherein the writing unit applies a pulse voltage as the first writing voltage and / or the second writing voltage to the magnetoresistive element. [3] The storage device according to claim 2, wherein the writing unit continuously repeats the application of the pulse voltage to the magnetoresistive element. [4] A storage device according to claim 3, wherein a pulse width or an amplitude of the pulse voltage is different for each application of the pulse voltage. [5] The storage device according to claim 2, wherein the writing unit reads a state of the magnetization direction of the magnetoresistive element after applying the pulse voltage and applies the pulse voltage again when the read state is not a desired state. [6] The storage device according to claim 2, wherein the pulse voltage is a pulse voltage having a pulse width of 0.1 ns or more and 20 ns or less. [7] The storage device according to claim 2, wherein a pulse waveform of the pulse voltage used as the first write voltage is different from a pulse waveform of the pulse voltage used as the second write voltage. [8] The storage device according to claim 2, wherein a pulse waveform of the pulse voltage has a shape in which an amplitude changes from zero to a first amplitude value and the first amplitude value is maintained until an end of the pulse waveform. [9] The storage device according to claim 2, wherein a pulse waveform of the pulse voltage has a non-rectangular shape. [10] The storage device according to claim 9, wherein the pulse waveform of the pulse voltage has a shape in which an amplitude changes from zero to a first amplitude value, gradually decreases or increases from the first amplitude value to a second amplitude value, and changes from the second amplitude value to zero. [11] The storage device according to claim 10, wherein the pulse waveform of the pulse voltage has a shape that decreases or increases linearly, curvilinearly, or stepwise from the first amplitude value to the second amplitude value. [12] The storage device according to claim 9, wherein the pulse waveform of the pulse voltage has a shape in which an amplitude changes from zero to a first amplitude value, gradually decreases or increases from the first amplitude value to a second amplitude value, and the second amplitude value is maintained until an end of the pulse waveform. [13] The storage device according to claim 12, wherein the pulse waveform of the pulse voltage has a shape that decreases or increases linearly, curvilinearly, or stepwise from the first amplitude value to the second amplitude value. [14] The storage device according to claim 9, wherein the pulse waveform of the pulse voltage has a shape in which an amplitude changes from zero to a first amplitude value and gradually decreases from the first amplitude value to zero. [15] The storage device of claim 14, wherein the pulse waveform of the pulse voltage has a shape that decreases linearly, curvilinearly, or stepwise from the first amplitude value to zero. [16] The storage device according to claim 9, wherein the pulse waveform of the pulse voltage has a shape in which an amplitude gradually increases from zero to a first amplitude value and changes from the first amplitude value to zero. [17] The storage device of claim 16, wherein the pulse waveform of the pulse voltage has a shape in which the amplitude increases linearly, curvilinearly, or stepwise from zero to the first amplitude value. [18] The storage device according to claim 9, wherein the pulse waveform of the pulse voltage has a shape in which an amplitude gradually increases from zero to a first amplitude value and gradually decreases from the first amplitude value to zero. [19] The storage device of claim 18, wherein the pulse waveform of the pulse voltage has a shape in which the amplitude increases linearly, curvilinearly, or stepwise from zero to the first amplitude value and decreases linearly, curvilinearly, or stepwise from the first amplitude value to zero. [20] Storage device according to claim 1, wherein the writing unit applies the first write voltage when the magnetization direction of the magnetoresistive element is set to the first state, and applies the first write voltage and then applies the second write voltage when the magnetization direction of the magnetoresistive element is set to the second state. [21] Storage device according to claim 1, wherein the selection element has a drain terminal, a source terminal and a gate terminal, one of two terminals of the magnetoresistive element is connected to a bit line and another terminal is connected to the drain terminal, the source terminal is connected to a source line, and the gate terminal is connected to a word line. [22] Storage device according to claim 1, wherein the selection element has a drain terminal, a source terminal and a gate terminal, one terminal of two terminals of the magnetoresistive element is connected to a source line and another terminal is connected to the source terminal, the drain terminal is connected to a bit line, and the gate terminal is connected to a word line. [23] The storage device according to claim 21, wherein the write unit applies a first voltage to the source line, applies a second voltage to the bit line or the word line, applies a first pulse voltage to the word line or the bit line to apply the first write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the first state, and applies a second pulse voltage to the word line or the bit line to apply the second write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the second state. [24] The storage device according to claim 22, wherein the write unit applies a first voltage to the source line, applies a second voltage to the bit line or the word line, applies a first pulse voltage to the word line or the bit line to apply the first write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the first state, and applies a second pulse voltage to the word line or the bit line to apply the second write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the second state. [25] The storage device of claim 23, wherein the first pulse voltage is higher than the second pulse voltage. [26] The storage device according to claim 21, wherein the write unit applies a third voltage to the source line, applies a third pulse voltage to the word line or the bit line, applies a fourth voltage to the bit line or the word line to apply the first write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the first state, and applies a fifth voltage to the bit line or the word line to apply the second write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the second state. [27] The storage device according to claim 22, wherein the write unit applies a third voltage to the source line, applies a third pulse voltage to the word line or the bit line, applies a fourth voltage to the bit line or the word line to apply the first write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the first state, and applies a fifth voltage to the bit line or the word line to apply the second write voltage to the magnetoresistive element if the magnetization direction of the magnetoresistive element is set to the second state. [28] The storage device of claim 26, wherein the fourth voltage is higher than the fifth voltage. [29] Electronic device comprising: a storage device that stores data, wherein the storage device includes: a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application; a selection element connected to the magnetoresistive element; and a write unit that switchably applies a first write voltage for setting the magnetization direction of the magnetoresistive element to the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element to the second state to the magnetoresistive element. [30] A storage device control method comprising: switchable application, to a magnetoresistive element whose magnetization direction is variable between a first state and a second state by voltage application, of a first write voltage for setting the magnetization direction of the magnetoresistive element in the first state and a second write voltage for setting the magnetization direction of the magnetoresistive element in the second state.

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