Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate has a display side and comprises a base substrate (110), a driver circuit layer (120), a first electrode layer, and a pixel definition layer (1017). The driver circuit layer (120) is arranged on the base substrate (110) and comprises a plurality of first gaps (D1) that allow light from the display side to pass through it. The first electrode layer is arranged on a side of the driver circuit layer (120) facing away from the base substrate (110) and comprises a plurality of first electrode patterns (1041) and a plurality of light-blocking patterns (SH).The pixel definition layer (1017) is arranged on a side of the first electrode layer facing away from the base substrate (110) and comprises a plurality of subpixel openings (PO), each of which exposes a plurality of first electrode patterns (1041). In a direction perpendicular to the base substrate (110), at least a portion of the plurality of light-blocking patterns (SH) does not overlap with the plurality of subpixel openings (PO), and this at least portion of the plurality of light-blocking patterns (SH) corresponds to and at least partially overlaps with at least a portion of the plurality of first gaps (D1), so that light from the display side is at least partially blocked.

Description

FIELD OF TECHNOLOGY

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. STATE OF THE ART

[0002] OLED (Organic Light Emitting Diode) displays have many advantages, such as self-illumination, high contrast, high resolution, wide viewing angle, low power consumption, fast response time, and low manufacturing costs. They have become one of the key development directions for the new generation of display devices, and accordingly, they have attracted more and more attention.

[0003] Currently, the display device usually has many functions, such as fingerprint recognition. In this case, the structure of the display device can be adapted accordingly to the functions. SUMMARY

[0004] At least one embodiment of the disclosure provides a display substrate having a display side and comprising: a base substrate; a driver circuit layer disposed on the base substrate and comprising a plurality of first gaps, the plurality of first gaps allowing light from the display side to pass therethrough; a first electrode layer disposed on a side of the driver circuit layer facing away from the base substrate and comprising a plurality of first electrode patterns and a plurality of light-blocking patterns;and a pixel definition layer disposed on a side of the first electrode layer facing away from the base substrate and comprising a plurality of subpixel openings, wherein the plurality of subpixel openings expose the plurality of first electrode patterns, wherein in a direction perpendicular to the base substrate, at least a portion of the plurality of light-blocking patterns does not overlap with the plurality of subpixel openings, wherein the at least a portion of the plurality of light-blocking patterns corresponds to and at least partially overlaps with at least a portion of the plurality of first gaps, such that light from the display side is at least partially blocked.;

[0005] For example, in the display substrate provided by at least one embodiment of the disclosure, a width of the plurality of first gaps is less than or equal to 4.0 micrometers.

[0006] For example, in the display substrate provided by at least one embodiment of the disclosure, a distance of the plurality of first gaps from a center of the plurality of subpixel openings is less than 33 micrometers.

[0007] For example, in the display substrate provided by at least one embodiment of the disclosure, at least a part of the plurality of light-blocking patterns is each integrally connected to the plurality of first electrode patterns.

[0008] For example, in the display substrate provided by at least one embodiment of the disclosure, each of the plurality of first electrode patterns includes a main part and a connection part, and a planar shape of the main part is a polygon or a shape having an arc edge, and a planar shape of the plurality of light-blocking patterns is a polygon.

[0009] For example, in the display substrate provided by at least one embodiment of the disclosure, the display substrate includes a plurality of subpixels, each of the plurality of subpixels includes a light-emitting device, and the plurality of first electrode patterns are respectively used as anodes of the light-emitting devices of the plurality of subpixels.

[0010] For example, in the display substrate provided by at least one embodiment of the disclosure, the plurality of subpixels include red subpixels, green subpixels, and blue subpixels, wherein a planar shape of the main part of the first electrode pattern of the light-emitting device of each of the red subpixels is a hexagon, and a shape of the light-blocking pattern integrally connected to the first electrode pattern of the light-emitting device of each of the red subpixels is a triangle.

[0011] For example, in the display substrate provided by at least one embodiment of the disclosure, a number of light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the red sub-pixels is two, and the two light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the red sub-pixels are arranged symmetrically.

[0012] For example, in the display substrate provided by at least one embodiment of the disclosure, a planar shape of the main part of the first electrode pattern of the light-emitting device of each of the blue sub-pixels is a hexagon, and a shape of the light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the blue sub-pixels is triangular or rectangular.

[0013] For example, in the display substrate provided by at least one embodiment of the disclosure, a number of light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the blue sub-pixels is three, and the three light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the blue sub-pixels are integrally connected to three edges of the first electrode pattern of the light-emitting device of each of the blue sub-pixels.

[0014] For example, in the display substrate provided by at least one embodiment of the disclosure, a planar shape of the main part of the first electrode pattern of the light-emitting device of each of the green sub-pixels is a pentagon, and a shape of the light-blocking patterns integrally bonded to the first electrode pattern of the light-emitting device of each of the green sub-pixels is rectangular.

[0015] For example, in the display substrate provided by at least one embodiment of the disclosure, a number of light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the green sub-pixels is one or two, and the one or two light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the green sub-pixels are integrally connected to one edge and two edges, respectively, of the first electrode pattern of the light-emitting device of each of the green sub-pixels.

[0016] For example, in the display substrate provided by at least one embodiment of the disclosure, for the subpixel opening and the first electrode pattern corresponding to each other, a shape of the subpixel opening is the same as a shape of the main part of the first electrode pattern, a first orthographic projection of the subpixel opening on the base substrate is within a second orthographic projection of the main part of the first electrode pattern on the base substrate, and a minimum distance between an edge of the first orthographic projection and an edge of the second orthographic projection is from 1.5 micrometers to 3.5 micrometers.

[0017] For example, in the display substrate provided by at least one embodiment of the disclosure, the light-emitting devices of the red subpixels and the blue subpixels are arranged in the same rows, the light-emitting devices of the green subpixels are arranged in substantially the same rows, and the rows in which the light-emitting devices of the red subpixels and the blue subpixels are arranged and the rows in which the light-emitting devices of the green subpixels are arranged are arranged alternately.

[0018] For example, in the display substrate provided by at least one embodiment of the disclosure, the driving circuit layer further includes a plurality of second gaps, the plurality of second gaps allowing light from the display side to pass therethrough, in the direction perpendicular to the base substrate, the plurality of second gaps do not overlap with the plurality of first electrode patterns and the plurality of light-blocking patterns.

[0019] For example, in the display substrate provided by at least one embodiment of the disclosure, a distance of the plurality of second gaps from a center of the plurality of subpixel openings is greater than 33 micrometers.

[0020] For example, in the display substrate provided by at least one embodiment of the disclosure, an orthographic projection of each of the plurality of second gaps on the base substrate is located between an orthographic projection of a light emission control signal line on the base substrate and an orthographic projection of a reset voltage line closest to the light emission control signal line on the base substrate.

[0021] For example, in the display substrate provided by at least one embodiment of the disclosure, an orthographic projection of each of at least a portion of the plurality of second gaps on the base substrate is located between an orthographic projection of a light emission control signal line for a blue subpixel on the base substrate and an orthographic projection of a reset voltage line for a red subpixel on the base substrate, wherein the red subpixel is arranged in a row adjacent to a row in which the blue subpixel is arranged and is adjacent to the blue subpixel;and / or an orthographic projection of each of at least a portion of the plurality of second gaps on the base substrate is arranged between an orthographic projection of a light emission control signal line for a red subpixel on the base substrate and an orthographic projection of a reset voltage line for the blue subpixel on the base substrate, wherein the blue subpixel is arranged in a row adjacent to a row in which the red subpixel is arranged and is adjacent to the red subpixel;

[0022] For example, in the display substrate provided by at least one embodiment of the disclosure, a width of each of at least a portion of the plurality of second gaps is greater than 4.0 micrometers.

[0023] For example, in the display substrate provided by at least one embodiment of the disclosure, the driver circuit layer comprises a plurality of pixel driver circuits and a first planarization layer arranged on a side of the plurality of pixel driver circuits facing away from the base substrate and comprising a plurality of first through-holes, wherein the plurality of first through-holes respectively expose output terminals of the plurality of pixel driver circuits, wherein the first electrode layer is arranged on a side of the first planarization layer facing away from the base substrate, and the plurality of first electrode patterns are connected to the output terminals of the plurality of pixel driver circuits via the plurality of first through-holes, wherein the display substrate further comprises a spacer layer,which is arranged on a side of the pixel definition layer facing away from the base substrate, and the spacer layer comprises a plurality of spacers; in the direction perpendicular to the base substrate, the plurality of spacers do not overlap with the plurality of first through-holes.

[0024] For example, in the display substrate provided by at least one embodiment of the disclosure, a minimum distance between the plurality of spacers and the plurality of first through-holes is greater than 2.0 micrometers in a direction parallel to the base substrate.

[0025] For example, in the display substrate provided by at least one embodiment of the disclosure, the driver circuit layer comprises: a plurality of pixel driver circuits; a first planarization layer disposed on a side of the plurality of pixel driver circuits remote from the base substrate and comprising a plurality of first through-holes, the plurality of first through-holes respectively exposing output terminals of the plurality of pixel driver circuits; a connection electrode layer disposed on a side of the first planarization layer remote from the base substrate and comprising a plurality of connection electrodes, the plurality of connection electrodes respectively being electrically connected to the output terminals of the plurality of pixel driver circuits via the first through-holes;and a second planarization layer disposed on a side of the connection electrode layer facing away from the base substrate and comprising a plurality of second through-holes, wherein the plurality of second through-holes each expose the plurality of connection electrodes; wherein the first electrode layer is disposed on a side of the second planarization layer facing away from the base substrate, and the plurality of first electrode patterns are electrically connected to the plurality of connection electrodes via the plurality of second through-holes, the display substrate further comprising: a spacer layer disposed on a side of the pixel definition layer facing away from the base substrate and comprising a plurality of spacers, wherein, in the direction perpendicular to the base substrate, the plurality of spacers do not overlap with the plurality of second through-holes;

[0026] For example, in the display substrate provided by at least one embodiment of the disclosure, a minimum distance between the plurality of spacers and the plurality of second through-holes is greater than 2.0 micrometers in a direction parallel to the base substrate.

[0027] For example, in the display substrate provided by at least one embodiment of the disclosure, in the direction perpendicular to the base substrate, a height of each of the plurality of spacers is 1.8 micrometers to 2.4 micrometers.

[0028] For example, in the display substrate provided by at least one embodiment of the disclosure, in a direction perpendicular to the base substrate, the plurality of pixel driver circuits at least partially overlap with the plurality of pixel openings.

[0029] At least one embodiment of the disclosure provides a display device comprising the display substrate provided by any of the above embodiments. SHORT DESCRIPTION OF THE CHARACTERS

[0030] To clarify the technical solution of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. It is obvious that the described drawings relate only to some embodiments of the present disclosure and are therefore not limiting the present disclosure. Fig. 1 is a partial planar schematic diagram of a display substrate provided by at least one embodiment of the present disclosure; Fig. 2 is a partial planar schematic diagram of a first electrode layer of a display substrate provided by at least one embodiment of the disclosure; Fig. 3 is a partial planar schematic diagram of a driver circuit layer of a display substrate provided by at least one embodiment of the disclosure; Fig. 4 is a partial schematic cross-sectional diagram of a subpixel of a display substrate provided by at least one embodiment of the disclosure; Fig. 5 is a partial planar schematic diagram in which a first electrode layer overlaps with a pixel definition layer of the display substrate provided by at least one embodiment of the disclosure; Fig. 6 is a schematic diagram in which a subpixel opening overlaps with a first electrode pattern in a subpixel of the display substrate provided by at least one embodiment of the disclosure; Fig. 7 is a diagram of the planar arrangement of a plurality of spacers of a display substrate provided by at least one embodiment of the disclosure; Fig. 8 is another partial schematic cross-sectional diagram of a subpixel of a display substrate provided by at least one embodiment of the disclosure; Fig. 9 is a circuit diagram of a pixel driver circuit of a display substrate provided by at least one embodiment of the disclosure; Fig. 10-14 are partial planar schematic diagrams in which respective conductive layers are sequentially stacked in a driver circuit layer of a display substrate provided by at least one embodiment of the disclosure; and Fig. 15 is a partial schematic cross-sectional diagram of a display device provided by at least one embodiment of the disclosure. DETAILED DESCRIPTION OF REVELATION

[0031] In order to clarify the objects, technical details, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments are described in a clear and fully understandable manner in conjunction with the drawings relating to the embodiments of the present disclosure. It is obvious that the described embodiments represent only a part, but not all, of the embodiments of the present disclosure. Based on the embodiments described here, one skilled in the art can obtain other embodiments without inventive work, which should fall within the scope of the present disclosure.

[0032] Unless otherwise specified, technical or scientific terms used in this disclosure have a generic meaning as understood by those skilled in the art. In the disclosure, words such as "first," "second," and the like do not denote order, quantity, or importance, but are used to distinguish various components. Words such as "including" or "comprising" and the like mean that elements or items appearing before the words "including" or "comprising" include the elements or items enumerated after the words "including" or "comprising," or their equivalents, and are not exclusive of other elements or items. Words such as "connected" or "connecting," and the like are not limited to physical or mechanical connections, but can also include direct or indirect electrical connection.Words such as "top", "bottom", "left", "right", and the like are used only to express a relative positional relationship; if the absolute position of the described object is changed, the relative positional relationship may also change accordingly.

[0033] In a display device with fingerprint recognition functionality, an image sensor for fingerprint recognition is typically combined with a non-display side of a display substrate of the display device. In this case, the display substrate must have light transmittance gaps. When a finger touches a surface on the display side of the display device, a signal light containing fingerprint information reflected from the finger will pass through the light transmittance gaps to the image sensor, allowing the image sensor to capture the signal light for operations such as fingerprint sensing and recognition.

[0034] In the above display device, the display substrate must have stable light transmittance to ensure that the image sensor can capture the signal light containing fingerprint information for fingerprint sensing and recognition functions. Generally, the display substrate has a plurality of circuit patterns. The circuit patterns are stacked on top of each other, so the display substrate has irregular light transmittance gaps in some places. Light transmittance gaps with a larger size of the irregular light transmission gaps can be used to transmit signal light containing fingerprint information. Due to errors in the preparation process, such as alignment errors of a plurality of functional layers and size errors in the circuit patterns, light transmittance gaps with a smaller size are often unstable, and their size, number, and existence are uncertain.As a result, the overall light transmittance of the display substrate is unstable, which affects the yield in the production of the display substrate.

[0035] At least one embodiment of the disclosure provides a display substrate and a display device. The display substrate has a display side and includes: a base substrate; a driver circuit layer disposed on the base substrate and including a plurality of first gaps, the plurality of first gaps allowing light from the display side to pass therethrough; a first electrode layer disposed on a side of the driver circuit layer facing away from the base substrate and including a plurality of first electrode patterns and a plurality of light-blocking patterns;and a pixel definition layer disposed on a side of the first electrode layer facing away from the base substrate and comprising a plurality of subpixel openings, wherein the plurality of subpixel openings expose the plurality of first electrode patterns, wherein in a direction perpendicular to the base substrate, at least a portion of the plurality of light-blocking patterns does not overlap with the plurality of subpixel openings, wherein the at least a portion of the plurality of light-blocking patterns corresponds to and at least partially overlaps with at least a portion of the plurality of first gaps, such that light from the display side is at least partially blocked.;

[0036] In the above display substrate provided in the embodiment of the disclosure, at least a part of the first gaps is shaded by the light-blocking patterns, which can eliminate the instability of the first gap caused by the process variation to avoid the instability of the overall light transmittance of the display substrate caused by the instability of the first gaps, that is, to improve the stability of the light transmittance of the display substrate; on the other hand, the light-blocking patterns and the first electrode patterns are arranged in the same first electrode layer, so that they can be formed in the manufacturing process by applying the same material and the same patterning process, which can simplify the manufacturing process of the display substrate.

[0037] A display substrate and a display device are particularly described by several specific embodiments as follows.

[0038] At least one embodiment of the disclosure provides a display substrate. Fig. 1 illustrates a partial planar schematic diagram of the display substrate, Fig. Figure 2 illustrates a partial planar schematic diagram of a first electrode layer of the display substrate of Fig. 1, Fig. Figure 3 illustrates a partial planar schematic diagram of a pixel driver circuit of the display substrate of Fig. 1, and Fig. Figure 4 illustrates a partial schematic cross-sectional diagram of a subpixel of the display substrate of Fig. 1.

[0039] As in Fig. 1 to Fig. 4, the display substrate has a display side, ie a top side in Fig. 4, and a non-display page, ie a subpage in Fig. 4, and includes a base substrate 110, a driver circuit layer 120, a first electrode layer 1041 and a pixel definition layer 1017, etc.

[0040] The driver circuit layer 120 is disposed on the base substrate and includes a plurality of first gaps D1. The plurality of first gaps D1 allow light from the display side to pass through them. The first electrode layer is disposed on a side of the driver circuit layer 120 facing away from the base substrate 110 and includes a plurality of first electrode patterns 1041 and a plurality of light-blocking patterns SH. The pixel definition layer 1017 is disposed on a side of the first electrode layer 1041 facing away from the base substrate 110 and includes a plurality of subpixel openings PO. The plurality of subpixel openings PO expose the plurality of first electrode patterns 1041.

[0041] In a direction perpendicular to the base substrate 110, ie in a vertical direction of Fig. 4, at least a part of the plurality of light-blocking patterns SH (e.g., all) does not overlap with the plurality of subpixel openings PO, wherein the at least a part of the plurality of light-blocking patterns SH (e.g., all) corresponds to and at least partially overlaps with at least a part of the plurality of first gaps D1 (e.g., all) to at least partially block light from the display side.

[0042] Thus, in the embodiment of the disclosure, at least a portion of the first gaps D1 is blocked by the light-blocking patterns SH, which can eliminate the instability of the overall light transmittance of the display substrate caused by the size, number, etc. of the first gaps D1, that is, improve the stability of the light transmittance of the display substrate. On the other hand, the light-blocking patterns and the first electrode patterns are arranged in the same first electrode layer, so they can be formed in the manufacturing process by using the same material and the same patterning process, which can simplify the manufacturing process of the display substrate.

[0043] For example, in some embodiments, the width of the plurality of first gaps is less than or equal to 4.0 micrometers, for example, less than or equal to 3.0 micrometers, less than or equal to 2.0 micrometers, less than or equal to 1.5 micrometers, or less than or equal to 1.0 micrometer. The width of the first gap D1 refers to a size of the first gap D1 perpendicular to its extension direction. For example, if the first gap D1 has the shape of a rectangle (or approximately the shape of a rectangle), its width corresponds to the short side length of the rectangle. If the first gap D1 has an irregular shape, a direction of the longest span of the irregular shape is the extension direction, and a size perpendicular to the extension direction is the width of the first gap D1.

[0044] Since the first gap D1 with a smaller width is more likely to be subject to large process fluctuations during the manufacturing process, such as large size deviations, the first gap D1 with a smaller width is more likely to cause a large deviation in the overall light transmittance of the display substrate. By using the light-blocking pattern SH to shade the first gap D1 with a smaller width, the stability of the overall light transmittance of the display substrate can be greatly improved.

[0045] For example, in some embodiments, a distance W1 from the plurality of first gaps D1 to a center of the plurality of subpixel openings PO is less than 33 micrometers. With reference to Fig. 1, for example, the distance W1 from the edge of the plurality of first gaps D1 facing away from the plurality of subpixel openings PO to a center of the plurality of subpixel openings PO is less than 33 micrometers. This means that the plurality of first gaps D1 are distributed within a range of 33 micrometers from the center of the plurality of subpixel openings PO.

[0046] For example, in some embodiments, at least a part of the plurality of light-blocking patterns SH is integrally connected to the plurality of first electrode patterns 1041. In this case, as shown in the Fig. 1 and Fig. 2, the first electrode pattern 1041 and the light-blocking pattern SH, which are integrally connected, have an irregular shape as a whole.

[0047] For example, in some embodiments, the display substrate includes a plurality of subpixels arranged in an array. Each of the plurality of subpixels includes a light-emitting device EM, and the plurality of first electrode patterns 1041 are respectively used as anodes of the light-emitting devices EM of the plurality of subpixels. As shown in Fig. 4, the light-emitting device EM further comprises a light-emitting material layer 1042 arranged on a side of the first electrode pattern 1041 facing away from the base substrate 110, and a second electrode layer 1043 arranged on a side of the light-emitting material layer 1042 facing away from the base substrate 110.

[0048] In some embodiments, as in Fig. 2, the first electrode pattern 1041 includes, for example, a main part M and a connecting part CL, and the connecting part CL extends from the main part M. The main part M is used to drive the light-emitting device. For example, the light-emitting material layer 1042 directly contacts at least a part of the main part M to be driven by the main part M. The connecting part CL serves to electrically connect the main part M to the pixel driving circuit. The connecting part CL does not directly contact the part of the light-emitting material layer 1042 that emits light.

[0049] For example, in Fig. 2, a planar shape of the main part M of each of the plurality of first electrode patterns 1041 is a polygon (such as hexagon, pentagon, quadrilateral, etc.) or a shape with arc edges (such as circle, oval, mango, etc.), a planar shape of each of the plurality of light-blocking patterns SH is a polygon such as triangle or quadrilateral (such as rectangle, parallelogram, rhombus, etc.), and the like.

[0050] For example, in some embodiments, the plurality of subpixels include a red subpixel R, a green subpixel G, and a blue subpixel B. As shown in Fig. 1 and Fig. As shown in Figure 2, a planar shape of the main part M of the first electrode pattern 1041 of the red sub-pixel light-emitting device R is a hexagon (hereinafter referred to as the first hexagon), and a shape of the light-blocking patterns RSH integrally bonded to the first electrode pattern 1041 of the red sub-pixel light-emitting device R is a triangle. For example, the number of light-blocking patterns RSH integrally bonded to the first electrode pattern 1041 of the red sub-pixel light-emitting device R is two, and the two light-blocking patterns are arranged symmetrically.

[0051] For example, in some embodiments, as in Fig. 1 and Fig. As shown in Figure 2, a planar shape of the main part M of the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is a hexagon (hereinafter referred to as the second hexagon). The shape of the second hexagon is, for example, similar to that of the first hexagon, and the size of the second hexagon is larger than that of the first hexagon. For example, the light-blocking pattern BSH integrally bonded to the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is triangular or rectangular. For example, the number of light-blocking patterns BSH integrally bonded to the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B is three, and the three light-blocking patterns BSH are integrally bonded to three edges of the first electrode pattern 1041 of the light-emitting device of the blue sub-pixel B.

[0052] As in Fig. 1 and Fig. As shown in Figure 2, the three light-blocking patterns BSH include, for example, two triangular light-blocking patterns and one rectangular pattern. The two triangular light-blocking patterns are distributed symmetrically, and the rectangular pattern is connected to a left side of the first electrode pattern 1041 and a left side of the triangle.

[0053] For example, in some embodiments, as shown in the Fig. 1 and Fig. 2, a planar shape of the main part M of the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is a pentagon, and a shape of the light-blocking pattern GSH integrally bonded to the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is rectangular. For example, the number of the light-blocking pattern GSH integrally bonded to the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G is one or two, and the one or two light-blocking patterns GSH are integrally bonded to one edge and two edges, respectively, of the first electrode pattern 1041 of the light-emitting device of the green sub-pixel G.

[0054] For example, in some embodiments, one red subpixel R, two green subpixels G, and one blue subpixel B form a pixel unit, and a plurality of pixel units are arranged in an array on the base substrate 110. For example, as shown in the Fig. 1 and Fig. 2, the first electrode pattern 1041 of the light-emitting device of one of the two green subpixels G is connected to a rectangular light-blocking pattern GSH, and the first electrode pattern 1041 of the light-emitting device of the other of the two green subpixels G is connected to two rectangular light-blocking patterns GSH.

[0055] For example, the light-emitting devices of the red subpixels R and the blue subpixels B are arranged in the same rows, the light-emitting devices of the green subpixels are located in substantially the same rows, and the rows in which the light-emitting devices of the red subpixels and the blue subpixels are located and the rows in which the light-emitting devices of the green subpixels are located are arranged alternately.

[0056] For example, in the embodiment of the disclosure, the light-emitting devices of the green subpixels G are arranged substantially in the same row, which is evident from reference to Fig. 5 refers to at least parts of the light-emitting devices of any two adjacent green subpixels G being arranged on a same straight line, and the light-emitting devices of the two adjacent green subpixels G may be offset relative to a direction of the array. That is, a line connecting the centers of the light-emitting devices of any two adjacent green subpixels G may be a folded line Z.

[0057] Fig. For example, Fig. 5 shows a planar schematic diagram in which the first electrode and the pixel definition layer are stacked, and Fig. Figure 6 shows a planar schematic diagram in which the main part of the blue subpixel and the subpixel aperture are stacked. In some embodiments, as shown in the Fig. 5 and Fig. 6, in a subpixel opening PO and a first electrode pattern 1041 corresponding to each other, a shape of the subpixel opening PO is the same as that of the main part M of the first electrode pattern 1041. A first orthographic projection of the subpixel opening PO on the base substrate 110 is located within a second orthographic projection of the main part M of the first electrode pattern 1041 on the base substrate 110, and a minimum distance L1 between an edge of the first orthographic projection and an edge of the second orthographic projection is 1.5 micrometers to 3.5 micrometers, for example, 2.0 micrometers, 2.5 micrometers, or 3.0 micrometers. Therefore, the subpixel opening PO completely exposes the first electrode pattern 1041, and an area defined by the subpixel opening PO is an effective light-emitting area of ​​the light-emitting device EM.The light-emitting material layer 1042 is in direct contact with the main part M of the first electrode pattern 1041 in this area, so that it is controlled.

[0058] For example, in some embodiments, as in Fig. As shown in Figure 5, the first electrode pattern 1041 of the green subpixel G of each of the pixel units may further include a light-blocking transistor pattern TSH. The light-blocking transistor pattern TSH is used to shade a thin-film transistor (such as a thin-film transistor T2) disposed thereunder to prevent light from irradiating the thin-film transistor and thereby impairing the switching performance of the thin-film transistor.

[0059] In some embodiments, as in the Fig. 1 and Fig. 3, the driving circuit layer 120 includes, for example, a plurality of second gaps D2. The plurality of second gaps D2 allow light from the display side to pass through them. In the direction perpendicular to the base substrate 110, the plurality of second gaps D2 do not overlap with the plurality of first electrode patterns 1041 and the plurality of light-blocking patterns SH. Thus, the second gaps D2 can transmit light from the display side to the non-display side of the display substrate. For example, when an image sensor S is disposed on the non-display side of the display substrate, the second gap D2 can transmit the signal light containing finger information to the image sensor S.

[0060] For example, in some embodiments, a width of at least some second gaps D2 of the plurality of second gaps D2 is greater than 1.0 micrometer, or greater than 1.5 micrometers, or greater than 2.0 micrometers, or greater than 3.0 micrometers, or greater than 4.0 micrometers. The width of the second gap D2 refers to a size of the second gap D2 perpendicular to an extending direction of the second gap D2. Thus, the size of the second gap D2 is larger, whereby the light transmission function can be fully realized. In addition, since the size of the second gap D2 is larger, no large deviation occurs during manufacturing. Even if a small deviation occurs, it has little impact on the overall transmission stability of the display substrate.

[0061] For example, in some embodiments, a distance W2 from the plurality of second gaps D2 to a center of the plurality of subpixel openings PO is greater than 33 micrometers. For example, based on Fig. 1, a distance W2 from an edge of the plurality of second gaps D2 facing away from the subpixel opening D2 to a center of the subpixel opening PO is greater than 33 micrometers.

[0062] In some embodiments, as in Fig. 1, for example, an orthographic projection of each of the plurality of second gaps D2 on the base substrate 110 is located between an orthographic projection of a light emission control signal line EM on the base substrate 110 and an orthographic projection of a reset voltage line VINT, which is closest to the light emission control signal line EM, on the base substrate 110. The connection relationship between the light emission control signal line EM and the reset voltage line VINT and their use will be described in detail later.

[0063] As in Fig. 1, for example, an orthographic projection of each of the plurality of second gaps D2 (e.g., the second gap D2 on the right side of Fig. 1) on the base substrate 110 between an orthographic projection of a light emission control signal line EM for the blue subpixel B on the base substrate 110 and an orthographic projection of a reset voltage line VINT for the red subpixel R on the base substrate 110. The red subpixel R is located in a row next to the row in which the blue subpixel B is located and is adjacent to the blue subpixel B.

[0064] For example, in Fig. 1, an orthographic projection of each of the plurality of second gaps D2 (for example, the second gap on the left side of Fig. 1) on the base substrate 110 between an orthographic projection of a light emission control signal line EM for the red subpixel R on the base substrate 110 and an orthographic projection of a reset voltage line VINT for the blue subpixel B on the base substrate 110. The above blue subpixel B is located in a row next to the row in which the red subpixel R is located and is adjacent to the red subpixel R.

[0065] That is, in the embodiment of the disclosure, the plurality of second gaps D2 are located in gaps between the pixel driving circuits of the blue subpixel B and the red subpixel R.

[0066] In some embodiments, as in Fig. 4, the driver circuit layer 120 includes, for example, a plurality of pixel driver circuits and a first planarization layer 1016. The pixel driver circuit includes a plurality of thin-film transistors and at least one storage capacitor. It may, for example, have the structures 2T1C (i.e., two thin-film transistors and one storage capacitor), 7T1C (i.e., seven thin-film transistors and one storage capacitor), or 8T2C (i.e., eight thin-film transistors and one storage capacitor), etc. The specific structure of the pixel driver circuit is not limited in the embodiments of the disclosure.

[0067] In Fig. For example, in Figure 4, a thin-film transistor T and a storage capacitor C are shown, which are electrically connected to the light-emitting device EM. As in Fig. 4, the thin-film transistor T comprises an active layer 1021, a gate electrode 1022, a first source-drain electrode 1023, and a second source-drain electrode 1024. The storage capacitor C comprises a first capacitor electrode 1031 and a second capacitor electrode 1032. The first capacitor electrode 1031 is arranged in the same layer as the gate electrode 1022.

[0068] It should be noted that in the embodiment of the disclosure, "arranged in the same layer" means that in the hierarchical structure of the display substrate, two functional layers or two structural layers are formed in the same layer and from the same material. That is, during manufacturing, the two functional layers or structural layers can be formed from the same material layer, and the required patterns and structures can be formed through the same patterning process.

[0069] For example, in Fig. 4, the first planarization layer 1016 is disposed on a side of the plurality of pixel driver circuits remote from the base substrate 1011 and includes a plurality of first through-holes VH1. The plurality of first through-holes VH1 respectively expose output terminals of the plurality of pixel driver circuits, e.g., the first source-drain electrode 1023. The first electrode layer is disposed on a side of the first planarization layer 1016 remote from the base substrate 110, and the plurality of first electrode patterns 1041 are each connected to the output terminals of the plurality of pixel driver circuits via the plurality of first through-holes VH1. Thus, the pixel driver circuit can control the voltage applied to the first electrode pattern 1041 through the thin-film transistor T.

[0070] As in Fig. 4, the display substrate further comprises, for example, a spacer layer 1018 arranged on a side of the pixel definition layer 1017 facing away from the base substrate 110. The spacer layer 1018 comprises a plurality of spacers PS. In the direction perpendicular to the base substrate 110, ie, in a vertical direction in Fig. 4, the height of each of the plurality of spacers PS is, for example, 1.8 micrometers to 2.4 micrometers, such as 2.0 micrometers or 2.2 micrometers. Thus, the spacer PS can have a sufficient height so that during the manufacturing process of the display substrate, e.g., when the light-emitting material layer 1042 is formed by evaporation, etc., the adopted mask plate can be fully supported on the plurality of spacers PS without causing defects such as scratches in the structure of the display substrate due to deformation of the mask plate, etc.

[0071] For example, in some embodiments, in the direction perpendicular to the base substrate 110, the plurality of spacers PS do not overlap with the plurality of first through-holes VH1. Since the first through-hole VH1 is formed by hollowing out a portion of the material of the first planarization layer 1016, the material above the first through-hole VH1 is likely to sink. Forming the spacer PS above the first through-hole VH1 will result in sinking of the spacer PS and thus a reduction in the height of the spacer PS relative to the base substrate 110, thereby impairing the supporting function of the spacer PS. The plurality of spacers PS do not overlap with the plurality of first through-holes VH1, so that the plurality of spacers PS can effectively realize the supporting function.

[0072] Fig. For example, Figure 7 shows a schematic diagram of a planar arrangement of a plurality of spacers PS. As in Fig. 7, in some embodiments, a minimum distance between the plurality of spacers PS and the plurality of first through-holes VH1 is greater than 2.0 micrometers in a direction parallel to the base substrate 110. Since a sidewall of the first through-hole VH1 is typically an inclined sidewall, the material formed above the first through-hole VH1 is likely to also condense around the first through-hole VH1. Therefore, by arranging the spacer PS at a certain distance from the first through-hole VH1, the interference of the spacer PS that may be caused by the first through-hole VH1 can be completely avoided, so that the spacer PS has a sufficient height to fully realize the support function.

[0073] In other embodiments, Fig. 8, for example, shows another partially schematic cross-sectional diagram of a subpixel on the display substrate. As in Fig. 8, the driver circuit layer includes a plurality of pixel driver circuits, a first planarization layer 1016, an interconnection electrode layer, and a second planarization layer 1019. The specific structure of the pixel driver circuit can be found in the above embodiments, which are omitted here.

[0074] As in Fig. 8, the first planarization layer 1016 is disposed on a side of the plurality of pixel driver circuits facing away from the base substrate 110 and includes a plurality of first through-holes VH1. The plurality of first through-holes VH1 expose the output terminals of the plurality of pixel driver circuits, for example, the first source-drain electrode 1023. The connection electrode layer is disposed on a side of the first planarization layer 1016 facing away from the base substrate 110 and includes a plurality of connection electrodes CEL. The plurality of connection electrodes CEL are each connected to the output terminals of the plurality of pixel driver circuits via the first through-holes VH1. The second planarization layer 1019 is disposed on a side of the connection electrode layer facing away from the base substrate 110 and includes a plurality of second through-holes VH2.The plurality of second through-holes VH2 expose the plurality of connection electrodes CEL. The first electrode layer is disposed on a side of the second planarization layer 1019 facing away from the base substrate 110, and the plurality of first electrode patterns 1041 are each electrically connected to the plurality of connection electrodes CEL via the plurality of second through-holes VH2.

[0075] As in Fig. 8, the display substrate further comprises a spacer layer 1018 arranged on a side of the pixel definition layer 1017 facing away from the base substrate 110, and the spacer layer 1018 comprises a plurality of spacers PS. For example, in the direction perpendicular to the base substrate 110, ie, in a vertical direction in Fig. 4, a height of each of the plurality of spacers PS is from 1.8 micrometers to 2.4 micrometers, such as 2.0 micrometers or 2.2 micrometers. In the direction perpendicular to the base substrate 110, the plurality of spacers PS do not overlap, for example, with the plurality of second through-holes VH2. Fig. 7, for example, a minimum distance L2 between the plurality of spacers PS and the plurality of second through-holes VH2 is greater than 2.0 micrometers in a direction parallel to the base substrate 110. Thus, interference with the spacer PS caused by the second through-hole VH2 can be completely avoided, so that the spacer PS has a sufficient height to fully realize the support function.

[0076] For example, in the embodiment of the disclosure, a plurality of pixel driver circuits at least partially overlap with the plurality of subpixel openings PO in the direction perpendicular to the base substrate 110. In this case, the light-emitting devices formed in the subpixel openings PO may be top-emission light-emitting devices.

[0077] For example, the display substrate, as shown in Fig. 4 and Fig. 8, further comprise a barrier layer 1012 and a buffer layer 1013 disposed on the base substrate 110. The barrier layer 1012 and the buffer layer 1013 can prevent impurities in the base substrate 110 from penetrating a plurality of functional layers of the display substrate 110, thereby providing a protective function. The barrier layer 1012 and the buffer layer 1013 can be formed, for example, from one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0078] As in Fig. 4 and Fig. For example, as shown in Figure 8, the display substrate may further include a first gate insulating layer 1014A disposed on a side of the active layer 1021 remote from the base substrate 110, a second gate insulating layer 1014B disposed on a side of the gate electrode 1022 and the first capacitor electrode 1031 remote from the base substrate 110, and an interlayer insulating layer 1015 disposed on a side of the second capacitor electrode 1032 remote from the base substrate 110. For example, the first gate insulating layer 1014A, the second gate insulating layer 1014B, and the interlayer insulating layer 1015 may be formed from one or more inorganic insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0079] For example, the display substrate may be Fig. 4 and Fig. 8, further comprise an encapsulation layer EN arranged on a side of the light-emitting device EM facing away from the base substrate 110, and the encapsulation layer EN may be a composite encapsulation layer comprising a first inorganic encapsulation layer 1051, a first organic encapsulation layer 1052, and a second inorganic encapsulation layer 1053. The first inorganic encapsulation layer 1051 and the second inorganic encapsulation layer 1053 may be formed from one or more inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, etc. The first organic encapsulation layer 1052 may be formed from one or more organic insulating materials such as resin and polyimide, etc.

[0080] For example, in one embodiment, the pixel driver circuit of the subpixel has a 7T1C structure. Fig. Figure 9 shows a circuit diagram of the pixel driver circuit of the 7T1C structure. As shown in Fig. As shown in Figure 9, the pixel driver circuit of the 7T1C structure includes seven thin-film transistors T1-T7 and a storage capacitor C1, and has a connection relationship as shown in the figure. The pixel driver circuit has, for example, the following four stages of the drive process. In the following description, the seven thin-film transistors T1-T7 are all P-type transistors, meaning that the gate electrode of each of the transistors is turned on when inputted with a low level and turned off when inputted with a high level.

[0081] In an initialization stage 1, a first reset signal RST1 is input to turn on the fourth transistor T4, and a reset voltage VINT is applied to a control terminal (such as the gate electrode) of the driver transistor T1; a first light emission control signal EM1 is input to turn on the fifth transistor T5, and a first voltage VDD is applied to a second node N2.

[0082] For example, in initialization stage 1, the fourth transistor T4 is turned on by a low level of a first reset signal RST1, and the fifth transistor T5 is turned on by a low level of the first light emission control signal EM1. At the same time, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are turned off by corresponding high-level input signals.

[0083] In initialization stage 1, since the fourth transistor T4 is turned on, a reset voltage VINT (a low-level signal, such as ground or other low-level signals) can be applied to the gate electrode of the first transistor T1. At the same time, since the fifth transistor T5 is turned on, the first voltage VDD (high-level signal) can be applied to the source electrode of the first transistor T1, so that in initialization stage 1, the voltage VGS of the gate electrode and the source electrode of the first transistor T1 can satisfy the condition |VGS| > |Vth| (Vth is a threshold voltage of the first transistor T1, e.g., Vth is negative when the first transistor T1 is a P-type transistor), so that the first transistor T1 is in an on state in which VGS is fixedly biased.

[0084] In a data write and compensation stage 2, a strobe signal GATE and a data signal DATA are input to turn on the second transistor T2, the driver transistor T1, and the third transistor T3. The data signal DATA is written to the driver transistor T1, and the third transistor T3 performs threshold compensation on the driver transistor T1.

[0085] In data write and compensation stage 2, the second transistor T2 and the third transistor T3 are turned on by a low level of the sampling signal GATE. At the same time, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off by corresponding high-level input signals.

[0086] In the data write and compensation stage 2, the data signal DATA charges the first node N1 via the second transistor T2, the first transistor T1, and the third transistor T3 (i.e., charges the storage capacitor C1), that is, a potential of the first node N1 gradually rises. It is easy to understand that because the second transistor T2 is turned on, a potential of the second node N2 is maintained at Vdata, and at the same time, according to the characteristics of the first transistor T1, when the potential of the first node N1 rises to Vdata+Vth, the first transistor T1 is turned off and the charging operation ends. Note that Vdata represents a voltage value of the data signal DATA, and Vth represents a threshold voltage of the first transistor.

[0087] After the data writing and compensation stage 2, the potentials of the first node N1 and the third node N3 are both Vdata+Vth, that is, voltage information including the data signal DATA and the threshold voltage Vth is stored in the storage capacitor C1, which is used to provide grayscale display data in a subsequent light emission stage and to compensate the threshold voltage of the first transistor T1 itself.

[0088] In a reset stage 3, a second light emission control signal EM2 and a second reset signal RST2 are input to turn on the sixth transistor T6 and the seventh transistor T7, so as to reset the first transistor T1, the third transistor T3 and the sixth transistor T6.

[0089] In reset stage 3, the sixth transistor T6 is turned on by a low level of the second light emission control signal EM2, and the seventh transistor T7 is turned on by a low level of the second reset signal RST2. At the same time, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned off by corresponding high-level input signals.

[0090] In the reset stage 3, the drain electrode of the first transistor T1 is discharged via the sixth transistor T6 and the seventh transistor T7 because the reset voltage VINT is a low-level signal (e.g., ground or other low-level signals), thereby resetting the potentials of the third node N3 and the fourth node N4 simultaneously.

[0091] In reset stage 3, the drain electrode of the first transistor T1 is reset so that it can be maintained at a fixed potential, and the display effect of the pixel circuit display device is not affected by the uncertainty of the drain electrode potential. At the same time, the fourth node N4 is also reset, i.e., the OLED is reset, so that the OLED can be displayed in a black state before light emission stage 4, and the display effect, such as contrast, of the pixel circuit display device is improved.

[0092] In the light emission stage 4, the first light emission control signal EM1 and the second light emission control signal EM2 are input to turn on the thin film transistor T5, the thin film transistor T6 and the driving thin film transistor T1, and the thin film transistor T6 applies a driving current to the light emission element 600 to emit light.

[0093] In the light-emitting stage 4, the fifth transistor T5 is turned on by a low level of the first light-emitting control signal EM1, the sixth transistor T6 is turned on by a low level of the second light-emitting control signal EM2, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are turned off by corresponding high input levels. At the same time, the potential of the first node N1 is Vdata+Vth, and the potential of the second node N2 is VDD, so the first transistor T1 is also kept on.

[0094] As in Fig. 8, in the light emission stage 4, the first electrode pattern (e.g., anode) and the second electrode layer (e.g., cathode) of the light-emitting device D1 are supplied with the first voltage VDD (high voltage) and the second voltage VSS (low voltage), respectively, whereby light is emitted under the action of the drive current flowing through the first transistor T1.

[0095] Fig. For example, FIGS. 10-14 show partial planar schematic diagrams of the respective conductive layers of the driver circuit layer stacked one after another. Insulating layers (e.g., the gate insulating layer and the interlayer insulating layer) are disposed between adjacent conductive layers. The insulating layers have a plurality of through-holes for electrical connection. In the following embodiments, the respective conductive layers are described with emphasis, and the insulating layers are omitted.

[0096] Fig. For example, Figure 10 shows a planar schematic diagram of a semiconductor layer of the driver circuit layer. The semiconductor layer includes active layers of the respective thin-film transistors T1-T7. For example, the active layers of the thin-film transistors T1-T7 are integrally connected to one another to form a structure. For example, a part of the semiconductor layer that is Fig. 10, outlined with dashed lines, are the active layers of the thin-film transistors T1-T7 of the pixel driver circuit of the subpixel. For example, a first gate insulating layer 1014A is arranged over the semiconductor layer, which is not shown in the figure.

[0097] Fig. For example, Fig. 11 shows a planar schematic diagram in which the first conductive layer of the driver circuit layer is deposited on the semiconductor layer of Fig. 10 stacked. As in Fig. As shown in Figure 11, the first conductive layer includes a gate electrode of each of the transistors, a first capacitor electrode plate 1031 of the storage capacitor, and several scanning lines GATE, light emission control lines EM, and reset control lines RST. For example, the gate electrode of each of the transistors is a part of the scanning line GATE, the light emission control line EM, and the reset control line RST that overlaps with the active layer. For example, each row of subpixels is connected to one scanning line GATE, two reset control lines RST, and one light emission control line EM. The first gate insulating layer 1014B is disposed over the first conductive layer, which is not shown in the figure.

[0098] Fig. For example, Fig. 12 shows a planar schematic diagram in which the second conductive layer of the driver circuit layer is applied to the stacked structure of Fig. 11 is stacked. As in Fig. As shown in Figure 12, the second conductive layer includes a second capacitor electrode plate 1032 of the storage capacitor and a plurality of reset voltage lines VINT. An interlayer insulating layer 1015, not shown in the figure, is disposed over the second conductive layer.

[0099] Fig. For example, Fig. 13 shows a planar schematic diagram in which the third conductive layer of the driver circuit layer is applied to the stacked structure of Fig. 12 stacked. As in Fig. 13, the third conductive layer comprises a first power supply line VDD, part of the data lines Data, source-drain electrodes of the thin-film transistors T1-T7, etc. A planarization layer 1016, which is not shown in the figure, is arranged above the third conductive layer.

[0100] Fig. For example, Fig. 14 shows a planar schematic diagram in which a fourth conductive layer of the driver circuit layer is applied to the stacked structure of Fig. 13 is stacked. As in Fig. As shown in Figure 13, the fourth conductive layer comprises another portion of the data lines Data. In some embodiments, the fourth conductive layer may, for example, comprise a connection electrode CEL. A planarization layer 1019, not shown in the figure, is arranged above the third conductive layer. In this embodiment, the data lines Data are thus distributed across two conductive layers to facilitate the arrangement of the data lines Data.

[0101] Fig. For example, Figure 1 shows a planar schematic diagram in which the first electrode layer is applied to the stacked structure of Fig. 14 is stacked. For details, refer to the description of Fig. 1, which is omitted here.

[0102] In the embodiment of the disclosure, the base substrate 110 may be, for example, a rigid substrate made of glass or quartz, etc., or a flexible substrate made of polyimide, etc. The gate electrode 1022 may be formed of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), etc., or an alloy material, e.g., in the form of a single-layer metal layer structure or a multi-layer metal layer structure such as titanium / aluminum / titanium, etc. The first source-drain electrode 1023 and the first source-drain electrode 1024 may be formed of a metal material such as copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), etc., or an alloy material, for example, to form a single-layer metal layer structure or a multi-layer metal layer structure such as titanium / aluminum / titanium, etc. The material of the first electrode 1031 and the second electrode 1032 consists of a metal such as aluminum, titanium, cobalt, copper, etc.or an alloy material. The active layer 1021 can be formed from a material such as polysilicon and metal oxide, etc.

[0103] For example, the first planarization layer 1016, the second planarization layer 1019, the pixel definition layer 1017, the spacer layer 1018, and the first organic encapsulation layer 1052 of the encapsulation layer EN may be formed of an organic insulating material such as polyimide and resin, etc.

[0104] For example, the display substrate may have other structures in addition to the above-mentioned structures. For details, please refer to the related art, which will be omitted here.

[0105] Furthermore, it should be noted that the material of each of the functional layers in the embodiments of the disclosure is not limited, and the material of each of the functional layers is not limited to the above-mentioned examples. In the embodiment of the disclosure, each of the thin-film transistors may be a P-type thin-film transistor or an N-type thin-film transistor, and the structure may be a bottom-gate type, a top-gate type, or a double-gate type. The structure illustrated in the attached drawings is only an example, and the embodiment of the disclosure does not limit the specific shape of each thin-film transistor. For example, if the thin-film transistor is of the double-gate type, the display substrate in Fig. 4 and Fig. 8 has at least one further conductive layer and one further insulating layer, and a further gate electrode is arranged in the conductive layer. In this case, the two gate electrodes can be arranged on a side of the active layer of the thin-film transistor close to the base substrate or on a side of the active layer of the thin-film transistor facing away from the base substrate.

[0106] At least one embodiment of the disclosure provides a display device, and the display device comprises one of the above-mentioned display substrates. Fig. For example, Figure 15 shows a partial schematic sectional diagram of the display device. As in Fig.As shown in Figure 15, the display device may further comprise an image sensor S disposed on the non-display side of the display substrate and configured to receive the light transmitted from the second gap D2. For example, in some embodiments, the orthographic projection of the image sensor S on the base substrate 110 at least partially overlaps the orthographic projection of the second gap D2 on the base substrate 110.

[0107] The image sensor S can, for example, be several suitable types of image sensors, such as a CCD (Charge Coupled Device) image sensor, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, or a photodiode (such as a PIN photodiode), etc. Depending on the requirements, the image sensor can detect only a specific wavelength of light (e.g., red or green light) or all visible light.

[0108] The display device may be, for example, a mobile phone, a tablet computer, a television, a display, a laptop, a digital photo frame, a navigation device and other products or components with a display function.

[0109] In this context, a few points need to be explained: (1) The drawings of the embodiments of the present disclosure refer only to structures related to the embodiments of the present disclosure, and other structures may refer to the general design. (2) For clarity, in the drawings used to describe embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, ie, these drawings are not drawn to scale. (3) Unless there is a conflict, features in the same embodiment and in different embodiments of the present disclosure may be combined.

[0110] The above embodiments are merely exemplary embodiments of the present disclosure and are not intended to define the scope of the present disclosure, and the scope of the present disclosure is determined by the appended claims.

Claims

[1] A display substrate having a display side, and comprising: a base substrate, a driver circuit layer disposed on the base substrate and including a plurality of first gaps, the plurality of first gaps allowing light from the display side to pass therethrough, a first electrode layer disposed on a side of the driver circuit layer facing away from the base substrate and comprising a plurality of first electrode patterns and a plurality of light-blocking patterns, a pixel definition layer arranged on a side of the first electrode layer facing away from the base substrate and comprising a plurality of subpixel openings, wherein the plurality of subpixel openings each expose the plurality of first electrode patterns, wherein, in a direction perpendicular to the base substrate, at least a portion of the plurality of light-blocking patterns does not overlap with the plurality of subpixel openings, wherein the at least a portion of the plurality of light-blocking patterns each corresponds to and at least partially overlaps at least a portion of the plurality of first gaps to at least partially block light from the display side. [2] The display substrate of claim 1, wherein the width of the plurality of first gaps is less than or equal to 4.0 micrometers. [3] The display substrate of claim 1 or 2, wherein the distance of the plurality of first gaps from a center of the plurality of subpixel openings is less than 33 micrometers. [4] The display substrate according to any one of claims 1 to 3, wherein at least a part of the plurality of light-blocking patterns is integrally bonded to the plurality of first electrode patterns. [5] The display substrate according to any one of claims 1 to 4, wherein each of the plurality of first electrode patterns includes a main part and a connecting part, and a planar shape of the main part is a polygon or a shape having an arc edge, and a planar shape of the plurality of light-blocking patterns is a polygon. [6] The display substrate according to any one of claims 1 to 5, wherein the display substrate comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a light-emitting device, and the plurality of first electrode patterns are respectively used as anodes of the light-emitting devices of the plurality of sub-pixels. [7] The display substrate according to claim 6, wherein the plurality of subpixels include red subpixels, green subpixels, and blue subpixels, wherein a planar shape of the main part of the first electrode pattern of the light-emitting device of each of the red subpixels is a hexagon, and a shape of the light-blocking pattern integrally connected to the first electrode pattern of the light-emitting device of each of the red subpixels is a triangle. [8] The display substrate according to claim 7, wherein a number of light-blocking patterns integrally bonded to the first electrode pattern of the light-emitting device of each of the red sub-pixels is two, and the two light-blocking patterns integrally bonded to the first electrode pattern of the light-emitting device of each of the red sub-pixels are arranged symmetrically. [9] The display substrate according to claim 7 or 8, wherein a planar shape of the main part of the first electrode pattern of the light-emitting device of each of the blue sub-pixels is a hexagon, and a shape of the light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the blue sub-pixels is a triangle or a rectangle. [10] The display substrate according to claim 9, wherein a number of light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the blue sub-pixels is three, and the three light-blocking patterns integrally connected to the first electrode pattern of the light-emitting device of each of the blue sub-pixels are integrally connected to three edges of the first electrode pattern of the light-emitting device of each of the blue sub-pixels. [11] The display substrate according to any one of claims 7 to 10, wherein a planar shape of the main part of the first electrode pattern of the light-emitting device of each of the green sub-pixels is a pentagon, and a shape of the light-blocking patterns integrally bonded to the first electrode pattern of the light-emitting device of each of the green sub-pixels is rectangular. [12] The display substrate according to claim 11, wherein a number of light-blocking patterns integrally bonded to the first electrode pattern of the light-emitting device of each of the green sub-pixels is one or two, and the one or two light-blocking patterns integrally bonded to the first electrode pattern of the light-emitting device of each of the green sub-pixels are integrally bonded to one edge or two edges, respectively, of the first electrode pattern of the light-emitting device of each of the green sub-pixels. [13] The display substrate according to any one of claims 1 to 12, wherein for the subpixel opening and the first electrode pattern corresponding to each other, a shape of the subpixel opening is the same as a shape of the main part of the first electrode pattern, a first orthographic projection of the subpixel opening on the base substrate is within a second orthographic projection of the main part of the first electrode pattern on the base substrate, and a minimum distance between an edge of the first orthographic projection and an edge of the second orthographic projection is from 1.5 micrometers to 3.5 micrometers. [14] The display substrate according to any one of claims 7 to 13, wherein the light-emitting devices of the red sub-pixels and the blue sub-pixels are arranged in the same rows, the light-emitting devices of the green sub-pixels are arranged in substantially the same rows, and the rows in which the light-emitting devices of the red sub-pixels and the blue sub-pixels are arranged and the rows in which the light-emitting devices of the green sub-pixels are arranged are arranged alternately. [15] The display substrate according to any one of claims 1 to 14, wherein the driving circuit layer further comprises a plurality of second gaps, the plurality of second gaps allowing light from the display side to pass therethrough, in the direction perpendicular to the base substrate, the plurality of second gaps do not overlap with the plurality of first electrode patterns and the plurality of light-blocking patterns. [16] The display substrate of claim 15, wherein a distance of the plurality of second gaps from a center of the plurality of subpixel openings is greater than 33 micrometers. [17] The display substrate according to claim 15 or 16, wherein an orthographic projection of each of the plurality of second gaps on the base substrate is arranged between an orthographic projection of a light emission control signal line on the base substrate and an orthographic projection of a reset voltage line closest to the light emission control signal line on the base substrate. [18] The display substrate according to claim 17, wherein an orthographic projection of each of at least a portion of the plurality of second gaps on the base substrate is disposed between an orthographic projection of a light emission control signal line for a blue sub-pixel on the base substrate and an orthographic projection of a reset voltage line for a red sub-pixel on the base substrate, the red sub-pixel being disposed in a row adjacent to a row in which the blue sub-pixel is disposed and adjacent to the blue sub-pixel;and / or an orthographic projection of each of at least a portion of the plurality of second gaps on the base substrate is arranged between an orthographic projection of a light emission control signal line for a red subpixel on the base substrate and an orthographic projection of a reset voltage line for the blue subpixel on the base substrate, wherein the blue subpixel is arranged in a row adjacent to a row in which the red subpixel is arranged and is adjacent to the red subpixel; [19] The display substrate of any one of claims 15 to 18, wherein the width of each of at least a portion of the plurality of second gaps is greater than 4.0 micrometers. [20] A display substrate according to any one of claims 1 to 19, wherein the driver circuit layer comprises: a variety of pixel driver circuits, and a first planarization layer arranged on a side of the plurality of pixel driver circuits facing away from the base substrate and comprising a plurality of first through-holes, the plurality of first through-holes each exposing output terminals of the plurality of pixel driver circuits, wherein the first electrode layer is arranged on a side of the first planarization layer facing away from the base substrate, and the plurality of first electrode patterns are connected to the output terminals of the plurality of pixel driver circuits via the plurality of first through holes, respectively, the display substrate further comprises a spacer layer disposed on a side of the pixel definition layer facing away from the base substrate, and the spacer layer comprises a plurality of spacers; in the direction perpendicular to the base substrate, the plurality of spacers do not overlap with the plurality of first through-holes. [21] The display substrate of claim 20, wherein, in a direction parallel to the base substrate, a minimum distance between the plurality of spacers and the plurality of first through-holes is greater than 2.0 micrometers. [22] A display substrate according to any one of claims 1 to 19, wherein the driving circuit layer comprises: a variety of pixel driver circuits, a first planarization layer arranged on a side of the plurality of pixel driver circuits facing away from the base substrate and comprising a plurality of first through-holes, the plurality of first through-holes each exposing output terminals of the plurality of pixel driver circuits, a connection electrode layer arranged on a side of the first planarization layer facing away from the base substrate and comprising a plurality of connection electrodes, wherein the plurality of connection electrodes are electrically connected to the output terminals of the plurality of pixel driver circuits via the first through holes, respectively, and a second planarization layer disposed on a side of the connecting electrode layer facing away from the base substrate and comprising a plurality of second through-holes, the plurality of second through-holes exposing the plurality of connecting electrodes, respectively; wherein the first electrode layer is arranged on a side of the second planarization layer facing away from the base substrate, and the plurality of first electrode patterns are each electrically connected to the plurality of connection electrodes, the display substrate further comprises a spacer layer arranged on a side of the pixel definition layer facing away from the base substrate, and the spacer layer comprises a plurality of spacers, in the direction perpendicular to the base substrate, the plurality of spacers do not overlap with the plurality of second through-holes. [23] The display substrate of claim 22, wherein, in a direction parallel to the base substrate, a minimum distance between the plurality of spacers and the plurality of second through-holes is greater than 2.0 micrometers. [24] A display substrate according to any one of claims 20 to 23, wherein in the direction perpendicular to the base substrate, the height of each of the plurality of spacers is between 1.8 micrometers and 2.4 micrometers. [25] A display substrate according to any one of claims 22 to 24, wherein in a direction perpendicular to the base substrate, the plurality of pixel driver circuits at least partially overlap with the plurality of pixel openings. [26] A display device comprising the display substrate according to any one of claims 1 to 25.

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