semiconductor chip

Abstract

A semiconductor chip (1) comprises a plurality of transistor cells (100) arranged side by side along a first direction (Y). The transistor cells comprise a first semiconductor region (17) extending along a second direction (X) orthogonal to the first direction and having a first conductivity type. The second semiconductor region is arranged such that the mutual inductance generated between the first semiconductor region of one transistor cell and the first semiconductor region of another transistor cell has a negative value, with the two transistor cells being adjacent to each other.

Description

TECHNICAL AREA

[0001] The present invention relates to semiconductor chips. STATE OF THE ART

[0002] The present application claims priority over Japanese patent application No. 2022-082047 dated May 19, 2022, which is included herein in its entirety by reference.

[0003] Semiconductor chips are known that contain a large number of transistor cells arranged in parallel (see, for example, patent literature 1). REFERENCE LIST PATENT LITERATURE

[0004] Patent literature 1: Published Japanese patent application no. 2012-23291 SUMMARY OF THE INVENTION

[0005] A semiconductor chip of the present invention comprises a plurality of transistor cells arranged side by side along a first direction. Each transistor cell comprises a first semiconductor region extending along a second direction orthogonal to the first direction and having a first conductivity type. The first semiconductor region is arranged such that any mutual inductance generated between the first semiconductor region of one transistor cell and the first semiconductor region of another transistor cell has a negative value, with the two transistor cells being adjacent to each other. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a circuit diagram of a semiconductor chip according to one embodiment. Fig. Figure 2 is a perspective cross-sectional view of the semiconductor chip according to the embodiment. Fig. Figure 3 is a view showing configurations of a field attenuation region and a connection region in the semiconductor chip according to the embodiment. Fig. Figure 4 is a view showing configurations of a contact area and the connection area in the semiconductor chip according to the embodiment. Fig. Figure 5 is a cross-sectional view of the semiconductor chip according to the embodiment (Part 1). Fig. Figure 6 is a cross-sectional view of the semiconductor chip according to the embodiment (Part 2). Fig. Figure 7 is a cross-sectional view of the semiconductor chip according to the embodiment (part 3). DETAILED DESCRIPTION OF THE INVENTION [Problem statement of the invention]

[0006] In existing semiconductor chips, a current of the same direction flows through p +-body layers of adjacent transistor cells. Therefore, the internal inductance of the p + -body layers due to the difference between the adjacent p + -Body layers increase mutual inductance.

[0007] It is an object of the present invention to provide a semiconductor chip in which the internal inductance can be reduced. [Effects of the invention]

[0008] According to the present invention, the internal inductance can be reduced.

[0009] The following describes embodiments of the present invention. [Description of embodiments of the present invention]

[0010] The following section lists and describes embodiments of the present invention. In the subsequent description, identical or corresponding elements are indicated by the same symbols, and a repeated description of these elements is omitted. [1] A semiconductor chip according to one aspect of the present invention comprises: a plurality of transistor cells arranged side by side along a first direction, each transistor cell comprising a first semiconductor region extending along a second direction orthogonal to the first direction and having a first conductivity type, the first semiconductor region being arranged such that a mutual inductance generated between the first semiconductor region of one transistor cell and the first semiconductor region of another transistor cell is negative, the one transistor cell and the other transistor cell being adjacent to each other. In this case, the mutual inductance acts in a direction that reduces the self-inductance of the gate connections. This allows the internal inductance of the first semiconductor regions to be reduced.Therefore, a semiconductor chip with excellent switching properties is obtained. [2] In [1] the first semiconductor region can be arranged such that the directions of currents flowing along the second direction are opposite to each other in the first semiconductor region of one transistor cell and in the first semiconductor region of the other transistor cell. In this case, the mutual inductance is likely to have a negative value. [3] In [1] or [2], the transistor cells may further comprise: a source electrode; and a second semiconductor region electrically connected to the first semiconductor region and the source electrode, and having the first conductivity type, wherein the second semiconductor region may be arranged such that the second semiconductor region of one transistor cell may be located in a different position in the second direction than the second semiconductor region of the other transistor cell. In this case, currents of opposite directions are likely to flow through the adjacent first semiconductor regions. [4] In [3], a plurality of second semiconductor regions, which constitute the second semiconductor region, can be arranged along the second direction, wherein the positions in the second direction at which the second semiconductor regions are arranged in one transistor cell can each be an intermediate position between two second semiconductor regions of the second semiconductor regions of the other transistor cell, wherein the two second semiconductor regions are adjacent to each other in the second direction. In this case, currents are likely to flow in opposite directions through the adjacent first semiconductor regions. [5] In [1] to [4], the first semiconductor regions can each be a field attenuation region. In this case, the internal inductance of the field attenuation region can be reduced. [6] In [1] to [5], the transistor cells can each be a vertical transistor cell. In this case, a reduction of the on-resistance and an increase in the breakdown voltage can be achieved. [Details of embodiments of the present invention]

[0011] The following section describes embodiments of the present invention in detail. However, the present invention is not limited to these embodiments.

[0012] A semiconductor chip 1 according to one embodiment is described.

[0013] Fig. Figure 1 is a circuit diagram of the semiconductor chip 1 according to the embodiment. As shown in Fig. As shown in Figure 1, the semiconductor chip 1 according to the embodiment comprises a plurality of transistor cells 100.

[0014] The transistor cells 100 are electrically connected in parallel. They are electrically connected via a common gate terminal G, a common source terminal S, and a common drain terminal D. In this case, the transistor cells 100 can be mounted on a single semiconductor chip 1. Each transistor cell 100 has a body diode BD between the source terminal S and the drain terminal D. Each transistor cell 100 can have an internal inductance in a semiconductor region between the source terminal S and the drain terminal D. The internal inductance includes the mutual inductance between the semiconductor region of each transistor cell 100 and the semiconductor region of the adjacent transistor cell 100.

[0015] Each semiconductor region is arranged such that the mutual inductance generated between this semiconductor region and the semiconductor region of the adjacent transistor cell 100 has a negative value. In this case, the internal inductance acts in the direction in which the self-inductance is reduced, thus reducing the internal inductance of the semiconductor region. Therefore, a semiconductor chip 1 with excellent switching characteristics can be obtained. Furthermore, the reverse recovery characteristics of the body diode BD are improved, and a step in the drain voltage can be suppressed.

[0016] If, for example, the absolute value of the self-inductance of each semiconductor region is given by L and the absolute value of the mutual inductance between the semiconductor regions is given by M, then the internal inductance of each semiconductor region is equal to LM. Therefore, the internal inductance of each semiconductor region can be reduced.

[0017] If each semiconductor region is arranged such that the mutual inductance generated between that semiconductor region and the semiconductor region of the adjacent transistor cell 100 has a positive value, the internal inductance of each semiconductor region is equal to L+M. This increases the internal inductance of each semiconductor region.

[0018] Each semiconductor region extends in a predetermined direction and is arranged, for example, such that the direction of the current flowing in the predetermined direction between this semiconductor region and the semiconductor region of the adjacent transistor cell 100 is opposite. In this case, the mutual inductance can easily be achieved with a negative value.

[0019] Each semiconductor region can be a field attenuation region 17 as described below. In this case, the internal inductance of the field attenuation region 17 can be reduced.

[0020] The following describes a configuration of a field-effect transistor as an example for the semiconductor chip 1 according to the embodiment.

[0021] Fig. Figure 2 is a perspective cross-sectional view of the semiconductor chip 1 according to the embodiment. Fig. 2 are a gate insulation film 21, a gate connection 22, an interlayer insulation film 23 and a source electrode 30, which are described below, but not shown. Fig. Figure 3 is a cross-sectional view showing the configurations of the field attenuation area 17 and a connection area 18 in the semiconductor chip 1 according to the embodiment. Fig. Figure 3 is a cross-sectional view along the lower end face of the connection area 18 in Fig. 2. Fig. Figure 4 is a cross-sectional view showing the configurations of a contact area 16 and the connection area 18 in the semiconductor chip 1 according to the embodiment. Fig. Figure 4 is a cross-sectional view along the upper end face of the contact area 16 in Fig. 2. As in Fig. 3 and Fig. As shown in Figure 4, the semiconductor chip 1 according to the embodiment contains the transistor cells 100.

[0022] The transistor cells 100 are arranged side by side along a Y-axis direction, with an X-axis direction being a longitudinal direction. The Y-axis direction is an example of the first direction, and the X-axis direction is an example of the second direction. Each transistor cell 100 can, for example, be a vertical transistor cell with a trench-shaped gate configuration. Each transistor cell 100 can also be a vertical transistor cell with a planar gate configuration. If each transistor cell 100 is a vertical transistor cell, a reduction in on-resistance and an increase in breakdown voltage are likely to be achieved.

[0023] Fig. Figures 5 to 7 are cross-sectional views showing the semiconductor chip 1 according to the embodiment. Fig. 5 is a cross-sectional view along line AA of Fig. 3 and Fig. 4. Fig. Figure 6 is a cross-sectional view along line BB of Fig. 3 and Fig. 4. Fig. 7 is a cross-sectional view along line CC of Fig. 3 and Fig. 4.

[0024] As in Fig. As shown in Figures 5 to 7, the semiconductor chip 1 according to the embodiment mainly comprises a silicon carbide substrate 10, the gate insulating film 21, the gate connection 22, the interlayer insulating film 23, the source electrode 30 and a drain electrode 40.

[0025] Silicon carbide substrate 10 is an example of a semiconductor substrate. Using silicon carbide substrate 10 is likely to result in excellent breakdown voltage. Silicon carbide substrate 10 comprises: a silicon carbide single-crystal substrate 11; and a silicon carbide epitaxial layer 12 on the silicon carbide single-crystal substrate 11. Silicon carbide substrate 10 includes a first principal surface 10A and a second principal surface 10B opposite the first principal surface 10A. The silicon carbide epitaxial layer 12 forms the first principal surface 10A, and the silicon carbide single-crystal substrate 11 forms the second principal surface 10B. The silicon carbide single-crystal substrate 11 and the silicon carbide epitaxy layer 12 are, for example, formed from a hexagonal silicon carbide of polytype 4H. The silicon carbide single-crystal substrate 11 comprises an n-type dopant such as nitrogen (N) or similar and exhibits an n-type conductivity.The transistor cells 100 are formed on the silicon carbide substrate 10.

[0026] The silicon carbide epitaxy layer 12 mainly comprises a drift region 13, a body region 14, a source region 15, the contact region 16, the field attenuation region 17 and the connection region 18.

[0027] Drift range 13 contains an n-type dopant such as nitrogen, phosphorus (P), or similar and exhibits an n-type conductivity. Drift range 13 comprises a first range 13A, a second range 13B, and a third range 13C.

[0028] Body area 14 is located on drift area 13. Body area 14 contains a p-type dopant such as aluminum (Al) or similar and exhibits a p-type conductivity.

[0029] Source area 15 is located on body area 14. Source area 15 contains an n-type dopant such as nitrogen, phosphorus, or similar and has an n-type conductivity. Source area 15 is separated from drift area 13 by body area 14. Source area 15 forms the first main surface 10A.

[0030] Contact area 16 contains a p-type dopant such as aluminum or similar and exhibits p-type conductivity. Contact area 16 extends through source area 15 and contacts body area 14. Contact area 16 forms the first main surface 10A. The effective concentration of the p-type dopant in contact area 16 is, for example, 1 × 10⁻⁶. 18 cm -3 or more and 2x10 20 cm -3 or less.

[0031] The first main surface 10A is provided with a gate trench 5, defined by a side surface 3 and a bottom surface 4. The side surface 3 extends through the source area 15 and the body area 14 and reaches the drift area 13. The side surface 3 can, for example, be a surface inclined relative to the second main surface 10B, or a surface perpendicular to the second main surface 10B. The bottom surface 4 adjoins the side surface 3. The bottom surface 4 is located in the drift area 13. The bottom surface 4 is, for example, a flat plane parallel to the second main surface 10B. The gate trench 5 is, for example, provided in the form of an island along the X-axis. In a plan view from a direction perpendicular to the first main surface 10A, the gate trenches 5 are provided at regular intervals along the Y-axis.

[0032] The field attenuation region 17 contains a p-type dopant such as aluminum or similar and has a p-type conductivity. The field attenuation region 17 extends along the X-axis direction. The field attenuation region 17 is located somewhere between the body region 14 and the second principal surface 10B. In a plan view from the direction perpendicular to the first principal surface 10A, the field attenuation region 17 includes a portion that overlaps the gate trench 5. The field attenuation region 17 reduces the concentration of the electric field at the gate insulating film 21, which contacts the bottom surface 4, when a high voltage is applied. In the direction perpendicular to the second principal surface 10B, the upper end surface of the field attenuation region 17 is separated from the bottom surface 4. The upper end surface of the field attenuation region 17 may include the bottom surface 4 of the gate trench 5.A portion of the upper end surface of the field attenuation region 17 faces a portion of the lower end surface of the body region 14. The field attenuation region 17 is electrically connected to the source electrode 30. In this case, the field attenuation region 17 becomes a source potential, thus reducing parasitic capacitance between the gate junction 22 and the drain electrode 40. This increases the switching speed. The effective concentration of the p-type dopant in the field attenuation region 17 is, for example, 5 × 10⁻⁶. 17 cm -3 or more and 5×10 18 cm -3 or less. The field attenuation region 17 is an example of the first semiconductor region.

[0033] The connection area 18 contains a p-type dopant such as aluminum or similar and exhibits p-type conductivity. Connection area 18 extends through the first area 13A and reaches the field attenuation area 17. Connection area 18 electrically connects the body area 14 and the field attenuation area 17. In this case, currents flow as indicated by the arrows. Fig. 6 and Fig. The currents from the source electrode 30 to the field attenuation region 17 are shown in Figure 7, passing through the contact region 16, the body region 14, and the connection region 18 in that order. The connection region 18 contacts the body region 14. The connection region 18 can be in contact with the contact region 16. The connection region 18 can also be in contact with both the body region 14 and the contact region 16. The connection region 18 is located somewhere between the contact region 16 and the field attenuation region 17. The connection region 18 is closer to the second principal surface 10B than the contact region 16. The connection region 18 is closer to the first principal surface 10A than the field attenuation region 17. The connection regions 18 are arranged, for example, at regular intervals along the X-axis.The effective concentration of the p-type dopant in the compound region 18 can be essentially the same as that of the p-type dopant in the field attenuation region 17. For example, the effective concentration of the p-type dopant in the compound region 18 is 5 × 10⁻⁶. 17 cm -3 or more and 5×10 18 cm -3 or less. The interconnection area 18 is an example of the second semiconductor area.

[0034] The connection area 18 is located at a different position in the X-axis direction than the connection area 18 of the adjacent transistor cell 100. In this case, currents likely flow as indicated by the arrows. Fig. 3 currents in opposite directions through the adjacent field weakening areas 17.

[0035] The position in the X-axis direction at which the connection area 18 is arranged can, for example, be an intermediate position between the two connection areas 18 adjacent to each other in the X-axis direction of the neighboring transistor cell 100. In this case, currents probably flow in opposite directions through the adjacent field attenuation areas 17.

[0036] The first area 13A of the drift area 13 is located somewhere between the body area 14 and the field attenuation area 17. The first area 13A is in contact with the body area 14 and the field attenuation area 17. The first area 13A is closer to the first main area 10A than the field attenuation area 17.

[0037] The second region 13B is closer to the second principal area 10B than the first region 13A. The second region 13B adjoins the first region 13A. The second region 13B is in contact with the field attenuation region 17 in a direction parallel to the second principal area 10B. The second region 13B and the field attenuation region 17 can be arranged in the same plane parallel to the second principal area 10B. The effective concentration of the n-type dopant in the second region 13B can be higher than that of the n-type dopant in the first region 13A.

[0038] The third region 13C is closer to the second principal surface 10B than the second region 13B. The third region 13C adjoins the second region 13B. The third region 13C is in contact with the field weakening region 17. The third region 13C is closer to the second principal surface 10B than the field weakening region 17. The third region 13C may be located between the second region 13B and the silicon carbide single-crystal substrate 11. The third region 13C may adjoin the silicon carbide single-crystal substrate 11. The effective concentration of the n-type dopant in the third region 13c may be equal to that of the n-type dopant in the second region 13B.

[0039] The gate insulation film 21 is, for example, an oxide film. The gate insulation film 21 is made of a material containing silicon dioxide and similar components. The gate insulation film 21 is in contact with side surface 3 and bottom surface 4. The gate insulation film 21 is in contact with the first region 13A on bottom surface 4. The gate insulation film 21 is in contact with source region 15, body region 14, and the first region 13A on side surface 3. The gate insulation film 21 can also be in contact with source region 15 on the first main surface 10A.

[0040] The gate connection 22 is provided on the gate insulation film 21. The gate connection 22 is formed, for example, from polysilicon containing conductive impurities. The gate connection 22 is provided in the gate groove 5. Part of the gate connection 22 may be provided on the first main surface 10A.

[0041] The interlayer insulating film 23 covers the gate junction 22. The interlayer insulating film 23 is in contact with the gate junction 22 and the gate insulating film 21. The interlayer insulating film 23 is, for example, an oxide film. The interlayer insulating film 23 is, for example, made of a material containing silicon dioxide. The interlayer insulating film 23 electrically isolates the gate junction 22 and the source electrode 30 from each other. A portion of the interlayer insulating film 23 may be located in the gate groove 5.

[0042] Contact holes 24 are provided in the interlayer insulating film 23 and the gate insulating film 21. The contact holes 24 are spaced at regular intervals along the Y-axis. In a top view from the direction perpendicular to the first main surface 10A, the contact holes 24 are arranged such that the gate groove 5 is located between the contact holes 24 that are adjacent to each other along the Y-axis. The contact holes 24 extend along the X-axis. The source region 15 and the contact region 16 are exposed to the interlayer insulating film 23 and the gate insulating film 21 through the contact holes 24. The contact region 16 need not extend continuously along the X-axis and can also be formed periodically. A boundary metal film can be formed that covers the upper and side surfaces of the interlayer insulating film 23 and the side surface of the gate insulating film 21.

[0043] The source electrode 30 is in contact with the first main surface 10A. The source electrode 30 comprises a contact electrode 31 and a source connection 32.

[0044] The contact electrode 31 is in contact with the source area 15 and the contact area 16 on the first main surface 10A. The contact electrode 31 is, for example, made of a material containing nickel silicide (NiSi). The contact electrode 31 can, for example, be made of a material containing titanium, aluminum, and silicon. The contact electrode 31 is in ohmic contact with the contact area 16.

[0045] The source compound 32 covers the upper and lateral surfaces of the interlayer insulating film 23 and the upper surface of the contact electrode 31. The source compound 32 is in contact with the contact electrode 31. The source compound 32 is, for example, made of a material containing aluminum.

[0046] The drain electrode 40 is in contact with the second main surface 10B. The drain electrode 40 is in contact with the silicon carbide single-crystal substrate 11 at the second main surface 10B. The drain electrode 40 is electrically connected to the drift region 13. The drain electrode 40 is, for example, made of a material containing nickel silicide. The drain electrode 40 can be made of a material containing titanium, aluminum, and silicon. The drain electrode 40 is in ohmic contact with the silicon carbide single-crystal substrate 11.

[0047] Various embodiments have been described above, but the present invention is not limited to the embodiments described here, which can also be modified in various ways without leaving the scope of the invention as defined by the claims. LIST OF REFERENCE MARKS 1 semiconductor chip 3 side surface 4 Floor area 5 Gate Trench 10 Silicon carbide substrate 10A first main area 10B second main area 11 Silicon carbide single crystal substrate 12 Silicon carbide epitaxy layer 13 Drift area 13A first area 13B second area 13C third area 14 Body area 15 Source area 16 Contact area 17 Field attenuation area 18 Connection area 21 Gate insulation film 22 Gate connection 23 Interlayer insulating film 24 contact holes 30 Source electrode 31 Contact electrode 32 Source connection 40 Drain electrode 100 transistor cells BD Body Diode D Drain connection G Gate connector S Source connection QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-082047

[0002] JP 2012-23291

[0004]

Claims

[1] Semiconductor chip, comprising: a plurality of transistor cells arranged side by side along a first direction, where the transistor cells each contain: a first semiconductor region extending along a second direction orthogonal to the first direction and having a first conductivity type, wherein the first semiconductor region is arranged such that a mutual inductance generated between the first semiconductor region of one transistor cell of the transistor cells and the first semiconductor region of another transistor cell of the transistor cells has a negative value, the one transistor cell and the other transistor cell being adjacent to each other. [2] A semiconductor chip according to claim 1, wherein: the first semiconductor region is arranged such that the directions of currents flowing along the second direction in the first semiconductor region of one transistor cell and in the first semiconductor region of the other transistor cell are opposite to each other. [3] A semiconductor chip according to claim 1, wherein: the transistor cells each further comprise: a source electrode, and a second semiconductor region electrically connected to the first semiconductor region and the source electrode and having the first conductivity type, wherein the second semiconductor region is arranged such that the second semiconductor region of the one transistor cell is arranged at a different position in the second direction than the second semiconductor region of the other transistor cell. [4] A semiconductor chip according to claim 3, wherein: a plurality of second semiconductor regions constituting the second semiconductor region are arranged along the second direction, and the positions in the second direction at which the second semiconductor regions are arranged in the one transistor cell are each a middle position between two second semiconductor regions of the second semiconductor regions of the other transistor cell, wherein the two second semiconductor regions are adjacent to each other in the second direction. [5] A semiconductor chip according to claim 1, wherein: the first semiconductor regions are each a field attenuation region. [6] Semiconductor chip according to one of claims 1 to 5, wherein: the transistor cells are each a vertical transistor cell.

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