DISPLAY SUBSTRATE AND DRIVING METHOD THEREFOR, DISPLAY DEVICE

Abstract

The present disclosure relates to a display substrate, a driving method therefor, and a display device.The display substrate comprises a plurality of circuit units, wherein at least one circuit unit comprises a pixel driver circuit comprising at least: a compensation transistor (T2), a driver transistor (T3), a data write transistor (T4), a first storage capacitor (10) and a second storage capacitor (20); wherein a gate electrode of the data write transistor (T4) is connected to a first scanning signal line (21), a gate electrode of the compensation transistor (T2) is connected to a second scanning signal line (22), a first end of the first storage capacitor (10) is connected to a gate electrode of the driver transistor (T3), a first end of the second storage capacitor (20) is connected to a first pole of the driver transistor (T3), a second end of the first storage capacitor (10) and a second end of the second storage capacitor (20) are connected to a first current line (53).

Description

TECHNICAL FIELDThe present text relates to the field of display technology, and is not limited thereto, and more particularly relates to a display substrate, a driving method thereof, and a display device.PRIOR ARTOrganic light emitting diodes (OLED) and quantum dot light emitting diodes (QLED) are active light emitting display devices having advantages of self-lighting, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, thin and light design, flexibility, and low cost. With the continuous development of display technology, a flexible display device (flexible display) having OLED or QLED as a light emitting device and a thin film transistor (TFT) for signal control has already become a main trend product in the display area.DISCLOSURE OF THE INVENTIONAn overview of the items described in detail in this text is given below. This summary is not intended to limit the scope of the claims.In one aspect, in the present disclosure, there is provided a display substrate including: a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit includes a pixel driving circuit, the pixel driving circuit includes at least: a compensation transistor, a driving transistor, a data writing transistor, a first node, a second node, a first storage capacitor, and a second storage capacitor; wherein the pixel driving circuit is connected to a first scan signal line, a second scan signal line, a first power line, and a data signal line, respectively; a gate electrode of the driving transistor is connected to the second node, a first pole of the driving transistor is connected to the first node, a second pole of the driving transistor is connected to a second pole of the compensation transistor; a gate electrode of the data write transistor is connected to the first scan signal line, a first pole of the data write transistor is connected to the data signal line, a second pole of the data write transistor is connected to the first node; a gate electrode of the compensation transistor is connected to the second scan signal line, a first pole of the compensation transistor is connected to the second node; a first end of the first storage capacitor is connected to the second node, a second end of the first storage capacitor is connected to the first power line; a first end of the second storage capacitor is connected to the first node, and a second end of the second storage capacitor is connected to the first power line.In an exemplary embodiment, the display substrate includes, on a plane perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a base substrate; wherein the first end of the first storage capacitor includes a first pole plate, the second end of the first storage capacitor includes a second pole plate, the first pole plate is disposed in the first conductive layer, the second pole plate is disposed in the second conductive layer; the first end of the second storage capacitor includes at least one third pole plate, the second end of the second storage capacitor includes a fourth pole plate, the third pole plate is disposed in the semiconductor layer, and the fourth pole plate is disposed in the second conductive layer.In an exemplary embodiment, the first end of the second storage capacitor further includes a fifth pole plate, wherein the fifth pole plate is disposed in the third conductive layer and the third pole plate is connected to the fifth pole plate.In an exemplary embodiment, the display substrate includes, on a plane perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a base substrate; wherein the first end of the first storage capacitor includes a first pole plate, the second end of the first storage capacitor includes a second pole plate, the first pole plate is disposed in the first conductive layer, the second pole plate is disposed in the second conductive layer; the first end of the second storage capacitor includes at least one fifth pole plate, the second end of the second storage capacitor includes a fourth pole plate, the fifth pole plate is disposed in the third conductive layer, and the fourth pole plate is disposed in the second conductive layer.In an exemplary embodiment, the semiconductor layer further comprises an active layer of the driver transistor, wherein the third pole plate and the active layer of the driver transistor are connected to each other into an integral structure.In an exemplary embodiment, the second pole plate and the fourth pole plate are connected to each other into an integral structure.In an exemplary embodiment, the first node is disposed in the third conductive layer, the first node and the fifth pole plate are connected to each other into an integral structure, and the first node is connected to the third pole plate through a through hole.In an exemplary embodiment, the display substrate includes, on a plane perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a base substrate; wherein the first end of the first storage capacitor includes a first pole plate, the second end of the first storage capacitor includes a second pole plate, the first pole plate is disposed in the first conductive layer, the second pole plate is disposed in the second conductive layer; the first end of the second storage capacitor includes a third pole plate, the second end of the second storage capacitor includes a fourth pole plate, the third pole plate is disposed in the first conductive layer, and the fourth pole plate is disposed in the second conductive layer.In an exemplary embodiment, the second conductive layer further includes a first pole plate connection block, wherein the second pole plate and the fourth pole plate are connected to each other by the first pole plate connection block.In an exemplary embodiment, the third conductive layer further includes a second pole plate connection block and the first node, the first node being connected to the second pole plate connection block, and the second pole plate connection block being connected to the third pole plate through a through hole.In an exemplary embodiment, the distance between the first pole plate and the third pole plate is equal to or greater than 2 μm, the distance regarding a dimension in a unit row direction.In an exemplary embodiment, the capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor.In an exemplary embodiment, the capacitance value of the second storage capacitor is 20% to 70% of the capacitance value of the first storage capacitor.In an exemplary embodiment, the pixel driving circuit is further connected to a first initial signal line and a second initial signal line, respectively, wherein the shape of the first initial signal line and the second initial signal line is a line shape extending along a first direction; the first initial signal line is connected to a first connection line extending along a second direction to form a mesh structure for transmitting a first initial signal, the second initial signal line is connected to a second connection line extending along a second direction to form a mesh structure for transmitting a second initial signal, wherein the first direction and the second direction intersect.In an exemplary embodiment, the first initial signal line and the second initial signal line are provided in circuit units of at least one unit row; wherein the first connection line is provided in circuit units in an odd-numbered unit column and the second connection line is provided in circuit units in an even-numbered unit column, or the first connection line is provided in circuit units in an even-numbered unit column and the second connection line is provided in circuit units in an odd-numbered unit column.In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on a base substrate; wherein the first initial signal line and the second initial signal line are disposed in the second conductive layer, and the first connection line and the second connection line are disposed in the fourth conductive layer.In an exemplary embodiment, the third conductive layer in at least one circuit unit further includes a first initial electrode, the first connection line is connected to the first initial electrode through a via hole, and the first initial electrode is connected to the first initial signal line through a via hole.In an exemplary embodiment, the third conductive layer in at least one circuit unit further includes a second initial electrode, the second connection line is connected to the second initial electrode through a via hole, and the second initial electrode is connected to the second initial signal line through a via hole.In an exemplary embodiment, the display substrate further includes a fifth conductive layer disposed on a side of the fourth conductive layer opposite the base substrate, wherein the data signal line is disposed in the fifth conductive layer, the orthographic projection of at least one data signal line on the base substrate overlaps at least partially with the orthographic projection of the first connection line on the base substrate, and the orthographic projection of at least one data signal line on the base substrate overlaps at least partially with the orthographic projection of the second connection line on the base substrate.In another aspect, the present disclosure further provides a display device including a display substrate as set forth above.In yet another aspect, the present disclosure further provides a driving method for driving the display substrate as set forth above, comprising:in a data writing phase, outputting a turn-on signal through the first scan signal line and the second scan signal line, turning on the compensation transistor and the data writing transistor, writing a data voltage output from the data signal line into the first storage capacitor and the second storage capacitor;in a threshold compensation phase, outputting a turn-off signal through the first scan signal line, outputting a turn-on signal through the second scan signal line, turning on the compensation transistor, turning off the data write transistor, writing a data voltage stored by the second storage capacitor into the first storage capacitor, performing threshold compensation for the driver transistor.In an exemplary embodiment, the time of the threshold compensation phase is greater than or equal to the time of the data write phase.In an exemplary embodiment, the time of the threshold compensation phase is n times the time of the data write phase, where n is a positive integer greater than or equal to 1 and less than or equal to 9.After reading and understanding the figures and the detailed description, other aspects are to be detected.BRIEF DESCRIPTION OF THE FIGURESThe figures are provided to further understand the technical solutions of the present disclosure. They form a part of the description and are used in conjunction with the embodiments of the present disclosure to explain the technical solutions of the present disclosure; however, they do not constitute a limitation on the technical solutions of the present disclosure. FIG. 1 is a schematic diagram showing the structure of a display device; FIG. 2 is a schematic diagram showing the structure of a display substrate; FIG. 3 is a schematic diagram showing the planar structure of a display area in a display substrate; FIG. 4 is a schematic diagram of the structure of a display area in a display substrate in section; FIG. 5 is a schematic equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure; FIG. 6 is a drive timing diagram of a pixel driving circuit according to an embodiment of the present disclosure; FIG. 7A is a schematic diagram of the surface structure of a display substrate according to an embodiment of the present disclosure; FIG. 7B is a schematic diagram of the structure of an initial signal line of a network structure according to an embodiment of the present disclosure; FIG. 8 is a schematic diagram of a display substrate after forming a semiconductor layer pattern according to the present disclosure; FIGS. 9A and 9B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure; FIGS. 10A and 10B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure; FIG. 11 is a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to the present disclosure; FIGS. 12A and 12B are schematic diagrams of a display substrate after forming a third conductive layer pattern according to the present disclosure; FIG. 13 is a schematic diagram of a display substrate after forming a fifth insulating layer pattern according to the present disclosure; FIGS. 14A and 14B are schematic diagrams of a display substrate after forming a fourth conductive layer pattern according to the present disclosure; FIG. 15 is a schematic diagram of a display substrate after forming a first planarization layer pattern according to the present disclosure; FIGS. 16A and 16B are schematic diagrams of a display substrate after forming a fifth conductive layer pattern according to the present disclosure; FIG. 17 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure; FIG. 18 is a schematic diagram of another display substrate after forming a semiconductor layer pattern according to the present disclosure; FIG. 19 is a schematic illustration of another display substrate after forming a first conductive layer pattern according to the present disclosure; FIG. 20 is a schematic diagram of another display substrate after forming a second conductive layer pattern according to the present disclosure; FIG. 21 is a schematic diagram of another display substrate after forming a fourth insulating layer pattern according to the present disclosure; FIG. 22 is a schematic diagram of another display substrate after forming a third conductive layer pattern according to the present disclosure; FIG. 23 is a schematic diagram of another display substrate after forming a fifth conductive layer pattern according to the present disclosure; FIG. 24 is a test result diagram of the brightness difference between rows when a one-to-two structure is used in the present disclosure; FIG. 25 is a test result diagram of threshold sensitivity at different times of the threshold compensation phase, in accordance with the present disclosure.List of reference numbers:10 - first storage capacitor; 11 - first active layer; 12 - second active layer; 13 - third active layer; 14 - fourth active layer; 15 - fifth active layer; 16 - sixth active layer; 17 - seventh active layer; 18 - third pole plate; 20 - second storage capacitor; 21 - first scan signal line; 22 - second scan signal line; 23 - third scan signal line; 24 - light emission control line; 25 - first pole plate; 31 - first initial signal line; 32 - second initial signal line; 33 - second pole plate; 34 - fourth pole plate; 35 - pole plate connection line; 36 - opening; 37 - shield electrode; 38 - first pole plate connection block; 41 - first connection electrode; 42 - second connection electrode; 43 - third connection electrode; 44 - fourth connection electrode; 45 - fifth connection electrode; 46 - sixth connection electrode; 47 - seventh connection electrode; 48 - fifth pole plate; 49 - second pole plate connection block; 51 - eleventh connection electrode; 52 - twelfth connection electrode; 53 - first power line; 61 - data signal line; 62 - anode connection electrode; 71 - first initial electrode; 72 - second initial electrode; 81 - first connection line; 82 - second connection line; 100 - display area; 101 - base substrate; 102 - driving circuit layer; 103 - light emitting pattern layer; 104 - encapsulation pattern layer; 200 - bonding area; 300 - frame area.EMBODIMENTS OF THE INVENTIONIn order to more clearly illustrate the purpose, technical solutions, and advantages of the present disclosure, the following explains the embodiments of the present disclosure in conjunction with the figures. It should be noted that the embodiments may be performed in various forms. A general person skilled in the art can easily understand a Tatche that the manner and content can be converted into various forms without departing from the concept and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited only to the contents indicated in the following embodiments. The embodiments and the features of the embodiments in the present disclosure may be combined with each other arbitrarily in conflict-free cases.The figure scale in the present disclosure may serve as a reference in a practical process, but is not limited thereto. For example, the width-length ratio of a trench, the thicknesses and the distances of respective film layers, and the widths and the distances of respective signal lines may be set as needed actually. The number of pixels in a display substrate and the number of subpixels in each pixel are also not limited to the numbers shown in the figures, and the figures described in the present disclosure are only schematic structural representations, and a manner of operation of the present disclosure is not limited to the shapes or values or the like shown in the appended figures.In this specification, ordinal terms such as "first", "second", "third", etc. are used to avoid mixing of components, but are not to be understood as being limited in terms of quantity.In this specification, for convenience, terms "center", "top", "bottom", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside", "outside" or the like indicating an orientation or a positional relationship are used to illustrate the positional relationships of the constituent elements with reference to the accompanying drawings; they are used solely for convenience of illustration of the present description as well as for convenience of illustration, and are not intended to indicate or imply that a device or element that is intended has a particular orientation or needs to be formed and operated in a particular orientation; therefore, they should not be construed as limiting the present disclosure. The positional relationship of the constituent elements accordingly varies depending on the description of the directions of the respective constituent elements. Therefore, this is not limited to the words and expressions described in the specification, but replacement may be suitably made as appropriate.Unless otherwise defined, technical terms "mounted", "connected", and "connected" should be understood in the description in the general sense. For example, it may be a fixed connection, a detachable connection or a one-piece connection; it may be a mechanical connection or an electrical connection; it may be a direct connection or an indirect connection by means of an intermediate element or a connection within two elements. The specific meaning of the above terms in the present disclosure can be understood by a general person skilled in the art depending on the subject.In the present specification, a transistor is an element having at least three terminals, namely, a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present specification, the channel region refers to a region through which the current predominantly flows.In the present specification, a first pole may be a drain electrode and a second pole may be a source electrode, or a first pole may be a source electrode and a second pole may be a drain electrode. The functions of the "source" and "drain" are sometimes reversed when transistors having opposite polarities are used or when the current direction changes in the circuit operation. Therefore, in the present specification, the "source electrode" and the "drain electrode" are interchangeable; a source end and a drain end are interchangeable.In the present specification, "an electrical connection" includes a case where constituent elements are connected to each other by an element having a certain electrical function. No special limitation is imposed on "an element having a certain electrical function" as long as it can perform the giving and accepting of electrical signals between connected constituent members. Examples of "an element having a certain electrical function" include not only electrodes and wirings but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.In the present specification, the term "parallel" refers to a state in which the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state in which the angle is greater than -5° and less than 5°. Moreover, the term "perpendicular" refers to a state in which the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state in which the angle is greater than 85° and less than 95°.In the present specification, "film" and "layer" may be changed with each other. For example, "conductive layer" may sometimes be replaced with "conductive film". Likewise, "insulating film" may sometimes be replaced with "insulating layer".Triangles, rectangles, trapezoids, pentagonals or hexagon, etc. in the present specification are not meant in a strict sense, but may be approximate triangles, rectangles, trapezoids, pentagonals or hexagon, etc. Slight deformations may be present caused by tolerances; and rounded angles, curved edges, as well as deformations or the like may be present.The terms "about" in the present specification refer to a value that is not strictly limited to a limit and may be within a range of allowed process and measurement errors.FIG. 1 is a schematic diagram showing the structure of a display device. As shown in FIG. 1, a display device may include: a timing controller, a data driver, a scan driver, a light emission driver, and a pixel array. The timing controller is connected to each of the data driver, the scan driver, and the light emission driver. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), respectively, and the light emission driver is connected to a plurality of light emission signal lines (E1 to Eo), respectively. The pixel array may include a plurality of subpixels Pxij, where i and j may be natural numbers. At least one subpixel Pxij may include: a circuit unit; and a light emitting device connected to the circuit unit. The circuit unit may include at least one pixel driving circuit that may be connected to each of the scan signal line, the light emission signal line, and the data signal line. In an exemplary embodiment, the timing controller may provide grayscale values suitable for the specifications of the data driver and control signals to the data driver, may provide a clock signal suitable for the specifications of the scan signal driver, a scan start signal, and the like to the scan driver, and may provide a clock signal suitable for a specification of the light emission driver, an emission stop signal, and the like to the light emission driver. The data signal driver may generate a data voltage supplied to the data signal lines D 1, D 2, D3,..... and Dn using a grayscale value and a control signal received from the timing controller. For example, the data driver may perform sampling of the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal lines D 1 to Dn in pixel lines, where n may be a natural number. The scan driver may generate a scan signal, which is supplied to the scan signal lines S 1, S 2, S3,..... and Sm, by a clock signal, a scan start signal and the like received from the timing controller. The scan driver may sequentially supply scan signals having power-on level pulses to the scan signal lines S 1 to Sm, for example. The scan signal driver may be configured in the form of a shift register, for example, and generate the scan signals by sequentially transmitting the scan start signals provided in the form of power-on level pulses to a circuit of a next stage under the control of the clock signal, where m may be a natural number. The light emission driver may generate an emission signal, which is supplied to the light emission signal lines E 1, E 2, E, E3,..... and Eo, by a clock signal, an emission stop signal and the like received from the timing controller. For example, the light emission driver may sequentially supply emission signals with cut-off level pulses to the light emission signal lines E 1 to Eo. The light emission driver may be configured in the form of a shift register, for example, and generate the light emission signals by sequentially transmitting light emission stop signals provided in the form of blocking level pulses to a next-stage circuit under the control of the clock signal, where o may be a natural number.FIG. 2 is a schematic diagram showing the structure of a display substrate. As shown in FIG. 2, the display substrate may include a display region 100, a bonding region 200 on one side of the display region 100, and a frame region 300 on other sides of the display region 100. In an exemplary embodiment, the display region 100 may be a flat region including a plurality of subpixels Pxij forming a pixel array. The plurality of subpixels Pxij may be configured to display dynamic images or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible base substrate and therefore the display substrate may be deformable, for example, corrugated, bent, folded, or rolled.In an exemplary embodiment, the bonding portion 200 may include a fanout portion, a bending portion, a driver chip portion, and a bonding pin portion, which are sequentially arranged in a direction away from the display portion 100. The fanout area is connected to the display area 100 and includes at least: a data fanout line. A plurality of data fanout lines are configured to connect to the data signal lines of the display area in the form of fanout cabling. The bending portion is connected to the fanout portion, may include a grooved composite insulating layer, and is configured to bend the bonding portion toward the back side of the display portion. The driver chip region may be equipped with an integrated circuit (IC) which may be configured to connect to multiple data fanout lines. The bonding pin portion may include a bonding pad (bonding pad), and the bonding pad may be configured to be bonded to an external flexible printed circuit (FPC).In an exemplary embodiment, the frame portion 300 may include a circuit portion, a power line portion, a crack dam portion, and a cutting portion that are sequentially arranged in a direction away from the display portion 100. The circuit portion is connected to the display portion 100 and may include at least: a plurality of cascaded gate driver circuits connected to a plurality of scan lines of the pixel driver circuit in the display portion 100. The power line portion is connected to the circuit portion and may include at least: a frame power supply that is parallel to the edge of the display portion and connected to the cathode in the display portion 100. The crack dam portion is connected to the power line portion and may include at least a plurality of cracks provided on the composite insulating layer. The cutting portion is connected to the crack dam portion and may include at least cutting grooves provided on the composite insulating layer. The cutting grooves are configured such that after the formation of all the film layers of the display substrate, a cutting device cuts along the cutting grooves, respectively.In an exemplary embodiment, the fanout region in the bonding region 200 and the power line region in the frame region 300 may be provided with a first insulation dam and a second insulation dam, and the first insulation dam and the second insulation dam may extend in a direction parallel to the edge of the display region to form an annular structure around the display region 100. The edge of the display region is the edge of one side of the bonding region or the frame region.FIG. 3 is a schematic diagram showing the surface structure of a display area in a display substrate. As shown in FIG. 3, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first subpixel P 1 that emits light of a first color, a second subpixel P 2 that emits light of a second color, and a third subpixel P 3 that emits light of a third color. Each subpixel may include a circuit unit and a light emitting unit. The circuit unit may at least include: a pixel driving circuit. The pixel driving circuit is connected to each of the scan signal line, the data signal line, and the light emission signal line. The pixel driving circuit may be configured to receive the data voltage transmitted from the data signal line and output the corresponding current to the light emitting device under the control of the scan signal line and the light emitting signal line. Each subpixel may include a light emitting unit including at least one light emitting device. The light emitting device is each connected to the pixel driving circuit of the same subpixel, and the light emitting device is configured to emit light having a corresponding brightness in response to a current output from the pixel driving circuit of the same subpixel.In an exemplary embodiment, the first subpixel P 1 may be a red subpixel (R) that emits red light, the second subpixel P 2 may be a blue subpixel (B) that emits blue light, and the third subpixel P 3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the shape of the subpixel may be rectangular, diamond-shaped, pentagonal, or hexagonal. The three sub-pixels may be arranged horizontally parallel, vertically parallel, or in a " "- manner, etc., which is not to be limited in the present disclosure.In an exemplary embodiment, the pixel unit may include four subpixels. The four sub-pixels may be arranged horizontally in parallel, vertically in parallel, or square, or the like, which is not to be limited in the present disclosure.FIG. 4 is a schematic cross-sectional view of the structure of a display area in a display substrate, and illustrates the structure of three sub-pixels in the display area. As shown in FIG. 4, the display region may include, in the direction perpendicular to the display substrate, a driving circuit layer 102 provided on the base substrate 101, a light emitting structure layer 103 provided on a side of the driving circuit layer 102 opposite to the base substrate 101, and an encapsulation structure layer 104 provided on a side of the light emitting structure layer 103 opposite to the base substrate 101. In some possible implementations, the display substrate may include other film layers, such as touch control structure layers or the like, which are not limited in the present disclosure.In an exemplary embodiment, the base substrate 101 may be a flexible base substrate or a rigid base substrate. The driver circuit layer 102 may include a plurality of circuit units. A circuit unit may include at least one pixel driver circuit, which may include multiple transistors and storage capacitors. The light emitting structure layer 103 may include a plurality of light emitting units. The light emitting unit may include at least one light emitting device. The light emitting device may include an anode, an organic light emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, and the organic light emitting layer emits light in a corresponding color under driving of the anode and the cathode. The encapsulation structure layer 104 may include a first packaging layer, a second packaging layer and a third packaging layer arranged in a stacked manner. The first packaging layer and the third packaging layer may be made of inorganic materials, and the second packaging layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stack layer structure, whereby it can be ensured that external water vapor cannot enter the light emitting structure layer 103.In an exemplary embodiment, the organic light emitting layer may include a light emitting layer (EML), and one or more of a cavity injection layer (HIL), a cavity transport layer (HTL), and an electron blocking layer (EBL), cavity blocking layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In an exemplary embodiment, one or more of the cavity injection layers, cavity transport layers, electron blocking layers, cavity blocking layers, electron transport layers, and electron injection layers of all sub-pixels may be a common layer bonded together, and the light emission layers of adjacent sub-pixels may have a small overlap or be isolated from each other.With the rapid expansion of display applications, consumers are making ever-increasing demands on display effects. In particular, high image refresh rates and even ultra high image refresh rates are gradually required in various sectors. At high frame rates (high frame rates), the insufficient charge time is the greatest difficulty. For example, when the refresh rate is increased to 144 Hz / 165 Hz, difficulties in data writing and insufficient compensation occur due to the shortened single-line data writing time in one frame, resulting in a high black state voltage and a poor threshold sensitivity.Exemplary embodiments of the present disclosure provide a display substrate. On a plane perpendicular to the display substrate, the display substrate may include a driver circuit layer disposed on a base substrate, a light emitting structure layer disposed on a side of the driver circuit layer opposite to the base substrate, and an encapsulation structure layer disposed on a side of the light emitting structure layer opposite to the base substrate. In a plane parallel to the display substrate, the driving circuit layer of the display region may include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns; and the light emitting structure layer of the display region may include a plurality of light emitting units forming a plurality of pixel rows and a plurality of pixel columns. At least one circuit unit comprises a pixel driver circuit; at least one light emitting unit may comprise a light emitting device connected to a corresponding pixel driver circuit. The light emitting device is configured to emit light having a corresponding brightness in response to a current output from the connected pixel circuit.In an exemplary embodiment, the light emitting unit mentioned in the present disclosure refers to a region divided due to a light emitting device; and the circuit unit mentioned in the present disclosure refers to a region divided due to a pixel driving circuit. In an exemplary embodiment, the position of the orthographic projection of the light emitting unit on the base substrate may correspond to the position of the orthographic projection of the circuit unit on the base substrate, or the position of the orthographic projection of the light emitting unit on the base substrate does not correspond to the position of the orthographic projection of the circuit unit on the base substrate.Exemplary embodiments of the present disclosure provide a display substrate including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns. At least one circuit unit includes a pixel driver circuit, and the pixel driver circuit includes at least: a compensation transistor, a driver transistor, a data write transistor, a first node, a second node, a first storage capacitor, and a second storage capacitor. The pixel driver circuit is connected to a first scan signal line, a second scan signal line, the first power line, and a data signal line, respectively; wherein a gate electrode of the driver transistor is connected to the second node, a first pole of the driver transistor is connected to the first node, a second pole of the driver transistor is connected to a second pole of the compensation transistor; wherein a gate electrode of the data write transistor is connected to the first scan signal line, a first pole of the data write transistor is connected to the data signal line, a second pole of the data write transistor is connected to the first node; wherein a gate electrode of the compensation transistor is connected to the second scan signal line, a first pole of the compensation transistor is connected to the second node, respectively; wherein a first end of the first storage capacitor is connected to the second node, a second end of the first storage capacitor is connected to the first power line; wherein a first end of the second storage capacitor is connected to the first node, a second end of the second storage capacitor is connected to the first power line.In an exemplary embodiment, the display substrate includes, on a plane perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed on a base substrate; wherein the first end of the first storage capacitor includes a first pole plate, the second end of the first storage capacitor includes a second pole plate, the first pole plate is disposed in the first conductive layer, and the second pole plate is disposed in the second conductive layer.In an exemplary embodiment, the first end of the second storage capacitor includes a third pole plate, the second end of the second storage capacitor includes a fourth pole plate, the third pole plate is disposed in the semiconductor layer, and the fourth pole plate is disposed in the second conductive layer.In another exemplary embodiment, the first end of the second storage capacitor includes a fifth pole plate, the second end of the second storage capacitor includes a fourth pole plate, the fourth pole plate is disposed in the second conductive layer, and the fifth pole plate is disposed in the third conductive layer.In another exemplary embodiment, the first end of the second storage capacitor includes a third pole plate and a fifth pole plate, the second end of the second storage capacitor includes a fourth pole plate, the third pole plate is disposed in the semiconductor layer, the fourth pole plate is disposed in the second conductive layer, the fifth pole plate is disposed in the third conductive layer, and the third pole plate is connected to the fifth pole plate.In another exemplary embodiment, the first end of the second storage capacitor includes a third pole plate, the second end of the second storage capacitor includes a fourth pole plate, the third pole plate is disposed on the first conductive layer, and the fourth pole plate is disposed in the second conductive layer.In an exemplary embodiment, the pixel driving circuit is further connected to a first initial signal line and a second initial signal line, respectively, the shapes of the first initial signal line and the second initial signal line being line shapes extending along a first direction; the first initial signal line being connected to a first connection line extending along the second direction to form a mesh structure for transmitting a first initial signal; the second initial signal line being connected to a second connection line extending along a second direction to form a mesh structure for transmitting a second initial signal; the first direction and the second direction intersecting each other.The display substrate of the present disclosure will be explained below by some exemplary embodiments.FIG. 5 is a schematic equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the pixel driver circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit of the exemplary embodiments of the present disclosure may include seven transistors (a first transistor T 1 to a seventh transistor T 7) and two storage capacitors (a first storage capacitor C 1 and a second storage capacitor C 2). The pixel driving circuit is connected to eight signal lines (a first scan signal line S 1, a second scan signal line S 2, a third scan signal line S 3, a light emission signal line E, a first initial signal line INIT 1 and a second initial signal line INIT 2, a data signal line D, and a first power line VDD), respectively.In an exemplary embodiment, the pixel driving circuit may include a first node N 1, a second node N 2, a third node N 3, and a fourth node N 4. In this case, the first node N 1 is connected in each case to a first pole of the third transistor T 3, a second pole of the fourth transistor T 4, a second pole of the fifth transistor T 5 and a second end of the second storage capacitor C 2. The second node N 2 is connected to a second pole of the first transistor, a first pole of the second transistor T 2, a gate electrode of the third transistor T 3, and a second end of the first storage capacitor C 1, respectively. The third node N 3 is connected to a second pole of the second transistor T 2, a second pole of the third transistor T 3 and a first pole of the sixth transistor T 6, respectively. The fourth node N 4 is connected to a second pole of the sixth transistor T 6 and a second pole of the seventh transistor T 7, respectively.In an exemplary embodiment, a first end of the first storage capacitor C 1 is connected to the second node N 2, the second end of the first storage capacitor C 1 is connected to the first power line VDD, a first end of the second storage capacitor C 2 is connected to the first node N 1, and the second end of the second storage capacitor C 2 is connected to the first power line VDD. The signal of the first power line VDD is a continuously provided high level signal.In an exemplary embodiment, a gate electrode of the first transistor T 1 is connected to the third scan signal line S 3, a first pole of the first transistor T 1 is connected to the first initial signal line INIT 1, and a second pole of the first transistor is connected to the second node N 2. When an on-level scan signal is applied to the third scan signal line S 3, the first transistor T 1 transmits the first initial voltage to the gate electrode of the third transistor T 3 to initialize the charge amount of the gate electrode of the third transistor T 3.In an exemplary embodiment, a gate electrode of the second transistor T 2 (the compensation transistor) is connected to the second scan signal line S 2, the first pole of the second transistor T 2 is connected to the second node N 2, and the second pole of the second transistor T 2 is connected to the third node N 3. When the turn-on level scan signal is applied to the second scan signal line S 2, the second transistor T 2 causes the gate electrode of the third transistor T 3 to be connected to the second pole.In an exemplary embodiment, the gate electrode of the third transistor T 3 is connected to the second node N 2, i.e., the gate electrode of the third transistor T 3 is connected to the second end of the first storage capacitor C 1, the first pole of the third transistor T 3 is connected to the first node N 1, and the second pole of the third transistor T 3 is connected to the third node N 3. The third transistor T 3 may be referred to as a driver transistor, and the third transistor T 3 determines the magnitude of the driver current depending on the potential difference between its gate electrode and the first pole.In an exemplary embodiment, the gate electrode of the fourth transistor T 4 (the data write transistor) is connected to the first scan signal line S 1, the first pole of the fourth transistor T 4 is connected to the data signal line D, and the second pole of the fourth transistor T 4 is connected to the first node N 1. When the power-on level scan signal is applied to the first scan signal line S 1, the fourth transistor T 4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.In an exemplary embodiment, the gate electrode of the fifth transistor T 5 is connected to the light emission signal line E, the first pole of the fifth transistor T 5 is connected to the first power line VDD, and the second pole of the fifth transistor T 5 is connected to the first node N 1. The gate electrode of the sixth transistor T 6 is connected to the light emission signal line E, the first pole of the sixth transistor T 6 is connected to the third node N 3, and the second pole of the sixth transistor T 6 is connected to the fourth node N 4. When the turn-on level sensing signal is applied to the light emission signal line E, the fifth transistor T 5 and the sixth transistor T 6 cause the light emitting device EL to emit light by forming a driving current path between the first power line VDD and the second power line VSS.In an exemplary embodiment, the gate electrode of the seventh transistor T 7 is connected to the first scan signal line S 1, the first pole of the seventh transistor T 7 is connected to the second initial signal line INIT 2, and the second pole of the seventh transistor T 7 is connected to the fourth node N 4. When the turn-on level scan signal is applied to the first scan signal line S 1, the seventh transistor T 7 transmits the second initial voltage to the first pole of the light emitting device EL, so that the amount of charge accumulated in the first pole of the light emitting device EL is initialized.In an exemplary embodiment, the light emitting device EL may be an OLED including a first pole (anode), an organic light emitting layer, and a second pole (cathode) stacked; or may be a QLED including a first pole (anode), a quantum dot light emitting layer, and a second pole (cathode) stacked. The first pole of the light emitting device EL is connected to the fourth node N 4, and the second pole of the light emitting device EL is connected to the second power line VSS. The signal of the second power line VSS is a continuously provided low level signal.In an exemplary embodiment, the first transistor T 1 to the seventh transistor T 7 may be P-type transistors or N-type transistors. By using transistors of a same type in the pixel driving circuit, the process flow can be simplified, the process difficulties of the display panel are reduced, and the product yield is increased. In some possible implementations, the first transistor T 1 to the seventh transistor T 7 may include P-type transistors and N-type transistors.In some example embodiments, the first transistor T 1 to the seventh transistor T 7 may use low-temperature polysilicon thin film transistors or oxide thin film transistors, or low-temperature polysilicon thin film transistors and oxide thin film transistors. In an active layer of a low-temperature polysilicon thin film transistor, low-temperature polysilicon (LTPS) is used, and in an active layer of an oxide thin film transistor, an oxide semiconductor (oxide) is used. Low temperature polysilicon thin film transistors have advantages of high mobility and rapid charging, and oxide thin film transistors have advantages of low leakage current. Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate, that is, an LTPS+oxide (abbreviated as LTPO) display substrate can take advantage of the two, whereby low-frequency driving can be enabled, power consumption can be reduced, and display quality can be improved.FIG. 6 is a drive timing diagram of a pixel driving circuit according to an embodiment of the present disclosure. As illustrated in FIG. 6, when the first transistor T 1 to the seventh transistor T 7 in the pixel driving circuit in FIG. 5 are all P-type transistors, the operation process of the pixel driving circuit may include:a first phase A1 referred to as a reset phase. The signal of the third scan signal line S 3 is a low level signal, and the signals of the first scan signal line S 1, the second scan signal line S 2, and the light emission signal line E are high level signals. The low level signal of the third scan signal line S 3 causes the first transistor T 1 to turn on. The first initial voltage of the first initial signal line INIT 1 is supplied to the second node N 2 to initialize the first storage capacitor C 1 and clear the original data voltage in the first storage capacitor. Since the second end of the first storage capacitor C 1 is at a low level, the third transistor T 3 is turned on. The signals of the first scan signal line S 1, the second scan signal line S 2, and the light emission signal line E are high level signals, so that the second transistor T 2, the fourth transistor T 4, the fifth transistor T 5, the sixth transistor T 6, and the seventh transistor T 7 are turned off.a second phase A2 called a data write phase. The signals of the first scan signal line S 1 and the second scan signal line S 2 are low level signals, and the signals of the third scan signal line S 3 and the light emission signal line E are high level signals. The data signal line D outputs a data voltage. The low level signal of the first scan signal line S 1 causes the fourth transistor T 4 and the seventh transistor T 7 to be turned on. The low level signal of the second scan signal line S 2 causes the second transistor T 2 to turn on. The second transistor T 2 and the fourth transistor T 4 are turned on, so that the data voltage output from the data signal line D is charged into the second end of the second storage capacitor C 2 via the first node N 1, the turned-on transistor T 3, the third node N 3, the turned-on second transistor T 2, and the second node N 2 to the second end of the first storage capacitor C 1, on the one hand. The seventh transistor T 7 is turned on so that the second initial voltage of the second initial signal line INIT 2 is supplied to the fourth node N 4 (the first pole of the OLED) to initialize (reset) the first pole of the OLED and erase its internal prestored voltage so that the initialization is completed. The signals of the third scan signal line S 3 and the light emission signal line E are high level signals, so that the first transistor T 1, the fifth transistor T 5, and the sixth transistor T 6 are turned off. In an exemplary embodiment, the time of the data write phase may be referred to as a single line data write time (1 hour). The refresh rate of the display substrate refers to the frequency of the turn-on signal provided from the first scan signal line S 1.a third phase A3 referred to as a threshold compensation phase. Further, the signal of the second scan signal line S 2 is a low level signal, and the signals of the first scan signal line S 1, the third scan signal line S 3, and the light emission signal line E are high level signals. The low level signal of the second scan signal line S 2 causes the second transistor T 2 to be turned on further and further. The voltage charged by the second storage capacitor C 2 in the second phase is supplied to the second end of the first storage capacitor C 1 via the first node N 1, the turned-on third transistor T 3, the third node N 3, the turned-on second transistor T 2, and the second node N 2, so that the data voltage is continuously written into the first storage capacitor C 1 and the third transistor T 3 is compensated, and the difference between the data voltage and the threshold voltage of the third transistor T 3 is charged into the first storage capacitor C 1. The voltage at the second end of the first storage capacitor C 1 (the second node N 2) is Vd-|Vd|, where Vd is the data voltage output from the data signal line D and Vth is the threshold voltage of the third transistor T 3. In an exemplary embodiment, the time of the threshold compensation phase may be greater than or equal to the time of the data write phase.a fourth phase A4 referred to as a light emission phase. The signal of the light emission signal line E is a low level signal, and the signals of the first scan signal line S 1, the second scan signal line S 2, and the third scan signal line S 3 are high level signals. The signal of the light emission signal line E is a low level signal, so that the fifth transistor T 5 and the sixth transistor T 6 are turned on. The power supply voltage output from the first power line VDD provides a driving voltage to the first pole of the OLED via the turned-on fifth transistor T 5, the third transistor T 3, and the sixth transistor T 6 to drive the OLED to emit light.During the driving operation of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first pole. Since the voltage of the first node N 2 is Vdata-|Vth|, the driving current of the third transistor T 3 satisfies:Here, I is the driving current flowing through the third transistor T 3, i.e., a driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first pole of the third transistor T 3, Vth is the threshold voltage of the third transistor T 3, Vda is the data voltage output from the data signal line D, and Vdd is the power supply voltage output from the first power line VDD.In an exemplary embodiment, the time of the threshold compensation phase may be about n times the time of the data write phase, n may be a positive integer that is greater than or equal to 1 and less than or equal to 9.Table 1 shows the test results of the time of the threshold compensation phase and a data voltage range (Data Range), which are data voltage ranges of the R / G / B pixels corresponding to the time of different threshold compensation phases, the data voltages in parentheses respectively relate to a data voltage corresponding to the gray level 255 and a data voltage corresponding to the gray level 0. As shown in Table 1, in a 165Hz high-frequency display, as the time of the threshold compensation phase increases, not only is the black state voltage lowered, whereby writing of data in the high-frequency state can be ensured; the data voltage range is also increased, more clear limitation of various grayscale images is ensured, whereby the image quality of the screen at high frequencies is improved. Table 1: Test results of the time of threshold compensation phase and a data voltage range Table 1: Test results of the time of threshold compensation phase and a data voltage rangeData Voltage Rangen=1 (1-times)n=3 (3-times)n=5 (5-times)165Hz (1h=2,5μs )R is R2,63 (4,26-6,89)2,74 (3,52-6,26)2,72 (3,45-6,17)G.2,19 (4,73-6,92)2,30 (4,02-6,32)2,30 (3,95-6,25)B. B3,08 (3,60-6,68)3,18 (2,84-6,02)3,19 (2,76-5,95)In a solution of a pixel driver circuit with 7T1C, because the second transistor T2 and the fourth transistor T4 are controlled by the same scan signal line, only a single-line data write time holds for the data write and threshold compensation time. When the refresh rate is relatively high, the subpixels cannot display images with relatively low gray levels. In the pixel driving circuit provided according to an exemplary embodiment of the present disclosure, the data writing phase and the threshold compensation phase are separated, both the data writing time can be extended and a sufficient compensation time can be ensured by controlling the fourth transistor T 4 by the first scan signal line S 1, controlling the second transistor T 2 by the second scan signal line S 2, the time of the turn-on signal output from the second scan signal line S 2 is longer than the time of the turn-on signal output from the first scan signal line S 1, and providing the second storage capacitor C 2 between the first pole and the second pole of the fifth transistor T 5. In the process of driving the pixel driving circuit in the present disclosure, the first scan signal line S 1 corresponding to the fourth transistor T 4 controls the normal data writing within a single-line data writing time, and the second scan signal line S 2 corresponding to the second transistor T 2 controls the data writing and the threshold compensation within a plurality of single-line data writing times, thereby extending the data writing time. The newly added second storage capacitor C 2 not only allows the data voltage to be stored in the second storage capacitor C 2 during the data writing phase, so that the data writing phase does not react sensitively to the source signal load (source loading), and it can also be ensured that the data writing is continued during the turn-off of the fourth transistor T 4 and the turn-on of the second transistor T 2, and the image quality of low grayscales can be enabled. In the present disclosure, as compared with the existing 7T1C pixel driving circuit solution, by setting the writing and compensating manner, the problems of the present solution such as insufficient charging time and insufficient compensating time or the like are effectively improved, clearer limitation of various grayscale images is ensured, image quality displayed at high frequencies is guaranteed, and display effect and display quality are improved.FIG. 7A is a schematic diagram illustrating the planar structure of a display substrate according to an embodiment of the present disclosure, illustrating the structure of pixel driving circuits in two circuit units in the display area. As shown in FIG. 7A, the pixel driving circuit of at least one circuit unit may include at least a second transistor T 2 as a compensation transistor, a third transistor T 3 as a driving transistor, a fourth transistor T 4 as a data writing transistor, a third connection electrode 43 as a first node, a first connection electrode 41 as a second node, a first storage capacitor 10, and a second storage capacitor 20.In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light emission control line 24, the first initial signal line 31, and the second initial signal line 32 may be line shapes extending along the first direction X. The shapes of the first power line 53 and the data signal line 61 may be line shapes extending along the second direction Y. The first direction X and the second direction Y intersect. The first scan signal line 21 and the second scan signal line 22 are configured to provide a first scan signal and a second scan signal to the pixel driving circuit. The data signal line 51 is configured to provide a data signal to the pixel driving circuit. The first power line 52 is configured to provide a first current signal to the pixel driver circuit. The first initial signal line 31 and the second initial signal line 32 are configured to provide a first initial signal and a second initial signal, respectively, to the pixel driver circuit. The first initial signal may be configured to initialize (reset) the first storage capacitor and the second initial signal may be configured to initialize (reset) the light emitting device.In the present disclosure, "A extends along the direction B" A may include a main part and a sub part connected to the main part, the main part being a line, a line segment, or a strip-shaped body, the main part extending along the direction B, and the length of the main part extending along the direction B is greater than the length of the sub part extending along another direction.In an exemplary embodiment, the gate electrode of the second transistor T 2 is connected to the second scan signal line 22, the first pole of the second transistor T 2 is connected to the first connection electrode 41 (the second node), and the second pole of the second transistor T 2 is connected to the second pole of the third transistor T 3. The gate electrode of the third transistor T 3 is connected to the first connection electrode 41 (the second node), and the first pole of the third transistor T 3 is connected to the third connection electrode 43 (the first node). The gate electrode of the fourth transistor T 4 is connected to the first scan signal line 21, the first pole of the fourth transistor T 4 is connected to the data signal line 61, and the second pole of the fourth transistor T 4 is connected to the third connection electrode 43 (the first node). The first end of the first storage capacitor 10 is connected to the first connection electrode 41 (the second node), and the second end of the first storage capacitor 10 is connected to the first power line 53. The first end of the second storage capacitor 20 is connected to the third connection electrode 43 (the first node), and the second end of the second storage capacitor 20 is connected to the first power line 53.In an exemplary embodiment, the first end of the first storage capacitor 10 may include a first pole plate and the second end of the first storage capacitor 10 may include a second pole plate. The first pole plate may be disposed in the first conductive layer. The second pole plate may be disposed in the second conductive layer. The orthographic projection of the second pole plate on the base substrate overlaps at least partially with the orthographic projection of the first pole plate on the base substrate.In an exemplary embodiment, the first end of the second storage capacitor 20 may include a third pole plate and a fifth pole plate, and the second end of the second storage capacitor 20 may include a fourth pole plate. The third pole plate may be disposed in the semiconductor layer. The fourth pole plate may be disposed in the second conductive layer. The fifth pole plate may be disposed in the third conductive layer. The orthographic projection of the fourth pole plate on the base substrate overlaps at least partially with the orthographic projection of the third pole plate on the base substrate, the orthographic projection of the fifth pole plate on the base substrate overlaps at least partially with the orthographic projection of the fourth pole plate on the base substrate, and the third pole plate is connected to the fifth pole plate.In an exemplary embodiment, the capacitance value of the second storage capacitor 20 may be smaller than the capacitance value of the first storage capacitor 10.In an exemplary embodiment, the capacitance value of the second storage capacitor 20 may be about 20% to 70% of the capacitance value of the first storage capacitor 10. For example, the capacitance value of the second storage capacitor 20 may be about 30% to 50% of the capacitance value of the first storage capacitor 10.In an exemplary embodiment, the semiconductor layer may include at least the active layer of the third transistor T 3. The third pole plate and the active layer of the third transistor T 3 may be connected to each other into an integral structure.In an exemplary embodiment, the second pole plate and the fourth pole plate may be connected to each other into an integral structure.In an exemplary embodiment, the third connection electrode 43 (the first node) may be disposed in the third conductive layer. The third connection electrode 43 and the fifth pole plate are connected to each other into an integral structure. The third connection electrode 43 is connected to the third pole plate via a through hole.FIG. 7B is a schematic diagram of the structure of an initial signal line of a network structure according to an embodiment of the present disclosure. As shown in FIG. 7B, the first initial signal line 31 is connected to the first connection line 81 extending along the second direction Y, and the second initial signal line 32 is connected to the second connection line 82 extending along the second direction Y. On the display substrate, a mesh for transmitting the first initial signal and a mesh for transmitting the second initial signal are simultaneously formed.In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 are provided in a circuit unit of at least one unit row, a first connection line 81 is provided in a circuit unit of an odd-numbered unit column (the N+1-th column), and a second connection line 82 is provided in a circuit unit of an even-numbered unit column (the N-th column). A plurality of first connecting lines 81 of odd-numbered unit columns are connected to the first initial signal lines 31 of a plurality of unit rows, and a plurality of second connecting lines 82 of even-numbered unit columns are connected to the second initial signal lines 32 of a plurality of unit rows.In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 are provided in a circuit unit of at least one unit row, a first connection line 81 is provided in a circuit unit of an even-numbered unit column (the N-th column), and a second connection line 82 is provided in a circuit unit of an odd-numbered unit column (the N+1-th column). A plurality of first even-numbered unit column connection lines 81 are connected to the first initial signal lines 31 of a plurality of unit rows, and a plurality of second odd-numbered unit column connection lines 82 are connected to the second initial signal lines 32 of a plurality of unit rows.In an exemplary embodiment, the display substrate may include, on a plane perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the base substrate. The active layers of the second transistor T 2, the third transistor T 3 and the fourth transistor T 4 may be disposed in the semiconductor layer. The first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission control line 24 may be disposed in the first conductive layer. The first initial signal line 31 and the second initial signal line 32 may be disposed in the second conductive layer. The first connection electrode 41 and the third connection electrode 43 may be disposed in the third conductive layer. The first power line 53, the first connection line 81, and the second connection line 84 may be provided in the fourth conductive layer.In an exemplary embodiment, the third conductive layer in at least one circuit unit may further include a first initial electrode 71. The first connection line 81 in the fourth conductive layer is connected to the first initial electrode 71 in the third conductive layer via a through hole. The first initial electrode 71 in the third conductive layer is connected to the first initial signal line 31 in the second conductive layer via a via hole.In an exemplary embodiment, the third conductive layer in at least one circuit unit may further include a second initial electrode 72. The second connection line 82 in the fourth conductive layer is connected to the second initial electrode 72 in the third conductive layer via a through hole. The second initial electrode 72 in the third conductive layer is connected to the second initial signal line 32 in the second conductive layer via a via hole.In an exemplary embodiment, the orthographic projection of the data signal line 61 on the base substrate overlaps at least partially with the orthographic projection of the first connection line 81 on the base substrate, and the orthographic projection of the data signal line 61 on the base substrate overlaps at least partially with the orthographic projection of the second connection line 82 on the base substrate.In an exemplary embodiment, the display substrate may further include at least a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a first planarization layer. The first insulating layer is provided between the base substrate and the semiconductor layer, the second insulating layer is provided between the semiconductor layer and the first conductive layer, the third insulating layer is provided between the first conductive layer and the second conductive layer, the fourth insulating layer is provided between the second conductive layer and the third conductive layer, the fifth insulating layer is provided between the third conductive layer and the fourth conductive layer, and the first planarization layer is provided between the fourth conductive layer and the fifth conductive layer.As follows, an exemplary explanation will be given by a manufacturing process of the display substrate. The "patterning process" mentioned in the present disclosure includes treatments such as applying a photoresist, exposing a mask, developing, etching, and peeling off the photoresist or the like for a metallic material, an inorganic material, or a transparent conductive material, and includes treatments such as applying an organic material, exposing a mask, developing, or the like for an organic material. As the deposition, one or more of sputtering, vapor deposition, and chemical vapor deposition may be used, as the application, one or more of spray coating, spin coating, and inkjet printing may be used, and as the etching, one or more of dry etching and wet etching may be used, which is not limited in the present disclosure. "film" refers to a membrane made of a material on the base substrate by means of the deposition, application, or other method. If the "film" does not need a patterning process throughout the manufacturing process, the "film" may also be referred to as a "layer.". If the "film" still needs a patterning process throughout the manufacturing process, the "film" will be referred to as "film" before the patterning process and "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". In the present disclosure, the expression "A and B are provided in one and the same layer" means that A and B are simultaneously formed by the same patterning process, and the "thickness" of a film layer is a dimension of the film layer in a direction perpendicular to a display substrate. The phrase "an orthographic projection of B is within the scope of an orthographic projection of A" and the phrase "an orthographic projection of A includes an orthographic projection of B" in exemplary embodiments of the present disclosure mean that the boundary of the orthographic projection of B falls within the scope of the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A and the boundary of the orthographic projection of B are overlapped, respectively.In some example embodiments, the manufacturing process of the display substrate may include the following operations:(11) forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include depositing a first insulating thin film and a semiconductor film on a base substrate sequentially, patterning the semiconductor film by a patterning process, forming a first insulating layer covering the base substrate, and disposing the semiconductor layer on the first insulating layer as illustrated in FIG. 8.In an exemplary embodiment, the semiconductor layer of each circuit unit in the display area may at least include: a first active layer 11 of the first transistor T 1, a second active layer 12 of the second transistor T 2, a third active layer 13 of the third transistor T 3, a fourth active layer 14 of the fourth transistor T 4, a fifth active layer 15 of the fifth transistor T 5, a sixth active layer 16 of the sixth transistor T 6, a seventh active layer 17 of the seventh transistor T 7, and a third pole plate 18 of the second storage capacitor. The first active layer 11 to the third active layer 13, the fifth active layer 15 to the seventh active layer 17, and the third pole plate 18 may be connected to each other into an integral structure. The fourth active layer 14 may be separately provided.In order to bypass the third pole plate 18 provided to the semiconductor layer, in an exemplary embodiment, the fourth active layer 14 is separately provided on one side of the third pole plate 18 in the second direction Y.In an exemplary embodiment, the first active layer 11 and the second active layer 12 may be located on a side of the third active layer 18 of the circuit unit in the direction opposite to the second direction Y. The fourth active layer 14, the fifth active layer, the sixth active layer 16, and the seventh active layer 17 may be located on a side of the third active layer 13 of the circuit unit in the second direction Y.In an exemplary embodiment, the first active layer 11 may be represented in an "n" shape, the second active layer 12 and the fifth active layer 15 may be represented in an "L" shape, the third active layer 13 may be represented in an "Ω" shape, and the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 may be represented in an "I" shape.In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region. In an exemplary embodiment, the first active layer first region 11- 1, the fourth active layer first region 14- 1, the fourth active layer second region 14- 2, the fifth active layer first region 15- 1, and the seventh active layer first region 17- 1 may be separately disposed. The second region 11- 2 of the first active layer may be used as the first region 12- 1 of the second active layer. The first region 13- 1 of the third active layer may serve as the second region 15- 2 of the fifth active layer 15. The second third active layer region 13- 2 may be simultaneously used as the second active layer region 12- 2 and the first sixth active layer region 16- 1. The second region 16- 2 of the sixth active layer may be used as the second region 17- 2 of the seventh active layer.In an exemplary embodiment, the shape of the third pole plate 18 of the second storage capacitor may be a rectangular shape and the corners of the rectangular shape may be rounded. The third pole plate 18 may be disposed on the third circuit unit active layer 13 side in the direction X. They and the third active layer first region 13-1 and the fifth active layer second region 15-2 are joined together into an integral structure. In an exemplary embodiment, the third pole plate 18 may serve as a pole plate of the second storage capacitor.In an exemplary embodiment, the first region 13- 1 of the third active layer may serve as the first pole of the third transistor T 3 and the second region 15- 2 of the fifth active layer may serve as the second pole of the fifth transistor T 5. The first pole of the third transistor T3, the second pole of the fifth transistor T5 and the third pole plate 18 are connected to each other, the connection point being the first node N1 of the pixel driving circuit. The second active layer second region 12- 2 may serve as the second pole of the second transistor T 2, the third active layer second region 13- 2 may serve as the second pole of the third transistor T 3, and the sixth active layer first region 16- 1 may serve as the first pole of the sixth transistor T 6. The second pole of the second transistor T 2, the second pole of the third transistor T 3 and the first pole of the sixth transistor T 6 are connected to each other, the connection point being the third node N 3 of the pixel driving circuit. The second region 16- 2 of the sixth active layer may serve as the second pole of the sixth transistor T 6, and the second region 17- 2 of the seventh active layer may serve as the second pole of the seventh transistor T 7. The second pole of the sixth transistor T 6 and the second pole of the seventh transistor T 7 are connected to each other, the connection point being the fourth node N 4 of the pixel driving circuit.(12) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include depositing a second insulating thin film and a first conductive thin film sequentially on the base substrate on which the foregoing pattern is formed, patterning the first conductive thin film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and disposing the first conductive layer pattern on the second insulating layer as illustrated in FIGS. 9A and 9B. FIG. 9B is a schematic illustration of the first conductive layer in FIG. 9A. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal layer (GATE 1).In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emission control line 24, and a first pole plate 25 of the first storage capacitor.In an exemplary embodiment, the shape of the first pole plate 25 of the first storage capacitor may be rectangular and the corners of the rectangular shape may be rounded. The orthographic projection of the first pole plate 25 on the base substrate overlaps at least partially with the orthographic projection of the third active layer of the third transistor T 3 on the base substrate. In an exemplary embodiment, the first pole plate 25 may simultaneously serve as a pole plate of the first storage capacitor and as a gate electrode of the third transistor T 3.In an exemplary embodiment, the area of the orthographic projection of the third pole plate 18 on the base substrate may be smaller than the area of the orthographic projection of the first pole plate 25 on the base substrate.In an exemplary embodiment, the shape of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission control line 24 may be a line shape in which the main body part extends along the first direction X. The first scan signal line 21 and the light emission control line 24 may be located on a side of the first circuit unit pole plate 25 in the second direction Y, the second scan signal line 22 and the third scan signal line 23 may be located on a side of the first circuit unit pole plate 25 in the direction opposite to the second direction Y, the first scan signal line 21 may be located on a side of the circuit unit light emission control line 24 opposite to the first pole plate 25, and the third scan signal line 23 may be located on a side of the second circuit unit scan signal line 22 opposite to the first pole plate 25.In an exemplary embodiment, the overlapping region of the first scan signal line 21 and the fourth active layer may serve as a gate electrode of the fourth transistor T 4; the overlapping region of the first scan signal line 21 and the seventh active layer may serve as a gate electrode of the seventh transistor T 7; the overlapping region of the third scan signal line 23 and the first active layer may serve as a gate electrode of the first transistor T 1 of a double-gate structure; the overlapping region of the light emission control line 24 and the fifth active layer may serve as a gate electrode of the fifth transistor T 5; and the overlapping region of the light emission control line 24 and the sixth active layer may serve as a gate electrode of the sixth transistor T 6.In an exemplary embodiment, the second scan signal line 22 may be provided with a gate block 22- 1 protruding toward a side of the third scan signal line 23. The overlapping portion of the second scan signal line 22 as well as the gate block 22- 1 and the second active layer may serve as a gate electrode of the second transistor T 2 to form the second transistor T 2 of the double-gate structure.In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission control line 24 may extend along the first direction X to the frame region on one or two sides of the display region, are connected to corresponding gate drive circuit, and output a corresponding turn-on control signal according to a set drive timing.(13) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating thin film and a second conductive thin film sequentially on the base substrate on which the foregoing pattern is formed, patterning the second conductive thin film by a patterning process, forming a third insulating layer covering the first conductive layer, and disposing the second conductive layer pattern on the third insulating layer, as illustrated in FIGS. 10A and 10B. FIG. 10B is a schematic illustration of the second conductive layer in FIG. 10A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal layer (GATE 2).In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a first initial signal line 31, a second initial signal line 32, a second pole plate 33 of the first storage capacitor, and a fourth pole plate 34 of the second storage capacitor, a pole plate connection line 35, and the shield electrode 37.In an exemplary embodiment, the shape of the first scan signal line 31, the second scan signal line 32 may be a line shape in which the main body part extends along the first direction X. The first initial signal line 31 may be located between the second scan signal line 22 and the third scan signal line 23 of the circuit unit. The second initial signal line 32 may be located on a side of the first circuit unit scan signal line 21 opposite to the light emission control line 24.In an exemplary embodiment, the profile shape of the second pole plate 33 may be a rectangular shape. The corners of the rectangular shape may be rounded and the second pole plate 33 is located between the second scan signal line 22 and the light emission control line 24 of the circuit unit. The orthographic projection of the second pole plate 33 on the base substrate overlaps at least partially with the orthographic projection of the first pole plate 25 on the base substrate. The second pole plate 33 serves as another pole plate of the first storage capacitor. The first pole plate 25 and the second pole plate 33 form the first storage capacitor of the pixel driver circuit.In an exemplary embodiment, the profile shape of the fourth pole plate 34 may be a rectangular shape. The corners of the rectangular shape may be rounded and the fourth pole plate 34 is located between the second scan signal line 22 and the light emission control line 24 of the circuit unit. The orthographic projection of the fourth pole plate 34 on the base substrate overlaps at least partially with the orthographic projection of the third pole plate 18 on the base substrate. The fourth pole plate 34 serves as another pole plate of the second storage capacitor. The third pole plate 18 and the fourth pole plate 34 form a second storage capacitor of the pixel driver circuit.In an exemplary embodiment, the area of the orthographic projection of the fourth pole plate 34 on the base substrate may be smaller than the area of the orthographic projection of the first pole plate 25 on the base substrate, and the area of the orthographic projection of the fourth pole plate 34 on the base substrate may be smaller than the area of the orthographic projection of the second pole plate 33 on the base substrate.In an exemplary embodiment, the second pole plate 33 and the fourth pole plate 34 may be connected to each other into an integral structure. The overall profile shape of the second pole plate 33 and the fourth pole plate 34 of the integral structure may be rectangular.In an exemplary embodiment, the pole plate connection line 35 may be disposed on a side of the fourth pole plate 34 in the first direction X or on a side of the second pole plate 33 in the direction opposite to the first direction X. The first end of the pole plate connection line 35 is connected to the fourth pole plate 34 of the circuit unit, the second end of the pole plate connection line 35 extends along the first direction X and is thereafter connected to the second pole plate 33 of an adjacent circuit unit, or the first end of the pole plate connection line 35 is connected to the second pole plate 33 of the circuit unit, the second end of the pole plate connection line 35 extends along the direction opposite to the first direction X and is thereafter connected to the fourth pole plate 34 of an adjacent circuit unit. Thereby, the second pole plate 33 and the fourth pole plate 34 of adjacent circuit units are connected to each other in a unit row. In an exemplary embodiment, via pole plate connection lines, the second pole plates and the fourth pole plates of a plurality of circuit units in a unit row may be connected to each other and form an integral structure. The second pole plate and the fourth pole plate of the integral structure may be multiplexed as current signal connection lines to ensure that a plurality of second pole plates and fourth pole plates in a unit row have the same potential, which benefits the improvement of homogeneity of the field, thereby preventing a poor appearance of the display substrate and ensuring the display effect of the display substrate.In an exemplary embodiment, the second pole plate 33 is provided with an opening 36, and the opening 36 may be located at the center of the second pole plate 33. The opening 36 may be rectangular, so that the second pole plate 33 forms an annular structure. The opening 36 exposes the third insulating layer covering the first pole plate 25, and the orthographic projection of the first pole plate 25 on the base substrate includes the orthographic projection of the opening 36 on the base substrate. In an exemplary embodiment, the opening 36 is configured to receive a subsequently formed first through hole. The first through hole is located in the opening 36 and exposes the first pole plate 25 so that a subsequently formed first connection electrode is connected to the first pole plate 25.In an exemplary embodiment, the shield electrode 37 may be located on a side of the first initial signal line 31 facing the first scan signal line 22, and is connected to the first initial signal line 31. The orthographic projection of the shield electrode 37 on the base substrate overlaps at least partially with the orthographic projection of the second active layer between two gate electrodes of the second transistor T 2 on the base substrate. The shield electrode 37 is configured to shield the influence of the data surge on the second transistor T 2, to avoid the influence of the data surge on the normal operation of the pixel driving circuit, and to improve the display effect.(14) forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating film pattern may include: depositing a fourth insulating film on the base substrate on which the foregoing pattern is formed, patterning the fourth insulating film by a patterning process, forming a fourth insulating film covering the second conductive layer. A plurality of through holes are provided in each circuit unit as shown in FIG. 11.In an exemplary embodiment, the plurality of through-holes of each circuit unit in the display area include at least: a first through-hole V 1, a second through-hole V 2, a third through-hole V 3, a fourth through-hole V 4, a fifth through-hole V 5, a sixth through-hole V 6, a seventh through-hole V 7, an eighth through-hole V 8, a ninth through-hole V 9, a tenth through-hole V 10, an eleventh through-hole V 11, and a twelfth through-hole V 12.In an exemplary embodiment, the orthographic projection of the first through hole V 1 on the base substrate is within the perimeter of the orthographic projection of the opening 36 of the second pole plate 33 on the base substrate. The fourth insulating layer and the third insulating layer in the first through hole V1 are etched away to expose the surface of the first pole plate 25. The first through hole V 1 is configured such that the second pole of the subsequently formed first transistor T 1 is connected to the first pole plate 25 via the through hole.In an exemplary embodiment, the orthographic projection of the second through hole V 2 on the base substrate is within the perimeter of the orthographic projection of the second pole plate 33 on the base substrate. The fourth insulating layer in the second through hole V2 is etched away so that the surface of the second electrode plate 33 is exposed. The second through hole V 2 is configured such that the first pole of the subsequently formed fifth transistor T 5 is connected to the second pole plate 33 via the through hole.In an exemplary embodiment, the orthographic projection of the third through hole V 3 on the base substrate is within the scope of the orthographic projection of the first region of the fifth active layer on the base substrate. The fourth insulating layer, the third insulating layer and the second insulating layer in the third through hole V 3 are etched away so as to expose the surface of the first region of the fifth active layer. The third via V 3 is configured such that the first pole of the subsequently formed fifth transistor T 5 is connected to the first region of the fifth active layer via the via.In an exemplary embodiment, the orthographic projection of the fourth via V 4 on the base substrate is within the scope of the orthographic projection of the second region of the sixth active layer (also, the second region of the seventh active layer) on the base substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the fourth through hole V 4 are etched away so as to expose the surface of the second region of the sixth active layer. The fourth via V 4 is configured such that the second pole of the subsequently formed sixth transistor T 6 (also the second pole of the seventh transistor T 7) is connected to the sixth active layer via the via.In an exemplary embodiment, the orthographic projection of the fifth via V 5 on the base substrate is within the scope of the orthographic projection of the first region of the fourth active layer on the base substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the fifth through hole V 5 are etched away so as to expose the surface of the first region of the fourth active layer. The fifth via V 5 is configured such that the first pole of the subsequently formed fourth transistor T 4 is connected to the first region of the fourth active layer via the via.In an exemplary embodiment, the orthographic projection of the sixth through hole V 6 on the base substrate is within the scope of the orthographic projection of the first region of the seventh active layer on the base substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth through hole V 6 are etched away so as to expose the surface of the first region of the seventh active layer. The sixth via V 6 is configured such that the first pole of the subsequently formed seventh transistor T 7 is connected to the first region of the seventh active layer via the via.In an exemplary embodiment, the orthographic projection of the seventh through hole V 7 on the base substrate is within the scope of the orthographic projection of the first region of the third active layer (also, the second region of the fifth active layer) on the base substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh through hole V 7 are etched away so as to expose the surface of the first region of the third active layer. The seventh through hole V 7 is configured such that the first pole of the subsequently formed third transistor T 3 (also the second pole of the fifth transistor T 5) is connected to the first region of the third active layer via the through hole.In an exemplary embodiment, the orthographic projection of the eighth through hole V 8 on the base substrate is within the scope of the orthographic projection of the second region of the fourth active layer on the base substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the eighth through hole V 8 are etched away so as to expose the surface of the second region of the fourth active layer. The eighth through hole V 8 is configured such that the second pole of the fourth transistor T 4 formed subsequently is connected to the second region of the fourth active layer via the through hole.In an exemplary embodiment, the orthographic projection of the ninth through hole V 9 on the base substrate is within the scope of the orthographic projection of the second region of the first active layer (also, the first region of the second active layer) on the base substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the ninth through hole V 9 are etched away so as to expose the surface of the second region of the first active layer. The ninth through hole V 9 is configured such that the second pole of the subsequently formed first transistor T 1 (also the first pole of the second transistor T 2) is connected to the first active layer via the through hole.In an exemplary embodiment, the orthographic projection of the tenth through hole V 10 on the base substrate is within the scope of the orthographic projection of the first region of the first active layer on the base substrate. The fourth insulating layer, the third insulating layer, and the second insulating layer in the tenth through hole V 10 are etched away so as to expose the surface of the first region of the first active layer. The tenth through hole V 10 is configured such that the first pole of the subsequently formed first transistor T 1 is connected to the first region of the first active layer via the through hole.In an exemplary embodiment, the orthographic projection of the eleventh via V 11 on the base substrate is within the scope of the orthographic projection of the first initial signal line 31 on the base substrate. The fourth insulating film in the eleventh through hole V 11 is etched away so as to expose the surface of the first initial signal line 31. The eleventh through hole V 11 is configured such that the first pole of the subsequently formed first transistor T 1 is connected to the first initial signal line 31 via the through hole.In an exemplary embodiment, the orthographic projection of the twelfth through hole V 12 on the base substrate is within the scope of the orthographic projection of the second initial signal line 32 on the base substrate. The fourth insulating layer in the twelfth through hole V 12 is etched away so as to expose the surface of the second initial signal line 32. The twelfth through hole V 12 is configured such that the first pole of the subsequently formed seventh transistor T 7 is connected to the second initial signal line 32 via the through hole.(15) forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the base substrate on which the foregoing pattern is formed; patterning the third conductive thin film by a patterning process; forming a third conductive layer disposed on the fourth insulating layer, as illustrated in FIGS. 12A and 12B. FIG. 12B is a schematic illustration of the third conductive layer in FIG. 12A. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal layer (SD 1).In an exemplary embodiment, the third conductive layer patterns of the plurality of circuit units in the display area may each include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, the sixth connection electrode 46, the seventh connection electrode 47, and a fifth pole plate 48.In an exemplary embodiment, the shape of the first connection electrode 41 may be a strip shape in which the main body part extends along the second direction Y. The first end of the first connection electrode 41 is connected to the first pole plate 25 via the first through hole V 1, the second end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) via the ninth through hole V 9. In an exemplary embodiment, the first connection electrode 41 may serve as the second node N 2 of the pixel driving circuit of the present disclosure, and the first connection electrode 41 may simultaneously serve as the second pole of the first transistor T 1 and the first pole of the second transistor T 2 such that the second pole of the first transistor T 1, the first pole of the second transistor T 2, and the first pole plate 25 (the gate electrode of the third transistor T 3) have the same potential.In an exemplary embodiment, the shape of the second connection electrode 42 may be a strip shape in which the main body part extends along the second direction Y. The first end of the second connection electrode 42 is connected to the second pole plate 33 via the second through hole V 2, and the second end of the second connection electrode 42 is connected to the first region of the fifth active layer via the third through hole V 3. In an exemplary embodiment, the second connection electrode 42 may serve as the first pole of the fifth transistor T 5 such that the second pole plate 33, the fourth pole plate 34, and the first pole of the fifth transistor T 5 have the same potential. The second connection electrode 42 is configured to be connected to the subsequently formed first power line. Because the second pole plate 33 has the potential of the first power line and the first pole plate 25 has the potential of the second node N 2, the first pole plate 25 and the second pole plate 33 form the first storage capacitor of the pixel driving circuit.In an exemplary embodiment, the shape of the third connection electrode 43 may be a strip shape in which the main body part extends along the second direction Y. The first end of the third connection electrode 43 is connected to the first region of the third active layer via the seventh through hole V 7, and the second end of the third connection electrode 43 is connected to the second region of the fourth active layer via the eighth through hole V 8. In an exemplary embodiment, the third connection electrode 43 may serve as the first node N 1 of the pixel driving circuit of the present disclosure, and the third connection electrode 43 may simultaneously serve as the first pole of the third transistor T 3, the second pole of the fourth transistor T 4, and the second pole of the fifth transistor T 5, such that the first pole of the third transistor T 3, the second pole of the fourth transistor T 4, and the second pole of the fifth transistor T 5 have the same potential.In an exemplary embodiment, the shape of the fourth connection electrode 44 may be a rectangular shape, and the fourth connection electrode 44 is connected to the first region of the fourth active layer via the fifth through hole V 5. The fourth connection electrode 44 may serve as the first pole of the fourth transistor T 4, and the fourth connection electrode 44 is configured to be connected to the eleventh connection electrode formed subsequently.In an exemplary embodiment, the shape of the fifth connection electrode 45 may be a rectangular shape, and the fifth connection electrode 45 is connected to the second region of the sixth active layer (also, the second region of the seventh active layer) via the fourth through hole V 4. The fifth connection electrode 45 may serve as the second pole of the sixth transistor T 6 (also the second pole of the seventh transistor T 7), and the fifth connection electrode 45 is configured to be connected to the twelfth connection electrode formed subsequently.In an exemplary embodiment, the shape of the sixth connection electrode 46 may be a strip shape in which the main body part extends along the second direction Y. The first end of the sixth connection electrode 46 is connected to the first active layer region via the tenth via hole V 10, and the second end of the sixth connection electrode 46 is connected to the first initial signal line 31 via the eleventh via hole V 11. The sixth connection electrode 46 may serve as the first pole of the first transistor T 1, so that the first initial signal line 31 may be allowed to write the first initial signal to the first pole of the first transistor T 1.In an exemplary embodiment, the shape of the seventh connection electrode 47 may be a strip shape in which the main body part extends along the second direction Y. The first end of the seventh connection electrode 47 is connected to the first region of the seventh active layer via the sixth via hole V 6, and the second end of the seventh connection electrode 47 is connected to the second initial signal line 32 via the twelfth via hole V 12. The seventh connection electrode 47 may serve as the first pole of the seventh transistor T 7, so that the second initial signal line 32 may be allowed to write the second initial signal to the first pole of the seventh transistor T 7.In an exemplary embodiment, the shape of the fifth pole plate 48 may be a rectangular shape. The corners of the rectangular shape may be rounded and the fifth pole plate 48 may be located on a side of the circuit unit third connection electrode 43 in the opposite direction to the second direction Y (on the side opposite to the fourth transistor T 4). The orthographic projection of the fifth pole plate 48 on the base substrate overlaps, at least in part, with the orthographic projection of the fourth pole plate 34 on the base substrate. The fifth pole plate 48 may serve as another pole plate of the second storage capacitor. The fourth pole plate 34 and the fifth pole plate 48 form a further second storage capacitor of the pixel driver circuit.In an exemplary embodiment, the area of the orthographic projection area of the fifth pole plate 48 on the base substrate may be smaller than the area of the orthographic projection area of the first pole plate 25 on the base substrate.In an exemplary embodiment, the third connection electrode 43 and the fifth pole plate 48 may be connected to each other and form an integral structure. Since the third pole plate 18 is directly connected to the second region of the fifth active layer, the fifth pole plate 48 is connected to the third connection electrode 43 and the third connection electrode 43 is connected via a through hole to the first region of the fifth active layer, the third pole plate 18 and the fifth pole plate 48 have the same potential, the fourth pole plate 34 has the potential of the first power supply, the third pole plate 18 and the fourth pole plate 34 form a second storage capacitor of the pixel driver circuit, the fifth pole plate 48 and the fourth pole plate 34 form a further second storage capacitor of the pixel driver circuit, and the two second storage capacitors are connected in parallel and form a complete second storage capacitor of the pixel driver circuit. In the present disclosure, by using second storage capacitors connected in parallel, not only the wiring space is effectively utilized but also the capacitance value of the second storage capacitor is effectively increased, thereby more sufficiently writing the data voltage and ensuring the quality of data writing.In an exemplary embodiment, the capacitance value of the second storage capacitor may be smaller than the capacitance value of the first storage capacitor.In an exemplary embodiment, the capacitance value of the second storage capacitor may be about 20% to 70% of the capacitance value of the first storage capacitor. For example, the capacitance value of the second storage capacitor 20 may be about 30% to 50% of the capacitance value of the first storage capacitor 10.In some possible example embodiments, the second storage capacitor may include only the third pole plate 18 and the fourth pole plate 34, or the second storage capacitor may include only the fifth pole plate 48 and the fourth pole plate 34, which is not limited herein in the present disclosure.In an exemplary embodiment, the third conductive layer pattern of at least one circuit unit may further include a first initial electrode 71 and a second initial electrode 72.In an exemplary embodiment, the shape of the first initial electrode 71 may be a strip shape in which the main body part extends along the first direction X, and the first initial electrode 71 may be disposed on a side of the sixth connection electrode 46 in the first direction X. The first end of the first initial electrode 71 is connected to the sixth connection electrode 46, and the second end of the first initial electrode 71 extends along the first direction X to an adjacent circuit unit. The first initial electrode 71 is configured to be connected to the first connection line formed subsequently, so that the first initial signal line and the first connection line form a mesh connection structure. For example, the first end of the first initial electrode 71 is connected to the sixth connection electrode 46 in the circuit unit of the Nth column. The second end of the first initial electrode 71 is located in the circuit unit of the N+1th column, and is configured to be connected to the first connection line subsequently formed in the circuit unit of the N+1th column.In an exemplary embodiment, the shape of the second initial electrode 72 may be a block shape. The second initial electrode 72 may be disposed on a side of the seventh connection electrode 47 in the direction opposite to the first direction X, and is connected to the seventh connection electrode 47. The second initial electrode 72 is configured to be connected to the second connection line formed subsequently, so that the second initial signal line and the second connection line form a mesh connection structure. For example, the second initial electrode 72 may be located in the Nth column circuit unit, is connected to the sixth connection electrode 46 in the Nth column circuit unit, and is configured to be connected to the second connection line subsequently formed in the Nth column circuit unit.(16) forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating film pattern may include: depositing a fifth insulating film on the base substrate on which the foregoing pattern is formed, patterning the fifth insulating film by a patterning process, forming a fifth insulating film covering the third conductive layer. A plurality of through holes are provided in each circuit unit as shown in FIG. 13.In an exemplary embodiment, the plurality of through holes of each circuit unit in the display area includes at least: a twenty-first through hole V 21, a twenty-second through hole V 22, and a twenty-third through hole V 23.In an exemplary embodiment, the orthographic projection of the twenty-first through hole V 21 on the base substrate is within the perimeter of the orthographic projection of the second connection electrode 42 on the base substrate. The fifth insulating layer in the twenty-first through hole V 21 is removed so as to expose the surface of the second connection electrode 42. The twenty-first through hole V 21 is configured such that the first power line formed subsequently is connected to the second connection electrode 42 through the through hole.In an exemplary embodiment, the orthographic projection of the twenty-second through hole V 22 on the base substrate is within the perimeter of the orthographic projection of the fourth connection electrode 44 on the base substrate. The fifth insulating layer in the twenty-second through hole V 22 is removed so as to expose the surface of the fourth connection electrode 44. The twenty-second through hole V 22 is configured such that the eleventh connection electrode formed subsequently is connected to the fourth connection electrode 44 through the through hole.In an exemplary embodiment, the orthographic projection of the twenty-third through hole V 23 on the base substrate is within the circumference of the orthographic projection of the fifth connection electrode 45 on the base substrate, the fifth insulating layer in the twenty-third through hole V 23 is removed so as to expose the surface of the fifth connection electrode 45, and the twenty-third through hole V 23 is configured so as to connect the twelfth connection electrode formed subsequently to the fifth connection electrode 45 through the through hole.In an exemplary embodiment, the fifth insulation layer of at least one circuit unit is further provided with a twenty-fourth through hole V 24, and the fifth insulation layer of at least one other circuit unit is further provided with a twenty-fifth through hole V 25.In an exemplary embodiment, the orthographic projection of the twenty-fourth via hole V 24 on the base substrate is within the scope of the orthographic projection of the first initial electrode 71 on the base substrate. The fifth insulating layer in the twenty-fourth through hole V 24 is removed so as to expose the surface of the first initial electrode 71, and the twenty-fourth through hole V 24 is configured so that the first connection line formed subsequently is connected to the first initial electrode 71 through the through hole. For example, the twenty-fourth via hole V 24 may be located in a circuit unit of the N+1-th column, so that the first connection line located in the circuit unit of the N+1-th column is connected to first initial electrodes 71 in a plurality of unit rows via a plurality of twenty-fourth via holes V 24.In an exemplary embodiment, the orthographic projection of the twenty-fifth via V 25 on the base substrate is within the perimeter of the orthographic projection of the second initial electrode 72 on the base substrate. The fifth insulating layer in the twenty-fifth through hole V 25 is removed so as to expose the surface of the second initial electrode 72, and the twenty-fifth through hole V 25 is configured so that the second connection line formed subsequently is connected to the second initial electrode 72 through the through hole. For example, the twenty-fifth via hole V 25 may be located in a circuit unit of the N-th column, so that the second connection line located in the circuit unit of the N-th column is connected to second initial electrodes 72 in a plurality of unit rows via a plurality of twenty-fifth via holes V 25.(17) forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive thin film on the base substrate on which the foregoing pattern is formed, patterning the fourth conductive thin film by a patterning process, forming a fourth conductive layer disposed on the fifth insulating layer, as illustrated in FIGS. 14A and 14B. FIG. 14B is a schematic illustration of the fourth conductive layer in FIG. 14A. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal layer (SD 2).In an exemplary embodiment, the fourth conductive layer patterns of a plurality of circuit units in the display area may each include: an eleventh connection electrode 51, a twelfth connection electrode 52, and a first power line 53.In an exemplary embodiment, the shape of the eleventh connection electrode 51 may be a rectangular shape. The eleventh connection electrode 51 is connected to the fourth connection electrode 44 via the twenty-second through hole V 22, and the eleventh connection electrode 51 is configured to be connected to a data signal line formed thereafter.In an exemplary embodiment, the shape of the twelfth connection electrode 52 may be a rectangular shape. The twelfth connection electrode 52 is connected to the fifth connection electrode 45 via the twenty-third through hole V 23, and the twelfth connection electrode 52 is configured to be connected to a subsequently formed anode connection electrode.In an exemplary embodiment, the shape of the first power line 53 may be a folded line shape in which the main body part extends along the second direction Y. The first power line 53 is connected to the second connection electrode 42 via the twenty-first through hole V 21. Since the second connection electrode 42 is connected to the second pole plate and the first region of the fifth active layer via through holes, respectively, the first power line 53 is allowed to write the current signal to the first pole of the fifth transistor T 5, and the first power line 53, the second pole plate of the first storage capacitor, and the fourth pole plate of the second storage capacitor are allowed to have the same potential.In an exemplary embodiment, the orthographic projection of the first power line 53 on the base substrate overlaps at least partially with the orthographic projection of the first connection electrode 41 on the base substrate. The first power line 53 can effectively shield the influence of other signals in the pixel driving circuit on the second node K 2, so that the influence of the data surge on the potential of the second node K 2 of the pixel driving circuit is avoided and the display effect is improved.In the exemplary embodiment, since only a relatively thin fifth insulating layer is present between the third conductive layer and the fourth conductive layer, the parasitic capacitance between the first connection electrode 41 and the first power line 53 is relatively large, whereby the second node N 2 can be more stabilized.In an exemplary embodiment, the first power lines 53 may be configured with unequal widths. The first power lines 53 having unequal widths can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the first power line and the data signal line.In an exemplary embodiment, the fourth conductive layer pattern of at least one circuit unit may further include a first connection line 81.In an exemplary embodiment, the first connection line 81 may be located in a circuit unit of the N+1th column. The shape of the first connection line 81 may be a line shape in which the main body part extends along the second direction Y. The first connection line 81 is connected to the first initial electrode 71 via the twenty-fourth through hole V 24. Since the first initial electrode 71 is connected to the sixth connection electrode 46, and the sixth connection electrode 46 is connected to the first initial signal line 31 via a through hole, the first initial signal line 31 whose main body part extends along the first direction X and the first connection line 81 whose main body part extends along the second direction Y are allowed to be connected to each other. Thereby, the first connection line 81 can be connected to first initial signal lines 31 in a plurality of unit lines via the first initial electrode 71 and the sixth connection electrode 46, so that the first initial signal lines 31 and the first connection lines 81 form a net-like net structure in the display area for transmitting the first initial signal, whereby not only the resistance of the first initial signal line can be effectively reduced and the voltage drop of the first initial signal can be reduced, but also the uniformity of the first initial signals in the display substrate can be effectively improved and the uniformity of display can be effectively improved, the display property and the display quality can be improved.In an exemplary embodiment, the fourth conductive layer pattern of at least one circuit unit may further include a second connection line 82.In an exemplary embodiment, the second connection line 82 may be located in a circuit unit of the Nth column. The shape of the second connection line 88 may be a line shape in which the main body part extends along the second direction Y. The second connection line 82 is connected to the second initial electrode 72 via the twenty-fifth through hole V 25. Since the second initial electrode 72 is connected to the seventh connection electrode 47, and the seventh connection electrode 47 is connected to the second initial signal line 32 via a through hole, the second initial signal line 32 whose main body part extends along the first direction X and the second connection line 82 whose main body part extends along the second direction Y are allowed to be connected to each other. Thereby, the second connection line 82 can be connected to second initial signal lines 32 in a plurality of unit lines via the second initial electrode 72 and the seventh connection electrode 47, so that the second initial signal lines 32 and the second connection lines 82 form a net-like net structure in the display area for transmitting the second initial signal, whereby not only the resistance of the second initial signal line can be effectively reduced and the voltage drop of the second initial signal can be reduced, but also the uniformity of the second initial signals in the display substrate can be effectively improved and the uniformity of display can be effectively improved, the display property and the display quality can be improved.In an exemplary embodiment, the first connection line 81 may be provided in an odd-numbered unit column circuit unit (the N+1-th column), and the second connection line 82 may be provided in an even-numbered unit column circuit unit (the N-th column); or the first connection line 81 may be provided in an even-numbered unit column circuit unit (the N-th column), and the second connection line 82 may be provided in an odd-numbered unit column circuit unit (the N+1-th column).In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 of the second conductive layer may be provided in each unit row, and the first connection line 81 and the second connection line 82 of the fourth conductive layer are provided alternately in each unit column. Since the plurality of first connection lines 81 in the plurality of odd-numbered unit columns are respectively connected to the plurality of first initial signal lines 31 in the plurality of unit rows, and the plurality of second connection lines 82 in the plurality of even-numbered unit columns are respectively connected to the plurality of second initial signal lines 32 in the plurality of unit rows, a mesh structure for transmitting the first initial signal and a mesh structure for transmitting the second initial signal are formed simultaneously in the display area, thereby reducing the voltage drop of the first initial signal and the second initial signal. Thus, the second node N2 can be reset in a shorter time, which is advantageous for the high frequency display, and the reset time of the fourth node N4 is shorter, which benefits the increase of the display effect of low gray levels.(18) forming a first planarization layer pattern. In an exemplary embodiment, forming the first planarization layer pattern may include: depositing a first planarization thin film on the base substrate on which the foregoing pattern is formed; patterning the first planarization thin film by a patterning process; forming a planarization layer covering the fourth conductive layer. The planarization layer is provided with a plurality of through holes as shown in FIG. 15.In an exemplary embodiment, the plurality of through-holes of each circuit unit in the display area includes at least: a thirty-first through-hole V 31 and a thirty-second through-hole V 32.In an exemplary embodiment, the orthographic projection of the thirty-first through hole V 31 on the base substrate is within the scope of the orthographic projection of the eleventh connection electrode 51 on the base substrate. The first planarization layer in the thirty-first through hole V 31 is removed so as to expose the surface of the eleventh connection electrode 51, and the thirty-first through hole V 31 is configured so that the data signal line formed subsequently is connected to the eleventh connection electrode 51 through the through hole.In an exemplary embodiment, the orthographic projection of the thirty-second through hole V 32 on the base substrate is within the perimeter of the orthographic projection of the twelfth connection electrode 52 on the base substrate. The first planarization layer in the thirty-second through hole V 32 is removed so as to expose the surface of the twelfth connection electrode 52, and the thirty-second through hole V 32 is configured so that the anode connection electrode formed subsequently is connected to the thirty-second through hole V 32 via the through hole.(19) forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on the base substrate on which the foregoing pattern is formed, patterning the fifth conductive thin film by a patterning process, forming a fifth conductive layer disposed on the first planarization layer, as illustrated in FIGS. 16A and 16B. FIG. 16B is a schematic illustration of the fifth conductive layer in FIG. 16A. In an exemplary embodiment, the fifth conductive layer may be referred to as a third source-drain metal layer (SD 3).In an exemplary embodiment, the fifth conductive layer pattern of each circuit unit in the display area may include: a data signal line 61 and an anode connection electrode 62.In an exemplary embodiment, the shape of the data signal line 61 may be a straight line shape with the main body part extending along the second direction Y. The data signal line 61 is connected to the eleventh connection electrode 51 via the thirty-first through hole V 31. Since the eleventh connection electrode 51 is connected to the fourth connection electrode 44 via a via hole and the fourth connection electrode 44 is connected to the first region of the fourth active layer via a via hole, the data signal line 61 is allowed to write the data signal to the first pole of the fourth transistor T 4. In the present disclosure, signal noise caused by disposing the data signal line and the initial signal line on the same conductive layer can be avoided by providing the data signal line on the fifth conductive layer and providing the first connection line and the second connection line on the fourth conductive layer. Since the fifth conductive layer and the fourth conductive layer are provided spaced apart by a relatively thick first planarization layer therebetween, the parasitic capacitance between the data signal lines and the signal lines and electrodes in other film layers can be reduced, thereby not only facilitating the improvement in the quality of data writing, but also reducing the influence of the data jumping voltage on key nodes of the pixel driving circuit.In an exemplary embodiment, the orthographic projection of the at least one data signal line 61 on the base substrate overlaps at least partially with the orthographic projection of the first connection line 81 on the base substrate, and the orthographic projection of the at least one data signal line 61 on the base substrate overlaps at least partially with the orthographic projection of the second connection line 82 on the base substrate.In an exemplary embodiment, the orthographic projection of the at least one data signal line 61 on the base substrate may be within the perimeter of the orthographic projection of the first connection line 81 on the base substrate, and the orthographic projection of the at least one data signal line 61 on the base substrate may be within the perimeter of the orthographic projection of the second connection line 82 on the base substrate, i.e., the fifth conductive layer data signal line and the fourth conductive layer initial signal connection line are fully overlapped to increase the transmission rate of the display substrate.In an exemplary embodiment, the shape of the anode connection electrode 62 may be a rectangular shape. The anode connection electrode 62 is connected to the twelfth connection electrode 52 via the thirty-second through hole V 32. Since the twelfth connection electrode 52 is connected to the fifth connection electrode 45 via a through hole and the fifth connection electrode 45 is connected to the second region of the sixth active layer via a through hole, the anode connection electrode 62 is allowed to be connected to the second pole of the sixth transistor T 6. In an exemplary embodiment, the anode connection electrode 62 is configured to be connected to the subsequently formed anode, which may allow the pixel driving circuit to drive the light emitting device.The subsequent manufacturing process may include: forming a second planarization layer pattern. In an exemplary embodiment, forming the second planarization layer pattern may include: applying a second planarization thin film to the base substrate on which the foregoing pattern is formed, patterning the second planarization thin film by a patterning process, forming a second planarization layer covering the fifth conductive layer. The second planarization layer is provided with a plurality of anode through holes. The orthographic projection of the anode via holes on the base substrate may be within the perimeter of the orthographic projection of the anode connection electrode on the base substrate. The second planarization layer in the anode via holes is removed to expose the surface of the anode connection electrode, and the anode via hole is configured to connect the subsequently formed anode to the anode connection electrode through the via hole.Until now, the driver circuit layer is formed and manufactured on the base substrate. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, and each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line and a third scan signal line, a light emission control line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a planarization layer, a fifth conductive layer, and a second planarization layer, which are provided sequentially stacked on the base substrate.In an exemplary embodiment, the base substrate may be a flexible base substrate or a rigid base substrate. The rigid substrate may be one or more of the following materials, and is not limited thereto: glass, quartz, and the flexible substrate may be one or more of the following materials: polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylester, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. In an exemplary embodiment, the flexible base substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer that are stacked, wherein as the material of the first flexible material layer and the second flexible material layer, a material such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated soft polymer film or the like may be used, as the material of the first inorganic material layer and the second inorganic material layer, silicon nitride (SiNx) or silicon oxide (SiOx), or the like may be used to improve the resistance of the base substrate to water and oxygen, and wherein as the material of the semiconductor layer, amorphous silicon (a-si) may be used.In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of a metallic material such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, and the like, The fourth insulating layer and the fifth insulating layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which may be a single layer, a multilayer, or a composite layer. The first insulating layer is referred to as a buffer layer (buffer layer), the second insulating layer and the third insulating layer are referred to as gate insulating layers (GI layers), the fourth insulating layer is referred to as an interlayer insulating layer (ILD layer), and the fifth insulating layer is referred to as a passivation layer (PVX layer). The first planarization layer and the second planarization layer may be made of an organic material such as resin. The active layer may be made of indium gallium zinc oxide (a-IGZO) amorphous materials, zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene or polythiophene, i.e., the present disclosure is suitable for the transistors manufactured on the basis of oxide technology, silicon technology or organic technology.In an exemplary embodiment, after the fabricated fabrication of the driver circuit layer, a light emitting structure layer and a packaging structure layer may be sequentially fabricated on the driver circuit layer, which is not repeated here.From the above-described structure and manufacturing process of the display substrate, it can be seen that the data writing phase and the threshold compensation phase are separated, both the data writing time can be prolonged, and a sufficient compensation time can be ensured, the problems of the present solution such as insufficient charging time and insufficient compensation time or the like can be effectively improved, clearer limitation of various grayscale images can be ensured, image quality displayed at high frequencies can be guaranteed, the display effect and display quality are improved by controlling the fourth transistor T 4 through the first scan signal line S 1, controlling the second transistor T 2 through the second scan signal line S 2, and providing the second storage capacitor in the pixel driving circuit.In the present disclosure, a first initial signal line and a second initial signal line whose main body parts extend along the first direction are provided in the second conductive layer, a first connection line and a second connection line whose main body parts extend along the second direction are provided in the fourth conductive layer, the first connection line is connected to the first initial signal line, the second connection line is connected to the second initial signal line, so that the first initial signal line transmitting the first initial signal forms a mesh structure, and the second initial signal line transmitting the second initial signal forms a mesh structure, whereby not only the resistances of the first and second initial signal lines can be effectively reduced and the voltage drops of the first and second initial voltages can be reduced, Therefore, the uniformity of the first and second initial voltages in the display substrate can be effectively improved and the uniformity of display can be effectively improved, the display property and the display quality can be increased, but the second node N 2 can also be reset in a shorter time, which is advantageous for the high-frequency display; the reset time of the fourth node N 4 is shorter, which promotes the increase of the display effect of low gray levels. In the present disclosure, a first storage capacitor is formed by the first conductive layer and the second conductive layer, two second storage capacitors connected in parallel are formed by the semiconductor layer, the second conductive layer, and the third conductive layer, whereby the capacitance value of the second storage capacitor is effectively increased, the data voltage can be written more sufficiently, and the quality of data writing is ensured. The manufacturing process of the present disclosure may be well compatible with the existing manufacturing process. The process is easy to realize, easy to implement, has high production efficiency, low production cost, and high yield.FIG. 17 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of pixel driving circuits in two circuit units in the display area. As shown in FIG. 17, the structure of the pixel driving circuit in this exemplary embodiment is basically the same as that in the foregoing exemplary embodiments. The difference is that the second storage capacitor 20 in this embodiment is composed of a first conductive layer and a second conductive layer.In an exemplary embodiment, the first end of the first storage capacitor 10 may include a first pole plate and the second end of the first storage capacitor 10 may include a second pole plate. The first pole plate may be disposed in the first conductive layer and the second pole plate may be disposed in the second conductive layer. The orthographic projection of the second pole plate on the base substrate overlaps at least partially with the orthographic projection of the first pole plate on the base substrate.In an exemplary embodiment, the first end of the second storage capacitor 20 may include a third pole plate and the second end of the second storage capacitor 20 may include a fourth pole plate. The third pole plate may be disposed in the first conductive layer, and the fourth pole plate may be disposed in the second conductive layer. The orthographic projection of the fourth pole plate on the base substrate overlaps at least partially with the orthographic projection of the third pole plate on the base substrate.In an exemplary embodiment, the capacitance value of the second storage capacitor 20 may be smaller than the capacitance value of the first storage capacitor 10.In an exemplary embodiment, the capacitance value of the second storage capacitor 20 may be about 20% to 70% of the capacitance value of the first storage capacitor 10. For example, the capacitance value of the second storage capacitor 20 may be about 30% to 50% of the capacitance value of the first storage capacitor 10.In an exemplary embodiment, the second conductive layer may further include a first pole plate connection block 38. The second pole plate and the fourth pole plate may be connected to each other via the first pole plate connection block 38.In an exemplary embodiment, the third conductive layer may further include a third connection electrode 43 (a first node) and a second pole plate connection block 49. The third connection electrode 43 is connected to the second pole plate connection block 49. The second pole plate connection block 49 is connected to the third pole plate via a through hole.In an exemplary embodiment, the manufacturing process of the display substrate of the present disclosure may include the following operations.(21) forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include depositing a first insulating thin film and a semiconductor film sequentially on the base substrate, patterning the semiconductor film by a patterning process, forming a first insulating layer covering the base substrate, and disposing the semiconductor layer on the first insulating layer as illustrated in FIG. 18.In an exemplary embodiment, the semiconductor layer of each circuit unit in the display area may include at least: a first active layer 11 of the first transistor T 1, a second active layer 12 of the second transistor T 2, a third active layer 13 of the third transistor T 3, a fourth active layer 14 of the fourth transistor T 4, a fifth active layer 15 of the fifth transistor T 5, a sixth active layer 16 of the sixth transistor T 6, and a seventh active layer 17 of the seventh transistor T 7.In an exemplary embodiment, the structures and connection relationships of the first active layers 11 to the seventh active layers 17 are basically the same as the structures and connection relationships according to the preceding exemplary embodiments. The difference is that since the semiconductor layer does not form a third pole plate, the first third active layer region 13- 1 and the second fifth active layer region 15- 2 are not connected to the third pole plate.(22) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include depositing a second insulating thin film and a first conductive thin film sequentially on the base substrate on which the foregoing pattern is formed, patterning the first conductive thin film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and disposing the first conductive layer pattern on the second insulating layer as shown in FIG. 19.In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emission control line 24, a first pole plate 25 of the storage capacitor, and a third pole plate 18 of the second storage capacitor.In an exemplary embodiment, the structures and connection relationships of the first sense signal line 21, the second sense signal line 22, the third sense signal line 23, the light emission control line 24, and the first pole plate 25 of the first storage capacitor are basically the same as the structures and connection relationships according to the foregoing embodiments.In an exemplary embodiment, the shape of the third pole plate 18 of the second storage capacitor may be rectangular and the corners of the rectangular shape may be rounded. The third pole plate 18 may be disposed on one side of the first pole plate 25 in the first direction X. The third pole plate 18 may serve as a pole plate of the second storage capacitor.In an exemplary embodiment, the distance L between the first pole plate 25 and the third pole plate 18 may be equal to or larger than 2 μm, and the distance L may be the dimension in the first direction X (unit row direction). For example, the distance L may be about 2.5 μm.In an exemplary embodiment, the area of the orthographic projection of the third pole plate 18 on the base substrate may be smaller than the area of the orthographic projection of the first pole plate 25 on the base substrate.In an exemplary embodiment, the dimension of the first pole plate 25 in the second direction Y is larger than the dimension of the first pole plate 25 in the second direction Y in the previous embodiment, thereby saving a relatively large excess space for the second storage capacitor under the condition of securing the capacitance value of the first storage capacitor.(23) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include depositing a third insulating thin film and a second conductive thin film sequentially on the base substrate on which the foregoing pattern is formed, patterning the second conductive thin film by a patterning process, forming a third insulating layer covering the first conductive layer, and disposing the second conductive layer pattern on the third insulating layer as shown in FIG. 20.In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least: a first initial signal line 31, a second initial signal line 32, a second pole plate 33 of the first storage capacitor, a fourth pole plate 34 of the second storage capacitor, a pole plate connection line 35, a shield electrode 37, and a first pole plate connection block 38.In an exemplary embodiment, the structures and connection relationships of the first initial signal line 31, the second initial signal line 32, the second pole plate 33, the fourth pole plate 34, the pole plate connection line 35, and the shield electrode 37 are the same as the structures and connection relationships according to the foregoing embodiments. The difference is that the second pole plate 33 of the first storage capacitor and the fourth pole plate 34 of the second storage capacitor are connected to each other via the first pole plate connection block 38, so that the second pole plate 33, the fourth pole plate 34, and the first pole plate connection block 38 are connected to each other in the circuit unit into an integral structure.In an exemplary embodiment, the area of the orthographic projection area of the fourth pole plate 34 on the base substrate may be smaller than the area of the orthographic projection area of the first pole plate 25 on the base substrate, and the area of the orthographic projection area of the fourth pole plate 34 on the base substrate may be smaller than the area of the orthographic projection area of the second pole plate 33 on the base substrate.In an exemplary embodiment, the capacitance value of the second storage capacitor may be smaller than the capacitance value of the first storage capacitor.In an exemplary embodiment, the capacitance value of the second storage capacitor may be about 20% to 70% of the capacitance value of the first storage capacitor. For example, the capacitance value of the second storage capacitor 20 may be about 30% to 50% of the capacitance value of the first storage capacitor 10.(24) forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating film pattern may include: depositing a fourth insulating film on the base substrate on which the foregoing pattern is formed, patterning the fourth insulating film by a patterning process, forming a fourth insulating film covering the second conductive layer. Each circuit unit is provided with a plurality of through holes as shown in Fig. 21.In an exemplary embodiment, the plurality of through-holes of each circuit unit in the display area include at least: a first through-hole V 1, a second through-hole V 2, a third through-hole V 3, a fourth through-hole V 4, a fifth through-hole V 5, a sixth through-hole V 6, a seventh through-hole V 7, an eighth through-hole V 8, a ninth through-hole V 9, a tenth through-hole V 10, an eleventh through-hole V 11, a twelfth through-hole V 12, and a thirteenth through-hole V 13.In the exemplary embodiment, the structures and connection relationships of the first through hole V 1 to the twelfth through hole V 12 are basically the same as the structures and connection relationships according to the foregoing embodiments. The orthographic projection of the thirteenth through hole V 13 on the base substrate is within the circumference of the orthographic projection of the third pole plate 18 on the base substrate. The fourth insulating layer and the third insulating layer in the thirteenth through hole V 13 are etched away so as to expose the surface of the third pole plate 18, and the thirteenth through hole V 13 is configured so that the second pole plate connection block formed subsequently is connected to the third pole plate 18 through the through hole.(25) forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive thin film on the base substrate on which the foregoing pattern is formed; patterning the third conductive thin film by a patterning process; forming a third conductive layer disposed on the fourth insulating layer, as illustrated in FIG. 22.In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display area may include: a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46, a seventh connection electrode 47, and a second pole plate connection block 49.In the exemplary embodiment, the structures and the connection relationships of the first connection electrode 41 to the seventh connection electrode 47 are basically the same as the structures and connection relationships according to the foregoing embodiments. The difference is that the third connection electrode 43 and the second pole plate connection block 49 are connected.In an exemplary embodiment, the shape of the second pole plate connection block 49 may be rectangular. It may be located on a side of the third connection electrode 43 of the circuit unit in the first direction X (a side facing away from a first storage capacitor). The orthographic projection of the second pole plate connection block 49 on the base substrate overlaps at least partially with the orthographic projection of the third pole plate 18 on the base substrate. The first end of the second pole plate connection block 49 is connected to the third connection electrode 43, and the second end of the second pole plate connection block 49 extends along the first direction X and is thereafter connected to the third pole plate 18 via the thirteenth through hole V 13.In an exemplary embodiment, the third connection electrode 43 and the second pole plate connection block 49 may be connected to each other into an integral structure. Since the third connection electrode 43 serves as the first node N 1 in the pixel driving circuit, the third pole plate 18 connected to the third connection electrode 43 via the second pole plate connection block 49 has the potential of the first node N 1. The third pole plate 18 and the fourth pole plate 34 form the second storage capacitor of the pixel driver circuit.In an exemplary embodiment, the third conductive layer pattern of at least one circuit unit may further include a first initial electrode 71 and a second initial electrode 72. The structures and connection relationships of the first initial electrode 71 and the second initial electrode 72 are the same as the structures and connection relationships according to the foregoing embodiments.(26) forming the patterns of the fifth insulating layer, the fourth conductive layer, the first planarization layer, the fifth conductive layer, and the second planarization layer sequentially, as illustrated in FIG. 23. In exemplary embodiments, the manufacturing processes and the associated structures are basically the same as those according to the preceding exemplary embodiments, which is not repeated here.In the display substrate provided according to an exemplary embodiment of the present disclosure, on the one hand, the data writing phase and the threshold compensation phase are separated, the data writing time and the threshold compensation time are extended, the problems of the prior art solutions such as insufficient charging time and insufficient compensation time or the like are effectively improved; on the other hand, mesh structures for transmitting the first initial signal and the second initial signal are allowed to be formed simultaneously, the voltage drop is decreased, the display uniformity is improved; and further, by the first conductive layer and the second conductive layer, the first storage capacitor and the second storage capacitor are formed simultaneously, the occupied space is small, the increase in the capacitance value of the second storage capacitor is facilitated, and the stability of the potential of the first node N 1 is increased. In the present disclosure, forming the second storage capacitor of two-layered metals contributes to the flatness of the third conductive layer, the fourth conductive layer, and the fifth conductive layer, thereby preventing the influence of the process variations on the capacitance value of the storage capacitor.The structures and the manufacturing processes thereof described above in the present disclosure are only schematic explanations. In an exemplary embodiment, the respective structures may be changed as needed and more or few patterning processes may be employed, which is not limited in the present disclosure.In an exemplary embodiment, the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (micro-LED or mini-LED), or a quantum dot light emitting diode display (QDLED), or the like, which is not limited herein in the present disclosure.In an exemplary embodiment, the frame portion of the display substrate may be provided with at least a plurality of cascaded gate driver on array (GOA). Each gate drive circuit is connected to the first scan signal line, the second scan signal line, the third scan signal line, and the light emission signal line in each unit row.In an exemplary embodiment, at least one gate driver circuit may include at least: a first gate circuit group, a second gate circuit group, and a third gate circuit group. The first gate circuit group may be connected to the first scan signal line and the third scan signal line, respectively, the second gate circuit group may be connected to the second scan signal line, and the third gate circuit group may be connected to the light emission signal line, i.e., the first scan signal line and the third scan signal line are driven by one group of gate circuits, and the second scan signal line is driven by another group of gate circuits.In an exemplary embodiment, the first gate circuit group, the second gate circuit group, and the third gate circuit group may be bilaterally driven simultaneously, or may be unilateral driven to meet narrow frame requirements, which is not limited herein in the present disclosure.In an exemplary embodiment, the second gate circuit group may use a one-to-two structure, i.e., a second gate circuit group may be connected to the second scan signal lines of two unit rows and controls the turning on and off of a plurality of second transistors T 2 in two unit rows to reduce the number of gate drive circuits and the wirings in the frame region, which is advantageous for realizing a narrow frame.FIG. 24 is a test result diagram of the brightness difference between rows when a one-to-two structure is used in the present disclosure. As illustrated in FIG. 24, the second gate circuit group uses a one-to-two structure. At the gray level of 32 and 500 nits, when the time of the threshold compensation phase is equal to or larger than four times the time of the data writing phase (n=4), the difference in brightness between the lines is more than 95%. In the present disclosure, by extending the time of the threshold compensation phase, the existing problem of the presence of a brightness difference between the rows in the one-to-two structure is solved.FIG. 25 is a test result diagram of threshold sensitivity at different times of the threshold compensation phase, in accordance with the present disclosure. As illustrated in FIG. 25, when the time of the threshold compensation phase is equal to the time of the data writing phase (n=1), the threshold sensitivity (Vth sensitivity) is relatively large; when the time of the threshold compensation phase is three times (n=3) and seven times (n=7) the time of the data writing phase, the threshold sensitivity is significantly reduced, whereby the compensation effect can be improved.In an exemplary embodiment, the difference in brightness between the rows and the change in threshold sensitivity are relatively small when the time of the threshold compensation phase is nine times the time of the data write phase. In consideration of factors such as the refresh rate, it is provided in the present disclosure that the time of the threshold compensation phase is n times the time of the data writing phase, where n is a positive integer greater than or equal to 1 and less than or equal to 9. For example, the time of the threshold compensation phase is three times, five times, or seven times the time of the data writing phase.The present disclosure also provides a display substrate driving method for driving the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including at least: a compensation transistor, a driving transistor, a data writing transistor, a first node, a second node, a first storage capacitor, and a second storage capacitor; the pixel driving circuit being connected to a first scan signal line, a second scan signal line, the first power line, and a data signal line, respectively; a gate electrode of the driving transistor being connected to the second node, a first pole of the driving transistor being connected to the first node, a second pole of the driving transistor being connected to a second pole of the compensation transistor; a gate electrode of the data write transistor is connected to the first scan signal line, a first pole of the data write transistor is connected to the data signal line, a second pole of the data write transistor is connected to the first node; a gate electrode of the compensation transistor is connected to the second scan signal line, a first pole of the compensation transistor is connected to the second node; a first end of the first storage capacitor is connected to the second node, a second end of the first storage capacitor is connected to the first power line; a first end of the second storage capacitor is connected to the first node, a second end of the second storage capacitor is connected to the first power line. The driving method may include:in a data writing phase, outputting a turn-on signal through the first scan signal line and the second scan signal line, turning on the compensation transistor and the data writing transistor, writing a data voltage output from the data signal line into the first storage capacitor and the second storage capacitor;in a threshold compensation phase, outputting a turn-off signal through the first scan signal line, outputting a turn-on signal through the second scan signal line, turning on the compensation transistor, turning off the data write transistor, writing a data voltage stored by the second storage capacitor into the first storage capacitor, and performing threshold compensation for the driver transistor.In an exemplary embodiment, the time of the threshold compensation phase is greater than or equal to the time of the data write phase.In an exemplary embodiment, the time of the threshold compensation phase is n times the time of the data write phase, and n is a positive integer greater than or equal to 1 and less than or equal to 9.The present disclosure further provides a display device including a display substrate as set forth above. The display device may be a mobile phone, a tablet computer, a television, a display, a notebook, a digital picture frame, a navigation device, or any other product or component having a display function. The embodiments of the present invention are not limited thereto.Although the embodiments disclosed in the present disclosure are as described above, the disclosure content relates only to embodiments that serve to facilitate understanding of the present disclosure and does not aim to limit the present invention. Any person skilled in the art is allowed to make any modifications and changes in the form and details of the implementations without departing from the spirit and scope of the disclosure. The scope of the present invention, however, still needs to be based on the scope defined by the appended claims.

Claims

A display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises a pixel driver circuit comprising at least: a compensation transistor, a driver transistor, a data write transistor, a first node, a second node, a first storage capacitor, and a second storage capacitor; wherein the pixel driver circuit is connected to a first scan signal line, a second scan signal line, a first power line, and a data signal line, respectively; a gate electrode of the driver transistor is connected to the second node, a first pole of the driver transistor is connected to the first node, a second pole of the driver transistor is connected to a second pole of the compensation transistor; a gate electrode of the data write transistor is connected to the first scan signal line, a first pole of the data write transistor is connected to the data signal line, a second pole of the data write transistor is connected to the first node; a gate electrode of the compensation transistor is connected to the second scan signal line, a first pole of the compensation transistor is connected to the second node; a first end of the first storage capacitor is connected to the second node, a second end of the first storage capacitor is connected to the first power line; a first end of the second storage capacitor is connected to the first node, a second end of the second storage capacitor is connected to the first power line.The display substrate of claim 1, wherein on a plane perpendicular to the display substrate, the display substrate comprises a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer, sequentially disposed on a base substrate; the first end of the first storage capacitor comprises a first pole plate, the second end of the first storage capacitor comprises a second pole plate, the first pole plate is disposed in the first conductive layer, the second pole plate is disposed in the second conductive layer; the first end of the second storage capacitor comprises at least one third pole plate, the second end of the second storage capacitor comprises a fourth pole plate, the third pole plate is disposed in the semiconductor layer, the fourth pole plate is disposed in the second conductive layer.The display substrate of claim 2, wherein the first end of the second storage capacitor further comprises a fifth pole plate disposed in the third conductive layer, the third pole plate being connected to the fifth pole plate.The display substrate of claim 1, wherein on a plane perpendicular to the display substrate, the display substrate comprises a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer, sequentially disposed on a base substrate; the first end of the first storage capacitor comprises a first pole plate, the second end of the first storage capacitor comprises a second pole plate, the first pole plate is disposed in the first conductive layer, the second pole plate is disposed in the second conductive layer; the first end of the second storage capacitor comprises at least one fifth pole plate, the second end of the second storage capacitor comprises a fourth pole plate, the fifth pole plate is disposed in the third conductive layer, the fourth pole plate is disposed in the second conductive layer.The display substrate of claim 2, wherein the semiconductor layer further comprises an active layer of the driving transistor, wherein the third pole plate and the active layer of the driving transistor are connected to each other into an integral structure.The display substrate according to claim 2, wherein the second pole plate and the fourth pole plate are connected to each other into an integral structure.The display substrate according to claim 3, wherein the first node is disposed in the third conductive layer, the first node and the fifth pole plate are connected to each other into an integral structure, and the first node is connected to the third pole plate through a through hole.The display substrate of claim 1, wherein on a plane perpendicular to the display substrate, the display substrate comprises a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer, sequentially disposed on a base substrate; the first end of the first storage capacitor comprises a first pole plate, the second end of the first storage capacitor comprises a second pole plate, the first pole plate is disposed in the first conductive layer, the second pole plate is disposed in the second conductive layer; the first end of the second storage capacitor comprises a third pole plate, the second end of the second storage capacitor comprises a fourth pole plate, the third pole plate is disposed in the first conductive layer, the fourth pole plate is disposed in the second conductive layer.The display substrate of claim 8, wherein the second conductive layer further comprises a first pole plate connection block, wherein the second pole plate and the fourth pole plate are connected to each other by the first pole plate connection block.The display substrate of claim 8, wherein the third conductive layer further comprises a second pole plate connection block and the first node, the first node is connected to the second pole plate connection block, and the second pole plate connection block is connected to the third pole plate through a through hole.The display substrate according to claim 8, wherein the distance between the first pole plate and the third pole plate is greater than or equal to 2 μm, the distance concerning a dimension in a direction of the unit rows.The display substrate according to any one of claims 1 to 11, wherein the capacitance value of the second storage capacitor is smaller than the capacitance value of the first storage capacitor.The display substrate of claim 11, wherein the capacitance value of the second storage capacitor is 20% to 70% of the capacitance value of the first storage capacitor.The display substrate according to any one of claims 1 to 11, wherein the pixel driving circuit is further connected to a first initial signal line and a second initial signal line, respectively, the shape of the first initial signal line and the second initial signal line is a line shape extending along a first direction; the first initial signal line is connected to a first connection line extending along a second direction to form a mesh structure for transmitting a first initial signal, the second initial signal line is connected to a second connection line extending along the second direction to form a mesh structure for transmitting a second initial signal, wherein the first direction and the second direction intersect.The display substrate according to claim 14, wherein in circuit units of at least one unit row, the first initial signal line and the second initial signal line are provided; in circuit units in an odd-numbered unit column, the first connection line is provided, in circuit units in an even-numbered unit column, the second connection line is provided, or in circuit units in an even-numbered unit column, the first connection line is provided, in circuit units in an odd-numbered unit column, the second connection line is provided.The display substrate of claim 14, wherein on a plane perpendicular to the display substrate, the display substrate comprises a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, which are sequentially disposed on a base substrate; the first initial signal line and the second initial signal line are disposed in the second conductive layer, the first connection line and the second connection line are disposed in the fourth conductive layer.The display substrate according to claim 16, wherein the third conductive layer in at least one circuit unit further comprises a first initial electrode, the first connection line is connected to the first initial electrode through a via hole, and the first initial electrode is connected to the first initial signal line through a via hole.The display substrate according to claim 16, wherein the third conductive layer in at least one circuit unit further comprises a second initial electrode, the second connection line is connected to the second initial electrode through a via hole, and the second initial electrode is connected to the second initial signal line through a via hole.The display substrate of claim 16, wherein the display substrate further comprises a fifth conductive layer disposed on a side of the fourth conductive layer opposite the base substrate, the data signal line is disposed in the fifth conductive layer, the orthographic projection of at least one data signal line on the base substrate overlaps at least partially with the orthographic projection of the first interconnect line on the base substrate, the orthographic projection of at least one data signal line on the base substrate overlaps at least partially with the orthographic projection of the second interconnect line on the base substrate.A display device comprising the display substrate according to any one of claims 1 to 19.A driving method for driving the display substrate according to any one of claims 1 to 19, comprising: in a data writing phase, outputting an on signal through the first scan signal line and the second scan signal line, turning on the compensation transistor and the data writing transistor, writing a data voltage output from the data signal line into the first storage capacitor and the second storage capacitor; in a threshold compensation phase, outputting an off signal through the first scan signal line, outputting an on signal through the second scan signal line, turning on the compensation transistor, turning off the data writing transistor, writing a data voltage stored by the second storage capacitor into the first storage capacitor, performing threshold compensation for the driving transistor.The driving method according to claim 21, wherein the time of the threshold compensation phase is equal to or greater than the time of the data writing phase.The driving method according to claim 22, wherein the time of the threshold compensation phase is n times the time of the data writing phase, where n is a positive integer greater than or equal to 1 and less than or equal to 9.

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