CHIP-ON FILM AND DISPLAY DEVICE

Abstract

The present disclosure presents a chip-on-film (001) and a display device, comprising: a base substrate (101), wherein the base substrate (101) includes a plurality of bonding regions (BA1, BA2, BA3) and edge regions (SA1, SA2, SA3, SA4, SA5) each arranged around each of the bonding regions (BA1, BA2, BA3); a plurality of pads (102) located on the base substrate (101), each of the bonding regions (BA1, BA2, BA3) being provided with a plurality of pads (102); an accompanying plating pattern (103) provided in the same layer and with the same material as the plurality of pads (102), wherein the accompanying plating pattern (103) is located in the edge region (SA1, SA2, SA3, SA4, SA5) on at least one side of the bonding region (BA1, BA2, BA3).

Description

Chip-on-film and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a chip-on-film and a display device. Background Art

[0002] Large-sized electronic products such as LCD monitors, LCD TVs, and plasma TVs, as well as small and medium-sized electronic products such as mobile phones and digital cameras, are all developing in a trend towards being thinner, lighter, and smaller. This requires a new generation of packaging technology that is high-density, compact, and can be freely installed to meet these needs. Chip On Film (COF) packaging technology has emerged as the answer to this question. COF is constructed by bonding and mounting a driver chip (source driver chip IC or gate driver chip IC) on a flexible wiring substrate with a wiring pattern formed. The wiring pattern of a COF is typically composed of inner leads connected to the electrodes of the driver chip and outer leads connected to the external circuit.

[0003] Summary of the Invention

[0004] The embodiments of the present disclosure provide a chip-on-film and a display device, and the specific solutions are as follows:

[0005] In one aspect, an embodiment of the present disclosure provides a chip-on-film (COF) comprising:

[0006] a base substrate, the base substrate comprising a plurality of binding regions and a peripheral region disposed around each of the binding regions;

[0007] A plurality of pads are located on the substrate, and each of the binding areas is provided with a plurality of pads;

[0008] The accompanying plating pattern is provided in the same layer and with the same material as the plurality of pads, and the accompanying plating pattern is located in the peripheral area on at least one side of the binding area.

[0009] In some embodiments, in the above-mentioned flip chip film provided by the embodiments of the present disclosure, in each of the binding areas, the pads are arranged into multiple rows along the extension direction of the pads, the peripheral area includes a first peripheral area on the side where the first row of pads is located, and the second peripheral area on the side where the last row of pads is located, and the accompanying plating pattern includes a first accompanying plating pattern located in the first peripheral area and / or the second peripheral area.

[0010] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, the first accompanying plating pattern corresponds one-to-one with each of the pads in the first row and / or each of the pads in the last row, and the first accompanying plating pattern is integrally arranged with the corresponding pads.

[0011] In some embodiments, in the above-mentioned chip-on-film provided by the embodiments of the present disclosure, one of the plurality of bonding regions includes a first sub-bonding region and a second sub-bonding region arranged side by side in the extending direction of the pad;

[0012] The peripheral region further includes a third peripheral region located between the first sub-binding region and the second sub-binding region, and the accompanying plating pattern includes a plurality of second accompanying plating patterns located in the third peripheral region.

[0013] In some embodiments, the above-mentioned flip chip film provided in the embodiments of the present disclosure further includes a plurality of support patterns, and the plurality of support patterns are located in the third peripheral area.

[0014] In some embodiments, in the above-mentioned chip-on-film provided by the embodiments of the present disclosure, the third peripheral region includes a first edge region adjacent to the first sub-binding region, and a second edge region adjacent to the second sub-binding region;

[0015] The chip-on-film further includes at least two groups of common routing lines, each group of common routing lines includes a first common routing line and a second common routing line, wherein the first common routing line is led out from the second sub-binding area and extends in the first edge area, and the second common routing line is led out from the second sub-binding area and extends in the second edge area;

[0016] In the pattern set consisting of the multiple supporting patterns and the multiple second accompanying plating patterns, each pattern is evenly distributed in the area between each group of the common routing lines and in the area between the first common routing line and the second common routing line in each group of the common routing lines.

[0017] In some embodiments, in the above-mentioned flip chip film provided by the embodiments of the present disclosure, the plurality of support patterns are integrally provided with a portion of the second accompanying plating pattern.

[0018] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, in the combined pattern formed by the integrally arranged support pattern and the second accompanying plating pattern, the support pattern is symmetrically arranged about the central axis of the combined pattern extending in the direction intersecting the extension direction of the pad.

[0019] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, the second accompanying plating pattern separated from the supporting pattern is an independent pattern, and each of the combined patterns is evenly distributed in the area between each group of the common routing lines and in the area between the first common routing line and the second common routing line in each group of the common routing lines.

[0020] In some embodiments, in the flip chip film provided by the embodiments of the present disclosure, in the extension direction of the pad, the length of the combined pattern and the length of the independent pattern are respectively more than 50% of the distance between the first common trace and the second common trace.

[0021] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, the second accompanying plating pattern separated from the supporting pattern is an independent pattern, each of the combined patterns forms at least one row, each of the independent patterns forms at least two rows, at least one row of the combined patterns and at least two rows of the independent patterns are arranged in the extension direction of the pad, and the row where the combined pattern is located is farther away from the first edge area and the second edge area than the row where the independent pattern is located.

[0022] In some embodiments, in the above-mentioned flip chip film provided by the embodiments of the present disclosure, the shape and width of the combined pattern, and the shape and width of the independent pattern are substantially the same as the shape and width of the pad, respectively.

[0023] In some embodiments, in the chip-on-film provided by the embodiments of the present disclosure, the second accompanying plating pattern spaced apart from the supporting pattern is an independent pattern, the combined patterns form at least one row, and the independent patterns are strip-shaped accompanying plating patterns between the area where the combined pattern is located and the first sub-binding area, and between the area where the combined pattern is located and the second sub-binding area;

[0024] In a direction intersecting the extending direction of the pads, the length of the strip-shaped accompanying plating pattern is greater than or equal to the distance between the starting and ending positions of a row of pads.

[0025] In some embodiments, in the above-mentioned flip chip film provided by the embodiments of the present disclosure, the length of the first accompanying plating pattern in the extending direction of the pad is greater than or equal to 300 μm and less than or equal to 1000 μm.

[0026] In some embodiments, in the chip-on-film provided by the embodiments of the present disclosure, the peripheral region includes a fourth peripheral region and a fifth peripheral region, the fourth peripheral region and the fifth peripheral region extend in the extending direction of the pad, and in a direction intersecting the extending direction of the pad, the fourth peripheral region and the fifth peripheral region are located on both sides of the binding region;

[0027] The chip-on-film further includes alignment marks located in the fourth peripheral area and the fifth peripheral area, and the alignment marks are provided in the same layer and the same material as the plurality of pads;

[0028] The accompanying plating pattern includes a third accompanying plating pattern located in the fourth peripheral area and / or the fifth peripheral area, and the third accompanying plating pattern is arranged around the alignment mark on both sides where the alignment mark and the extension direction of the pad are intersected, and on at least one side of the side of the alignment mark away from the binding area, and there is a preset distance between the third accompanying plating pattern and the alignment mark.

[0029] In some embodiments, in the above-mentioned flip chip film provided by the embodiments of the present disclosure, the third accompanying plating pattern is a block pattern.

[0030] In some embodiments, in the above-mentioned flip chip film provided by the embodiments of the present disclosure, the third accompanying plating pattern includes a plurality of strip patterns sequentially arranged in the extension direction of the pad.

[0031] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, on both sides of the alignment mark in the intersection direction with the pad extension direction, the length of the third accompanying plating pattern in the intersection direction with the pad extension direction is greater than or equal to 1 mm and less than or equal to 5 mm.

[0032] In some embodiments, in the above-mentioned flip chip film provided by the embodiments of the present disclosure, in the extension direction of the pad, the distance from the end surface of the third accompanying plating pattern away from the binding area to the binding area is substantially the same as the length of the first accompanying plating pattern.

[0033] In some embodiments, the above-mentioned flip chip film provided in the embodiments of the present disclosure further includes a first protective pattern located on the side of the layer where the multiple pads are located away from the base substrate, and the orthographic projection of the first protective pattern on the base substrate overlaps with the orthographic projections of the first accompanying plating pattern and the third accompanying plating pattern arranged side by side in the cross direction of the pad extension direction on the base substrate, and in the pad extension direction, there is a preset distance between the orthographic projection of the first protective pattern on the base substrate and the binding area.

[0034] In some embodiments, in the above-mentioned COF provided by the embodiments of the present disclosure, the multiple binding areas include a first binding area for binding the display substrate, and a second binding area for binding the circuit board.

[0035] In some embodiments, in the above-mentioned chip-on-film provided by the embodiments of the present disclosure, in the first binding area and the second binding area, two adjacent rows of the pads are partially staggered along a direction intersecting the extending direction of the pads.

[0036] In some embodiments, the above-mentioned flip chip film provided in the embodiments of the present disclosure further includes a second protective pattern integrally arranged with the first protective pattern, and the orthographic projection of the second protective pattern on the base substrate overlaps with the orthographic projection of the third accompanying plating pattern on the base substrate, and in the cross direction of the pad extension direction, there is a preset distance between the orthographic projection of the second protective pattern on the base substrate and the binding area.

[0037] In some embodiments, in the above-mentioned chip-on-film provided by the embodiments of the present disclosure, the plurality of binding regions include a third binding region for binding a driver chip.

[0038] In some embodiments, in the above-mentioned chip-on-film provided by the embodiments of the present disclosure, the third bonding area includes the first sub-bonding area and the second sub-bonding area, and in the first sub-bonding area and the second sub-bonding area, two adjacent rows of bonding pads are partially staggered along a direction intersecting with an extension direction of the bonding pads;

[0039] In a direction intersecting the extending direction of the pad, the second sub-binding area includes a first signal output area and a second signal output area arranged side by side, and a signal input area located between the first signal output area and the second signal output area;

[0040] The first sub-binding area includes a third signal output area and a fourth signal output area. The third signal output area and the first signal output area are arranged side by side in the extending direction of the pad. The fourth signal output area and the second signal output area are arranged side by side in the extending direction of the pad.

[0041] On the other hand, an embodiment of the present disclosure provides a display device, including a display substrate, a circuit board, a driver chip and a chip-on-chip film, wherein the chip-on-chip film is the above-mentioned chip-on-chip film provided in the embodiment of the present disclosure, and the chip-on-chip film includes binding areas corresponding one-to-one to the display substrate, the driver chip and the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a schematic diagram showing a thicker pad at the edge of a bonding area according to an embodiment of the present disclosure;

[0043] FIG2 is a schematic diagram of an area where a thicker pad is located in a binding area for binding a display substrate or a flexible circuit board according to an embodiment of the present disclosure;

[0044] FIG3 is a schematic diagram of an area where a relatively thick pad is located in a binding region for binding a driver chip according to an embodiment of the present disclosure;

[0045] FIG4 is a schematic structural diagram of a chip-on-film provided in an embodiment of the present disclosure;

[0046] FIG5 is a schematic diagram of another structure of a chip-on-film provided in an embodiment of the present disclosure;

[0047] FIG6 is a schematic diagram of an enlarged structure of the M1 region in FIG5 ;

[0048] FIG7 is a schematic diagram of an enlarged structure of the M2 region in FIG5 ;

[0049] FIG8 is a schematic diagram of an enlarged structure of the M3 region in FIG5 ;

[0050] FIG9 is another enlarged structural diagram of the M2 region in FIG5 ;

[0051] FIG10 is another enlarged structural diagram of the M2 region in FIG5 ;

[0052] FIG11 is another enlarged structural diagram of the M1 region in FIG5 ;

[0053] FIG12 is another enlarged structural diagram of the M2 region in FIG5 ;

[0054] FIG13 is another enlarged structural diagram of the M1 region in FIG5 ;

[0055] FIG14 is another enlarged structural diagram of the M2 region in FIG5 ;

[0056] FIG15 is another enlarged structural diagram of the M3 region in FIG5 ;

[0057] FIG16 is another enlarged structural diagram of the M2 region in FIG5 ;

[0058] FIG17 is another enlarged structural diagram of the M2 region in FIG5 ;

[0059] FIG18 is another enlarged structural diagram of the M1 region in FIG5 ;

[0060] FIG19 is another enlarged structural diagram of the M2 region in FIG5 ;

[0061] FIG20 is a schematic structural diagram of a chip-on-film during the manufacturing process provided by an embodiment of the present disclosure;

[0062] FIG21 is a schematic diagram of a partial structure of a layer where leads are provided in an embodiment of the present disclosure;

[0063] FIG22 is a cross-sectional view along the II' direction in FIG21;

[0064] FIG23 is a schematic structural diagram of a layer where leads are provided in an embodiment of the present disclosure;

[0065] FIG24 is a schematic diagram of the enlarged structure of the M4 region in FIG23;

[0066] FIG25 is another structural schematic diagram of a chip-on-film during the manufacturing process provided by an embodiment of the present disclosure;

[0067] FIG26 is another structural schematic diagram of a chip-on-film during the manufacturing process provided by an embodiment of the present disclosure;

[0068] FIG27 is another structural schematic diagram of a chip-on-film during the manufacturing process provided by an embodiment of the present disclosure;

[0069] FIG28 is another structural schematic diagram of a chip-on-film during the manufacturing process provided by an embodiment of the present disclosure;

[0070] FIG29 is another structural schematic diagram of a chip-on-film during the manufacturing process provided by an embodiment of the present disclosure;

[0071] FIG30 is another structural schematic diagram of a chip-on-film during the manufacturing process provided by an embodiment of the present disclosure;

[0072] FIG31 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure;

[0073] FIG32 is a schematic structural diagram of a display substrate or a flexible circuit board and a chip-on-film bonded together according to an embodiment of the present disclosure;

[0074] FIG33 is a schematic diagram of a structure after the driver chip and the flip chip film are bound together according to an embodiment of the present disclosure;

[0075] FIG34 is a schematic diagram of another structure after the driver chip and the flip chip are bound together according to an embodiment of the present disclosure;

[0076] FIG35 is another structural schematic diagram of a display device provided in an embodiment of the present disclosure;

[0077] FIG36 is another structural schematic diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual proportions, and the purpose is only to illustrate the contents of the present disclosure. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0079] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in this disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0080] With the continuous development of three-dimensional (3D) display technology, the market demand for 3D display products is rapidly increasing. The main development trend of 3D products is the continuous improvement of resolution (16K, 32K, etc.) to support the information volume of 3D displays. To support technologies such as multi-view and X-Zone, the number of data channels required for 3D display products has greatly increased, necessitating a higher-resolution COF packaging process to accommodate the massive amount of data transmission. Currently, COF products on the market are all roll-to-roll processes with low process precision. The metal is made of copper (Cu) and the trace pitch is large, making them unable to meet the demand for 3D products with more than 5,000 data pins (source pins).

[0081] Based on this, the inventors fabricated leads and pads (Pad) in layers on a flexible substrate (PI), wherein the leads include a laminated structure consisting of a stacked titanium metal layer / aluminum metal layer / titanium metal layer, and the pads include a single-layer copper structure. Through the design of multiple rows of pads, a COF production scheme for matching data pins (source pins) with a number of more than 10,000 is achieved. In this scheme, since the copper layer thickness of the pad is required to be above 5 μm and the pad spacing is less than 30 μm, only a semi-additive electroplating process can be used to produce the pads. However, the small area of ​​the pad will lead to an uneven proportion of local copper, resulting in the concentration of power lines and increased current density around the pad (P) during the electroplating process, as shown in Figure 1. The pad (P) near the edge is thicker, resulting in a large difference in pad thickness, which can easily lead to poor binding. Specifically: As shown in Figure 2, in the bonding area (OLB Bonding) used to bond the display substrate (panel) and the bonding area (FPC Bonding) used to bond the flexible circuit board (FPC), the pads P in the edge area A are more than 2μm thick, which can easily lead to poor bonding. In addition, as shown in Figure 3, in the bonding area (ILB Bonding) used to bond the driver chip (IC), the pads in the edge area B and the middle area C are too thick, which can also easily lead to poor bonding.

[0082] In order to solve the above technical problems existing in the related art, the present disclosure provides a flip chip film, as shown in Figures 4 to 8, comprising:

[0083] The base substrate 101 includes a plurality of binding areas (e.g., a first binding area BA1 for binding a display substrate, a second binding area BA2 for binding a flexible circuit board, and a third binding area BA3 for binding a driver chip), and peripheral areas (e.g., a first peripheral area SA1, a second peripheral area SA2, a third peripheral area SA3, a fourth peripheral area SA4, and a fifth peripheral area SA5) disposed around each binding area (e.g., the first binding area BA1, the second binding area BA2, and the third binding area BA3). The base substrate 101 may be a flexible substrate made of a material such as polyimide.

[0084] A plurality of pads 102 are located on the substrate 101. Each bonding area (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3) is provided with a plurality of pads 102. The material of the pads 102 can be copper, etc.

[0085] The accompanying plating pattern 103 is set in the same layer and material as the multiple pads 102. The accompanying plating pattern 103 is located in the peripheral area (for example, the first peripheral area SA1, the second peripheral area SA2, the third peripheral area SA3, the fourth peripheral area SA4, and the fifth peripheral area SA5) on at least one side of the binding area (for example, the first binding area BA1, the second binding area BA2, and the third binding area BA3).

[0086] In the above-mentioned flip chip film provided in the embodiment of the present disclosure, during the process of electroplating to form the pad 102 in the binding area (for example, the first binding area BA1, the second binding area BA2, and the third binding area BA3), a companion plating pattern 103 of the same layer and material as the pad 102 can be simultaneously formed in the peripheral area (for example, the first peripheral area SA1, the second peripheral area SA2, the third peripheral area SA3, the fourth peripheral area SA4, and the fifth peripheral area SA5). Since the peripheral area (e.g., the first peripheral area SA1, the second peripheral area SA2, the third peripheral area SA3, the fourth peripheral area SA4, and the fifth peripheral area SA5) where the accompanying plating pattern 103 is located is located outside the binding area (e.g., the first binding area BA1, the second binding area BA2, and the third binding area BA3) where the pad 102 is located, the phenomenon of concentrated electric lines and higher current density during the electroplating process will occur in the peripheral area (e.g., the first peripheral area SA1, the second peripheral area SA2, the third peripheral area SA3, the fourth peripheral area SA4, and the fifth peripheral area SA5), thereby ensuring that the electric lines and current density of the binding area (e.g., the first binding area BA1, the second binding area BA2, and the third binding area BA3) are normal, and then a pad 102 with uniform thickness can be formed in the binding area (e.g., the first binding area BA1, the second binding area BA2, and the third binding area BA3), which is beneficial to improving the binding yield. Optionally, the present disclosure can make the thickness uniformity difference of the pad 102 in the binding area (e.g., the first binding area BA1, the second binding area BA2, and the third binding area BA3) less than 1μm.

[0087] In some embodiments, in the flip chip film provided in the embodiments of the present disclosure, as shown in Figures 6 to 8, within each bonding area (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3), the pads 102 are arranged in multiple rows along their extension direction Y, the peripheral area includes a first peripheral area SA1 on the side where the first row of pads 102 are located, and a second peripheral area SA2 on the side where the last row of pads 102 are located, and the accompanying plating pattern 103 includes a first accompanying plating pattern 31 located in the first peripheral area SA1 and / or the second peripheral area SA2. Because the first row of pads 102 and the last row of pads 102 are located at the edge of the bonding area (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3), the edge area is where the electric lines of force are concentrated and the current density is high during the electroplating process. As a result, the thickness of the first row of pads 102 and the last row of pads 102 at the ends away from the bonding area (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3) is likely to be thicker. By setting the first accompanying plating pattern 31 in the first peripheral area SA1 on the side where the first row of solder pads 102 is located and / or the second peripheral area SA2 on the side where the last row of solder pads 102 is located, it is equivalent to transferring the area where the electric lines are concentrated and the current density is relatively high to the first peripheral area SA1 and / or the second peripheral area SA2, so as to meet the normal electric lines and current density in the edge areas where the first row of solder pads 102 and the last row of solder pads 102 are located, and thus the first row of solder pads 102 and the last row of solder pads 102 with uniform thickness can be formed.

[0088] In some embodiments, in the above-mentioned flip chip film provided by the embodiments of the present disclosure, as shown in Figures 6 to 8, the first accompanying plating pattern 31 can correspond one-to-one with each of the pads 102 in the first row and / or each of the pads 102 in the last row, and the first accompanying plating pattern 31 can be integrally provided with the corresponding pads 102. In other words, the first pads 102 in the first row and / or each of the pads 102 in the last row can be extended toward the first peripheral area SA1 and / or the second peripheral area SA2, and the portion of the pads 102 extending to the first peripheral area SA1 and / or the second peripheral area SA2 can serve as the first accompanying plating pattern 31. Taking into account that in the relevant electroplating process, the width of the area where the electric lines are concentrated and the current density is high is about 200μm. Therefore, in order to make the pad 102 completely avoid the area where the electric lines are concentrated and the current density is high, in the present disclosure, the length of the first accompanying plating pattern 31 in the extension direction Y of the pad 102 can be greater than or equal to 300μm and less than or equal to 1000μm. For example, the length of the first accompanying plating pattern 31 in the extension direction Y of the pad 102 is 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, 1000μm, etc.

[0089] In some embodiments, in the above-mentioned flip chip provided in the embodiment of the present disclosure, as shown in FIG7 and FIG8, one of the plurality of bonding areas (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3) (e.g., the third bonding area BA3) includes a first sub-bonding area BA arranged side by side in the extension direction Y of the pad 102. 31 and the second sub-binding region BA 32 , the first sub-binding area BA 31 Middle distance second sub-binding area BA 32 The farthest row of pads 102 is the first row of pads 102 in the bonding area (eg, the third bonding area BA3). 32 Middle distance first sub-binding area BA 31 The farthest row of pads 102 is the last row of pads 102 in the bonding area (eg, the third bonding area BA3). The peripheral area may also include pads 102 located in the first sub-bonding area BA3. 31 With the second sub-binding area BA 32 The third peripheral area SA3 between the first sub-binding area BA 31 With the second sub-binding area BA 32 The pads 102 adjacent to the third peripheral area SA3 are prone to uneven thickness. Therefore, to ensure uniform thickness of the pads 102 on both sides of the third peripheral area SA3, as shown in Figures 7 and 8, a plating pattern 103 can be provided that includes multiple second plating patterns 32 located in the third peripheral area SA3. Optionally, the sum of the orthographic projection areas of all second plating patterns 32 on the base substrate 101 accounts for less than 50% of the area of ​​the third peripheral area SA3, and optionally about 40%, for example, 45%, 40%, 35%, 30%, etc.

[0090] In some embodiments, the flip chip film provided in the embodiments of the present disclosure, as shown in Figures 7 to 10 , may further include multiple support patterns ST. These support patterns ST are used to support the driver chip IC and balance bonding pressure, and may not carry any electrical signals. Optionally, the multiple support patterns ST are located in the third peripheral area SA3, and the ratio of the sum of the orthogonal projection areas of the multiple support patterns ST on the base substrate 101 to the sum of the orthogonal projection areas of the gaps between the support patterns ST on the base substrate 101 is less than or equal to 1 / 9. This means that the sum of the orthogonal projection areas of all the support patterns ST on the base substrate 101 accounts for less than 10% of the area of ​​the third peripheral area SA3, for example, 10%, 9%, 8%, etc. Optionally, second accompanying plating patterns 32 are provided in the gaps between the support patterns ST. In some embodiments, the total area of ​​the second accompanying plating patterns 32 combined with the total area of ​​the support patterns ST in the third peripheral area SA3 accounts for less than 50%, for example, 30% to 50%.

[0091] In some embodiments, in the above-mentioned flip chip provided by the embodiment of the present disclosure, as shown in FIG. 7 to FIG. 10 , the third peripheral area SA3 includes the first sub-bonding area BA adjacent to the first 31 The first edge area SA 31 , and the adjacent second sub-binding area BA 32 The second edge area SA 32 The flip chip film also includes at least two groups of common lines, each group of common lines includes a first common line CL1 and a second common line CL2, wherein each first common line CL1 of each group of common lines is connected from the second sub-binding area BA 32 In the first edge area SA 31 Each second common line CL2 of each group of common lines extends from the second sub-binding area BA 32 In the second edge area SA 32 Extension; In order to ensure the thickness uniformity of the pads 102 on both sides of the third peripheral area SA3, in the pattern set composed of multiple support patterns ST and multiple second accompanying plating patterns 32, each pattern is evenly distributed in the area between each group of common routings, and in the area between the first common routing CL1 and the second common routing CL2 in each group of common routings.

[0092] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 7 to 10, in order to facilitate the uniform arrangement of the pattern set composed of the support pattern ST and the second accompanying plating pattern 32, multiple support patterns ST and part of the second accompanying plating pattern 32 can be set integrally. Optionally, in the cross direction X of the extension direction Y of the pad 102, the width of the support pattern ST is approximately the same as the width of the second accompanying plating pattern 32 (that is, the same or within the error range caused by factors such as manufacturing process and measurement).

[0093] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 7 to 10, in the combined pattern composed of the integrally arranged support pattern ST and the second accompanying plating pattern 32, the support pattern ST is symmetrically arranged about the central axis of the combined pattern extending in the cross direction X of the extension direction Y of the pad 102, that is, in the extension direction Y of the pad 102, both sides of the support pattern ST can have the second accompanying plating pattern 32 integrally arranged with the support pattern ST. Such an arrangement is conducive to the support pattern ST to more evenly support the driver chip IC.

[0094] In some embodiments, in the flip chip film provided in the embodiments of the present disclosure, as shown in Figures 7 and 8, the second accompanying plating pattern 32 spaced apart from the support pattern ST is an independent pattern. Each combined pattern (composed of the integrated support pattern ST and the second accompanying plating pattern 32) is evenly distributed in the area between each group of common lines, and in the area between the first common line CL1 and the second common line CL2 in each group of common lines. Optionally, an independent pattern is provided between any two adjacent combined patterns. The independent patterns can be distributed approximately evenly between any two adjacent combined patterns. In some embodiments, the area of ​​the independent pattern between any two adjacent combined patterns accounts for 30% to 50%, for example, 30%, 40%, 50%, etc.

[0095] It should be noted that the “uniform distribution” in the present disclosure can be understood as “distributed at approximately equal intervals”, that is, the intervals between adjacent patterns are the same or within the error range caused by factors such as production and measurement.

[0096] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, in order to ensure the area ratio of multiple support patterns ST and multiple second accompanying plating patterns 32 in the third peripheral area SA3, it can be set in the extension direction Y of the pad 102, and the length of the combined pattern (composed of the integrally arranged support pattern ST and the second accompanying plating pattern 32) and the length of the independent pattern (the second accompanying plating pattern 32 separated from the support pattern ST) are respectively more than 50% of the distance between the first common trace CL1 and the second common trace CL1, for example, 50%, 60%, 70%, 80%, 90%, etc.

[0097] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in FIG9 , each combined pattern (composed of an integrally provided support pattern ST and a second accompanying plating pattern 32) forms at least one row, and each independent pattern (a second accompanying plating pattern 32 separated from the support pattern ST) forms at least two rows, at least one row of combined patterns and at least two rows of independent patterns are arranged in the extension direction Y of the pad 102, and the row where the combined pattern is located is farther away from the first edge area SA than the row where the independent pattern is located. 31 and the second edge area SA 32 For example, the combined pattern consisting of the support pattern ST and the second accompanying plating pattern 32 can be evenly arranged in the middle region of the third peripheral area SA3 to evenly support the driver chip IC via the support pattern ST. Optionally, a portion of the first common trace CL1 and a portion of the second common trace CL2 can also be used to support the driver chip IC.

[0098] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in FIG9 , in order to improve etching uniformity, the shape and width (i.e., the dimension in the intersecting direction X of the extension direction Y of the pad 102) of the combined pattern (composed of an integrally provided support pattern ST and a second accompanying plating pattern 32) and the shape and width of the independent pattern (the second accompanying plating pattern 32 provided separately from the support pattern ST) can be substantially the same as the shape and width of the pad 102 (i.e., the shape is the same or similar, the width is the same or within the error range caused by factors such as manufacturing and measurement). Optionally, the height (also referred to as thickness) and length (i.e., the dimension in the extension direction Y of the pad 102) of the combined pattern, as well as the height and length of the independent pattern can also be substantially the same as the height and length of the pad 102 (i.e., the same or within the error range caused by factors such as manufacturing and measurement). Optionally, a chip bump (IC Bump) is provided on the side of the support pattern ST away from the base substrate.

[0099] In some embodiments, in the above-mentioned flip chip film provided in the embodiment of the present disclosure, as shown in FIG10, each combined pattern (composed of the integrally provided support pattern ST and the second accompanying plating pattern 32) forms at least one row, and each independent pattern (the second accompanying plating pattern 32 separated from the support pattern ST) is located between the area where the combined pattern is located and the first sub-binding area BA. 31 Between the area where the combination pattern is located and the second sub-binding area BA 32 The strip plating pattern 322 may be formed between the pads 102 and the strip plating pattern. Optionally, in the cross direction X of the extending direction Y of the pads 102, the length of the strip plating pattern 322 may be greater than or equal to the distance between the starting and ending positions of a row of pads 102. In some embodiments, in the cross direction X of the extending direction Y of the pads 102, the length of the strip plating pattern may be greater than the length of the driver chip IC.

[0100] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 6, 7, 9 and 10, the peripheral area may include a fourth peripheral area SA4 and a fifth peripheral area SA5, the fourth peripheral area SA4 and the fifth peripheral area SA5 respectively extending in the extension direction Y of the pad 102, and in the cross direction X of the extension direction Y of the pad 102, the fourth peripheral area SA4 and the fifth peripheral area SA5 are separated on both sides of the binding area (for example, the first binding area BA1, the second binding area BA2, and the third binding area BA3); the flip chip film may also include a fourth peripheral area SA4 and a fifth peripheral area SA5 located in the fourth peripheral area SA4. The alignment mark 104 of the peripheral area SA4 and the fifth peripheral area SA5 is provided in the same layer and with the same material as the multiple pads 102; the accompanying plating pattern 103 includes a third accompanying plating pattern 33 located in the fourth peripheral area SA4 and / or the fifth peripheral area SA5, and the third accompanying plating pattern 33 is arranged around the alignment mark 104 on both sides of the intersection of the alignment mark 104 and the extension direction Y of the pad 102, and at least one side of the side of the alignment mark 104 away from the binding area, and there is a preset distance l (for example, 0.3 mm) between the third accompanying plating pattern 33 and the alignment mark 104.

[0101] In the related art, due to the concentration of electric force lines and high current density in the edge areas of the bonding areas (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3) adjacent to the fourth peripheral area SA4 and / or the fifth peripheral area SA5 during the electroplating process, the thickness uniformity of the pad 102 in these edge areas is poor. By providing the third accompanying plating pattern 33 in the fourth peripheral area SA4 and / or the fifth peripheral area SA5, the areas with concentrated electric force lines and high current density are transferred to the fourth peripheral area SA4 and / or the fifth peripheral area SA5, thereby ensuring that the electric force lines and current density in the edge areas of the bonding areas (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3) adjacent to the fourth peripheral area SA4 and / or the fifth peripheral area SA5 are normal, thereby forming the pad 102 with uniform thickness. In addition, a preset distance (e.g., 0.3 mm) is provided between the third accompanying plating pattern 33 and the alignment mark 104 to ensure that the third accompanying plating pattern 33 and the alignment mark 104 are relatively independent, facilitating identification of the alignment mark 104 during the subsequent bonding process and improving bonding yield. Optionally, the third accompanying plating pattern 33 does not carry any electrical signal.

[0102] In some embodiments, in the flip chip film provided by the present disclosure, as shown in Figures 6, 7, 9, and 10, the third accompanying plating pattern 33 may include a plurality of strip patterns sequentially arranged along the extension direction Y of the pad 102. Alternatively, as shown in Figures 11 and 12, the third accompanying plating pattern 33 may be a block pattern. Alternatively, to ensure that the pad 102 within the bonding area (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3) completely avoids areas with concentrated electric field lines and high current density, the third accompanying plating pattern 33 may be arranged within the fourth peripheral area SA4 and the fifth peripheral area SA5 within a range of 1 mm to 5 mm from the bonding area (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3). Specifically, the third accompanying plating pattern 33 may have a length l1 greater than or equal to 1 mm and less than or equal to 5 mm, for example, 1 mm, 2 mm, 3 mm, 4 mm, 5 mm, etc., on both sides of the alignment mark 104 in the cross direction X intersecting the extension direction Y of the pad 102. Correspondingly, on the side of the alignment mark 104 away from the binding area (for example, the first binding area BA1, the second binding area BA2, and the third binding area BA3), the length of the third accompanying plating pattern 33 in the cross direction X is approximately equal to (l1-l2-l), where l2 is the length of the alignment mark 104 in the cross direction X, and l is the preset distance between the alignment mark 104 and the third accompanying plating pattern 33 in the cross direction X.

[0103] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 6, 7, 9 to 12, in the extension direction Y of the pad 102, the distance from the end surface of the third accompanying plating pattern 33 away from the binding area (for example, the first binding area BA1, the second binding area BA2, the third binding area BA3) to the binding area (for example, the first binding area BA1, the second binding area BA2, the third binding area BA3) is approximately the same as the length of the first accompanying plating pattern 31, that is, the two are the same or within the error range caused by factors such as manufacturing and measurement.

[0104] In some embodiments, the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 13 to 19, may further include a first protective pattern 105 located on the side of the layer where the multiple pads 103 are located away from the base substrate 101, and the orthographic projection of the first protective pattern 105 on the base substrate 101 overlaps with the orthographic projections of the first accompanying plating pattern 31 and the third accompanying plating pattern 33 arranged side by side in the cross direction X of the extension direction Y of the pad 102 on the base substrate 101, and in the extension direction Y of the pad 102, there is a preset distance (for example, a preset distance of 100 μm) between the orthographic projection of the first protective pattern 105 on the base substrate 101 and the binding area (for example, the first binding area BA1, the second binding area BA2, and the third binding area BA3). The first protective pattern 105 can improve the flatness of the first and third accompanying plating patterns 31 and 33 covered by it. Furthermore, considering the manufacturing precision of the first protective pattern 105 and the need for overflow space during the subsequent bonding of the display substrate and the chip-on-film (COF) using anisotropic conductive adhesive (ACF), a predetermined distance is provided between the first protective pattern 105 and the bonding areas (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3). This ensures that the first protective pattern 105 only covers the portion of the first accompanying plating pattern 31 away from the bonding areas (e.g., the first bonding area BA1, the second bonding area BA2, and the third bonding area BA3) and the portion of the third accompanying plating pattern 33 arranged alongside this portion. In some embodiments, the first protective pattern 105 can be formed from the same layer and material as the solder mask layer in the related art. Optionally, the first protective pattern 105 is made of green resin (SR) with a thickness of 5 μm to 20 μm, for example, 5 μm, 10 μm, 15 μm, or 20 μm.

[0105] In some embodiments, in the above-mentioned flip chip film provided in the embodiments of the present disclosure, as shown in Figures 14, 16, 17 and 19, it can also include a second protection pattern 106 integrally provided with the first protection pattern 105, and the orthographic projection of the second protection pattern 106 on the base substrate 101 overlaps with the orthographic projection of the third accompanying plating pattern 33 on the base substrate 101, and in the intersection direction X of the extension direction Y of the pad 102, there is a preset distance (for example, 100μm to 200μm) between the orthographic projection of the second protection pattern 106 on the base substrate 101 and the binding area (for example, the third binding area BA3). The second protective pattern 106 can improve the flatness of the position where the third accompanying plating pattern 33 covered by it is located; and taking into account the production accuracy of the second protective pattern 106, in order to prevent the second protective pattern 106 from covering the pad 102, the present disclosure provides a preset distance between the second protective pattern 105 and the binding area (for example, the third binding area BA3), so that the second protective pattern 105 only covers a portion of the third accompanying plating pattern 33 away from the binding area (for example, the third binding area BA3).

[0106] In some embodiments, in the COF provided by the embodiments of the present disclosure, the multiple bonding areas may include a first bonding area BA1 for bonding to a display substrate and a second bonding area BA2 for bonding to a flexible circuit board. Because the bonding punch used in the bonding process of the display substrate and the flexible circuit board has a larger dimension in the direction X intersecting the extension direction Y of the pad 102 than the dimensions of the bonding areas (e.g., the first bonding area BA1 and the second bonding area BA2), the punch simultaneously presses the bonding areas (e.g., the first bonding area BA1 and the second bonding area BA2), as well as the fourth and fifth peripheral areas SA4 and SA5. If the second protective pattern 106 covering the third accompanying plating pattern 33 is provided in the fourth and fifth peripheral areas SA4 and SA5, the film height in the fourth and fifth peripheral areas SA4 and SA5 will be greater than the film height in the bonding areas (e.g., the first and second bonding areas BA1 and BA2), resulting in uneven force distribution in the bonding areas (e.g., the first and second bonding areas BA1 and BA2). Therefore, only the first protective pattern 105 may be provided around the first and second bonding areas BA1 and BA2.

[0107] In some embodiments, the multiple binding areas may further include a third binding area BA3 for binding a driver chip IC. Since the size of the driver chip IC is approximately equal to the sum of the size of the third binding area BA3 and the size of the third peripheral area SA3, the film layer height of the peripheral area around the third binding area BA3 (for example, the first peripheral area SA1, the second peripheral area SA2, the fourth peripheral area SA4, and the fifth peripheral area SA5) has no effect on the binding of the driver chip IC. Therefore, the first protection pattern 105 and the second protection pattern 106 can be set simultaneously around the third binding area BA3.

[0108] In some embodiments, in the above-mentioned flip-chip film provided by the embodiments of the present disclosure, as shown in Figures 13 and 18, within the first bonding area BA1 and the second bonding area BA2, each row of pads 102 is arranged at equal intervals in the extension direction Y of the pads 102, and two adjacent rows of pads 102 are partially staggered along the direction X that intersects the extension direction Y of the pads 102. Compared to the solution in which each row of pads 102 is arranged flush, the present disclosure partially staggers any two adjacent rows of pads 102 along the intersecting direction X, thereby ensuring that there is more space for arranging leads 107 electrically connected to pads 102 in different rows.

[0109] In some embodiments, in the above-mentioned flip chip provided by the embodiment of the present disclosure, as shown in FIG. 14 to FIG. 17 and FIG. 19 , the third bonding area BA3 includes the first sub-bonding area BA 31 and the second sub-binding region BA 32 , and in the first sub-binding area BA 31 and the second sub-binding region BA32 , each row of pads 102 is arranged at equal intervals in the extending direction Y of the pads 102, and two adjacent rows of pads 102 are partially staggered along the intersecting direction X of the extending direction Y of the pads 102; in the intersecting direction X of the extending direction Y of the pads 102, the second sub-binding area BA 32 The first signal output area O1 and the second signal output area O2 are arranged side by side, and the signal input binding area I is located between the first signal output area O1 and the second signal output area O2; the first sub-binding area BA 31 The device includes a third signal output area O3 and a fourth signal output area O4. The third signal output area O3 is arranged side by side with the first signal output area O1 in the extension direction Y of the pads 102, and the fourth signal output area O4 is arranged side by side with the second signal output area O2 in the extension direction Y of the pads 102. Optionally, the rows of pads 102 in the first signal output area O1 and the rows of pads 102 in the third signal output area O3 are arranged symmetrically about the central axis of the driver chip IC along the intersecting direction X of the pads 102 extension direction Y, and the rows of pads 102 in the second signal output area O2 and the rows of pads 102 in the fourth signal output area O4 are arranged symmetrically about the central axis of the driver chip IC along the intersecting direction X of the pads 102 extension direction Y. Optionally, in the present disclosure, each pad 102 of the first signal output area O1, the second signal output area O2, the third signal output area O3, and the fourth signal output area O4 is connected to the data pin (Source pin) of the display substrate through the leads 107 arranged on both sides of the driver chip IC to maximize the number of data pins; the pad 102 of the signal input binding area I is connected to the flexible circuit board through the lead 107 to receive the driving signal provided by the flexible circuit board.

[0110] Accordingly, the present disclosure also provides a method for manufacturing the above-mentioned chip-on-film, which may include the following steps:

[0111] In the first step, as shown in Figure 20, a base substrate 101 is coated or bonded to the glass substrate G, and a barrier layer 108 is deposited on the base substrate 101; wherein the base substrate 101 can be a flexible substrate made of a material such as polyimide, and the thickness of the base substrate 101 can be greater than or equal to 10 μm and less than or equal to 40 μm, for example, the thickness of the base substrate 101 is 10 μm, 20 μm, 30 μm, 40 μm, etc.; the material of the barrier layer 108 can be silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), etc., and the barrier layer 108 can be a single-layer structure or a stacked-layer structure, and the thickness of the barrier layer 108 is greater than or equal to 100 nm and less than or equal to 500 nm, for example, the thickness of the barrier layer 108 is 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, etc.

[0112] In the second step, as shown in Figures 21 to 24, a metal film layer is deposited on the barrier layer 108. The material of the metal film layer can be molybdenum (Mo), aluminum (Al), titanium (Ti) and other materials suitable for dry etching. The metal film layer can be a single layer of metal or a laminated metal. For example, the metal film layer is a triple layer consisting of a titanium metal layer / an aluminum metal layer / a titanium metal layer. Optionally, the thickness of the metal film layer consisting of the titanium metal layer / an aluminum metal layer / a titanium metal layer is greater than or equal to 500nm and less than or equal to 1000nm. For example, the thickness of the metal film layer is 500nm, 600nm, 700nm. , 800nm, 900nm, 1000nm, etc.; the metal film layer is then patterned to form leads 107. To achieve a smaller lead pitch, the metal film layer is etched by a dry etching process to form the leads 107. The leads 107 include a routing portion 71 and a widened portion 72 for connecting to the subsequent pads 102. Due to the precision limitations of the binding equipment, the spacing of the widened portions 72 needs to be greater than 20μm. If single-layer wiring is used, the spacing of the routing portions 71 in the densest wiring area between the widened portions 72 is less than 4μm. To maximize the number of data pins (source pins), data lines are wired and connected above and below the third binding area BA3 for binding the driver chip IC. The lead 702 in the middle area at the lower end of the third binding area BA3 is an input signal line (input line) for connecting to the flexible circuit board.

[0113] In the third step, as shown in Figure 25, an insulating layer 109 is formed on the layer where the lead 107 is located. The material of the insulating layer 109 can be silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), etc. The insulating layer 109 can be a single-layer structure or a stacked structure. The thickness of the insulating layer 109 is greater than or equal to 100nm and less than or equal to 500nm. For example, the thickness of the insulating layer 109 is 100nm, 200nm, 300nm, 400nm, 500nm, etc., and a transfer hole V is set in the insulating layer 109 at the position of the widened portion 72. Optionally, each widened portion 72 is electrically connected to a corresponding pad 102 produced subsequently through at least one transfer hole V.

[0114] In the fourth step, as shown in FIG26 , a solder pad 102 is formed by electroplating on the insulating layer 109. The solder pad 102 is made of copper. To ensure sufficient space for glue overflow during the bonding process, the thickness of the solder pad 102 must be greater than or equal to 5 μm and less than or equal to 8 μm. For example, the thickness of the solder pad 102 is 5 μm, 6 μm, 7 μm, 8 μm, etc. It should be noted that when the solder pad 102 is formed, a plating pattern 103 and an alignment mark 104 are also formed. The description of the plating pattern 103 and the alignment mark 104 is as described above and will not be repeated here.

[0115] In the fifth step, as shown in Figure 27, an anti-oxidation layer 110 is formed on the pad 102. The material of the anti-oxidation layer 110 can be tin (Sn) metal, etc. In some embodiments, the anti-oxidation layer 110 can be formed by a chemical plating process. The thickness of the anti-oxidation layer 110 is greater than or equal to 0.5μm and less than or equal to 2μm, for example, 0.5μm, 1μm, 1.5μm, 2μm, etc.; in addition, the surface of the pad 102 can also be covered with indium tin oxide (ITO) to prevent the pad 102 from being oxidized.

[0116] In the sixth step, as shown in Figure 28, a solder resist layer 111 is brushed on the non-binding area above the anti-oxidation layer 110. The material of the solder resist layer 111 can be green oil, and the thickness of the solder resist layer 111 can be greater than or equal to 5μm and less than or equal to 20μm. Optionally, the thickness of the solder resist layer 111 is 5μm, 10μm, 15μm, 20μm, etc.; it should be noted that while forming the solder resist layer 111, a first protective pattern 105 and a second protective pattern 106 that partially cover the accompanying plating pattern 103 can also be formed near the binding area (for example, the first binding area BA1, the second binding area BA2, and the third binding area BA3), and the description of the accompanying plating pattern 103 and the alignment mark 104 can be found above and will not be repeated here.

[0117] In the seventh step, as shown in FIG29 , the large-sized COF is subjected to laser lift-off (LLO) to remove the glass substrate G, and the COF is cut to obtain a plurality of target-sized COFs.

[0118] In the eighth step, as shown in FIG30 , the flip chip of the target size is bonded to the driver chip IC at the third bonding area BA3 for bonding the driver chip IC, and is encapsulated by dispensing glue to obtain the flip chip with the driver chip IC.

[0119] It should be noted that in the above-mentioned fabrication methods provided in the embodiments of the present disclosure, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes. The specific process is based on the formation of the desired pattern during the actual fabrication process and is not limited here. For example, a post-baking process may be included after development and before etching.

[0120] Among them, the deposition process can be chemical vapor deposition, plasma enhanced chemical vapor deposition or physical vapor deposition, which is not limited here; the mask plate used in the mask process can be a half tone mask plate (Half Tone Mask), a single slit diffraction mask (Single Slit Mask) or a gray tone mask (Gray Tone Mask), which is not limited here; the etching can be dry etching or wet etching, which is not limited here.

[0121] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in Figure 31, which may include a cover chip film 001, a display substrate 002, a driver chip IC and a circuit board (such as a flexible circuit board FPC), wherein the cover chip film 001 is the above-mentioned cover chip film 001 provided in the embodiment of the present disclosure, and the cover chip film 001 includes binding areas corresponding one to one with the display substrate 001, the driver chip IC, and the circuit board (such as a flexible circuit board FPC). Optionally, the display substrate 002 is electrically connected to the first binding area BA1 of the cover chip film 001, the flexible circuit board FPC is electrically connected to the second binding area BA2 of the cover chip film 001, and the driver chip IC is electrically connected to the third binding area BA3 of the cover chip film 001.

[0122] In some embodiments, as shown in FIG32 , the pins 102 ' of the display substrate 002 or the flexible circuit board FPC are electrically connected to the pads 102 of the corresponding bonding area in the COF 001 in a one-to-one correspondence. Alternatively, as shown in FIG33 and FIG34 , the bumps BP of the driver chip IC are electrically connected to the first sub-bonding area BA. 31 , and the second sub-binding area BA 32 The pads 102 are electrically connected one by one, and in the first sub-bonding area BA 31 With the second sub-binding area BA 32 Within the third peripheral area SA3, support patterns ST are uniformly arranged, fixedly connected to the bumps BP of the driver chip IC. Optionally, the bumps BP corresponding to the support patterns ST do not provide electrical signals and only serve to balance the bonding pressure. Furthermore, as shown in Figures 33 and 34, first and second common traces CL1 and CL2 may also be provided. These first and second common traces CL1 and CL2 can be connected to power signals (Pwr) and ground signals (Gnd) provided by the flexible printed circuit board (FPC). Optionally, the bumps BP of the driver chip IC, which serve to balance the bonding pressure, may also be fixedly connected to the common traces CL.

[0123] In some embodiments, the display device provided by the embodiments of the present disclosure may be a liquid crystal display device. As shown in FIG35 , the liquid crystal display device includes a backlight module BLU and a liquid crystal display panel PNL located on the light-emitting side of the backlight module BLU. The liquid crystal display panel may be a twisted nematic (TN) liquid crystal display panel, an advanced dimension switch (ADS) liquid crystal display panel, a high-aperture ratio advanced dimension switch (HADS) liquid crystal display panel, an in-plane switch (IPS) liquid crystal display panel, or the like.

[0124] In some embodiments, the liquid crystal display panel PNL includes a first substrate 201 and a second substrate 202 disposed opposite to each other, a first liquid crystal layer 203 located between the first substrate 201 and the second substrate 202, a first sealant 204 surrounding the first liquid crystal layer 203 is provided between the first substrate 201 and the second substrate 202, a driving circuit 205 and a pixel electrode (not shown in the figure) may be provided on the side of the first substrate 201 facing the first liquid crystal layer 203, and a color filter 206 may be provided on the side of the second substrate 202 facing the first liquid crystal layer 203, the color filter 206 including a black matrix 61 and color resistance 62. Optionally, the common electrode (Com) of the liquid crystal display panel PNL can be arranged on the side of the layer where the driving circuit 205 is located away from the first substrate 201, or be arranged on the side of the color film 206 away from the second substrate 202. The liquid crystal display panel PNL may further include a first polarizer (pol, not shown in the figure) located on the side of the first substrate 201 away from the first liquid crystal layer 203, and a second polarizer (pol, not shown in the figure) located on the side of the second substrate 202 away from the first liquid crystal layer 203, etc., wherein the transmittance axis of the first polarizer is perpendicular to the transmittance axis of the second polarizer.

[0125] In some embodiments, the backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser, and a brightening film stacked on the light-emitting side of the matrix light source, and the reflective sheet includes an opening that is arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source may be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0126] Submillimeter or even micron-scale micro-LEDs are self-luminous devices, just like organic light-emitting diodes (OLEDs). Like organic light-emitting diodes, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angles. And because inorganic light-emitting diodes emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life compared to organic light-emitting diodes that emit light based on organic matter. And when micro-LEDs are used as backlight sources, they can achieve more precise dynamic backlight effects. While effectively improving screen brightness and contrast, they can also solve the glare phenomenon caused by traditional dynamic backlighting between bright and dark areas of the screen, thereby optimizing the visual experience.

[0127] In some embodiments, the display device provided by the embodiments of the present disclosure can be a 3D display device. In this case, as shown in FIG35 , the display device can further include a liquid crystal grating (LCG) positioned between the backlight module (BLU) and the liquid crystal display panel (PNL). The liquid crystal grating (LCG) can be secured to the liquid crystal display panel (PNL) via an adhesive layer (004). Optionally, based on the current position of the viewer's eyes, the liquid crystal grating (LCG) can be controlled to form alternating light-transmitting and light-blocking regions, allowing the viewer's left eye to see the left-eye image displayed on the display panel (PNL) through the light-transmitting regions of the liquid crystal grating (LCG), while the viewer's right eye sees the right-eye image displayed on the display panel (PNL) through the light-transmitting regions. By positioning the liquid crystal grating (LCG) on the light-incident side of the liquid crystal display panel (PNL), when the liquid crystal display panel (PNL) includes touch electrodes, the liquid crystal grating (LCG) does not shield the touch electrodes in the liquid crystal display panel (PNL), preventing touch failure and thereby improving the touch sensitivity and accuracy of the liquid crystal display panel (PNL).

[0128] In some embodiments, as shown in FIG35 , the liquid crystal grating LCG may include a third substrate 301 and a fourth substrate 302 disposed opposite to each other, a second liquid crystal layer 303 located between the third substrate 301 and the fourth substrate 302, first strip electrodes 304 located on the side of the third substrate 301 facing the second liquid crystal layer 303, second strip electrodes 305 located on the layer containing the first strip electrodes 304 facing the second liquid crystal layer 303, a planar electrode 306 located on the side of the fourth substrate 302 facing the second liquid crystal layer 303, a first transistor T1 electrically connected to the first strip electrodes 304, a second transistor T2 electrically connected to the second strip electrodes 305, and a second encapsulation layer 307 surrounding the second liquid crystal layer 303 between the third substrate 301 and the fourth substrate 302. In a specific implementation, by energizing the first strip electrode 304, the second strip electrode 305, and the planar electrode 306, the second liquid crystal layer 303 can be controlled to form a light-transmitting area and a light-shielding area, so as to cooperate with the liquid crystal display panel PNL that outputs the left-eye image and the right-eye image to achieve 3D display.

[0129] In some embodiments, the display device provided by the embodiments of the present disclosure can be a 3D display device. As shown in FIG36 , the 3D display device can further include a spectroscopic assembly SE located on the light-emitting side of the liquid crystal display panel PNL. Optionally, the spectroscopic assembly SE includes multiple spectroscopic structures 501 arranged parallel to each other and side by side. The spectroscopic structure 501 can be a composite lens formed by a high-refractive index resin layer 501a and a low-refractive index resin layer 501b. Specifically, the high-refractive index resin layer 501a is composed of multiple cylindrical lenses, and the low-refractive index resin layer 501b fills the gaps between the cylindrical lenses, and the thickness of the low-refractive index resin layer is greater than the arch height of the cylindrical lenses. The cylindrical lenses can have ridges or no ridges. Optionally, the composite lens can have a transparent substrate 502. For example, the substrate 502 can be made of polyethylene terephthalate (PET). In some embodiments, a spacer glass 006 can be provided between the liquid crystal display panel PNL and the spectroscopic assembly SE, and the spacer glass 006 and the spectroscopic assembly SE are bonded and fixed using optical adhesive 007.

[0130] In a specific implementation, the image plane of the liquid crystal display panel PNL is set to be located on the focal plane of the cylindrical lens. The pixels under each cylindrical lens are divided into several sub-pixels. The pixels at different positions on the liquid crystal display panel PNL are refracted and split by the cylindrical lens, and the light path changes, thereby forming different viewpoints in space. When the left eye receives the left viewpoint image, the right eye also receives the right viewpoint image, thereby realizing 3D display.

[0131] In some embodiments, the liquid crystal display panel in the above-mentioned display device provided by the embodiment of the present disclosure can also be replaced with an electroluminescent display panel (Organic Light Emitting Diodes, OLED) or a quantum dot display panel (Quantum Dot Light Emitting Diodes, QLED), which is not limited here. The OLED display panel or the QLED display panel includes a light-emitting device and a pixel driving circuit electrically connected to the light-emitting device; wherein the light-emitting device may include a cathode and an anode opposite to each other, and a light-emitting functional layer between the cathode and the anode; the pixel driving circuit may include a thin film transistor, a storage capacitor, etc., and can be implemented in various different types, such as a 2TIC type (i.e., including two thin film transistors and a storage capacitor), and can further include more transistors and / or capacitors on the basis of the 2T1C type to have compensation, reset, light control, detection and other functions. The embodiment of the present disclosure does not limit the pixel driving circuit. For example, in some embodiments, the thin film transistor directly electrically connected to the light-emitting element can be a driving transistor (Td) or a light-emitting control transistor (EM), etc.

[0132] In some embodiments, the light-emitting functional layer includes, but is not limited to, a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like. The light-emitting material layer may be a red light material layer, a green light material layer, a blue light material layer, a yellow light material layer, a white light material layer, and the like. For OLED display devices, the light-emitting material layer may include small molecule organic materials or polymer molecules, and may be fluorescent light-emitting materials, phosphorescent light-emitting materials, and the like. For QLED display devices, the light-emitting material layer may include silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, zinc selenide quantum dots, cadmium telluride quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, indium arsenide quantum dots, and the like.

[0133] In some embodiments, the anode material may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc.; in addition, the anode may include a metal with high reflectivity as a reflective layer, such as silver (Ag). The cathode material may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).

[0134] In some embodiments, the thin film transistor includes a gate, a source, a drain and an active layer, wherein the material of the active layer may include amorphous silicon, polycrystalline silicon or an oxide semiconductor (e.g., indium gallium zinc oxide). The materials of the gate, source and drain may include metal materials or alloy materials, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (e.g., a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti). Optionally, the thin film transistor may be a bottom gate transistor, a top gate transistor, a double gate transistor, etc. In some embodiments, the thin film transistor may be a P-type transistor or an N-type transistor, wherein the voltage difference V between the gate and the source of the P-type transistor is gs Its threshold voltage V th Satisfying the relationship V gs <V th When it is turned on, the voltage difference between its gate and its source is V gs Its threshold voltage V th Satisfying the relationship V gs ≥V th When the N-type transistor is turned off; the voltage difference V between its gate and its source gs Its threshold voltage V th Satisfy the relationship V gs >V th When it is turned on, the voltage difference between its gate and its source is V gs Its threshold voltage V th Satisfy the relationship V gs ≤V th Time deadline.

[0135] In some embodiments, the OLED / QLED display panel may further include an encapsulation layer on the light-emitting side of the light-emitting element. The encapsulation layer seals the light-emitting element, thereby reducing or preventing degradation of the light-emitting element caused by moisture and / or oxygen in the environment. The encapsulation layer may be a single-layer structure or a composite layer structure, wherein the composite layer structure includes a stacked structure of inorganic layers and organic layers. For example, the encapsulation layer may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer arranged in sequence. The material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, and the like. The material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, to flatten the surface of the display substrate and relieve stress in the first and second inorganic encapsulation layers. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that intrude into the interior.

[0136] In some embodiments, the OLED / QLED display panel may further include a touch structure located above the encapsulation layer, which may be a self-capacitive touch structure or a mutual capacitance touch structure. The self-capacitive touch structure includes a plurality of self-capacitive electrodes arranged in an array (on the same layer), each self-capacitive electrode being electrically connected to a touch processing circuit (touch driver chip) via a touch lead. Position detection is achieved by detecting changes in the capacitance of the self-capacitive electrode due to, for example, the proximity of a finger during touch. The mutual capacitance touch structure includes a plurality of first touch signal lines extending in a first direction and a plurality of second touch signal lines extending in a second direction, the first touch signal line and the second touch signal line being electrically connected to the touch processing circuit (touch driver chip) via touch leads. The first direction and the second direction intersect with each other and form an opening, thereby forming a touch capacitor at the intersection of the first touch signal line and the second touch signal line, and position detection is achieved by detecting changes in the touch capacitance due to, for example, the proximity of a finger during touch. The material forming the touch structure may be indium tin oxide, a metal mesh, or the like.

[0137] In some embodiments, the OLED / QLED display panel may further include a circular polarizer or a color film located above the layer where the touch structure is located, and the color film includes a grid-shaped black matrix and a color resistor arranged in the mesh. Optionally, a protective cover is provided on top of the circular polarizer or the color film. In some embodiments, the protective cover may be an ultra-thin glass (UTG) cover. Since the ultra-thin glass cover not only maintains the characteristics of glass but also has good flexibility, it can fully meet the needs of folding products. Specifically, ultra-thin glass (UTG) refers to a glass layer with a thickness of tens of microns or less, which can be bent and deformed and can be folded. Compared with polymer plastic film, ultra-thin glass can effectively avoid screen damage while providing better optical clarity. At the same time, ultra-thin glass is not prone to creases and has good reliability. Moreover, it will not be naturally decomposed like plastic and has a long life, thereby providing more stable and reliable protection for the display screen.

[0138] In some embodiments, the above-mentioned display device provided by the embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, etc. Optionally, the above-mentioned display device provided by the embodiment of the present disclosure includes but is not limited to components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer executable codes, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0139] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A chip-on-film, wherein: include: a base substrate, the base substrate comprising a plurality of binding regions and a peripheral region disposed around each of the binding regions; A plurality of pads are located on the substrate, and each of the binding areas is provided with a plurality of pads; The accompanying plating pattern is provided in the same layer and with the same material as the plurality of pads, and the accompanying plating pattern is located in the peripheral area on at least one side of the binding area.

2. The chip-on-film according to claim 1, wherein: In each of the binding areas, the pads are arranged into multiple rows along the extension direction of the pads, the peripheral area includes a first peripheral area on the side where the first row of pads is located, and the second peripheral area on the side where the last row of pads is located, and the accompanying plating pattern includes a first accompanying plating pattern located in the first peripheral area and / or the second peripheral area.

3. The chip-on-film according to claim 2, wherein: The first accompanying plating pattern corresponds one-to-one to each of the pads in the first row and / or each of the pads in the last row, and the first accompanying plating pattern is integrally provided with the corresponding pad.

4. The chip-on-film according to claim 2 or 3, wherein: One of the plurality of binding regions comprises a first sub-binding region and a second sub-binding region arranged side by side in an extending direction of the pad; The peripheral region further includes a third peripheral region located between the first sub-binding region and the second sub-binding region, and the accompanying plating pattern includes a plurality of second accompanying plating patterns located in the third peripheral region.

5. The chip-on-film according to claim 4, wherein: It also includes a plurality of support patterns, and the plurality of support patterns are located in the third peripheral area.

6. The chip-on-film according to claim 5, wherein: The third peripheral region includes a first edge region adjacent to the first sub-binding region, and a second edge region adjacent to the second sub-binding region; The chip-on-film further includes at least two groups of common routing lines, each group of common routing lines includes a first common routing line and a second common routing line, wherein the first common routing line is led out from the second sub-binding area and extends in the first edge area, and the second common routing line is led out from the second sub-binding area and extends in the second edge area; In the pattern set consisting of the multiple supporting patterns and the multiple second accompanying plating patterns, each pattern is evenly distributed in the area between each group of the common routing lines and in the area between the first common routing line and the second common routing line in each group of the common routing lines.

7. The chip-on-film according to claim 6, wherein: The plurality of supporting patterns are integrally provided with a portion of the second accompanying plating pattern.

8. The chip-on-film according to claim 7, wherein: In the combined pattern formed by the integrally arranged support pattern and the second accompanying plating pattern, the support pattern is symmetrically arranged about a central axis of the combined pattern extending in a direction intersecting the extending direction of the pad.

9. The chip-on-film according to claim 7 or 8, wherein: The second accompanying plating pattern separated from the supporting pattern is an independent pattern, and each of the combined patterns is evenly distributed in the area between each group of the common lines and in the area between the first common line and the second common line in each group of the common lines.

10. The chip-on-film according to claim 9, wherein: In the extending direction of the pad, the length of the combined pattern and the length of the independent pattern are both greater than 50% of the distance between the first common trace and the second common trace.

11. The chip-on-film according to claim 7 or 8, wherein: The second accompanying plating pattern separated from the supporting pattern is an independent pattern, each of the combined patterns forms at least one row, each of the independent patterns forms at least two rows, at least one row of the combined patterns and at least two rows of the independent patterns are arranged in the extension direction of the pad, and the row where the combined patterns are located is farther away from the first edge area and the second edge area than the row where the independent patterns are located.

12. The chip-on-film according to claim 9 or 11, wherein: The shape and width of the combined pattern, and the shape and width of the independent pattern are substantially the same as the shape and width of the pad, respectively.

13. The chip-on-film according to claim 7 or 8, wherein: The second accompanying plating patterns spaced apart from the supporting pattern are independent patterns, the combined patterns forming at least one row, and the independent patterns are strip-shaped accompanying plating patterns located between the area where the combined patterns are located and the first sub-binding area, and between the area where the combined patterns are located and the second sub-binding area; In a direction intersecting the extending direction of the pads, the length of the strip-shaped accompanying plating pattern is greater than or equal to the distance between the starting and ending positions of a row of pads.

14. The chip-on-film according to any one of claims 2 to 13, wherein: The length of the first accompanying plating pattern in the extending direction of the pad is greater than or equal to 300 μm and less than or equal to 1000 μm.

15. The chip-on-film according to any one of claims 1 to 14, wherein: The peripheral area includes a fourth peripheral area and a fifth peripheral area, the fourth peripheral area and the fifth peripheral area extend in the extending direction of the pad, and in the intersecting direction of the extending direction of the pad, the fourth peripheral area and the fifth peripheral area are located on both sides of the binding area; The chip-on-film further includes alignment marks located in the fourth peripheral area and the fifth peripheral area, and the alignment marks are provided in the same layer and the same material as the plurality of pads; The accompanying plating pattern includes a third accompanying plating pattern located in the fourth peripheral area and / or the fifth peripheral area, and the third accompanying plating pattern is arranged around the alignment mark on both sides where the alignment mark and the extension direction of the pad are intersected, and on at least one side of the side of the alignment mark away from the binding area, and there is a preset distance between the third accompanying plating pattern and the alignment mark.

16. The chip-on-film according to claim 15, wherein: The third accompanying plating pattern is a block pattern.

17. The chip-on-film according to claim 15, wherein: The third accompanying plating pattern includes a plurality of strip patterns sequentially arranged in an extending direction of the pad.

18. The chip-on-film according to any one of claims 15 to 17, wherein: On both sides of the alignment mark in the direction intersecting the extending direction of the pad, the length of the third accompanying plating pattern in the direction intersecting the extending direction of the pad is greater than or equal to 1 mm and less than or equal to 5 mm.

19. The chip-on-film according to any one of claims 15 to 18, wherein: In the extending direction of the pad, a distance from an end surface of the third accompanying plating pattern away from the binding area to the binding area is substantially the same as a length of the first accompanying plating pattern.

20. The chip-on-film according to any one of claims 15 to 19, wherein: It also includes a first protective pattern located on the side of the layer where the multiple pads are located away from the base substrate, and the orthographic projection of the first protective pattern on the base substrate overlaps with the orthographic projections of the first accompanying plating pattern and the third accompanying plating pattern arranged side by side in the cross direction of the pad extension direction, and in the pad extension direction, there is a preset distance between the orthographic projection of the first protective pattern on the base substrate and the binding area.

21. The chip-on-film according to claim 20, wherein: The plurality of binding areas include a first binding area for binding a display substrate, and a second binding area for binding a circuit board.

22. The chip-on-film according to claim 21, wherein: In the first binding area and the second binding area, two adjacent rows of pads are partially staggered along a direction intersecting with an extending direction of the pads.

23. The chip-on-film according to claim 20, wherein: It also includes a second protective pattern integrally arranged with the first protective pattern, the orthographic projection of the second protective pattern on the base substrate overlaps with the orthographic projection of the third accompanying plating pattern on the base substrate, and in the cross direction of the pad extension direction, there is a preset distance between the orthographic projection of the second protective pattern on the base substrate and the binding area.

24. The chip-on-film according to claim 23, wherein: The plurality of bonding areas include a third bonding area for bonding a driving chip.

25. The chip-on-film according to claim 24, wherein: The third binding area includes the first sub-binding area and the second sub-binding area, and in the first sub-binding area and the second sub-binding area, two adjacent rows of pads are partially staggered along a direction intersecting with an extending direction of the pads; In a direction intersecting the extending direction of the pad, the second sub-binding area includes a first signal output area and a second signal output area arranged side by side, and a signal input area located between the first signal output area and the second signal output area; The first sub-binding area includes a third signal output area and a fourth signal output area. The third signal output area and the first signal output area are arranged side by side in the extending direction of the pad. The fourth signal output area and the second signal output area are arranged side by side in the extending direction of the pad.

26. A display device, wherein: The device comprises a display substrate, a circuit board, a driver chip and a chip-on-film, wherein the chip-on-film is the chip-on-film according to any one of claims 1 to 25, and the chip-on-film comprises binding areas corresponding one-to-one to the display substrate, the driver chip and the circuit board.

Images