Low-complexity enhancement video coding using tile-level quantization parameters

Abstract

This disclosure describes systems, methods, and devices related to decoding Low-Complexity Enhancement Video Coding (LCEVC) video data. A device may receive a bitstream including a first layer and enhancement layers; decode a video frame of the first layer of the bitstream using a base decoder; upsample the decoded video image; decode the video image of a first enhancement layer using tile-level quantization parameters; generate a first combined intermediate video image using the upsampled video image and the decoded video data of the first enhancement layer; generate a first combined intermediate video image using the upsampled video image and the decoded video data of the first enhancement layer; upsample the first combined intermediate video image; decode encoded video data of a second enhancement layer;generate a second combined intermediate video image using the decoded video data of the second enhancement layer and a selected reference image; and generate a combined output video image using the first combined intermediate video image and the second combined intermediate video image.

Description

TECHNICAL FIELD

[0001] This disclosure relates generally to systems and methods for video coding, and more particularly to low-complexity enhancement video coding. BACKGROUND

[0002] LCEVC (Low-Complexity Enhanced Video Coding) encodes video into a lower-resolution version of a source image using any existing codec, and the difference between the reconstructed lower-resolution image and the source image is processed using a different compression technique. However, LCEVC is limited to the video frame-level quantization parameters. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an example block diagram of a Low-Complexity Enhancement Video Coding (LCEVC) decoder according to some example embodiments of the present disclosure. Fig. 2A shows an example of LCEVC using the same quantization parameters for all tiles of a video image, according to some example embodiments of the present disclosure. Fig. 2B shows an example of LCEVC with tile-based quantization parameters for a video image according to some example embodiments of the present disclosure. Fig. 3 is an example block diagram of an LCEVC encoder according to some example embodiments of the present disclosure. Fig. 4 shows a flowchart of an illustrative process for LCEVC using tile-level quantization parameters according to one or more example embodiments of the present disclosure. Fig. 5 shows an embodiment of an example system in accordance with one or more example embodiments of the present disclosure. DETAILED DESCRIPTION

[0003] The following description and drawings sufficiently illustrate certain embodiments to enable them to be practiced by those skilled in the art. Other embodiments may incorporate structural, logical, electrical, procedural, algorithmic, and other changes. Portions and features of some embodiments may be included in or substituted for other embodiments. The embodiments recited in the claims include all available equivalents of those claims.

[0004] With LCEVC (Low-Complexity Enhancement Video Coding), a lower-resolution version of a source image is encoded using any existing codec (e.g., the base codec such as AVC, HEVC, VP9, AV1, etc.), and the difference between the reconstructed lower-resolution image and the source image is encoded using a different compression technique (e.g., enhancement). LCEVC is an enhancement codec, meaning it not only enables good upscaling but also encodes the residual information required for a true match to the source video and compresses the information (e.g., through conversion, quantization, and encoding).

[0005] LCEVC residual layers (e.g., enhancement sublayers) encode the residual information required for video fidelity and compress the information (e.g., through conversion, quantization, and encoding). LCEVC can be used for higher resolutions or higher frame rates (e.g., 4Kp60, 8K, 12K) in video coding, adaptive video streaming, and the like. LCEVC supports a temporal layer in a Layer-2 (L-2) enhancement layer for BD rate improvement (Bjontegaard rate difference), which contains a temporal mask to specify INTRA_PRED or INTER_PRED information per transform block (e.g., whether the block was encoded with intra- or inter-prediction). The transform block can be, for example, 2x2 or 4x4. If the temporal mask of the block is INTER_PRED, only the residual delta (e.g., residual of the current L-2 enhancement layer - reconstructed residual of the previous L-2 enhancement layer) is encoded.

[0006] With the widespread adoption of 4K / 8K ultra-high-resolution displays, the demand for ultra-high-resolution images is increasing in various industries, and the number of application scenarios is expanding. LCEVC can be used for higher resolutions or higher frame rates (e.g., 4Kp60, 8K, 12K), video coding, adaptive video streaming, 360-degree videos, multi-view videos, light field videos, and more. Many of these video streaming applications require appropriate rate control techniques that utilize the specific characteristics of the video content, such as regions of interest (ROI). ROI- and tile-based rate control algorithms are being introduced in higher-resolution video coding, panoramic streaming, and more.

[0007] ROI coding takes into account that certain regions within a video frame are of greater interest to the viewer (e.g., due to an object represented in an ROI, due to motion within an ROI, etc.). With ROI coding, a video encoder can encode ROIs with less compression than non-ROIs. The ROIs can be denoted by numbers that represent pixel positions within a video frame. An encoded bitstream can specify the pixel positions corresponding to the ROIs. In this way, some tiles of a video frame can lie within the ROIs, and some tiles can be outside the ROIs.

[0008] The current implementation of the temporal layer in the LCEVC standard only supports quantization parameters (QPs) at the video frame level, but not tile / block level QPs, so LCEVC cannot utilize the ROI information. Quantization uses a quantization matrix containing step sizes (e.g., quantization step sizes) used to decode each group of coefficients. Quantization of the residuals / coefficients can be performed on bins with a specific step size. The quantization parameters control the strength of compression, with a larger quantization parameter resulting in greater compression. LCEVC presets standard coefficients for calculating the quantization matrix, and user-defined coefficients can also be signaled in the bitstream, altering the quantization process on a frame-by-frame basis.As an example, consider a 2x2 transformation for the residuals of enhancement substage 2. The residuals are transformed and decomposed into layers. Different tiles for each layer can have the same QP in the quantization. There is no feasible tile / block QP in LCEVC.

[0009] Therefore, the LCEVC coding needs to be improved by extending the syntax of LCEVC tile dimensions to allow tile-level step size updates to achieve the purpose of adapting the QP.

[0010] In one or more embodiments, enhanced LCEVC may utilize tiles in LCEVC and extend delta QP in tiles. Tile encoding may involve dividing a video frame into tiles that can be encoded and decoded independently (e.g., in parallel using multiple encoders / decoders). To enable tile-level QPs (e.g., QPs that apply to a specific tile of a video frame rather than an entire video frame), enhanced LCEVC may use a new syntax flag, delta_qp_per_tile_flag, for tiles in a process_payload_global_config (e.g., the global configuration for the bitstream) in the LCEVC bitstream, as shown in Tables 1A and 1B. The new syntax may enable delta QP information in "process_payload_encoded_data_tiled."The new tile syntax structure can extend the LCEVC encoding process by providing a switch to enable / disable delta QPs and adjust QP values for different tiles. Thus, the complexity of encoding and decoding must not be increased. Table 1A: Payload 'process_payload_global_config ()' in LCEVC Bitstream process_block Syntax: Syntax Des kriptor process_payload_globa 1_config(payload_size) { processed_planes_typ e_flag u(1) ..... .... if (tile dimensions type > 0) { if (tile_dimensions_type == 3) { custom_tile_width u(16 ) custom_tile_height u(16 ) } reserved_zeros_5bit u(5) compression_type_ent ropv_enabled_per_tile_flag u(1) compression_type_siz e_per_tile u(2) } ...... }

[0011] Using one of the five reserved bits u(5) from Table 1A to add the delta_qp_per_tile_flag can result in the global configuration payload shown in Table 1B below. Table 1B: Adding delta_qp_per_tile_flag to payload 'process_payload_global_config()' in LCEVC Bitstream process_block Syntax: Syntax Deskriptor process_payload_global_config(payload_size) { processed_planes_type_flag u(1) ...... ...... if (tile_dimensions_type > 0) { if (tile_dimensions_type == 3) { custom_tile_width u(16) custom_tile_height u(16) } reserved_zeros_4bit u(4) compression_type_entropy_enabled_per_tile_flag u(1) compression_type_size_per_tile u(2) delta_qp_per_tile_flag u(1) } ......

[0012] In one or more embodiments, the encoder may enable / disable delta_qp_per_tile_flag when tile_dimensions_type is greater than one. Table 2 below shows the available values for delta_qp_per_tile_flag. Table 3 shows the details of the process payload of the encoded tile data. Table 2: Enabling / Disabling Delta QP in the video tile: delta_qp_per_tile_fl ag Wert des Typs 0 Deaktivieren von Delta QP in Kachel 1 Aktivieren von Delta QP in Kachel Table 3: Process Payload - encoded tile data: Syntax Deskriptor process_payload_encoded_data_tiled(payload_size) { for (planeIdx = 0; planeIdx < nPlanes; planeIdx++) { for (levelIdx = 1; levelIdx <= 2; levelIdx++) { if (no_enhancement_bit_flag == 0) { for (layerIdx = 0; layerIdx < nLayers;layerIdx++) surfaces [planeIdx][levelIdx][layerIdx]. rle_only_flag u(1) } } if (temporal_signalling_present_flag == 1) temporal_surfaces [planeIdx]. rle_only_flag u(1) } byte_alignment( ) if (delta_qp_per_tile_flag == 1) { for (planeIdx = 0; planeIdx < nPlanes; planeIdx++) { if (no_enhancement_bit_flag == 0) { for (levelIdx = 1; levelIdx <= 2; levelIdx++) { if (levelIdx == 1 && step_width_level1_enabled_flag == 1) nTiles = nTilesL1 else if(levelIdx == 2 && step_width_level2_enabled_flag == 1) nTiles = nTilesL2 else nTiles = 0 for (layerIdx = 0; layerIdx < nLayers; layerIdx++) { for (tileIdx = 0; tileIdx < nTiles; tileIdx++) tile_QP_delta u(15) } } } } } byte_alignment( ) if (compression_type_entropy_enabled_per_tile_flag == 0) { for (planeIdx = 0; planeIdx < nPlanes; planeIdx++) { if (no_enhancement_bit_flag == 0) { for (levelIdx = 1; levelIdx <= 2; levelIdx++) { if (levelIdx == 1) nTiles = nTilesL1 else nTiles = nTilesL2 for (layerIdx = 0; layerIdx < nLayers; layerIdx++) { for (tileIdx = 0; tileIdx < nTiles; tileIdx++) surfaces [planeIdx][levelIdx][layerIdx]. tiles [tileIdx]. entropy_enabled_flag u(1) } } } if (temporal_signalling_present_flag == 1) { for (tileIdx = 0; tileIdx < nTilesL2; tileIdx++) temporal_surfaces [planeIdx]. tiles [tileIdx]. entropy_enabled_flag u(1) } } } else { entropy_enabled_per_tile_compressed_data_rle mb } ...... }

[0013] In one or more embodiments, the step width is one of the inputs to the dequantization process. QP can be expressed in terms of the step width based on equation (1): QP=f(step_width)

[0014] In one or more embodiments, the step size for each sub-level of enhancement (e.g., step_width_level1 and step_width_level2) may be updated with step_width_tile for each tile to dequantize the entropy-decoded quantized transform coefficient. The value for the tile step size step_width_tile may be derived based on Equation (2): step_width_tile=clip3(0,(215−1),step_width_levelN+(tile_QP_delta−214)) where step_width_levelN specifies the step width value to be used when decoding the encoded residuals in the enrichment sublevel N (1 or 2) defined in the process payload of the image configuration. The value of step_width_tile can range from 0 to 2 15 -1.

[0015] In one or more embodiments, a pseudocode example for updating step_width_tile by tile_QP_delta is provided below:

[0016] In one or more embodiments, enhanced LCEVC may be more flexible and achieve good performance in video transmission applications with region of interest (ROI) information by setting different QPs for different tiles (e.g., by including different tiles in the same video frame). The QP controls how much spatial detail is retained. For tiles with ROIs, QP is set to a small number so that almost all detail is preserved (e.g., ROI tiles are compressed less than non-ROI tiles to preserve ROI video data). For other non-ROI tiles, the QP is increased and some detail is aggregated, thus decreasing the bitrate, but at the cost of increased distortion and some quality loss.

[0017] The above descriptions are provided for illustrative purposes and are not to be considered limiting. Numerous other examples, configurations, methods, algorithms, etc. exist, some of which are described in more detail below. Example embodiments will now be described with reference to the accompanying drawings.

[0018] Fig. 1 is an example block diagram of a Low-Complexity Enhancement Video Coding (LCEVC) decoder 100, according to some example embodiments of the present disclosure.

[0019] Referring to Fig. 1, the LCEVC decoder 100 may receive a bitstream 102 (e.g., an encoded bitstream as received from the LCEVC encoder 300 of Fig. 3) with multiple layers (e.g., a base layer and enhancement layers). The frames encoded at the base layer of the bitstream 102 may include base layer data 104. Frames encoded with a first enhancement layer (e.g., Layer 1) may include Layer 1 coefficient data 106. Frames encoded at a second enhancement layer (e.g., Layer 2) may include Layer 2 coefficient data 108. Frames encoded at a temporal layer may include temporal data 110. The headers 112 of the bitstream 102 may be input to a decoder configuration 114 used by the LCEVC decoder 100. The layers of the bitstream and how they are encoded are described below with reference to Fig. 6 explained.

[0020] As in Fig. 1, the base layer data 104 may be decoded by a base layer decoder 116 (e.g., a non-LCEVC decoder), resulting in a decoded base layer image 118. An upscaler 120 may upscale the decoded base layer image 118 (e.g., increase the pixel count of the image), resulting in an upscaled base layer image 122 (e.g., a preliminary intermediate image). The Layer 1 coefficient data 106 may be decoded with an entropy decoder 124, and inverse quantization 126 with tile-level QPs may be performed on the decoded Layer 1 coefficient data to identify the transform coefficients. The inverse transform 128 may determine the transform used to generate the Layer 1 coefficient data 106. The reverse-transformed Layer 1 data may be passed through a Layer 1 filter 130 to produce a decoded Layer 1 image 132.The decoded layer 1 image 132 and the upsampled base layer image 122 may be added by an adder 134 to produce a combined intermediate image 136. The combined intermediate image 136 may be upscaled by an upscaler 138 to produce a full-resolution combined intermediate image 140.

[0021] As in Fig. 4, the Layer 2 coefficient data 108 may be decoded with an entropy decoder 142, and inverse quantization 144 with tile-level QPs may be performed on the decoded Layer 2 coefficient data to identify the transform coefficients. The inverse transform 146 may determine the transform used to generate the Layer 2 coefficient data 108. The inversely transformed Layer 2 data may generate Layer 2 residual values 148. The temporal data 110 may be decoded with an entropy decoder 150. If the inter-prediction 152 was used (e.g., according to the syntax of the bitstream 102), only the Layer 2 residual values 148 may be decoded. The decoded temporal data may be compared to a reference image in a reference image buffer 154.The reference image buffer 154 may store one or more reference images at a given time so that the LCEVC decoder 100 may select one of the reference images (e.g., the best-matching reference image for the given image to be decoded) to combine with the decoded temporal data to generate an intermediate image 156. The intermediate image 156 may be combined with the Layer 2 residual values 148 in an adder 158 to generate a combined intermediate image 160. The combined intermediate image 160 and the combined intermediate image 140 may be combined by an adder 162 to generate a combined output video image. The combined output video images 164 of the LCEVC decoder 100 may be presented for playback.

[0022] In one or more embodiments, to enable tile-level QPs (e.g., inverse quantization 126 and inverse quantization 144), bitstream 102 may use a new syntax flag, delta_qp_per_tile_flag, for tiles in a process_payload_global_config (e.g., the global configuration), as shown in Table 1B. The new syntax may enable delta QP information in "process_payload_encoded_data_tiled." The new syntax structure for tiles may represent an extension of the LCEVC encoding process by providing a switch to enable / disable delta QPs and adjust the QP values for different tiles. Thus, the complexity of encoding and decoding must not be increased.

[0023] In one or more embodiments, the decoder may enable / disable delta_qp_per_tile _flag when tile_dimensions_type in the bitstream 102 syntax is greater than one. Furthermore, Table 2 above shows the available value of delta_qp_per_tile_flag. Table 3 shows the details of the process payload of the encoded tile data. As shown in Table 2, tile-level delta QPs may be disabled when delta_qp_per_tile_flag is 0, and when delta_qp_per_tile_flag is 1, tile-level delta QPs may be enabled, indicating to the LCEVC decoder 200 whether or not inverse quantization uses tile-level QPs. As shown in Table 3, if the delta_qp_per_tile_flag is 1, a corresponding QP (e.g., tile_QP_delta) for inverse quantization can be applied to each layer of a video image of the bitstream 102.The QP for each tile of a video frame of bitstream 102 may be a function of the step width according to equation (1) above. For each LCEVC enhancement layer, each tile may have a step width tile for each tile to inversely quantize (dequantize) the decoded quantized transform coefficient. The step width for each tile is based on equation (2) above.

[0024] Fig. 2A shows an example of LCEVC 200 in which the same quantization parameters are used for all tiles of a video image, according to some example embodiments of the present disclosure.

[0025] As in Fig. 2A, a video image 202 (e.g., a tiger) may be transformed using a transform (e.g., a 2x2 transform), resulting in the video image 202 being divided into four layers (e.g., layer 0, layer 1, layer 2, layer 3). Each tile of each layer of the video image 202 may be quantized using a tile-level QP (e.g., QP0 for layer 0, QP1 for layer 1, QP2 for layer 2, QP3 for layer 3). Although some tiles of the video image 202 showing portions of the tiger may be considered ROIs, the LCEVC 200 may not alter the QPs for the tiles of the video image 202.

[0026] Fig. 2B shows an example of LCEVC 250 with tile-based quantization parameters for a video image according to some example embodiments of the present disclosure.

[0027] As in Fig. 2B, the video image 252 (e.g., a tiger) can be divided into four layers (e.g., layer 0, layer 1, layer 2, layer 3) using a transformation (e.g., a 2x2 transformation). Each tile of each layer of the video image 252 can be quantized with a tile-level QP (e.g., QP00 for layer 0 non-ROI tiles, QP0N for another QP of layer 0 ROI tiles corresponding to the location where the tiger or other object of interest is located - where N can be different for any given tile, QP10 for layer 1 non-ROI tiles, QP1N for another QP of layer 1 ROI tiles corresponding to the location where the tiger or other object of interest is located - where N can be different for any given tile, QP20 for layer 2 non-ROI tiles, QP2N for another QP of layer 2 ROI tiles corresponding to the location,where the tiger or other object of interest is located—where N can be different for any tile, QP30 for layer 3 non-ROI tiles, QP3N for another QP of layer 3 ROI tiles corresponding to the location where the tiger or other object of interest is located—where N can be different for any tile). Tiles that are part of ROIs 254 (e.g., the regions of video image 252 where the tiger is depicted as an object of interest) can be quantized differently than non-ROI tiles. In this way, the tiles (e.g., rectangles, as shown) corresponding to ROIs 254 of video image 252 can use different QPs than the non-ROI tiles, allowing the ROI tiles to be compressed less than the non-ROI tiles, for example.

[0028] As opposed to Fig. 2A enables the LCEVC 250 from Fig. 2B QPs at the tile level, so that ROI tiles (e.g., tiles of the video image 252 in which parts of the tiger are depicted) can be quantized with different QPs than non-ROI tiles of the video image 252.

[0029] In one or more embodiments, the bitstream 102 may be Fig. 1 use a new syntax flag delta_qp_per_tile_flag for tiles in a process_payload_global_config (e.g., the global configuration) to specify tile-level QPs (e.g., QPXY, as shown, where X is the layer and Y is the QP for the layer) of the LCEVC 250 from Fig. 2B, as shown above in Table 1B. The new syntax can enable delta QP information in "process_payload_encoded_data_tiled." The new tiling syntax structure can represent an extension of the LCEVC encoding process by providing a switch to enable / disable delta QPs and adjust the QP values for different tiles. Thus, the complexity of encoding and decoding must not be increased.

[0030] In one or more embodiments, the decoder may enable / disable delta_qp_per_tile_flag when tile_dimensions_type in the bitstream 102 syntax is greater than one. Furthermore, Table 2 above shows the available value of delta_qp_per_tile_flag. Table 3 shows the details of the process payload of the encoded tile data. As shown in Table 2, tile-level delta QPs may be disabled when delta_qp_per_tile_flag is 0, and when delta_qp_per_tile_flag is 1, tile-level delta QPs may be enabled, indicating to the LCEVC decoder 200 whether or not inverse quantization uses tile-level QPs. As shown in Table 3, if the delta_qp_per_tile_flag is 1, a corresponding QP (e.g., tile_QP_delta) for inverse quantization can be applied to each layer of a video image of the bitstream 102.The QP for each tile of a video frame of bitstream 102 may be a function of the step width according to equation (1) above. For each LCEVC enhancement layer, each tile may have a step width tile for each tile to inversely quantize (dequantize) the decoded quantized transform coefficient. The step width for each tile is based on equation (2) above.

[0031] Fig. 3 is an example block diagram of an LCEVC encoder 300 according to some example embodiments of the present disclosure.

[0032] As in Fig. 3, the LCEVC encoder 300 can convert the bit stream 102 from Fig. 1. An input sequence 302 of video images may be used to generate the bitstream 102 using an encoder configuration 304. The input sequence 302 may be downscaled by a downscaler 306 to generate a downscaled image 308, which may be further downscaled by a downscaler 310 to generate a downscaled image 312. The downscaled image 312 may be encoded by a base encoder 314 (e.g., a non-LCEVC encoder) to generate an encoded base 316 (e.g., the base layer of the bitstream 102, which is responsible for the base layer data 104 of Fig. 1 is used). The encoded image from the base encoder 314 may be upscaled by an upscaler 318 and subtracted from the downscaled image 308 by a subtractor 320 to generate Layer 1 residual values on which a transform 322 and quantization 324 (e.g., using tile-level QPs) may be performed (e.g., for reconstruction). The transformed and quantized Layer 1 data may be used for inverse quantization 326 and inverse transform 328 (e.g., for reconstruction of the pixel data) and passed through a Layer 1 filter 330. The quantized Layer 1 data from quantization 324 may generate the Layer 1 coefficient layers 334 for the bitstream 102. The filtered Layer 1 data can be added to the image upscaled by the upscaler 318 using an adder 336 to generate an intermediate image, which in turn can be upscaled by an upscaler 338.An image from the input sequence 302 may be subtracted from the intermediate image by a subtractor 340 to generate Layer 2 residuals for the temporal prediction 342. A transformation 344 and quantization 346 (e.g., using tile-level QPs) may be performed on the temporal prediction 342, which may then be entropy encoded 348 to generate Layer 2 coefficient layers 350 for the bitstream 102. The temporal prediction 342 data may be entropy encoded 352 to generate the temporal layer 354 of the bitstream 102. The encoder configuration 304 may be specified in the headers 356 of the bitstream 102 syntax.

[0033] With reference to Fig. 1 and Fig. 3, a subtractor may generate a residual value, as further explained herein. Transformation and quantization may generate and quantize transformation units to facilitate encoding by an encoder (e.g., entropy encoder). The transformed and quantized data may be inversely transformed and inversely quantized by an inverse transformer and quantizer on the decoder side. An adder may compare the inversely transformed and inversely quantized data with a prediction block generated by a prediction unit (e.g., temporal prediction), resulting in reconstructed images. A filter (e.g., an in-loop filter for resizing / cropping, color conversion, deinterlacing, compositing / blending, etc.) may rework the images reconstructed by an adder and store the reconstructed images in a frame buffer (e.g., the reference frame buffer 154 of Fig. 1). A controller may manage many coding aspects (e.g., parameters), including at least the setting of a quantization parameter (QP), but could also include the setting of bit rate, rate distortion, or scene characteristics, prediction and / or transform partition or block sizes, available prediction mode types, and parameters for selecting the best mode, e.g., based at least in part on data from the prediction unit. Using the coding aspects, the transform and quantization processes may generate and quantize transform units to facilitate coding by the encoder, which may generate encoded data that can be transmitted (e.g., an encoded bitstream).

[0034] Continue on Fig. 1 and Fig. 3, through inverse transformation and quantization, pixel data can be reconstructed based on the quantized residual coefficients and context data. An adder can add the residual pixel data to a predicted block generated by a prediction unit. A filter can filter the data provided by the adder. The filtered data can be output via a media output and also stored as reconstructed images in a frame buffer (e.g., the reference frame buffer 154 in Fig. 1) be stored for use by the prediction unit.

[0035] With reference to Fig. 1 and Fig. 3, LCEVC decoder 100 and encoder 300 perform the intra-prediction techniques disclosed herein and are arranged to perform at least one or more of the implementations described herein, including intra-block copying. In various implementations, LCEVC decoder 100 and encoder 300 may be configured to perform video encoding and / or implement video codecs according to one or more standards. Furthermore, LCEVC decoder 100 and encoder 300 may be implemented in various forms as part of an image, video, and / or media processor and perform inter-prediction, intra-prediction, predictive coding, and residual prediction. In various implementations, LCEVC decoder 100 and encoder 300 may perform video compression and decompression and / or implement video codecs according to one or more standards or specifications, such as BH264 (Advanced Video Coding or AVC), VP8, H.265 (High Efficiency Video Coding or HEVC) and its SCC extensions, VP9, Alliance Open Media Version 1 (AV1), H.266 (Versatile Video Coding or VVC), DASH (Dynamic Adaptive Streaming over HTTP) and others.

[0036] As used herein, the term "encoder" can refer to an encoder and / or a decoder. Similarly, the term "encoding" can refer to encoding via an encoder and / or decoding via a decoder. An encoder, encoder, or decoder can include both encoder and decoder components. An encoder can have a decoder loop, as described below.

[0037] For example, the LCEVC encoder 300 may be an encoder that receives current video information in the form of data about a sequence of video frames to be compressed. In one form, a video sequence is formed from input images of synthetic screen content, e.g., from or for business applications such as word processors, PowerPoint slides or spreadsheets, computers, video games, virtual reality images, etc. In other forms, the images may consist of a combination of synthetic screen content and natural images captured with the camera. In another form, the video sequence may be just video captured with a natural camera. A partitioner can divide each frame into smaller, more manageable units and then compare the frames to calculate a prediction.If a difference or residue is determined between an original block and the prediction, this resulting residue is transformed and quantized, then entropy encoded and transmitted in a bitstream along with reconstructed images to decoders or memory. To perform these operations, LCEVC encoder 300 may receive an input image from input sequence 302. The input images may be images that have been sufficiently preprocessed for encoding.

[0038] The LCEVC encoder 300 can also manage many encoding aspects, including at least the setting of a quantization parameter (QP), but also the setting of bit rate, rate distortion or scene characteristics, prediction and / or transform partition or block sizes, available prediction mode types and parameters for selecting the best mode, to name a few examples.

[0039] The output of the transformed and quantized data can be fed to the inverse transform and quantization to generate the same reference or reconstructed blocks, images, or other units as generated in a decoder such as the LCEVC decoder 100. Thus, the prediction unit can use the inverse transform and quantization, the adder, and the filter to reconstruct the images.

[0040] A prediction unit may perform inter-prediction including motion estimation and motion compensation, intra-prediction as described herein, and / or combined inter-intra prediction. The prediction unit may select the best prediction mode (including intra-modes) for a particular block, typically based on bit cost and other factors. The prediction unit may select an intra-prediction and / or inter-prediction mode if multiple such modes are available. The prediction output of the prediction unit in the form of a prediction block may be fed both to the subtractor to generate a residual value and, in the decoding loop, to the adder to add the prediction to the reconstructed residual from the inverse transform to reconstruct an image.

[0041] The partitioner or other first units (not shown) can arrange images in encoding order and assign classifications to the images, e.g., I-picture, B-picture, P-picture, etc., where I-pictures are intra-predicted. Otherwise, images can be divided into slices (e.g., an I-slice), where each slice can be predicted differently. Thus, for HEVC or AV1 encoding of an entire I-picture or I-slice, spatial or intra-prediction is used in one form: from only the data in the image itself.

[0042] In various implementations, the prediction unit may perform an intra-block copy (IBC) prediction mode and a non-IBC mode that serves any other available intra-prediction mode, such as adjacent horizontal, diagonal, or direct coding (DC) prediction mode, palette mode, direction or angle modes, and any other available intra-prediction mode. Other video coding standards, such as HEVC or VP9, may have different sub-block dimensions but may still use the IBC search described herein. However, it should be noted that the foregoing are only example sizes and shapes, and that the present disclosure is not limited to particular partitions and partition shapes and / or sizes unless such a limitation is mentioned or the context suggests such a limitation, such as with the mentioned optional maximum efficiency size.Note that multiple alternative partitions can be provided as prediction candidates for the same image region (see below).

[0043] The prediction unit can select previously decoded reference blocks. Comparisons can then be performed to determine if any of the reference blocks match a current block being reconstructed. This can involve a hash match, a SAD search, or some other comparison of image data, and so on. Once a match is found with a reference block, the prediction unit can use the image data of the one or more matching reference blocks to select a prediction mode. In one form, the previously reconstructed image data of the reference block is provided as the prediction; alternatively, the original pixel image data of the reference block can be provided as the prediction. Both options can be used regardless of the type of image data used to match the blocks.

[0044] The predicted block can then be subtracted from the current block of original image data in the subtractor, and the resulting residue can be split into one or more transform blocks (TUs), so that the transformation and quantization can transform the split residual data into transform coefficients, e.g., using the discrete cosine transform (DCT). Using the quantization parameter (QP) set by the LCEVC encoder 300, the transformation and quantization are then performed by lossy resampling or quantizing the coefficients. The images and residual values, along with the size of the supporting or contextual data blocks and the internal displacement vectors, etc., can be entropy-coded by the LCEVC encoder 300 and transmitted to the decoders.

[0045] In one or more embodiments, LCEVC decoder 100 may receive encoded video data in the form of a bitstream containing the image data (chroma and luma pixel values) and context data, including residual values in the form of quantized transform coefficients and the identity of reference blocks, including at least the size of the reference blocks. The context may also include prediction modes for individual blocks, other partitions such as slices, motion vectors between predictions, partitions, quantization parameters, filter information, etc. The LCEVC decoder 100 may process the bitstream with an entropy decoder to extract the quantized residual coefficients and the context data. The LCEVC decoder 100 may then use the inverse transform and quantization to reconstruct the remaining pixel data.

[0046] The LCEVC decoder 100 may then use an adder (along with assemblers not shown) to add the remainder to a predicted block. The LCEVC decoder 100 may also decode the resulting data using a decoding technique employed depending on the encoding mode specified in the bitstream syntax, and either a first path containing a prediction unit or a second path containing a filter. The prediction unit performs intra-prediction using reference block sizes and the intra-displacement or motion vectors extracted from the bitstream and previously set in the encoder. The prediction unit may use both reconstructed frames and inter-prediction motion vectors from the bitstream to reconstruct a predicted block.The prediction unit can set the correct prediction mode for each block, and the prediction mode can be extracted and decompressed from the compressed bitstream.

[0047] In one or more embodiments, the encoded data (e.g., bitstream 102) may include both video and audio data.

[0048] It is understood that the above descriptions are for illustrative purposes and are not to be construed as limiting.

[0049] Fig. 4 shows a flowchart of an illustrative process 400 for LCEVC using tile-level quantization parameters according to one or more example embodiments of the present disclosure.

[0050] In block 402, a device (e.g., the LCEVC decoder 100 of Fig. 1, the graphics card 565 from Fig. 5, the LCEVC device 519 of Fig. 5) a bit stream (e.g. the bit stream 102 of Fig. 1) which is generated using a base encoder (e.g., the base layer data 104 of Fig. 1 of the coded base 316 generated by the base encoder 314 of Fig. 1) and enrichment layers (e.g., the Layer 1 coefficient data 106 of Fig. 1 of the Layer 1 coefficient layers 334 of Fig. 3, the Layer 2 coefficient data 108 of Fig. 1 of the Layer 2 coefficient layers 350 of Fig. 3, the temporal data 110 of the temporal layer 354 of Fig. 3) and headers (e.g. headers 112 of Fig. 1 and the headers 356 of Fig. 3). The bitstream syntax may include one or more indicators, including the delta_qp_per_tile_flag of Table 1B above in the global configuration for the bitstream, which indicates a 0 bit for disabling tile-level QPs and a 1 bit for enabling tile-level QPs, as shown in Table 2 above. The indicators may also include tile-level QPs for each tile, each layer, and each frame, as shown in Table 3.

[0051] At block 404, the device may decode a first video image of the first layer of the bitstream with a base decoder (e.g., decode an image with the base layer 104 data with the base layer decoder 116). The base decoder may be a non-LCEVC decoder (e.g., with a codec other than LCEVC).

[0052] In block 406, the device may upscale the decoded first video image (e.g., the decoded base layer image 118 of Fig. 1 using the upscaler 120 from Fig. 1 extrapolate).

[0053] In block 408, the device may decode encoded video data of a first enhancement layer of the enhancement layers (e.g., decoding the Layer 1 coefficient data 106 using the entropy decoding 124 of Fig. 1). The decoding can be based on the QPs used to encode the video image, which can be tile-level QPs, so that each tile has its own QP, which can be different from any other tile in the image (e.g., as in Fig. 2B). The syntax of the bitstream may specify whether the QPs are at the tile or frame level. If the QPs are at the tile level (e.g., so that ROI tiles are encoded differently than non-ROI tiles in a same frame and / or than other ROI tiles in a same frame), the syntax may provide the QPs for each tile for each layer of a frame. The image configuration of the syntax may specify the stride parameter to be used in decoding the frame's encoded residuals (e.g., limited to a range of values by a function). Using the stride parameter, the QP for a tile may be based on the stride parameter, and the different tiles of a frame may be decoded based on their different QPs.

[0054] In block 410, the device may generate a first combined intermediate video image (e.g., the combined intermediate image 136 of Fig. 1) by combining the upscaled first video image and the decoded video data of the first enhancement layer.

[0055] In block 412, the device may upscale the first combined intermediate video image (e.g., with the upscaler 138 of Fig. 1).

[0056] In block 414, the device may decode encoded video data of a second enhancement layer of the enhancement layers (e.g., decoding the Layer 2 coefficient data 108 using the entropy decoding 142 of Fig. 1). As mentioned for block 408, the QPs may be at the tile level, so that the QPs for each tile of the frame on the second enhancement layer may be individually signaled like the tiles on the first enhancement layer in block 408.

[0057] In block 416, the device may display a second combined intermediate video image (e.g., the combined intermediate image 160 of Fig. 1) by combining the decoded video data of the second enhancement layer and a selected reference image.

[0058] In block 418, the device may generate a combined output video image (e.g., the combined output video images 164 of Fig. 1) by combining the first combined intermediate video image and the second combined intermediate video image. The combined output video images generated by process 400 may represent the video images used for playback. In block 420, the combined output video images may be presented for playback.

[0059] It is understood that the above descriptions are for illustrative purposes and are not to be construed as limiting.

[0060] Fig. 8 shows an embodiment of an example system 500 in accordance with one or more example embodiments of the present disclosure.

[0061] In various embodiments, the computer system 500 may include or be implemented as part of an electronic device.

[0062] For example, in some embodiments, computer system 500 may represent a computer system that includes one or more components of Fig. 1 and Fig. 3 implemented.

[0063] The embodiments are not limited in this context. More generally, the computer system 500 is configured to implement all of the embodiments described herein and with reference to Fig. 1-4 described logics, systems, processes, logical sequences, methods, equations, devices and functions are implemented.

[0064] System 500 may be a computer system with multiple processor cores, e.g., a distributed computing system, a supercomputer, a high-performance computing system, a computer cluster, a mainframe computer, a minicomputer, a client-server system, a personal computer (PC), a workstation, a server, a portable computer, a laptop computer, a tablet computer, a handheld device, e.g., a personal digital assistant (PDA), or other devices for processing, displaying, or transmitting information. Similar embodiments may include, for example, entertainment devices such as a portable music player or video player, a smartphone or other mobile phone, a telephone, a digital video camera, a digital still camera, an external storage device, or the like. In other embodiments, larger server configurations are implemented.In other embodiments, system 500 may have a single, single-core processor or more than one processor. The term "processor" refers to a single-core processor or a processor package with multiple processor cores.

[0065] In at least one embodiment, the computing system 500 is representative of one or more components of Fig. 1 and Fig. 3. More generally, the computing system 500 is configured to implement all of the logic, systems, processes, logic flows, methods, devices, and functions described herein with reference to the above figures.

[0066] In this application, the terms "system," "component," and "module" refer to a computer-based entity, either hardware, a combination of hardware and software, software, or software in execution, of which the example system 500 provides examples. A component may be, for example, but is not limited to, a process running on a processor, a processor, a hard disk drive, multiple storage drives (with optical and / or magnetic storage media), an object, an executable file, a thread of execution, a program, and / or a computer.

[0067] To illustrate, both an application running on a server and the server can be a component. One or more components can be in a process and / or a thread of execution, and a component can be localized on one computer and / or distributed across two or more computers. Furthermore, the components can be interconnected via various types of communication media to coordinate operations. The coordination can involve unidirectional or bidirectional information exchange. For example, the components can communicate information in the form of signals over the communication media. The information can be implemented as signals associated with various signal lines. In such assignments, each message is a signal. However, other embodiments can alternatively use data messages.Such data messages can be sent over various connections. Examples include parallel interfaces, serial interfaces, and bus interfaces.

[0068] As shown in this figure, the system 500 includes a motherboard 505 for mounting platform components. The motherboard 505 is a point-to-point interconnect platform that includes a processor 510, a processor 530 coupled via a point-to-point interconnect as an Ultra Path Interconnect (UPI), and an LCEVC device 519 (e.g., capable of performing the functions of Fig. 1-4 to be carried out).

[0069] In other embodiments, system 500 may have a different bus architecture, such as a multi-drop bus. Additionally, each of processors 510 and 530 may be a processor package with multiple processor cores. As an example, processors 510 and 530 are shown with processor core(s) 520 and 540, respectively. While system 500 is an example of a two-socket (2S) platform, other embodiments may include more than two sockets or one socket. For example, some embodiments may include a four-socket (4S) or an eight-socket (8S) platform. Each socket is a holder for a processor and may have a socket identifier. The term platform refers to the motherboard on which certain components, such as processors 510 and chipset 560, are mounted. Some platforms may include additional components, while others may only include sockets for mounting the processors and / or chipset.

[0070] The 510 and 530 processors can be various commercially available processors, including, but not limited to, Intel® Celeron®, Core®, Core (2) Duo®, Itanium®, Pentium®, Xeon®, and XScale® processors; AMD® Athlon®, Duron®, and Opteron® processors; ARM® application, embedded, and secure processors; IBM® and Motorola® DragonBall® and PowerPC® processors; IBM and Sony® Cell processors; and similar processors. Dual microprocessors, multi-core processors, and other multi-processor architectures can also be used as the 510 and 530 processors.

[0071] Processor 510 includes an integrated memory controller (IMC) 514 and point-to-point (PP) interfaces 518 and 552. Similarly, processor 530 includes an IMC 534 and PP interfaces 538 and 554. IMCs 514 and 534 couple processors 510 and 530 to respective memories, a memory 512 and a memory 532. Memories 512 and 532 may be portions of main memory (e.g., dynamic random access memory (DRAM)) for the platform, such as double data rate synchronous DRAM (SDRAM) Type 3 (DDR3) or Type 4 (DDR4). In the present embodiment, memories 512 and 532 are locally coupled to respective processors 510 and 530.

[0072] In addition to processors 510 and 530, system 500 may include LCEVC device 519. LCEVC device 519 may be connected to chipset 560 via PP interfaces 529 and 569. LCEVC device 519 may also be connected to memory 539. In some embodiments, LCEVC device 519 may be connected to at least one of processors 510 and 530. In other embodiments, memories 512, 532, and 539 may be connected to processors 510 and 530 and LCEVC device 519 via a bus and a common memory hub.

[0073] System 500 includes chipset 560, which is connected to processors 510 and 530. Chipset 560 may also be coupled to storage medium 503, for example, via an interface (I / F) 566. I / F 566 may be, for example, a Peripheral Component Interconnect-enhanced (PCI-e). Processors 510, 530, and LCEVC device 519 may access storage medium 503 via chipset 560.

[0074] The storage medium 503 may be any non-transitory, computer-readable, or machine-readable storage medium, such as an optical, magnetic, or semiconductor storage medium. In various embodiments, the storage medium 503 may be comprised of an article of manufacture. In some embodiments, the storage medium 503 may store computer-executable instructions, such as computer-executable instructions 502, to implement one or more of the processes or operations described herein (e.g., process 400 of Fig.4). Computer-executable instructions for all of the equations described above can be stored on storage medium 503. Computer-executable instructions for the models and / or networks described herein, such as a neural network or the like, can also be stored on storage medium 503. Examples of a computer-readable storage medium or a machine-readable storage medium can be any tangible media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. Examples of computer-executable instructions can include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like.It is understood that the embodiments are not limited in this context.

[0075] Processor 510 is connected to chipset 560 via PP interfaces 552 and 562, and processor 530 is connected to chipset 560 via PP interfaces 554 and 564. Direct media interfaces (DMI) may couple PP interfaces 552 and 562 and PP interfaces 554 and 564, respectively. The DMI may be a high-speed connection, enabling, for example, eight giga transfers per second (GT / s), such as DMI 3.0. In other embodiments, processors 510 and 530 may be interconnected via a bus.

[0076] Chipset 560 may include a controller hub, such as a platform controller hub (PCH). Chipset 560 may include a system clock for performing clocking functions and interfaces for an I / O bus, such as a universal serial bus (USB), peripheral component interconnects (PCIs), serial peripheral interconnects (SPIs), integrated interconnects (I2Cs), etc., to facilitate the connection of peripherals on the platform. In other embodiments, chipset 560 may include more than one controller hub, e.g., a chipset with a memory controller hub, a graphics controller hub, and an input / output (I / O) controller hub.

[0077] In the present embodiment, chipset 560 is connected to a Trusted Platform Module (TPM) 572 and the UEFI, BIOS, and Flash component 574 via an interface (I / F) 570. The TPM 572 is a special-purpose microcontroller designed to secure hardware by integrating cryptographic keys into devices. The UEFI, BIOS, and Flash component 574 can provide pre-boot code.

[0078] Additionally, chipset 560 includes interface 866 for coupling chipset 560 to a high-performance graphics card 565. In other embodiments, system 500 may include a flexible display interface (FDI) between processors 510 and 530 and chipset 560. The FDI connects a graphics processor core in a processor to chipset 560.

[0079] Various I / O devices 592 are connected to bus 581, along with a bus bridge 580 that connects bus 581 to a second bus 591, and an I / O 868 that connects bus 581 to chipset 560. In one embodiment, second bus 591 may be a low-pin-count (LPC) bus. Various devices may be connected to second bus 591, such as a keyboard 582, a mouse 584, communication devices 586, a storage device 501, and audio I / O 590.

[0080] The artificial intelligence (AI) accelerator 567 may be circuitry configured to perform AI-related computations. The AI accelerator 567 may be connected to the storage medium 503 and the chipset 560. The AI accelerator 567 may provide the necessary computing power and energy efficiency to enable abundant data processing. The AI accelerator 567 is a class of specialized hardware accelerators or computer systems for accelerating artificial intelligence and machine learning applications, including artificial neural networks and computer vision. The AI accelerator 567 may be used for algorithms for robotics, the Internet of Things, and other data-intensive and / or sensor-driven tasks.

[0081] Many of the I / O devices 592, communication devices 586, and storage medium 501 may be located on the motherboard 505, while the keyboard 582 and mouse 584 may be additional peripherals. In other embodiments, some or all of the I / O devices 592, communication devices 586, and storage medium 501 are additional peripherals and are not located on the motherboard 505.

[0082] Some examples may be described using the phrase "in an example" or "an example," and their derivatives. These terms mean that a particular feature, structure, or property described in connection with the example is included in at least one example. The phrase "in an example," which appears in various places in the specification, does not necessarily refer to one and the same example.

[0083] Some examples can be described using the terms "coupled" and "connected," and their derivatives. These terms are not necessarily synonymous. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" can also mean that two or more elements are not in direct contact, but still cooperate or interact with each other.

[0084] In addition, in the foregoing Detailed Description, various features are grouped into a single example to simplify the disclosure. This manner of disclosure should not be construed to imply that the claimed examples require more features than are expressly recited in the individual claims. Rather, as the following claims indicate, the subject matter of the invention lies in fewer than all of the features of a single disclosed example. Therefore, the following claims are incorporated into the Detailed Description, with each claim standing on its own as a standalone example. In the appended claims, the terms "including" and "in which" are used as plain English equivalents of the respective terms "comprising" and "wherein." In addition, the terms "first," "second," "third," etc., are used merely as labels and are not intended to impose numerical requirements on their subject matter.

[0085] Although the subject matter has been described in language referring to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as exemplary forms of implementing the claims.

[0086] A data processing system capable of storing and / or executing program code includes at least one processor connected directly or indirectly to storage elements via a system bus. The storage elements may include local memory used during actual execution of the program code, mass storage, and cache memories that temporarily store at least a portion of the program code to reduce the number of times code is retrieved from mass storage during execution. The term "code" covers a broad spectrum of software components and constructs, including applications, drivers, processes, routines, methods, modules, firmware, microcode, and subroutines. The term "code" can therefore be used to refer to any collection of instructions that, when executed by a processing system, performs a desired operation or set of operations.

[0087] The logical circuits, devices, and interfaces described here can perform functions implemented in hardware and executed by code on one or more processors. Logical circuits refer to the hardware, or the hardware and code, that implement one or more logical functions. Circuits are hardware and can refer to one or more circuits. Each circuit can perform a specific function. A circuit of the circuits can consist of individual electrical components connected by one or more conductors, an integrated circuit, a chip package, a chipset, memory, or the like. Integrated circuits include circuits that are fabricated on a substrate such as a silicon wafer and can consist of components. Integrated circuits, processor packages, chip packages, and chipsets can contain one or more processors.

[0088] Processors can receive signals such as instructions and / or data at inputs and process the signals to produce one or more outputs. During code execution, the code changes the physical states and properties of the transistors that make up a processor's pipeline. The physical states of the transistors are translated into logical bits of ones and zeros, which are stored in registers within the processor. The processor can transfer the physical states of the transistors to registers and transfer the physical states of the transistors to another storage medium.

[0089] A processor may include circuitry for performing one or more subfunctions implemented to fulfill the overall function of the processor. An example of a processor is a state machine or an application-specific integrated circuit (ASIC) that has at least one input and at least one output. A state machine may manipulate the at least one input to produce the at least one output by performing a predetermined series of serial and / or parallel manipulations or transformations on the at least one input.

[0090] The logic described above may be part of the design for an integrated circuit. The chip design is created in a graphical computer programming language and stored on a computer storage medium or a data storage medium (e.g., a disk, tape, physical disk, or virtual disk, e.g., in a memory access network). If the designer does not manufacture chips or the photolithographic masks used to fabricate chips, they submit the resulting design directly or indirectly to such facilities by physical means (e.g., by providing a copy of the storage medium on which the design is stored) or electronically (e.g., via the Internet). The stored design is then converted into the format suitable for manufacturing (e.g., GDSII).

[0091] The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., a single wafer containing multiple unpackaged chips), as bare chips, or in packaged form. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip package (e.g., a ceramic carrier having either surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices either (a) into an intermediate product, such as a processor board, server platform, or motherboard, or (b) into a final product.

[0092] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. As used herein, the terms "computing device," "user device," "communications station," "station," "hands-free device," "mobile device," "wireless device," and "user equipment" (UE) refer to a wireless communications device such as a cellular phone, smartphone, tablet, netbook, wireless terminal, laptop, femtocell, high data rate (HDR) subscriber station, access point, printer, point-of-sale device, access terminal, or other personal communication system (PCS) device. The device may be either mobile or stationary.

[0093] The term "communicating" as used in this document includes sending, receiving, or both sending and receiving. This can be particularly useful in claims when describing the organization of data transmitted by one device and received by another, but only the functionality of one of those devices is required to infringe the claim. Likewise, the bidirectional exchange of data between two devices (both devices sending and receiving during the exchange) can be said to be "communicating" when only the functionality of one of those devices is claimed. The term "communicating" as used herein with reference to a wireless communication signal includes sending the wireless communication signal and / or receiving the wireless communication signal.A wireless communication unit capable of transmitting a wireless communication signal may, for example, comprise a wireless transmitter for transmitting the wireless communication signal to at least one other wireless communication unit and / or a wireless communication receiver for receiving the wireless communication signal from at least one other wireless communication unit.

[0094] Unless otherwise indicated, the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object merely means that different instances of similar objects are meant, and is not intended to imply that the objects so described must be in any particular order, whether temporally, spatially, in rank, or otherwise.

[0095] Some embodiments may be used in connection with various devices and systems, such as a personal computer (PC), a desktop computer, a mobile computer, a laptop computer, a notebook computer, a tablet computer, a server computer, a handheld computer, a handheld device, a personal digital assistant (PDA), a handheld PDA device, an on-board device, an off-board device, a hybrid device, a vehicle device, a non-vehicle device, a mobile or portable device, a consumer device, a non-mobile or non-portable device, a wireless communication station, a wireless communication device, a wireless access point (AP), a wired or wireless router, a wired or wireless modem, a video device, an audio device, an audio-video (A / V) device, a wired or wireless network, a wireless area network,a wireless video network (WVAN), a local area network (LAN), a wireless LAN (WLAN), a personal area network (PAN), a wireless PAN (WPAN), and the like.

[0096] Some embodiments may be used in connection with one-way and / or two-way radio communication systems, cellular radiotelephone communication systems, a mobile phone, a cellular telephone, a cordless telephone, a Personal Communication System (PCS) device, a PDA device including a wireless communication device, a mobile or portable Global Positioning System (GPS) device, a device including a GPS receiver or transceiver or chip, a device including an RFID element or an RFID chip, a MIMO transceiver or device with multiple inputs and multiple outputs, a SIMO transceiver or device with single inputs and multiple outputs, a MISO transceiver or device with multiple inputs and single outputs, a device with one or more internal antennas and / or external antennas, DVB devices or systems, multi-standard radio devices or systems, a wired or wireless handheld device, e.g.a smartphone, a wireless application protocol (WAP) device, or the like.

[0097] Some embodiments may be used in connection with one or more types of wireless communication signals and / or systems that follow one or more wireless communication protocols, e.g. E.g. Radio Frequency (RF), Infrared (IR), Frequency Division Multiplexing (FDM), Orthogonal FDM (OFDM), Time Division Multiple Access (TDM), Time Division Multiple Access (TDMA), Enhanced TDMA (E-TDMA), General Packet Radio Service (GPRS), Extended GPRS, Code-Division Multiple Access (CDMA), Wideband CDMA (WCDMA), CDMA 2000, Single-Carrier CDMA, Multi-Carrier CDMA, Multi-Carrier Modulation (MDM), Discrete Multi-Tone (DMT), Bluetooth®, Global Positioning System (GPS), Wi-Fi, Wi-Max, ZigBee, Ultra Wideband (UWB), Global System for Mobile Communications (GSM), 2G, 2.5G, 3G, 3.5G, 4G, Fifth Generation (5G) Mobile Networks, 3GPP, Long Term Evolution (LTE), LTE Advanced, Enhanced Data Rates for GSM Evolution (EDGE) or the like.Other embodiments may be used in various other devices, systems, and / or networks.

[0098] The following examples refer to further embodiments.

[0099] Example 1 may be an apparatus for decoding video data encoded using Low-Complexity Enhancement Video Coding (LCEVC), the apparatus comprising processing circuitry coupled to a memory and configured to: identify a bitstream received from a device, the bitstream comprising a first layer encoded using a base encoder and enhancement layers encoded using LCEVC; decoding a first video image of the first layer of the bitstream using a base decoder; upsampling the decoded first video image; identifying a first quantization parameter of a first tile of the first video image encoded using a first enhancement layer of the enhancement layers;Identifying a second quantization parameter of a second tile of the first video image encoded using the first enhancement layer, wherein the second quantization parameter differs from the first quantization parameter; Decoding, based on the first quantization parameter and the second quantization parameter, the first video image encoded using the first enhancement layer; Generating a first combined intermediate video image by combining the upsampled first video image and the decoded first video image encoded using the first enhancement layer; Upsampling the first combined intermediate video image; Decoding the first video image encoded using a second enhancement layer of the enhancement layers;Generating a second combined intermediate video image by combining the decoded first video image encoded using the second enhancement layer and a reference image; and generating a combined output video image by combining the first combined intermediate video image and the second combined intermediate video image.

[0100] Example 2 may include the apparatus of Example 1 and / or any other example herein, wherein the processing circuitry is further configured to: identify a third quantization parameter of a third tile of the first video image encoded using the second enhancement layer; and identify a fourth quantization parameter of a fourth tile of the first video image encoded using the second enhancement layer, wherein the fourth quantization parameter is different from the second quantization parameter, wherein decoding the first video image encoded using the second enhancement layer is based on the third quantization parameter and the fourth quantization parameter.

[0101] Example 3 may include the apparatus of Example 1 and / or any other example herein, wherein the processing circuitry is further configured to: identify a global configuration syntax of the bitstream; identify a tile-level quantization parameter indicator in the global configuration syntax; and determine that the level quantization parameter indicator indicates that the first tile and the second tile have separate quantization parameters.

[0102] Example 4 may include the apparatus of Example 3 and / or any other example herein, wherein the processing circuitry is further configured to: identify a process payload of an image configuration of the bitstream; and identify, in the process payload, quantization parameters for layers of the first video image encoded using the first enhancement layer, the quantization parameters comprising the first quantization parameter and the second quantization parameter.

[0103] Example 5 may include the apparatus of any of Examples 1-3 and / or any other example herein, wherein the first quantization parameter is based on a first stride quantization step size for the first tile, and wherein the second quantization parameter is based on a second stride quantization step size for the second tile.

[0104] Example 6 may include the apparatus of Example 5 and / or any other example herein, wherein the first step size quantization step size and the second step size quantization step size are based on a function limited to a range of 0 to 2 15 -1 is limited.

[0105] Example 7 may include the apparatus of Example 5 and / or any other example herein, wherein the processing circuitry is further configured to: store step size quantization stepsizes of each layer and each tile for each level of residuals of the first video image.

[0106] Example 8 may include the apparatus of Example 1 and / or any other example herein, wherein the first tile is associated with a region of interest representing at least a portion of an object, wherein the second tile is not associated with the region of interest, and wherein the first quantization parameter is less than the second quantization parameter based on the first tile being associated with the region of interest.

[0107] Example 9 may include a computer-readable storage medium comprising instructions to cause processing circuitry of an apparatus for decoding video data encoded using Low-Complexity Enhancement Video Coding (LCEVC), upon execution of the instructions by the processing circuitry: identifying a bitstream received from a device, the bitstream comprising a first layer encoded using a base encoder and enhancement layers encoded using LCEVC; decoding a first video image of the first layer of the bitstream using a base decoder; upsampling the decoded first video image; identifying a first quantization parameter of a first tile of the first video image encoded using a first enhancement layer of the enhancement layers;Identifying a second quantization parameter of a second tile of the first video image encoded using the first enhancement layer, wherein the second quantization parameter differs from the first quantization parameter; Decoding, based on the first quantization parameter and the second quantization parameter, the first video image encoded using the first enhancement layer; Generating a first combined intermediate video image by combining the upsampled first video image and the decoded first video image encoded using the first enhancement layer; Upsampling the first combined intermediate video image; Decoding the first video image encoded using a second enhancement layer of the enhancement layers;Generating a second combined intermediate video image by combining the decoded first video image encoded using the second enhancement layer and a reference image; and generating a combined output video image by combining the first combined intermediate video image and the second combined intermediate video image.

[0108] Example 10 may include the computer-readable medium of Example 9 and / or any other example herein, wherein execution of the instructions further causes the processing circuitry to: identify a third quantization parameter of a third tile of the first video image encoded using the second enhancement layer; and identify a fourth quantization parameter of a fourth tile of the first video image encoded using the second enhancement layer, the fourth quantization parameter being different from the second quantization parameter, wherein decoding the first video image encoded using the second enhancement layer is based on the third quantization parameter and the fourth quantization parameter.

[0109] Example 11 may include the computer-readable medium of Example 9 and / or any other example herein, wherein execution of the instructions further causes the processing circuitry to: identify a global configuration syntax of the bitstream; identify a tile-level quantization parameter indicator in the global configuration syntax; and determine that the level quantization parameter indicator indicates that the first tile and the second tile have separate quantization parameters.

[0110] Example 12 may include the computer-readable medium of Example 11 and / or any other example herein, wherein execution of the instructions further causes the processing circuitry to: identify a process payload of an image configuration of the bitstream; and identify, in the process payload, quantization parameters for layers of the first video image encoded using the first enhancement layer, the quantization parameters comprising the first quantization parameter and the second quantization parameter.

[0111] Example 13 may include the computer-readable medium of Examples 9-11 and / or any other example herein, wherein the first quantization parameter is based on a first stride quantization step size for the first tile, and wherein the second quantization parameter is based on a second stride quantization step size for the second tile.

[0112] Example 14 may include the computer-readable medium of Example 13 and / or any other example herein, wherein the first step size quantization step size and the second step size quantization step size are based on a function limited to a range of 0 to 2 15 -1 is limited.

[0113] Example 15 may include the computer-readable medium of Example 14 and / or any other example herein that stores step size quantization steps of each layer and each tile for each level of residuals of the first video image.

[0114] Example 16 may include the computer-readable medium of Example 9 and / or any other example herein, wherein the first tile is associated with a region of interest that represents at least a portion of an object, wherein the second tile is not associated with the region of interest, and wherein the first quantization parameter is less than the second quantization parameter based on the first tile being associated with the region of interest.

[0115] Example 17 may include a method for decoding video data encoded using Low-Complexity Enhancement Video Coding (LCEVC), the method comprising: identifying, by at least one processor of a first device, a bitstream received from a second device, the bitstream comprising a first layer encoded using a base encoder and enhancement layers encoded using LCEVC; decoding, by the at least one processor, a first video image of the first layer of the bitstream using a base decoder; upsampling, by the at least one processor, the decoded first video image; identifying, by the at least one processor, a first quantization parameter of a first tile of the first video image encoded using a first enhancement layer of the enhancement layers;Identifying, by the at least one processor, a second quantization parameter of a second tile of the first video image encoded using the first enhancement layer, wherein the second quantization parameter is different from the first quantization parameter; Decoding, by the at least one processor, the first video image encoded using the first enhancement layer based on the first quantization parameter and the second quantization parameter; Generating, by the at least one processor, a first combined intermediate video image by combining the upsampled first video image and the decoded first video image encoded using the first enhancement layer; Upsampling, by the at least one processor, the first combined intermediate video image;Decoding, by the at least one processor, the first video image encoded using a second enhancement layer of the enhancement layers; generating, by the at least one processor, a second combined intermediate video image by combining the decoded first video image encoded using the second enhancement layer and a reference image; and generating, by the at least one processor, a combined output video image by combining the first combined intermediate video image and the second combined intermediate video image.

[0116] Example 18 may include the method of Example 17 and / or any other example herein, further comprising: identifying a third quantization parameter of a third tile of the first video image encoded using the second enhancement layer; and identifying a fourth quantization parameter of a fourth tile of the first video image encoded using the second enhancement layer, wherein the fourth quantization parameter is different from the second quantization parameter, wherein decoding the first video image encoded using the second enhancement layer is based on the third quantization parameter and the fourth quantization parameter.

[0117] Example 19 may include the method of Example 18 and / or any other example herein, further comprising: identifying a global configuration syntax of the bitstream; identifying a tile-level quantization parameter indicator in the global configuration syntax; and determining that the level quantization parameter indicator indicates that the first tile and the second tile have separate quantization parameters.

[0118] Example 20 may include the method of Example 19 and / or any other example herein, further comprising: identifying a process payload of an image configuration of the bitstream; and identifying, in the process payload, quantization parameters for layers of the first video image encoded using the first enhancement layer, the quantization parameters comprising the first quantization parameter and the second quantization parameter.

[0119] Example 21 may include the method of any of Examples 17-19 and / or any other example herein, wherein the first quantization parameter is based on a first stride quantization step size for the first tile, and wherein the second quantization parameter is based on a second stride quantization step size for the second tile.

[0120] Example 22 may include the example of claim 21 and / or any other example herein, wherein the first step size quantization step size and the second step size quantization step size are based on a function limited to a range of 0 to 2 15 -1 is limited.

[0121] Example 23 may include the method of Example 21 and / or any other example herein, further comprising: storing step size quantization stepsizes of each layer and each tile for each level of residuals of the first video image.

[0122] Example 24 may include the method of Example 17 and / or any other example herein, wherein the first tile is associated with a region of interest that represents at least a portion of an object, wherein the second tile is not associated with the region of interest, and wherein the first quantization parameter is less than the second quantization parameter based on the first tile being associated with the region of interest.

[0123] Example 25 may include an apparatus having means for performing any of the methods of Examples 17-24.

[0124] Example 26 may include one or more non-transitory computer-readable media containing instructions for causing an electronic device, upon execution of the instructions by one or more processors of the electronic device, to perform one or more elements of a method described in or related to any of Examples 1-25, or any other method or process described herein.

[0125] Example 27 may include a device having logic, modules, and / or circuitry for performing one or more elements of a method described in or associated with Examples 1-25 or any other method or process described herein.

[0126] Example 28 may include a method, technique, or process as described in or associated with any of Examples 1-25, or portions or parts thereof.

[0127] Example 29 may include an apparatus comprising: one or more processors; and one or more computer-readable media comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform the method, techniques, or process as described in or associated with any of Examples 1-25, or portions thereof.

[0128] Embodiments according to the disclosure are particularly disclosed in the appended claims, which relate to a method, a storage medium, a device, and a computer program product, wherein each feature mentioned in one claim category, e.g., method, can also be claimed in another claim category, e.g., system. The dependencies or backreferences in the appended claims are chosen for formal reasons only. However, any subject-matter resulting from a deliberate reference to earlier claims (in particular to multiple dependencies) can also be claimed, so that any combination of claims and their features is disclosed and can be claimed independently of the dependencies chosen in the appended claims.The claimable subject matter includes not only the feature combinations set forth in the appended claims, but also any other feature combination in the claims, wherein any feature recited in the claims may be combined with any other feature or feature combination in the claims. Furthermore, any of the embodiments and features described or illustrated herein may be claimed in a separate claim and / or in any combination with any embodiment or feature described or illustrated herein, or with any of the features of the appended claims.

[0129] The foregoing description of one or more embodiments is provided for purposes of illustration and description, but is not intended to be exhaustive or to limit the scope of the embodiments to the precise form disclosed. Modifications and variations are possible in light of the above teachings or may be acquired from practice of the various embodiments.

[0130] Certain aspects of the disclosure are described above with reference to block and flow diagrams of systems, methods, apparatus, and / or computer program products according to various implementations. It should be understood that one or more blocks of the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, may be implemented by computer-executable program instructions. Likewise, some blocks of the block diagrams and flowcharts need not be performed in the order presented, or in some embodiments, they may not be performed at all.

[0131] These computer-executable program instructions may be loaded onto a special purpose computer or other particular machine, processor, or other programmable data processing device to produce a particular machine, such that the instructions, executing on the computer, processor, or other programmable data processing device, provide means for implementing one or more functions specified in the block or blocks of the flowchart.These computer program instructions may also be stored in a computer-readable storage medium or memory that can instruct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that perform one or more functions specified in the flowchart block or blocks. For example, certain implementations may provide a computer program product comprising a computer-readable storage medium having computer-readable program code or program instructions implemented therein, wherein the computer-readable program code is executable to implement one or more functions specified in the flowchart block or blocks.The computer program instructions may also be loaded onto a computer or other programmable data processing device to cause a series of operational elements or steps to be executed on the computer or other programmable device to produce a computer-implemented process, such that the instructions executing on the computer or other programmable device provide elements or steps for implementing the functions specified in the flowchart block or blocks.

[0132] Accordingly, blocks of the block diagrams and flowcharts support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions, and program instruction means for performing the specified functions. It is also understood that each block of the block diagrams and flowcharts, and combinations of blocks in the block diagrams and flowcharts, may be implemented by special-purpose hardware-based computer systems that perform the specified functions, elements, or steps, or by combinations of special-purpose hardware and computer instructions.

[0133] Conditional expressions such as "may", "could", "might", or "may", unless explicitly stated otherwise or understood differently in the relevant context, are generally intended to express that certain implementations may include certain features, elements, and / or operations, while other implementations do not include them. Thus, such conditional language is not intended to generally imply that features, elements, and / or operations are in any way required of one or more implementations, or that one or more implementations necessarily include logic to decide, with or without user input or prompting, whether those features, elements, and / or operations should be included or performed in a particular implementation.

[0134] Many modifications and other implementations of the disclosure set forth herein will be apparent with the benefit of the teachings presented in the foregoing descriptions and the accompanying drawings. It is therefore to be understood that the disclosure is not limited to the specific implementations disclosed, and that modifications and other implementations are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used only in a generic and descriptive sense and not for purposes of limitation.

Claims

[1] An apparatus for decoding video data encoded using Low-Complexity Enhancement Video Coding (LCEVC), the apparatus comprising a processing circuit coupled to a memory and configured to: Identifying a bitstream received from a device, the bitstream comprising a first layer encoded with a base encoder and enhancement layers encoded with LCEVC, comprising: Decoding a first video image of the first layer of the bitstream with a base decoder; Extrapolation of the decoded first video image; identifying a first quantization parameter of a first tile of the first video image encoded using a first enhancement layer of the enhancement layers; identifying a second quantization parameter of a second tile of the first video image encoded using the first enhancement layer, the second quantization parameter being different from the first quantization parameter; Decoding, based on the first quantization parameter and the second quantization parameter, the first video image encoded using the first enhancement layer; generating a first combined intermediate video image by combining the upsampled first video image and the decoded first video image encoded using the first enhancement layer; Extrapolating the first combined intermediate video image; Decoding the first video image encoded with a second enhancement layer of the enhancement layers; Generating a second combined intermediate video image by combining the decoded first video image encoded using the second enhancement layer and a reference image; and Generating a combined output video image by combining the first combined intermediate video image and the second combined intermediate video image. [2] The apparatus of claim 1, wherein the processing circuit is further configured to: Identifying a third quantization parameter of a third tile of the first video image encoded using the second enhancement layer; and Identifying a fourth quantization parameter of a fourth tile of the first video image encoded using the second enhancement layer, wherein the fourth quantization parameter differs from the second quantization parameter, wherein decoding the first video image encoded using the second enhancement layer is based on the third quantization parameter and the fourth quantization parameter. [3] The apparatus of claim 1, wherein the processing circuit is further configured to: Identifying a global configuration syntax of the bitstream; Identifying a tile-level quantization parameter indicator in the global configuration syntax; and Notice that the layer quantization parameter indicator shows that the first tile and the second tile have separate quantization parameters. [4] The apparatus of claim 3, wherein the processing circuit is further configured to: Identifying a process payload of an image configuration of the bitstream; and Identifying, in the process payload, quantization parameters for layers of the first video image encoded using the first enhancement layer, the quantization parameters comprising the first quantization parameter and the second quantization parameter. [5] The apparatus of any of claims 1-3, wherein the first quantization parameter is based on a first step size quantization step size for the first tile and wherein the second quantization parameter is based on a second step size quantization step size for the second tile. [6] The apparatus of claim 5, wherein the first step size quantization step size and the second step size quantization step size are based on a function limited to a range of 0 to 2 15 -1 is limited. [7] The apparatus of claim 5, wherein the processing circuit is further configured to: Store the step size quantization steps of each layer and each tile for each level of the residuals of the first video frame. [8] The apparatus of claim 1, wherein the first tile is associated with a region of interest representing at least a portion of an object, the second tile is not associated with the region of interest, and the first quantization parameter is less than the second quantization parameter based on the first tile being associated with the region of interest. [9] A computer-readable storage medium containing instructions for causing the processing circuitry of an apparatus for decoding video data encoded using Low-Complexity Enhancement Video Coding (LCEVC), upon execution of the instructions by the processing circuitry: Identifying a bitstream received from a device, the bitstream comprising a first layer encoded with a base encoder and enhancement layers encoded with LCEVC, comprising: Decoding a first video image of the first layer of the bitstream with a base decoder; Extrapolation of the decoded first video image; identifying a first quantization parameter of a first tile of the first video image encoded using a first enhancement layer of the enhancement layers; identifying a second quantization parameter of a second tile of the first video image encoded using the first enhancement layer, the second quantization parameter being different from the first quantization parameter; Decoding, based on the first quantization parameter and the second quantization parameter, the first video image encoded using the first enhancement layer; generating a first combined intermediate video image by combining the upsampled first video image and the decoded first video image encoded using the first enhancement layer; Extrapolating the first combined intermediate video image; Decoding the first video image encoded with a second enhancement layer of the enhancement layers; generating a second combined intermediate video image by combining the decoded first video image encoded using the second enhancement layer and a reference image; and Generating a combined output video image by combining the first combined intermediate video image and the second combined intermediate video image. [10] The computer-readable medium of claim 9, wherein execution of the instructions further causes the processing circuitry to: Identifying a third quantization parameter of a third tile of the first video image encoded using the second enhancement layer; and Identifying a fourth quantization parameter of a fourth tile of the first video image encoded using the second enhancement layer, wherein the fourth quantization parameter differs from the second quantization parameter, wherein decoding the first video image encoded using the second enhancement layer is based on the third quantization parameter and the fourth quantization parameter. [11] The computer-readable medium of claim 9, wherein execution of the instructions further causes the processing circuitry to: Identifying a global configuration syntax of the bitstream; Identifying a tile-level quantization parameter indicator in the global configuration syntax; and Notice that the layer quantization parameter indicator shows that the first tile and the second tile have separate quantization parameters. [12] The computer-readable medium of claim 11, wherein execution of the instructions further causes the processing circuitry to: Identifying a process payload of an image configuration of the bitstream; and Identifying, in the process payload, quantization parameters for layers of the first video image encoded using the first enhancement layer, the quantization parameters comprising the first quantization parameter and the second quantization parameter. [13] The computer-readable medium of claims 9-11, wherein the first quantization parameter is based on a first stride quantization step size for the first tile, and wherein the second quantization parameter is based on a second stride quantization step size for the second tile. [14] The computer-readable medium of claim 13, wherein the first step size quantization step size and the second step size quantization step size are based on a function limited to a range of 0 to 2 15 -1 is limited. [15] The computer-readable medium of claim 14, storing step size quantization stepsizes of each layer and each tile for each level of residuals of the first video image. [16] The computer-readable medium of claim 9, wherein the first tile is associated with a region of interest representing at least a portion of an object, the second tile is not associated with the region of interest, and the first quantization parameter is less than the second quantization parameter based on the first tile being associated with the region of interest. [17] A method for decoding video data encoded using Low-Complexity Enhancement Video Coding (LCEVC), the method comprising: Identifying, by at least one processor of a first device, a bitstream received from a second device, the bitstream comprising a first layer encoded using a base encoder and enhancement layers encoded using LCEVC; Decoding a first video image of the first layer of the bitstream by the at least one processor using a base decoder; extrapolating the decoded first video image by the at least one processor; identifying, by the at least one processor, a first quantization parameter of a first tile of the first video image encoded using a first enhancement layer of the enhancement layers; identifying, by the at least one processor, a second quantization parameter of a second tile of the first video image encoded using the first enhancement layer, wherein the second quantization parameter is different from the first quantization parameter; Decoding, by the at least one processor, the first video image encoded using the first enhancement layer based on the first quantization parameter and the second quantization parameter; generating a first combined intermediate video image by the at least one processor by combining the upsampled first video image and the decoded first video image encoded using the first enhancement layer; extrapolating the first combined intermediate video image by the at least one processor; decoding, by the at least one processor, the first video image encoded using a second enhancement layer of the enhancement layers; generating a second combined intermediate video image by the at least one processor by combining the decoded first video image encoded using the second enhancement layer and a reference image; and Generating, by the at least one processor, a combined output video image by combining the first combined intermediate video image and the second combined intermediate video image. [18] The method of claim 17, further comprising: Identifying a third quantization parameter of a third tile of the first video image encoded using the second enhancement layer; and Identifying a fourth quantization parameter of a fourth tile of the first video image encoded using the second enhancement layer, wherein the fourth quantization parameter differs from the second quantization parameter, wherein decoding the first video image encoded using the second enhancement layer is based on the third quantization parameter and the fourth quantization parameter. [19] The method of claim 18, further comprising: Identifying a global configuration syntax of the bitstream; Identifying a tile-level quantization parameter indicator in the global configuration syntax; and Notice that the layer quantization parameter indicator shows that the first tile and the second tile have separate quantization parameters. [20] The method of claim 19, further comprising: Identifying a process payload of an image configuration of the bitstream; and Identifying, in the process payload, quantization parameters for layers of the first video image encoded using the first enhancement layer, the quantization parameters comprising the first quantization parameter and the second quantization parameter. [21] The method of any of claims 17-19, wherein the first quantization parameter is based on a first step size quantization step size for the first tile, and wherein the second quantization parameter is based on a second step size quantization step size for the second tile. [22] The method of claim 21, wherein the first step size quantization step size and the second step size quantization step size are based on a function limited to a range of 0 to 2 15 -1 is limited. [23] The method of claim 21, further comprising: Store the step size quantization steps of each layer and each tile for each level of the residuals of the first video frame. [24] The method of claim 17, wherein the first tile is associated with a region of interest representing at least a portion of an object, the second tile is not associated with the region of interest, and the first quantization parameter is less than the second quantization parameter based on the first tile being associated with the region of interest. [25] Apparatus comprising means for carrying out one of the methods according to claims 17-24.

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