Semiconductor wafer, semiconductor device, power conversion device and cooling system

Abstract

The aim is to provide a technique capable of suppressing a crack from extending to the lower side of an interlayer insulating film when an external stress due to thermal shrinkage stress is applied to a corner of a semiconductor element. A semiconductor wafer (1) includes a semiconductor substrate (10) on which an interlayer insulating film (9) and a surface protective film (8) covering the interlayer insulating film (9) are laminated on an upper surface. A plurality of semiconductor elements (3) to be divided into small pieces by dicing along an opening (2a) formed in the surface protective film (8) are formed on the semiconductor substrate (10).An end of the interlayer insulating film (9) is recessed more than an end of the surface protective film (8) with respect to an end of the semiconductor substrate (10) to be formed by the dicing, and a shape of the end of the interlayer insulating film (9) is set such that, in each of the semiconductor elements (3) after dicing, a distance Lx from a corner of the semiconductor substrate (10) to be formed by the dicing to the end of the interlayer insulating film (9) and a thickness d of the semiconductor substrate (10) satisfy a relationship of a formula 1.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor wafer, a semiconductor device, a power conversion device, and a cooling system. BACKGROUND TECHNOLOGY

[0002] Patent Document 1 discloses a structure in which an interlayer insulating film is formed on a semiconductor wafer, and a surface protective film is formed to overlap and cover the interlayer film. In this structure, for example, the length from one end of a semiconductor element to the surface protective film, excluding an 80 μm width of an opening of the surface protective film and a 50 μm gap of a scribe line, is 30 μm / 2 = 15 μm, and the thickness of a product is 180 μm. DOCUMENT ACCORDING TO THE PRIOR ART PATENT DOCUMENT

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2016-225511 SUMMARY PROBLEM TO BE SOLVED BY THE INVENTION

[0004] In a technique described in Patent Document 1, since the length from the end of the semiconductor element to the surface protective film is as short as about 15 μm, there is a problem that external stress due to thermal shrinkage stress is applied to the end of the semiconductor element, so a crack is likely to occur from the surface protective film to the lower side of the interlayer insulating film. When the crack extends to the lower side of the interlayer insulating film, a withstand voltage of the semiconductor element decreases, and thus a crack length is important. The external stress due to thermal shrinkage stress increases at four corners in the ends of the semiconductor element, so the withstand voltage of the semiconductor element is likely to decrease when the crack extends to the lower side of the interlayer insulating film.

[0005] Furthermore, such a semiconductor element is mounted on a power module. For example, a power module of a vehicle-mounted power conversion device has a wider operating temperature range (for example, in the range of -40°C or more and 150°C or less) than an indoor power module, and is used in an environment with a severe thermal cycle or large temperature fluctuations. Furthermore, in a low-temperature environment, torque is applied to a motor at the time of starting, so the temperature of the entire power system rises rapidly. For this reason, there is a problem that delamination occurs between a sealing resin and the semiconductor element in the power module, resulting in dielectric breakdown of the semiconductor element.

[0006] Therefore, an object of the present disclosure is to provide a technique capable of suppressing a crack from extending to the lower side of an interlayer insulating film when an external stress due to a thermal shrinkage stress is applied to a corner of a semiconductor element. MEANS TO SOLVE THE PROBLEM

[0007] A semiconductor wafer according to the present disclosure is a semiconductor wafer including a semiconductor substrate in which an interlayer insulating film and a surface protective film covering the interlayer insulating film are laminated on an upper surface, wherein a plurality of semiconductor elements to be divided into small pieces by dicing along an opening formed in the surface protective film are formed on the semiconductor substrate, one end of the interlayer insulating film being more recessed with respect to an end of the semiconductor substrate to be formed by dicing.is withdrawn as an end of the surface protective film and a shape of the end of the interlayer insulating film is set in such a manner that, in each of the semiconductor elements after dicing, a distance Lx from a corner of the semiconductor substrate to be formed by dicing to the end of the interlayer insulating film and a thickness d of the semiconductor substrate satisfy a relationship of a formula 1. EFFECTS OF THE INVENTION

[0008] According to the present disclosure, since the distance Lx from the corner of the semiconductor substrate to the end of the interlayer insulating film is long, it is possible to suppress the crack from extending to the lower side of the interlayer insulating film when the external stress due to the thermal shrinkage stress is applied to the corner of the semiconductor element.

[0009] Objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS [ Fig. 1] is a plan view of a semiconductor wafer according to a first embodiment. [ Fig. 2] is a plan view and a cross-sectional view of a corner of a semiconductor element to be formed by dicing in the semiconductor wafer according to the first embodiment. [ Fig. 3] is a graph showing a relationship between a length of a crack from the corner of the semiconductor element and a thickness of the semiconductor element when an external stress due to a thermal shrinkage stress is applied to the corner of the semiconductor element. [ Fig. 4] is a cross-sectional view of a corner of a semiconductor element to be formed by dicing in a semiconductor wafer according to a third embodiment. [ Fig. 5] is a cross-sectional view of a corner of a semiconductor element to be formed by dicing in a semiconductor wafer according to a fourth embodiment. [ Fig. 6] is a block diagram illustrating a configuration of a power conversion system to which a power conversion device according to a fifth embodiment is applied. [ Fig. 7] is a block diagram illustrating a configuration of a cooling system according to a sixth embodiment. DESCRIPTION OF THE EMBODIMENTS<Erste Ausführungsform>

[0010] With reference to the drawings, a first embodiment is described below. Fig. 1 is a plan view of a semiconductor wafer 1 according to the first embodiment. Fig. 2(a) is a plan view of corners of semiconductor elements 3 to be formed by dicing in the semiconductor wafer 1 according to the first embodiment. Fig. 2(b) is a cross-sectional view of the corners of the semiconductor elements 3 to be formed by dicing in the semiconductor wafer 1 according to the first embodiment.

[0011] As in Fig. As illustrated in FIG. 1, the semiconductor wafer 1 is formed in a disc shape. In a region of the semiconductor wafer 1 excluding a peripheral edge portion, a plurality of semiconductor elements 3 to be divided into small pieces by dicing are formed. Further, in the region of the semiconductor wafer 1 excluding the peripheral edge portion, a plurality of dicing lines 2 for dividing into the plurality of semiconductor elements 3 are formed in intersecting directions. Each of the semiconductor elements 3 obtained from the semiconductor wafer 1 is mounted on a semiconductor device (a power module) through a known processing.

[0012] As in Fig. 2(a) and Fig. As illustrated in Fig. 2(b), the semiconductor wafer 1 includes a semiconductor substrate 10, an interlayer insulating film 9, and a surface protective film 8.

[0013] The semiconductor substrate 10 is formed in a disk shape. A base material of the semiconductor substrate 10 is SiC. Note that the base material of the semiconductor substrate 10 can be Si or GaN. The interlayer insulating film 9 and the surface protective film 8 are laminated on a top surface of the semiconductor substrate 10.

[0014] The interlayer insulating film 9 is, for example, a TEOS film and covers the upper surface of the semiconductor substrate 10. Specifically, the interlayer insulating film 9 is disposed in a region excluding a peripheral edge portion of the semiconductor element 3 to be formed by dicing, and portions of the interlayer insulating film 9 corresponding to four corners of the semiconductor element 3 are formed in a curved shape with rounded corners in plan view.

[0015] The surface protection film 8 is made of polyimide, for example, and is arranged to cover the interlayer insulating film 9 from above. The dicing line 2 is formed by means of an opening 2a that is open upward. One end of the interlayer insulating film 9 is recessed more than one end of the surface protection film 8 with respect to an end of the semiconductor substrate 10 to be formed by dicing. That is, the surface protection film 8 covers the entire interlayer insulating film 9. Note that an arrow in Fig. 2(b) indicates a direction in which a crack extends.

[0016] In the first embodiment, in order to prevent the crack from extending to the lower side of the interlayer insulating film 9 when an external stress due to a thermal shrinkage stress is applied to the corner of the semiconductor element 3, a shape of the end of the interlayer insulating film 9 is set so that a distance Lx from a corner of the semiconductor substrate 10 to be formed by dicing to the end of the interlayer insulating film 9 and a thickness d of the semiconductor substrate 10 in each of the semiconductor elements 3 after dicing satisfy a relationship of a formula 1. Lx>10×d−717μm

[0017] Hereinafter, a reason will be described why the effect of suppressing expansion of the crack toward the lower side of the interlayer insulating film 9 when the external stress due to the thermal shrinkage stress is applied to the corner of the semiconductor element 3 can be obtained by setting the shape of the end of the interlayer insulating film 9 to satisfy the relationship of Formula 1. Fig. 3 is a graph showing a relationship between a length D of the crack from the corner of the semiconductor element 3 and the thickness d of the semiconductor element 3 when the external stress due to the thermal shrinkage stress is applied to the corner of the semiconductor element 3.

[0018] As the thickness d of the semiconductor element 3 increases, the thermal shrinkage stress on the semiconductor element 3 increases, so that the external stress is likely to be applied. A point where the highest external stress is applied is the corner of the semiconductor element 3, and the crack is likely to occur at that point. Therefore, as the thickness d of the semiconductor substrate 10 (hereinafter also referred to as the "thickness d") increases, it is necessary to take measures against the occurrence of the crack. Specifically, even if the crack occurs, the crack is less likely to extend to the end of the interlayer insulating film 9 by increasing a length of the distance Lx from the corner of the semiconductor substrate 10 to the end of the interlayer insulating film 9 (hereinafter also referred to as the "distance Lx"), and thus, the distance Lx must be increased as the thickness d increases.The inventor of the present application conducted an experiment using the semiconductor elements 3 having different thicknesses d and found that a relationship between the distance Lx and the thickness d is represented by an expression of a linear relationship of Formula 1.

[0019] Fig. Figure 3 shows the relationship between the length D of the crack from the corner of the semiconductor element 3 and the thickness d using data obtained by evaluating the semiconductor elements 3 with different thicknesses d. As in Fig. 3, in the semiconductor element 3 with d = 100 µm and the semiconductor element 3 with d = 300 µm, the length D of the crack is longer when d = 300 µm, and their relationship is expressed by an expression of a linear relationship of Formula 1. Since the crack does not extend to the end of the interlayer insulating film 9 when the distance Lx is longer than the length D of the crack, the above effect can be obtained by satisfying Formula 1.

[0020] Here, the thickness d is, for example, approximately 100 µm, and the distance Lx is, for example, approximately 300 µm. The interlayer insulating film 9 is completely covered by the surface protective film 8 up to its end, and a width of the interlayer insulating film 9 covered by the surface protective film 8 is, for example, approximately 1 / 3 of the distance Lx.

[0021] As described above, the semiconductor wafer 1 according to the first embodiment includes the semiconductor substrate 10 in which the interlayer insulating film 9 and the surface protective film 8 covering the interlayer insulating film 9 are laminated on the upper surface, and the plurality of semiconductor elements 3 to be divided into small pieces by dicing along the opening 2a formed in the surface protective film 8 are formed on the semiconductor substrate 10.The end of the interlayer insulating film 9 is recessed more than the end of the surface protective film 8 with respect to the end of the semiconductor substrate 10 to be formed by dicing, and the shape of the end of the interlayer insulating film 9 is set so that in each of the semiconductor elements 3 after dicing, the distance Lx from the corner of the semiconductor substrate 10 to be formed by dicing to the end of the interlayer insulating film 9 and the thickness d of the semiconductor substrate 10 satisfy the relationship of Formula 1.

[0022] Therefore, since the distance Lx from the corner of the semiconductor substrate 10 to the end of the interlayer insulating film 9 becomes long, when the external stress due to thermal shrinkage stress is applied to the corner of the semiconductor element 3, it is possible to suppress the crack from extending to the lower side of the interlayer insulating film 9. As described above, the durability of the semiconductor device including the semiconductor element 3 obtained from the semiconductor wafer 1 is improved. <Zweite Ausführungsform>

[0023] Next, the semiconductor wafer 1 according to a second embodiment will be described. Note that in the second embodiment, the same components as those described in the first embodiment are denoted by the same reference numerals, and their descriptions will be omitted.

[0024] The distance Lx is affected by a finish of the dicing line 2, which is a cut state with a dicing line width W and a kerf width C. Therefore, it is necessary to consider the finish of the dicing line 2 in order to determine a shape of an end of the interlayer insulating film 9 with high accuracy. Therefore, in the second embodiment, the shape of the end of the interlayer insulating film 9 is determined to satisfy the following Formula 2 in addition to Formula 1 to consider the finish of the dicing line 2.

[0025] The shape of the end of the interlayer insulating film 9 is set so that the width W of the dicing line 2, the kerf width C which is a width of the dicing line 2 removed by dicing, a width L from an end of the surface protective film 8 to the end of the interlayer insulating film 9 in each of the semiconductor elements 3, a curvature R of the interlayer insulating film 9 at a corner of the semiconductor element 3, and the distance Lx satisfy the relationship of Formula 2. Lx=2×((W−C) / 2+L)+(2−1)×R

[0026] A procedure for deriving formula 2 is given with reference to Fig. 2. As described in Fig. As illustrated in Figure 2, a square whose side length is R + L + (W - C) / 2) has a diagonal length Lx + R. The diagonal length of the square is expressed by an expression Lx + R = R + L + (W - C) / 2) × √2. Formula 2 is obtained from this expression.

[0027] Here, the width W of the dicing line 2 is, for example, about 150 μm, and the kerf width C is, for example, about 50 μm. In addition, the width L from the end of the surface protective film 8 to the end of the interlayer insulating film 9 in each of the semiconductor elements 3 is, for example, about 80 μm, and the curvature R of the interlayer insulating film 9 is, for example, about 500 μm. As a result, the distance Lx is, for example, 391 μm. Note that setting the shape of the end of the interlayer insulating film 9 to satisfy the relationship of Formula 2 in addition to the relationship of Formula 1 can also be adopted in the following third and fourth embodiments.

[0028] As described above, since the shape of the end of the interlayer insulating film 9 is determined to satisfy the relationship of Formula 2 in addition to the relationship of Formula 1 in the semiconductor wafer 1 according to the second embodiment, the shape of the end of the interlayer insulating film 9 can be determined with high accuracy by taking into account the finishing of the dicing line 2. As a result, it is possible to improve the effect of suppressing the extension of a crack to the lower side of the interlayer insulating film 9 when an external stress due to thermal shrinkage stress is applied to the corner of the semiconductor substrate 1. <Dritte Ausführungsform>

[0029] Next, a semiconductor wafer 1A according to the third embodiment will be described. Fig. 4 is a cross-sectional view of corners of semiconductor elements 3A to be formed by dicing in the semiconductor wafer 1A according to the third embodiment. Note that in the third embodiment, the same components as those described in the first and second embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0030] As in Fig. 4, in the third embodiment, an AISi film 14 is disposed on an outer peripheral surface of one end of the interlayer insulating film 9 so as to cover the end of the interlayer insulating film 9 in each of the semiconductor elements 3A. The AISi film 14 is disposed so as to cover the entire outer peripheral surface of the end of the interlayer insulating film 9 and functions as a buffer against a crack extending from a corner of the semiconductor element 3A. Note that the AISi film 14 may be disposed up to an upper surface of the interlayer insulating film 9 from the end of the interlayer insulating film 9, instead of being disposed only on the outer peripheral surface of the end of the interlayer insulating film 9.

[0031] As described above, in the semiconductor wafer 1A according to the third embodiment, the AISi film 14 is disposed on the outer peripheral surface of the end of the interlayer insulating film 9 so as to cover the end of the interlayer insulating film 9 in each of the semiconductor elements 3A. Therefore, the AISi film 14 functions as the buffer for the crack extending from the corner of the semiconductor element 3A, so that it is possible to improve the effect of suppressing the extension of the crack to the lower side of the interlayer insulating film 9 when an external stress due to thermal shrinkage stress is applied to the corner of the semiconductor element 3A. <Vierte Ausführungsform>

[0032] Next, a semiconductor wafer 1B according to the fourth embodiment will be described. Fig. 5 is a cross-sectional view of corners of semiconductor elements 3B to be formed by dicing in the semiconductor wafer 1B according to the fourth embodiment. Note that in the fourth embodiment, the same components as those described in the first to third embodiments are denoted by the same reference numerals, and their descriptions are omitted.

[0033] As in Fig. 5, in the fourth embodiment, the AISi film 14 is formed to be thicker than the interlayer insulating film 9 and is disposed from the outer peripheral surface of one end of the interlayer insulating film 9 over one end of the semiconductor substrate 10 to be formed by dicing in each of the semiconductor elements 3B. The AISi film 14 is disposed to cover the entire outer peripheral surface of the end of the interlayer insulating film 9 and a partial region of the peripheral upper surface thereof, and functions as a buffer against a crack extending from a corner of the semiconductor element 3A.

[0034] When the AISi film 14 is not interposed between the semiconductor substrate 10 and the surface protective film 8, an external stress is applied to a contact point between the semiconductor substrate 10 and the surface protective film 8. However, in the fourth embodiment, the AISi film 14 is disposed from the end of the interlayer insulating film 9 to the end of the semiconductor substrate 10 to be formed by dicing in each of the semiconductor elements 3B. That is, since the AISi film 14 is disposed from the end of the interlayer insulating film 9 to one end of the semiconductor element 3B, an external stress is applied to a contact point between one end of the surface protective film 8, which is laminated to cover the interlayer insulating film 9, and the AISi film 14 disposed from the end of the interlayer insulating film 9 to one end of the semiconductor element 3A.Since a linear expansion coefficient of the AISi film 14 is larger than that of the semiconductor substrate 10, the external stress applied to the contact point is slightly attenuated.

[0035] As described above, in the semiconductor wafer 1B according to the fourth embodiment, when the external stress due to thermal shrinkage stress is applied to the corner of the semiconductor element 3, the effect of suppressing an extension of the crack to the lower side of the interlayer insulating film 9 can be further improved compared with the case of the third embodiment. <Fünfte Ausführungsform>

[0036] In the present embodiment, the semiconductor devices according to the first to fourth embodiments described above are used for a power conversion device. The use of the semiconductor devices according to the first to fourth embodiments is not limited to a specific power conversion device, and a case where the semiconductor devices according to the first to fourth embodiments are used for a three-phase inverter will be described below as the fifth embodiment.

[0037] Fig. 6 is a block diagram illustrating a configuration of a power conversion system to which a power conversion device 16 according to the fifth embodiment is applied.

[0038] The Fig. The power conversion system illustrated in Figure 6 includes a power source 15, a power conversion device 16, and a load 18. The power source 15 is a DC power source and provides DC power to the power conversion device 16. The power source 15 may include various components and may, for example, include a DC system, a solar cell, and a storage battery, or may include a rectifier circuit and an AC / DC converter connected to an AC system. Furthermore, the power source 15 may include a DC / DC converter that converts DC power output from the DC system into a predetermined power.

[0039] The power conversion device 16 is a three-phase inverter connected between the power source 15 and the load 18, converts DC power provided by the power source 15 into AC power, and supplies the AC power to the load 18. As shown in Fig. 6, the power conversion device 16 includes a main conversion circuit 17 that converts DC power into AC power and outputs the AC power, a drive circuit 19 that outputs a drive signal for driving each of semiconductor elements of the main conversion circuit 17, and a control circuit 20 that outputs a control signal for controlling the drive circuit 19 to the drive circuit 19.

[0040] The load 18 is a three-phase electric motor driven by the AC power provided by the power conversion device 16. Note that the load 18 is not limited to a specific application, but is an electric motor mounted on various types of electrical equipment and is used, for example, as an electric motor for a hybrid vehicle, an electric vehicle, a rail vehicle, a lift, or an air conditioner.

[0041] Details of the power conversion device 16 will be described below. The main conversion circuit 17 includes the switching elements (not shown) and freewheeling diodes (not shown), converts DC power supplied from the power source 15 into AC power by switching the switching elements, and supplies the AC power to the load 18. Although there are various specific circuit configurations of the main conversion circuit 17, the main conversion circuit 17 according to the present embodiment is a two-level, three-phase full-bridge circuit and may include six switching elements and six freewheeling diodes in antiparallel with the respective switching elements.The semiconductor device according to any one of the first to fourth embodiments described above is used for at least one of the respective switching elements and the respective freewheeling diodes of the main conversion circuit 17. The six switching elements are connected in series in pairs to form upper and lower arms, and each pair of upper and lower arms forms one phase (U-phase, V-phase, W-phase) of the full-bridge circuit. Output terminals of each pair of upper and lower arms, i.e., three output terminals of the main conversion circuit 17, are then connected to the load 18.

[0042] The drive circuit 19 generates a drive signal for driving each of the switching elements of the main conversion circuit 17 and provides the drive signal to a control electrode of the switching element of the main conversion circuit 17. Specifically, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each of the switching elements according to the control signal from the control circuit 20 to be described later. The drive signal is a voltage signal (ON signal) equal to or higher than a threshold voltage of the switching element when the switching element is maintained in the ON state, and the drive signal is a voltage signal (OFF signal) equal to or lower than the threshold voltage of the switching element when the switching element is maintained in the OFF state.

[0043] The control circuit 20 controls the switching elements of the main conversion circuit 17 so that a desired power is supplied to the load 18. Specifically, based on the power to be supplied to the load 18, a time (ON time) during which each of the switching elements of the main conversion circuit 17 should be turned on is calculated. For example, the main conversion circuit 17 can be controlled by means of a PWM controller that modulates the ON time of the switching element according to a voltage to be output. A control command (control signal) is then output to the drive circuit 19 so that the ON signal and the OFF signal are output to the switching element to be turned on and the switching element to be turned off at each time. The drive circuit 19 outputs the ON signal or the OFF signal as the drive signal to the control electrode of each of the switching elements according to the control signal.

[0044] In the power conversion device according to the present embodiment, the semiconductor devices according to the first to fourth embodiments are used as the switching elements of the main conversion circuit 17, so that the durability can be improved.

[0045] Although the example in which the semiconductor devices according to the first to fourth embodiments are used for the three-phase two-level inverter has been described in the present embodiment, the use of the semiconductor devices according to the first to fourth embodiments is not limited thereto, and use is possible for various power conversion devices. Although a two-level power conversion device is assumed in the present embodiment, a power conversion device with three or more levels may be adopted. In a case where power is supplied to a single-phase load, the semiconductor devices according to the first to fourth embodiments can be used for a single-phase inverter.In addition, when power is supplied to a DC load or the like, the semiconductor devices according to the first to fourth embodiments can be used for a DC / DC converter or an AC / DC converter.

[0046] Moreover, a power conversion device using the semiconductor devices according to the first to fourth embodiments is not limited to the above-described case where the load is the electric motor, but can also be used as, for example, a power supply device of an electrical discharge machine, a laser processing machine, an induction heating cooking device, or a wireless power supply system, and can further be used as a power conditioner for a photovoltaic power generation system or a power storage system. <Sechste Ausführungsform>

[0047] Next, a cooling system 26 according to a sixth embodiment will be described. Fig. 7 is a block diagram illustrating a configuration of the cooling system 26 according to the sixth embodiment.

[0048] For example, a power module (a semiconductor device) of a vehicle-mounted power conversion device has a wider range of operating temperatures (for example, in the range of -40°C or more and 150°C or less) than a power module used indoors and is used in an environment with severe thermal cycles or large temperature fluctuations.

[0049] Furthermore, in a low-temperature environment, torque is applied to a motor at the time of startup, so the temperature of the entire power plant rises rapidly. For example, if snow accumulates in winter, high torque is required, and thus a greater load is applied to the power plant. For this reason, there is a problem that peeling occurs between a sealing resin and a semiconductor element in the power module, resulting in dielectric breakdown of the semiconductor element. The sixth embodiment is provided to solve such a problem and will be described in detail below.

[0050] As in Fig. 7, the cooling system 26 comprises a radiator 21, a pump 22, a battery cooling device 23, a flow rate adjustment device 24, a coolant flow path 25, and a PCU cooling device 27.

[0051] In the cooling system 26, devices that cool a PCU (not shown) and a battery (not shown) are connected in parallel to the radiator (heat exchanger) 21 via the coolant flow path 25. When the pump 22 operates, a coolant flowing through the coolant flow path 25 flows in the illustrated direction F. The flow rate adjustment device 24 may be arranged at a branching point where the coolant that has passed through the radiator 21 branches into the battery cooling device 23 and the PCU. Note that the battery cooling device 23 and the PCU cooling device 27 may be connected in series to the radiator 21.

[0052] As a result, a crack may occur between the sealing resin (not illustrated) in the semiconductor device and the semiconductor element 3 (see Fig.1) can be suppressed, so that a cooling load of the PCU cooling device 27 is reduced compared to the prior art, and the cooling capacity can be distributed to the battery. Since the battery cooling performance is improved, a driving distance of the vehicle can be further extended compared to the prior art. Furthermore, the size of the PCU cooling device 27 for cooling the PCU including the semiconductor device can be reduced. Therefore, the space in the vehicle can be effectively utilized.

[0053] While the present disclosure has been described in detail, the above description is in all aspects illustrative and not restrictive. It should be understood that numerous non-illustrated modifications may be adopted.

[0054] Note that each of the embodiments can be freely combined, and each of the embodiments can be appropriately modified or omitted. EXPLANATION OF REFERENCE SYMBOLS

[0055] 1 semiconductor wafer, 2a opening, 3, 3A, 3B semiconductor element, 8 surface protective film, 9 interlayer insulating film, 10 semiconductor substrate, 14 AISi film, 16 power conversion device, 17 main conversion circuit, 19 drive circuit, 20 control circuit, 21 cooler, 23 battery cooling device, 25 coolant flow path, 26 cooling system, 27 PCU cooling device. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2016-225511

[0003]

Claims

[1] A semiconductor wafer comprising a semiconductor substrate in which an interlayer insulating film and a surface protective film covering the interlayer insulating film are laminated on an upper surface, wherein a plurality of semiconductor elements to be divided into small pieces by dividing along an opening formed in the surface protective film are formed on the semiconductor substrate, an end of the interlayer insulating film is recessed more than an end of the surface protective film with respect to an end of the semiconductor substrate to be formed by dicing, and a shape of the end of the interlayer insulating film is determined in such a way that, in each of the semiconductor elements after dicing, a distance Lx from a corner of the semiconductor substrate to be formed by dicing to the end of the interlayer insulating film and a thickness d of the semiconductor substrate have a relationship of Lx>10×d−717 μm fulfill. [2] A semiconductor wafer according to claim 1, wherein the interlayer insulating film is formed in a curved shape at a corner of each of the semiconductor elements in plan view, and the shape of the end of the interlayer insulating film is set in such a way that a width W of a dicing line, a kerf width C which is a width of the dicing line removed by dicing, a width L from the end of the surface protective film to the end of the interlayer insulating film in each of the semiconductor elements, a curvature R of the interlayer insulating film at the corner of the semiconductor element and the distance Lx have a relationship of Lx=2×((W−C) / 2+L)+(2−1)×R fulfill. [3] The semiconductor wafer according to claim 1 or 2, wherein an AISi film is disposed on an outer peripheral surface of the end of the interlayer insulating film in such a manner as to cover the end of the interlayer insulating film in each of the semiconductor elements. [4] The semiconductor wafer according to claim 3, wherein the AISi film is formed to be thicker than the interlayer insulating film and is disposed from the outer peripheral surface of the end of the interlayer insulating film over the end of the semiconductor substrate to be formed by the dicing in each of the semiconductor elements. [5] A semiconductor device comprising the semiconductor element obtained from the semiconductor wafer according to any one of claims 1 to 4. [6] Semiconductor device comprising a semiconductor element comprising a semiconductor substrate in which an interlayer insulating film and a surface protective film covering the interlayer insulating film are laminated on an upper surface, wherein one end of the interlayer insulating film is recessed more than one end of the surface protective film with respect to one end of the semiconductor substrate which is one end of the semiconductor element, and a shape of the end of the interlayer insulating film is set in such a way that, in the semiconductor element, a distance Lx from a corner of the semiconductor substrate to the end of the interlayer insulating film and a thickness d of the semiconductor substrate have a relationship of Lx>10×d−717 μm fulfill. [7] A semiconductor device according to claim 6, wherein an AISi film is disposed on an outer peripheral surface of the end of the interlayer insulating film in such a manner as to cover the end of the interlayer insulating film in the semiconductor element. [8] The semiconductor device according to claim 7, wherein the AISi film is formed to be thicker than the interlayer insulating film and is disposed from the outer peripheral surface of the end of the interlayer insulating film over the end of the semiconductor substrate in the semiconductor element. [9] Power conversion device, comprising: a main conversion circuit including the semiconductor device according to claim 5 and converting input power and outputting the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit. [10] Cooling system, comprising: a PCU including the semiconductor device according to claim 5; a radiator that cools a coolant; a battery that provides power to the PCU; a battery cooling device that cools the battery using the coolant; a PCU cooling device that cools the PCU using the coolant; and a coolant flow path through which the coolant flows.

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