Semiconductor device and method for manufacturing the semiconductor device

Abstract

A semiconductor device (1) comprises: a semiconductor substrate (2) in which a semiconductor element is formed; a front-side electrode (5) formed on a first main surface of the semiconductor substrate (2); a back-side electrode (6) formed on a second main surface of the semiconductor substrate (2); and a surface protective layer (7) formed on the first main surface of the semiconductor substrate (2) to cover the front-side electrode (5) and having an opening portion exposing a part of the front-side electrode (5). An upper surface of the surface protective layer (7) is roughened by a cutting groove.

Description

Technical area

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. State of the art

[0002] A semiconductor device is known that has a surface on which a surface protective layer made of, for example, polyimide resin is formed. For example, Patent Document 1 below describes a technique for non-smoothing (hereinafter referred to as "roughening") the surface of the surface protective layer by sputtering. State of the art documentsPatent document(s)

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2007-158113 SummaryProblem to be solved by the invention

[0004] In a case where a semiconductor device including a surface protective layer is mounted on a mold resin package, if adhesion between the surface protective layer and the mold resin cannot be ensured, the mold resin will separate from the surface protective layer due to stress caused by heat generation during operation of the semiconductor device, and reliability of the semiconductor device will be reduced. If an upper surface of the surface protective layer is roughened, an improvement in the adhesion between the surface protective layer and the mold resin can be expected.However, even if roughening is performed by sputtering processing as in Patent Document 1, since a maximum surface roughness of the upper surface of the surface protective layer is small, such as several nanometers to several tens of nanometers, the adhesion between the surface protective layer and the molding resin cannot be sufficiently increased.

[0005] The present disclosure has therefore been made to solve the above problems, and it is an object to provide a semiconductor device capable of increasing adhesion between a surface protective layer and a mold resin. Means to solve the problem

[0006] A semiconductor device according to the present disclosure includes: a semiconductor substrate in which a semiconductor element is formed; a front-side electrode formed on a first main surface of the semiconductor substrate; a back-side electrode formed on a second main surface of the semiconductor substrate; and a surface protective layer formed on the first main surface of the semiconductor substrate to cover the front-side electrode and having an opening portion exposing a portion of the front-side electrode, wherein an upper surface of the surface protective layer is roughened by a cutting groove. Effects of the invention

[0007] According to the present disclosure, a maximum surface roughness of the upper surface of the surface protective layer can be increased. Therefore, when the semiconductor device is sealed using the molding resin, the adhesion between the surface protective layer and the molding resin can be increased, and such a configuration can contribute to an increase in reliability of the semiconductor device.

[0008] These and other objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when taken in conjunction with the accompanying figures. Short description of the characters [ Fig. 1] is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 1. [ Fig. 2] is a cross-sectional view illustrating a configuration of a semiconductor device according to Embodiment 2. [ Fig. 3] is a process diagram illustrating a method of manufacturing a semiconductor device according to Embodiment 3. [ Fig. 4] is a process diagram illustrating the method of manufacturing the semiconductor device according to Embodiment 3. [ Fig. 5] is a process diagram illustrating the method of manufacturing the semiconductor device according to Embodiment 3. [ Fig. 6] is a process diagram illustrating the method of manufacturing the semiconductor device according to Embodiment 3. [ Fig. 7] is a process diagram illustrating the method of manufacturing the semiconductor device according to Embodiment 3. [ Fig. 8] is a process diagram illustrating the method of manufacturing the semiconductor device according to Embodiment 3. Description of the embodiment(s)<Ausführungsform 1>

[0009] Fig. 1 is a cross-sectional view illustrating a configuration of a semiconductor device 1 according to Embodiment 1.

[0010] The semiconductor device 1 comprises a semiconductor substrate 2 in which a semiconductor element is formed. Here, a surface on an upper side of the semiconductor substrate 2 is Fig. 1 is defined as a “first principal surface”, a surface on a lower side thereof is defined as a “second principal surface”.

[0011] A material of the semiconductor substrate 2 can be silicon (Si) and a wide-bandgap semiconductor such as silicon carbide (SiC) and gallium nitride (GaN). When the wide-bandgap semiconductor is used as the material of the semiconductor substrate 2, excellent characteristics are obtained during operation at high voltage, high current, and high temperature, compared to a case of a semiconductor device using silicon. There is no limitation on a type of semiconductor element formed in the semiconductor substrate 2. When the semiconductor device 1 is a semiconductor device for controlling electric power, a power element such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a Schottky diode (SBD), and a PN diode (PND) is formed in the semiconductor substrate 2.

[0012] In the present embodiment, an example is described in which a PN diode is formed as a vertical power element in the semiconductor substrate 2. In this case, as shown in Fig. 1, a P-type anode region 3 is formed on a surface part of the N-type semiconductor substrate 2 on one side of the first main surface, and an N-type region below the anode region 3 serves as a cathode region 4. The anode region 3 contains a P-type impurity (for example, boron (B)) with a high concentration, and the cathode region 4 contains an N-type impurity (for example, phosphorus (P)) with a high concentration.

[0013] A front-side electrode 5 as an anode electrode is formed on the first main surface of the semiconductor substrate 2, and a back-side electrode 6 as a cathode electrode is formed on the second main surface of the semiconductor substrate 2. A surface protective layer 7 made of a thermosetting resin such as polyimide is formed on the first main surface of the semiconductor substrate 2 to cover the front-side electrode 5. An opening portion exposing a part of the front-side electrode 5 is formed in the surface protective layer 7, and, for example, wiring can be connected to the front-side electrode 5 through the opening portion.

[0014] As in Fig. As illustrated in Figure 1, the semiconductor device 1 is sealed with a molding resin 8. For example, an epoxy resin or a polyimide resin is applied to a material of the molding resin 8.

[0015] Here, cutting processing is performed on the upper surface of the surface protective layer 7 using a cutting machine, and the upper surface thereof is roughened by a cutting groove by the cutting processing. The roughening processing by the cutting processing can increase a roughness of the upper surface of the surface protective layer 7 compared to a roughening processing by the sputtering processing disclosed in Patent Document 1 described above. In the present embodiment, a maximum surface roughness of the upper surface of the surface protective layer 7 is adjusted to be equal to or greater than 100 nm. In this way, strong adhesion is obtained between the surface protective layer 7 having such a large maximum surface roughness and the molding resin 8 through an anchor effect.

[0016] Although details are described below, a protective layer corresponding to the surface protective layer 7 is provided to protect the front surface (the first main surface) of the semiconductor substrate 2 during processing of the back surface (the second main surface) of the semiconductor substrate in a conventional semiconductor device, and is removed when shipping a product.

[0017] According to the semiconductor device 1 in Embodiment 1, strong adhesion is obtained between the mold resin 8 and the surface protective layer 7, and accordingly, separation of the mold resin 8 from the surface protective layer 7 caused by stress caused by heat generation in the semiconductor device 1 is avoided, and reliability of the semiconductor device is increased.

[0018] The above effect is particularly effective when the semiconductor substrate 2 is a wide band-gap semiconductor because the semiconductor device 1 is assumed to operate at a high temperature. Since a thermal stress occurring in a case where the semiconductor substrate 2 is formed of silicon carbide is significantly larger than in a case where the semiconductor substrate 2 is formed of silicon as a general semiconductor material, the above effect is significantly effective in the case where the semiconductor substrate 2 is formed of silicon carbide. <Ausführungsform 2>

[0019] Fig. 2 is a cross-sectional view illustrating a configuration of the semiconductor device 1 according to Embodiment 2. As shown in Fig. 2, the surface protective layer 7 is formed of a first protective layer 7a and a second protective layer 7b in Embodiment 2. The other configuration thereof is similar to that of Embodiment 1 ( Fig. 1).

[0020] The first protective layer 7a is an upper layer portion of the surface protective layer 7, and an upper surface thereof is roughened by a cutting groove. The second protective layer 7b is a lower layer portion of the surface protective layer 7, and is sandwiched between the first protective layer 7a and the semiconductor substrate 2. The first protective layer 7a and the second protective layer 7b are formed of a thermosetting resin such as polyimide. However, a respective material of the first protective layer 7a and the second protective layer 7b is selected such that a thermal expansion coefficient of the second protective layer 7b has a value intermediate between a thermal expansion coefficient of the first protective layer 7a and a thermal expansion coefficient of the semiconductor substrate 2.Since a thermal expansion coefficient of silicon or silicon carbide as a material of the semiconductor substrate 2 is, for example, lower than that of polyimide, the thermal expansion coefficient of the first protective layer 7a is set to, for example, 80 ppm / K, and the thermal expansion coefficient of the second protective layer 7b is set to, for example, 50 ppm / K.

[0021] When the thermal expansion coefficient of the surface protective layer 7 and the thermal expansion coefficient of the semiconductor substrate 2 differ significantly from each other, a crack or separation may occur at an interface between the surface protective layer 7 and the semiconductor substrate 2 due to stress caused by heat generation in the semiconductor device 1. In the present embodiment, the second protective layer 7b, which has the thermal expansion coefficient relatively close to the semiconductor substrate 2, is located in a part where the surface protective layer 7 is in contact with the semiconductor substrate 2; therefore, stress occurring between the surface protective layer 7 and the semiconductor substrate 2 can be reduced. <Ausführungsform 3>

[0022] In an embodiment 3, a method for manufacturing the semiconductor device 1 described in embodiments 1 and 2 is described. Fig. 3 to Fig. 8 are process diagrams to explain the manufacturing process thereof.

[0023] First, a semiconductor element (in Fig. 3 to Fig. 8 not shown) is formed like a PN diode in the semiconductor substrate 2, and the front side electrode 5 is formed on the first main surface of the semiconductor substrate 2.

[0024] Next, as in Fig. As illustrated in Figure 3, the surface protective layer 7 covering the front electrode 5 is formed on the first main surface of the semiconductor substrate 2. When the semiconductor device 1 according to Embodiment 2 is formed, the surface protective layer 7 has a double-layered structure of the first protective layer 7a and the second protective layer 7b.

[0025] Subsequently, the upper surface of the surface protective layer 7 is cut by a cutting machine, and it is roughened by a cutting groove, while a large unevenness (an unevenness corresponding to a shape of the front electrode 5) on the upper surface of the surface protective layer 7 is flattened. Heat processing for curing the surface protective layer may be performed after the cutting processing.

[0026] Below, as in Fig. As illustrated in Figure 5, the semiconductor substrate 2 is reversed, while the first main surface of the semiconductor substrate 2 is covered by the surface protection layer 7, and the second main surface of the semiconductor substrate 2 is processed. In this process, for example, the semiconductor substrate 2 is thinned by grinding the second main surface, and an impurity is implanted into the second main surface. As shown in Fig. As illustrated in Figure 6, the backside electrode 6 is formed on the second main surface of the semiconductor substrate 2, while the first main surface of the semiconductor substrate 2 is covered by the surface protection layer 7. In this way, one side of the second main surface of the semiconductor substrate 2 is processed while the first main surface thereof is covered by the surface protection layer 7. Thus, the surface protection layer 7 also has a role of protecting a structure on the first main surface side of the semiconductor substrate 2 during processing of the second main surface side of the semiconductor substrate 2.

[0027] Then, as in Fig. 7, the semiconductor substrate 2 is reversed, and a part of the surface protection layer 7 is removed, thereby forming the opening part which exposes a part of the front electrode 5 in the surface protection layer 7. Subsequently, as shown in Fig. 8, the semiconductor substrate 2 is cut and divided to form a chip of the semiconductor device 1.

[0028] Finally, the semiconductor device 1 is sealed by means of the molding resin 8 to obtain the configuration of the semiconductor device 1, which is shown in Fig. 1 or Fig. 2 is illustrated.

[0029] In the method for manufacturing the semiconductor device 1 according to the present embodiment, the surface protective layer 7 plays a useful role as a protective layer for protecting the structure on the first main surface side of the semiconductor substrate 2 during processing of the second main surface side of the semiconductor substrate 2. Although, as described above, the protective layer corresponding to the surface protective layer 7 in the conventional semiconductor device is removed when shipping the product, the surface protective layer 7 is retained in the semiconductor device 1 after manufacturing in the present embodiment. Thus, costs can be reduced by reducing the number of processes.The upper surface of the surface protection layer 7 is processed by the cutting process using the cutting machine; therefore, the maximum surface roughness of the upper surface of the surface protection layer 7 can be adjusted without adding the further process.

[0030] Each embodiment may be combined as desired, or each embodiment may be varied or omitted as appropriate.

[0031] The foregoing description is illustrative in all aspects, and it is therefore to be understood that numerous modifications not shown by way of example may be devised. List of reference symbols

[0032] 1 semiconductor device, 2 semiconductor substrate, 3 anode region, 4 cathode region, 5 front side electrode, 6 back side electrode, 7 surface protective layer, 7a first protective layer, 7b second protective layer, 8 molding resin. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2007-158113

[0003]

Claims

[1] Semiconductor device comprising: • a semiconductor substrate in which a semiconductor element is formed; • a front side electrode formed on a first main surface of the semiconductor substrate; • a backside electrode formed on a second main surface of the semiconductor substrate; and • a surface protection layer formed on the first main surface of the semiconductor substrate to cover the front electrode and having an opening portion exposing a portion of the front electrode, wherein • an upper surface of the protective surface layer is roughened by a cutting groove. [2] The semiconductor device according to claim 1, wherein a maximum surface roughness of the upper surface of the surface protective layer is equal to or greater than 100 nm. [3] The semiconductor device according to claim 1 or 2, wherein the surface protective layer is formed of a thermosetting resin. [4] A semiconductor device according to any one of claims 1 to 3, wherein • the surface protection layer comprises a first protection layer having an upper surface roughened by the cutting groove and a second protection layer located between the first protection layer and the semiconductor substrate, and • a thermal expansion coefficient of the second protective layer has a value which lies between a thermal expansion coefficient of the first protective layer and a thermal expansion coefficient of the semiconductor substrate. [5] A semiconductor device according to any one of claims 1 to 4, wherein the semiconductor substrate is formed of a wide bandgap semiconductor. [6] A method for manufacturing a semiconductor device comprising: • Forming a semiconductor element in a semiconductor substrate; • Forming a front side electrode on a first main surface of the semiconductor substrate; • Forming a surface protection layer covering the front electrode on the first main surface of the semiconductor substrate; • Cutting an upper surface of the surface protection layer to roughen the upper surface of the surface protection layer by a cutting groove; • Forming a backside electrode on a second main surface of the semiconductor substrate while the first main surface of the semiconductor substrate is covered by the surface protection layer; • Forming an opening part exposing a part of the front side electrode in the surface protection layer after forming the back side electrode; and • Cutting and dividing the semiconductor substrate, thereby forming a chip of a semiconductor device.

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