Semiconductor device and power conversion device

Abstract

The purpose of the present invention is to provide a semiconductor device in an RC-IGBT that can suppress a snapback phenomenon when the IGBT is switched on and hole injection from the IGBT region to a diode region when the diode is conducting, using a simple structure. The semiconductor device, which has an IGBT region 21 and a diode region 22 within the same chip, is characterized in that the gate resistance R of the IGBT near the boundary of the IGBT region 21 and the diode region 22 is larger than the gate resistance of the IGBT near the center of the IGBT region 21.

Description

Technical area

[0001] The present invention relates to a semiconductor device and a power conversion device. State of the art

[0002] In a reverse-conducting insulated-gate bipolar transistor (RC-IGBT), which is obtained by integrating an insulated-gate bipolar transistor (IGBT) and a diode within the same chip, a termination region can be shared between the IGBT and the diode, thus making it possible to reduce the chip size. Furthermore, since the IGBT and the diode operate at different timings, heat due to loss generated in one of the IGBT regions or the diode regions is distributed to the other, allowing heat to be dissipated throughout the chip, thus making it possible to reduce thermal resistance.

[0003] On the other hand, in the RC-IGBT, when the IGBT is turned on, electrons implanted from the front surface side of the IGBT, especially near a boundary portion with the diode, do not escape from a p-layer which is a collector layer on the back surface side of the IGBT, but escape to an n+ layer which is a cathode layer of the diode, and thus there is a problem that hole implantation from the p-layer on the back surface does not occur unless a voltage equal to or greater than a built-in voltage of a pn junction on the back surface side is applied, that is, a snapback phenomenon occurs when the IGBT is turned on.

[0004] Furthermore, in the RC-IGBT, when the IGBT is off, the potential of a front surface electrode is higher than the potential of a back surface electrode, and the diode is conductive, hole implantation occurs from the p-type layer, which is a body layer on the front surface side of the IGBT, into the diode region, particularly near the boundary portion with the diode. The concentration of holes in a drift layer increases near the boundary portion between the diode region and the IGBT region. After that, when the potential of the front surface electrode becomes lower than the potential of the back surface electrode and the diode performs a recovery operation, the holes in the drift layer flow toward the front surface electrode, causing a recovery current to flow.However, since the concentration of holes is high near the boundary portion between the diode region and the IGBT region, there is a problem that the recovery current flows at a high density near the boundary portion and a high load is applied to a semiconductor substrate, that is, hole implantation occurs from the IGBT region to the diode region when the diode is conductive.

[0005] Here, Patent Literature 1 describes a semiconductor device in which a semiconductor substrate includes an IGBT region overlapping a collector region, a diode region overlapping a cathode region, a drift region distributed from the IGBT region to the diode region, a body region, a body contact region, and an emitter region disposed in the IGBT region, and an anode region and an anode contact region disposed in the diode region, wherein the body region includes a first body region and a second body region having a lower p-type impurity concentration than the first body region and the anode region, the second body region is adjacent to the anode region, and the first body region is adjacent to the second body region on a side opposite to the anode region (abstract, Fig. 2).

[0006] According to the semiconductor device of Patent Literature 1, since the p-type impurity concentration in the second body region adjacent to the anode region is low, when the diode is turned on, few holes flow from the second body region toward the cathode region, and the hole concentration in the drift region near the boundary between the diode region and the IGBT region is not so high. This prevents a high recovery current from flowing near the boundary between the diode region and the IGBT region during a recovery operation, thereby reducing the load on the semiconductor substrate (paragraph 0007).

[0007] Thus, Patent Literature 1 describes a structure for solving the problem that hole implantation occurs from the IGBT region to the diode region when the diode is conducting. Furthermore, although Patent Literature 1 does not mention the problem of the snapback phenomenon that occurs when the IGBT is turned on, it is believed that this problem can be solved by the structure of Patent Literature 1. Citation listPatent literature

[0008] Patent literature 1: JP 2019 - 106 430 A Summary of the inventionTechnical problem

[0009] However, in Patent Literature 1, in order to make the p-type impurity concentration in the body region of the IGBT near the boundary portion (the second body region of the IGBT adjacent to the anode region) lower than that in the body region of the IGBT near the center portion (the first body region of the IGBT), a new photolithography process or a new implantation process is required, which poses a problem of increased manufacturing cost.

[0010] Therefore, an object of the invention is to provide a semiconductor device as an RC-IGBT by which a snapback phenomenon that occurs when an IGBT is turned on and a hole implantation from an IGBT region to a diode region that occurs when a diode is conductive can be suppressed with a simple structure and a power conversion device. Solution to the problem

[0011] To achieve this object, a semiconductor device of the present invention is, for example, a semiconductor device having an IGBT region and a diode region in the same chip, wherein a gate resistance of an IGBT near a boundary portion between the IGBT region and the diode region is larger than a gate resistance of an IGBT near a center portion of the IGBT region.

[0012] Furthermore, a power conversion device of the present invention includes, for example, the above-described semiconductor device as a switching element. Advantageous effects of the invention

[0013] According to the present invention, due to a simple structure in which the gate resistance of the IGBT near the boundary portion is made larger than that near the middle portion, when the IGBT is turned on, the IGBT near the middle portion, which is away from the vicinity of the boundary portion, is turned on before the IGBT near the boundary portion.As a result, a path through which the electrons flow from the IGBT near the center portion near the front surface of the pn junction portion on the back surface side to reach the cathode layer of the diode becomes longer, and thus a voltage drop occurs while the electrons flow over this length, resulting in a forward bias, and when the voltage exceeds the built-in voltage, hole implantation from the collector layer on the back surface side starts, and thus the snapback phenomenon that occurs when the IGBT is turned on can be suppressed.

[0014] Moreover, due to a simple structure in which the gate resistance of the IGBT near the boundary portion is made larger than that near the middle portion, when the IGBT is turned off, the IGBT near the middle portion, which is far from the boundary portion, is turned off before the IGBT near the boundary portion. The IGBT near the middle portion, which is turned off first, is far from the boundary portion, and thus the amount of hole implantation therefrom is small. In the IGBT near the boundary portion, which is turned off later, a time for hole implantation to occur is short, and thus the amount of hole implantation therefrom can be reduced.As a result, the hole implantation from the IGBT region to the diode region, which occurs when the diode is conductive, can be suppressed compared to the case where the IGBTs are turned off simultaneously. Short description of the drawings [ Fig. 1] Fig. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device of Example 1. [ Fig. 2] Fig. 2 is a plan view illustrating a form of gate wiring of the semiconductor device of Example 1. [ Fig. 3] Fig. 3 is a plan view illustrating a form of gate wiring of a semiconductor device of Example 2. [ Fig. 4] Fig. Figure 4 shows a current-voltage characteristic curve illustrating a snapback phenomenon in an RC-IGBT. Description of embodiments

[0015] Examples of the present invention will be described below with reference to the drawings. In each drawing and example, the same or similar components are denoted by the same reference numerals, and overlapping descriptions are omitted. Example 1

[0016] Fig. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device of Example 1.

[0017] A semiconductor device 100 of Example 1 is an RC-IGBT and includes an IGBT region 21 and a diode region 22 in the same chip (on the same semiconductor substrate).

[0018] An IGBT is formed in the IGBT region 21, and the IGBT includes, for example, a drift layer 1 of a first conductivity type (an n-type in Fig. 1), a trench 3, a gate electrode 5 provided in the trench 3, a body layer 2 of a second conductivity type (a p-type in Fig. 1) provided adjacent to the trench 3 on a front surface side relative to the drift layer 1, an emitter layer 7 of a first conductivity type provided on a front surface side of the body layer 2, and a collector layer 11 of a second conductivity type provided on a back surface side relative to the drift layer 1.

[0019] In Fig. 1, a description will be given using an example in which the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, electrons and holes are reversed.

[0020] A diode is formed in the diode region 22, the diode comprising, for example, the drift layer 1, the body layer 2 serving as an anode layer of a second conductivity type provided on a front surface side relative to the drift layer 1, and a cathode layer 12 of a first conductivity type provided on a back surface side relative to the drift layer 1.

[0021] Furthermore, the semiconductor device 100 includes a buffer layer 10 of a first conductivity type formed between the collector layer 11 or the cathode layer 12 and the drift layer 1, a front surface electrode 13, an interlayer insulating film 9 provided between the emitter layer 7 or the body layer 2 and the front surface electrode 13, and a back surface electrode 14 common to the IGBT region 21 and the diode region 22.

[0022] The front surface electrode 13 is connected to the body layer 2 via a contact hole and a body contact layer 8 of a second conductivity type in the IGBT region 21 and the diode region 22. Therefore, the potential of the front surface electrode 13 is at an emitter potential E and an anode potential A.

[0023] The gate electrode 5 is adjacent to the body layer 2 and the emitter layer 7 via an insulating film 4 formed in the trench 3. A gate potential G is supplied to the gate electrode 5 from a gate drive circuit (not shown) or the like.

[0024] The diode region 22 also includes a trench 3, and an insulating film 4 and a dummy electrode 6 are provided in the trench 3 of the diode region 22. The dummy electrode 6 is supplied with an emitter potential E, for example, but the present invention is not limited thereto, and the dummy electrode 6 may be supplied with another potential, such as a gate potential.

[0025] The impurity concentration of each layer is as follows. For example, the impurity concentration of drift layer 1 is a low concentration of n-type, the impurity concentration of emitter layer 7 is a high concentration of n+ type, and the impurity concentration of cathode layer 12 is a high concentration of n+ type.

[0026] Here, in the semiconductor device 100 of Example 1, a gate resistance R of an IGBT near a boundary portion between the IGBT region 21 and the diode region 22 is larger than a gate resistance of an IGBT near a center portion of the IGBT region 21.

[0027] With such a simple structure, a timing at which the IGBT near the boundary portion is turned on is later than a timing at which the IGBT near the middle portion is turned on, thereby making it possible to suppress a snapback phenomenon that occurs when the IGBT is turned on, as described below, and a timing at which the IGBT near the boundary portion is turned off is later than a timing at which the IGBT near the middle portion is turned off, thereby making it possible to suppress hole implantation from the IGBT region to the diode region that occurs when the diode is conductive, as described below.

[0028] Fig. Figure 4 shows a current-voltage characteristic curve illustrating the snapback phenomenon in an RC-IGBT.

[0029] In Fig. 4, the horizontal axis represents a voltage V and the vertical axis represents a current I. In Fig. 4, a characteristic curve 31 without snapback is shown by a dashed line and a characteristic curve 32 with snapback is shown by a solid line.

[0030] In the IGBT, as shown in the characteristic curve 31 without snapback, hole implantation normally starts when the voltage of a pn junction portion on the back surface side (the collector layer 11 of a p-type and the buffer layer 10 of an n-type in Fig. 1) becomes greater than or equal to a built-in voltage, and the IGBT starts a process, and thus the current I increases in a curved line with respect to the voltage V.

[0031] However, in the RC-IGBT, when the IGBT is turned on, initially the voltage of the pn junction portion on the back surface side is lower than the built-in voltage, and therefore, near the boundary portion between the IGBT region 21 and the diode region 22, electrons 15 implanted from the body layer 2 on the front surface side of the IGBT do not escape from the p-layer, which is the collector layer 11 on the back surface side of the IGBT, but escape to the n+ layer, which is the cathode layer 12 of the diode, and as shown by the characteristic curve 32 with snapback, an MOS operation is initially performed in which the current I increases linearly with respect to the voltage V. The reason is that the structure in which the n+ layer is used instead of the p-layer on the back surface of the IGBT is the same as the structure of a metal-oxide-semiconductor field-effect transistor (MOSFET).After that, the IGBT begins to operate when the voltage applied to the pn junction portion on the back surface side increases and exceeds the built-in voltage. At this time, the characteristic curve returns to the same as the non-snapback characteristic curve 31, and thus the voltage V temporarily decreases, as shown by the snapback characteristic curve 32. This phenomenon is called the snapback phenomenon. When the snapback phenomenon occurs, the voltage during the MOS operation becomes higher than the waveform during the normal IGBT operation, resulting in a correspondingly larger loss.

[0032] In contrast, in the semiconductor device 100 of Example 1, due to a simple structure in which the gate resistance R of the IGBT near the boundary portion is made larger than that near the middle portion, when the IGBT is turned on, the IGBT near the middle portion, which is away from the boundary portion, is turned on before the IGBT near the boundary portion. As a result, as shown in Fig. 1, a path through which the electrons 15 flow from the IGBT near the center portion near the front surface of the pn junction portion on the back surface side to reach the cathode layer 12 of the diode is longer, and thus a voltage drop occurs while the electrons 15 flow over this length, resulting in a forward bias, and when the voltage exceeds the built-in voltage, hole implantation from the collector layer 11 on the back surface side starts, and thus the snapback phenomenon that occurs when the IGBT is turned on can be suppressed.

[0033] Furthermore, in the semiconductor device 100 of Example 1, due to a simple structure in which the gate resistance R of the IGBT near the boundary portion is made larger than that near the middle portion, when the IGBT is turned off, the IGBT near the middle portion, which is far from the vicinity of the boundary portion, is turned off before the IGBT near the boundary portion. The IGBT near the middle portion, which is turned off first, is far from the vicinity of the boundary portion, and thus the amount of hole implantation therefrom is small. In the IGBT near the boundary portion, which is turned off later, a time for hole implantation to occur is short, and thus the amount of hole implantation therefrom can be reduced.As a result, the hole implantation from the IGBT region 21 into the diode region 22, which occurs when the diode is conductive, can be suppressed compared to the case where the IGBTs are turned off simultaneously.

[0034] Next, a method is described to make the gate resistance R of the IGBT near the boundary portion larger than that near the middle portion in Example 1.

[0035] Fig. 2 is a plan view illustrating a form of gate wiring of the semiconductor device of Example 1.

[0036] As in Fig. As shown in Figure 2, the gate wiring of the semiconductor device 100 of Example 1 includes a common gate wiring 16, also referred to as a gate finger, and a gate lead-out wiring 17 connecting the common gate wiring 16 and each gate electrode 5. A gate potential G is supplied to the gate electrode 5 via the gate wiring. Furthermore, the dummy electrodes 6 of the diode region 22 are connected to each other by a dummy wiring 18, and an emitter potential E is supplied to them.

[0037] The gate lead-out wiring 17 of the IGBT near the boundary section is thinner than the gate lead-out wiring 17 of the IGBT near the middle section. This makes it possible to make the gate resistance R of the IGBT near the boundary section larger than that near the middle section.

[0038] Here, it is desirable that the gate lead-out wiring 17 gradually becomes thicker from the vicinity of the boundary portion toward the vicinity of the center portion. Fig. 2 shows an example in which the width of the gate lead-out wiring 17 becomes wider from the vicinity of the boundary portion toward the vicinity of the center portion, that is, Wc < Wb < Wa.

[0039] This makes it possible to achieve the effects of Example 1 more effectively.

[0040] In addition, since this can be achieved simply by changing the shape of the gate wiring, only the shape of a mask for patterning the gate wiring can be changed during manufacturing, and a new photolithography process or a new implantation process is not required, so there is no increase in manufacturing cost. Example 2

[0041] Fig. 3 is a plan view illustrating a form of gate wiring of a semiconductor device of Example 2.

[0042] Example 2 is a modified example of Example 1 and differs from Example 1 in that the gate lead-out wiring 17 is integrally formed by interconnecting the gate lead-out wirings 17 provided for the gate electrodes 5 adjacent to each other near the center portion. In this case, the width of the gate lead-out wiring 17 corresponding to each gate electrode 5 can be considered as Wa, as shown in Fig.3, since the midpoint between the adjacent gate electrodes 5 is considered as a virtual boundary between the gate lead-out wirings 17. As a result, it is possible to reduce the gate resistance of the IGBT near the center portion compared to Example 1. Other than that, this example is the same as Example 1, and thus the overlapping description is omitted. Example 3

[0043] Example 3 is an example of a power conversion device in which the semiconductor device of Example 1 or Example 2 is used as a switching element. The configuration of the power conversion device is the same as a general configuration, and thus, its detailed description is omitted.

[0044] Although the examples of the present invention have been described above, the present invention is not limited to the configurations described in the examples, and various modifications are possible within the scope of the technical concept of the present invention. Furthermore, some or all of the configurations described in each example can be combined and applied. List of reference symbols 1 drift layer 2 body layer 3 ditch 4 Insulating film 5 Gate electrode 6 Dummy electrode 7 Emitter layer 8 Body contact layer 9 Interlayer insulating film 10 Buffer layer 11 Collector layer 12 Cathode layer 13 Front surface electrode 14 Back surface electrode 15 electrons 16 common gate wiring 17 Gate lead-out wiring 18 Dummy wiring 21 IGBT area 22 diode area 31 characteristic curve without snapback 32 characteristic curve with snapback 100 semiconductor devices G Gate potential E emitter potential A anode potential R resistance I Current V voltage QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2019 - 106 430 A

[0008]

Claims

[1] A semiconductor device comprising an IGBT region and a diode region in the same chip, wherein a gate resistance of an IGBT near a boundary portion between the IGBT region and the diode region is larger than a gate resistance of an IGBT near a center portion of the IGBT region. [2] The semiconductor device according to claim 1, wherein a timing at which the IGBT near the boundary portion is turned on is later than a timing at which the IGBT near the center portion is turned on. [3] The semiconductor device according to claim 1, wherein a timing at which the IGBT near the boundary portion is turned off is later than a timing at which the IGBT near the center portion is turned off. [4] The semiconductor device according to claim 1, wherein a gate lead-out wiring of the IGBT near the boundary portion is thinner than a gate lead-out wiring of the IGBT near the center portion. [5] A semiconductor device according to claim 4, wherein the gate lead-out wiring gradually becomes thicker from the vicinity of the boundary portion toward the vicinity of the center portion. [6] A semiconductor device according to claim 1, wherein the IGBT comprises a drift layer of a first conductivity type, a trench, a gate electrode provided in the trench, a body layer of a second conductivity type provided adjacent to the trench on a front surface side relative to the drift layer, an emitter layer of a first conductivity type provided on a front surface side of the body layer, and a collector layer of a second conductivity type provided on a back surface side relative to the drift layer, and wherein a diode in the diode region comprises the drift layer, the body layer serving as an anode layer of a second conductivity type provided on a front surface side relative to the drift layer, and a cathode layer of a first conductivity type provided on a back surface side relative to the drift layer. [7] A power conversion device comprising the semiconductor device according to any one of claims 1 to 6 as a switching element.

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