WAFER STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

Abstract

The wafer structure includes a wafer having a first surface on one side and a second surface on the other side, a first electrode covering the first surface, a second electrode covering an inner section of the second surface such that a circumferential edge section of the second surface is exposed, and a protective tape having the properties that adhesion to the circumferential edge section of the second surface is higher than adhesion to the second electrode, and which is bonded to the circumferential edge section of the second surface and the second electrode.

Description

Technical area

[0001] This application claims priority based on Japanese Patent Application No. 2022-095664, filed with the Japan Patent Office on June 14, 2022, the entire disclosure of which is incorporated herein by reference. The present disclosure relates to a wafer structure and a manufacturing method for semiconductor devices. State of the art

[0002] Patent Literature 1 discloses a manufacturing method for a semiconductor device, including a step of forming a first electrode on a first main surface of a semiconductor wafer, a step of forming a second electrode covering an entire area of ​​a second main surface of the semiconductor wafer, a step of adhering a first tape to an entire area of ​​the second main surface so as to cover the entire area of ​​the second electrode, a step of adhering a second tape to an entire end of the semiconductor wafer so as to overlap the first tape, and a step of forming a plating layer on the first electrode in a state where the first tape and the second tape are adhered. List of citationsPatent literature

[0003] Patent Literature 1: US Patent Application Publication No. 2022-0020628 Brief description of the inventionTechnical problem

[0004] An embodiment provides a wafer structure contributing to the fabrication of a semiconductor device with high reliability and a fabrication method for the semiconductor device. Solution to the problem

[0005] One embodiment provides a wafer structure including a wafer having a first surface on one side and a second surface on the other side, a first electrode covering the first surface, a second electrode covering an inner portion of the second surface such that a peripheral edge portion of the second surface is exposed, and a protective tape having properties such that adhesion to the peripheral edge portion of the second surface is higher than adhesion to the second electrode, and being adhered to the peripheral edge portion of the second surface and the second electrode.

[0006] One embodiment provides a manufacturing method for a semiconductor device, including a step of preparing a wafer structure including a wafer having a first surface on one side and a second surface on the other side and a first electrode covering the first surface, a step of forming a second electrode covering an inner portion of the second surface so as to expose a peripheral edge portion of the second surface, and a step of adhering a protective tape having properties that adhesion to the peripheral edge portion of the second surface is higher than adhesion to the second electrode, to the peripheral edge portion of the second surface and to the second electrode.

[0007] The above and other objects, features and advantages of the present invention will become apparent from the embodiments described with reference to the accompanying drawings. Short description of the drawings [ Fig. 1] Fig. 1 is a plan view in which a wafer structure according to a first embodiment is viewed from a first main surface side. [ Fig. 2] Fig. 2 is a cross-sectional view along a Fig. Line II-II shown in Figure 1. [ Fig. 3] Fig. 3 is a schematic cross-sectional view of the Fig. 1 shown wafer structure. [ Fig. 4] Fig. 4 is a plan view showing the Fig. 1 shown wafer structure is viewed from the side of a second main surface. [ Fig. 5] Fig. 5 is a plan view showing a layout example of a Fig. 3 shows the second electrode. [ Fig. 6] Fig. 6 is an enlarged cross-sectional view showing a peripheral edge portion of the Fig. 1 together with a second electrode according to a first configuration example. [ Fig. 7A] Fig. 7A is an enlarged cross-sectional view showing the peripheral edge portion of the Fig. 1 together with a second electrode according to a second configuration example. [ Fig. 7B] Fig. 7B is an enlarged cross-sectional view showing the peripheral edge portion of the Fig. 1 together with a second electrode according to a third configuration example. [ Fig. 8A] Fig. 8A is a cross-sectional view showing a manufacturing method for a semiconductor device according to the Fig. 1 shows the wafer structure. [ Fig. 8B] Fig. 8B is a cross-sectional view showing a step after the step of Fig. 8A shows. [ Fig. 8C] Fig. Figure 8C is a cross-sectional view showing one step after the step of Fig. 8B shows. [ Fig. 8D] Fig. 8D is a cross-sectional view showing one step after the step of Fig. 8C shows. [ Fig. 8E] Fig. Figure 8E is a cross-sectional view taken one step after the step of Fig. 8D shows. [ Fig. 8F] Fig. Figure 8F is a cross-sectional view taken one step after the step of Fig. 8E shows. [ Fig. 8G] Fig. 8G is a cross-sectional view showing one step after the step of Fig. 8F shows. [ Fig. 9A] Fig. 9A is a cross-sectional view showing a step of forming the second electrode. [ Fig. 9B] Fig. 9B is a cross-sectional view showing a step after the step of Fig. 9A shows. [ Fig. 9C] Fig. Figure 9C is a cross-sectional view showing one step after the step of Fig. 9B shows. [ Fig. 10] Fig. 10 is a plan view in which a wafer structure according to a second embodiment is viewed from a first main surface side. [ Fig. 11] Fig. 11 is a cross-sectional view along a Fig. Line XI-XI shown in Figure 10. [ Fig. 12] Fig. 12 is an enlarged cross-sectional view showing a main portion of a Fig. 11 shows the functional device shown. [ Fig. 13] Fig. 13 is a schematic cross-sectional view of the Fig. 10 shown wafer structure. [ Fig. 14A] Fig. 14A is a cross-sectional view showing a manufacturing method for a semiconductor device according to the Fig. 10 shows the wafer structure. [ Fig. 14B] Fig. 14B is a cross-sectional view taken one step after the step of Fig. 14A shows. [ Fig. 14C] Fig. 14C is a cross-sectional view taken one step after the step of Fig. 14B shows. [ Fig. 14D] Fig. 14D is a cross-sectional view taken one step after the step of Fig. 14C shows. [ Fig. 14E] Fig. 14E is a cross-sectional view taken one step after the step of Fig. 14D shows. [ Fig. 14F] Fig. 14F is a cross-sectional view taken one step after the step of Fig. 14E shows. [ Fig. 14G] Fig. 14G is a cross-sectional view taken one step after the step of Fig. 14F shows. [ Fig. 15] Fig. 15 is a plan view showing a wafer according to a modified example. [ Fig. 16] Fig. 16 is a schematic cross-sectional view showing a step of forming a second electrode according to a first modified example. [ Fig. 17] Fig. 17 is a schematic cross-sectional view showing a step of forming a second electrode according to a second modified example. [ Fig. 18] Fig. 18 is a schematic cross-sectional view showing a step of forming a second electrode according to a third modified example. Description of embodiments

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic views and are not shown precisely, and are not necessarily consistent in scale and the like. In addition, the same reference numeral is assigned to a structure corresponding to each structure in the accompanying drawings, and duplicate descriptions of that structure are omitted or simplified. A description of a structure that has not yet been omitted or simplified will be applied to a corresponding structure whose description has been omitted or simplified. In the embodiments, phrases such as "first," "second," "third," etc. are used, and these are symbols given to a name of each structure to clarify a description order, not to limit the name of each structure.

[0009] Fig. 1 is a plan view in which a wafer structure 1A according to the first embodiment is viewed from the side of a first main surface 3. Fig. 2 is a cross-sectional view along the Fig. Line II-II shown in Figure 1. Fig. 3 is a schematic cross-sectional view of the Fig. 1 shown wafer structure 1A. Fig. 4 is a plan view showing the Fig. 1 shown wafer structure 1A is viewed from the side of a second main surface 4. Fig. 5 is a plan view showing a layout example of a Fig. 3 shows the second electrode 24.

[0010] Fig. 6 is an enlarged cross-sectional view showing a peripheral edge portion of the Fig. 1 together with the second electrode 24 according to the first configuration example. Fig. 7A is an enlarged cross-sectional view showing the peripheral edge portion of the Fig. 1 together with the second electrode 24 according to the second configuration example. Fig. 7B is an enlarged cross-sectional view showing the peripheral edge portion of the Fig. 1 together with the second electrode 24 according to the third configuration example.

[0011] With reference to the Fig. 1 to 6, the wafer structure 1A includes a wafer 2. In this embodiment, the wafer 2 is formed in the shape of a flat disk. Of course, the wafer 2 may also be formed in the shape of a flat, rectangular parallelepiped. In this embodiment, the wafer 2 is made of a semiconductor single crystal whose plating reaction rate is slower than a plating reaction rate of a Si single crystal (silicon single crystal). That is, the wafer 2 is made of a semiconductor single crystal whose oxidation / reduction reaction rate is slower than that of the Si single crystal. More preferably, the wafer 2 is made of the semiconductor single crystal whose Ni plating reaction rate is slower than a Ni plating reaction rate of the Si single crystal.

[0012] Most preferably, wafer 2 is made of a high-hardness semiconductor single crystal whose hardness is higher than that of the Si single crystal. Wafer 2 is preferably made of a wide-bandgap semiconductor wafer including a wide-bandgap semiconductor single crystal. That is, wafer structure 1A is preferably a wide-bandgap semiconductor wafer structure. The wide-bandgap semiconductor is a semiconductor whose bandgap is larger than that of Si.

[0013] In this embodiment, wafer 2 is made of a SiC wafer including a hexagonal SiC single crystal (silicon carbide single crystal) as an example of a wide band gap semiconductor. That is, wafer structure 1A is a SiC wafer structure. The hexagonal SiC single crystal has a variety of polytypes, including 2H (hexagonal) SiC single crystal, 4H SiC single crystal, 6H SiC single crystal, and so on. Although an example in which wafer 2 includes a 4H SiC single crystal is shown in this embodiment, wafer 2 may include a SiC single crystal made of other polytypes.

[0014] The wafer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and a side surface 5 connecting the first main surface 3 and the second main surface 4. Hereinafter, a direction along the first main surface 3 is referred to as a first direction X, a direction perpendicular to the first direction X along the first main surface 3 is referred to as a second direction Y, and a direction vertically intersecting the first main surface 3 is referred to as a vertical direction Z. The first direction X may be an m-axis direction of the SiC single crystal, and the second direction Y may be an a-axis direction of the SiC single crystal. The first direction X may be an a-axis direction of the SiC single crystal, and the second direction Y may be an m-axis direction of the SiC single crystal.

[0015] The first main surface 3 and the second main surface 4 face a c-plane of the SiC single crystal. Preferably, the first main surface 3 faces a silicon plane of the SiC single crystal, and the second main surface 4 faces a carbon plane of the SiC single crystal. The first main surface 3 is a device-forming surface, and the second main surface 4 is a non-device-forming surface. The second main surface 4 is formed as a flat surface extending horizontally from an inner portion to a peripheral edge portion and having no step at the peripheral edge portion. In this embodiment, the second main surface 4 is formed from a ground surface having a plurality of grinding marks hollowed toward the first main surface 3. A thickness of the grinding mark is preferably not more than 0.5 μm.Particularly preferably, the thickness of the grinding track is not more than 0.1 µm.

[0016] The first main surface 3 and the second main surface 4 may have an off-angle that is inclined at a predetermined angle in a predetermined off-angle direction with respect to the c-plane. That is, a c-axis of the SiC single crystal may be inclined with respect to the vertical direction Z only by the off-angle. The off-angle direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may exceed 0° and be no greater than 10°. The off-angle is preferably no greater than 5°. More preferably, the off-angle is no less than 2° and no more than 4.5°.

[0017] The wafer 2 has a mark 6 representing a crystal orientation of the SiC single crystal in the side surface 5. In this embodiment, the mark 6 includes an alignment flat that has been linearly cut out in a plan view from the vertical direction Z (hereinafter referred to simply as "plan view"). In this embodiment, the alignment flat extends in the second direction Y.

[0018] The alignment flat does not necessarily have to extend in the second direction Y and may extend in the first direction X. Of course, the mark 6 may include a first alignment flat extending in the first direction X and a first alignment flat extending in the second direction Y.

[0019] The wafer 2 may have a diameter of not less than 50 mm and not more than 300 mm (i.e., not less than 2 inches and not more than 12 inches) in plan view. The diameter of the wafer 2 is defined by a length of a chord passing through the center of the wafer 2 outside the mark 6.

[0020] The wafer 2 is preferably made of a thin wafer with a thickness of not less than 30 µm and not more than 200 µm. The thickness of the wafer 2 may optionally be not less than 30 µm and not more than 50 µm, not less than 50 µm and not more than 75 µm, not less than 75 µm and not more than 100 µm, not less than 100 µm and not more than 125 µm, not less than 125 µm and not more than 150 µm, not less than 150 µm and not more than 175 µm, or not less than 175 µm and not more than 200 µm. The thickness of the wafer 2 is preferably not more than 160 µm.

[0021] In this embodiment, the wafer structure 1A includes an n-type first region 7 (first semiconductor region) formed in a region (surface layer portion) on the first main surface 3 side within the wafer 2. The first region 7 is formed in a layered shape extending along the first main surface 3 and exposed from the first main surface 3 and the side surface 5. In this embodiment, the first region 7 is made of an epitaxial layer (SiC epitaxial layer). The second region 7 may have a thickness of not less than 1 μm and not more than 50 μm. The thickness of the first region 7 is preferably not less than 5 μm and not more than 30 μm. More preferably, the thickness of the first region 7 is not more than 25 μm.

[0022] In this embodiment, the wafer structure 1A includes an n-type second region 8 (second semiconductor region) formed in a region (surface layer portion) on the second main surface 4 side within the wafer 2. The second region 8 has a higher n-type impurity concentration than the first region 7 and is electrically connected to the first region 7 within the wafer 2. The second region 8 is formed in a layered shape extending along the second main surface 4 and exposed from the second main surface 4 and the side surface 5. In this embodiment, the second region 8 is made of a semiconductor substrate (SiC substrate). That is, the wafer 2 has a laminated structure including the substrate and the epitaxial layer.

[0023] The second region 8 may have a thickness of not less than 1 µm and less than 200 µm. The thickness of the second region 8 is preferably less than 160 µm. The thickness of the second region 8 is preferably not less than 10 µm. The thickness of the second region 8 may exceed the thickness of the first region 7. The thickness of the second region 8 may be less than the thickness of the first region 7.

[0024] The wafer structure 1A includes a plurality of device regions 10 provided in the first main surface 3. Each of the device regions 10 is a region corresponding to a semiconductor device (wide bandgap semiconductor device / SiC semiconductor device). The plurality of device regions 10 are each arranged in a quadrangular shape in plan view. In this embodiment, the plurality of device regions 10 are arrayed in a matrix-like manner along the first X direction and the second Y direction in plan view.

[0025] The plurality of device regions 10 are each arranged in an array-like manner in plan view, starting from a peripheral edge portion of the first main surface 3 at a distance inward, and delimit a space 11 in which the plurality of device regions 10 are not present in the peripheral edge portion of the first main surface 3. That is, the wafer 2 has an inner portion with the plurality of device regions 10 and a peripheral edge portion without the device regions 10. The space 11 is formed in a ring-shaped form in plan view, which surrounds the plurality of device regions 10. The space 11 has a portion that extends in a circular arc shape in a region outside the mark 6 and a portion that extends rectilinearly in a region along the mark 6.

[0026] A length of one side of each of the device regions 10 may optionally be not less than 0.5 mm and not more than 20 mm. The length of one side of each device region 10 is preferably not less than 1 mm. The length of one side of each device region 10 is particularly preferably not less than 2 mm. In this embodiment, the length of one side of each device region 10 is set in a range of not less than 4 mm and not more than 6 mm.

[0027] The wafer structure 1A includes a plurality of predetermined cut lines 12 provided in the first main surface 3. The plurality of predetermined cut lines 12 are arranged in a lattice pattern extending along the first direction X and the second direction Y, so as to define the plurality of device regions 10.

[0028] The wafer structure 1A also includes a functional device 13 formed in each of the device regions 10 in the first main surface 3. Each functional device 13 is formed at a distance inward from a peripheral edge of each of the device regions 10. The functional device 13 may include at least one of a switching device, a rectifying device, and a passive device.

[0029] The switching device may include at least one of a MISFET (metal-insulator-semiconductor field-effect transistor), a BJT (bipolar transistor), an IGBT (insulated-gate bipolar transistor), and a JFET (junction field-effect transistor). The rectification device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, an SBD (Schottky barrier diode), and an FRD (fast recovery diode). The passive device may include at least one of a resistor, a capacitor, and an inductor.

[0030] Each of the functional devices 13 may include a circuit network (e.g., an integrated circuit such as an LSI) in which at least two of the switching device, the rectifying device, and the passive device are combined. In this embodiment, each of the functional devices 13 includes the SBD. Configurations of the plurality of device regions 10 (functional devices 13) are the same, and therefore, the configuration of the single device region 10 (functional device 13) will be described below.

[0031] Referring to Fig. 5, the wafer structure 1A includes an n-type diode region 14 formed in a surface layer portion of the first main surface 3 in the device region 10. In this embodiment, the diode region 14 is formed by using the first region 7. The diode region 14 is formed at a distance inward from the peripheral edge of the device region 10. The diode region 14 is formed in a polygonal shape (a quadrangular shape in this embodiment) in plan view.

[0032] The wafer structure 1A includes a p-type protection region 15 (second conductivity type protection region) formed in the surface layer portion of the first main surface 3 in the device region 10. The protection region 15 is formed in a surface layer portion of the first region 7 at a distance inward from the peripheral edge of the device region 10. The protection region 15 is formed in a polygonal annular shape (a quadrangular annular shape in this embodiment) in plan view, surrounding the diode region 14. The protection region 15 has an inner edge portion on the inner portion side of the device region 10 and an outer edge portion on the peripheral edge side of the device region 10.

[0033] The wafer structure 1A includes a main surface insulating film 16 that selectively covers the first main surface 3 in the device region 10. The main surface insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the main surface insulating film 16 has a single-layer structure including a silicon oxide film. The main surface insulating film 16 has a contact opening 17 that exposes the diode region 14 and the inner edge portion of the protection region 15.

[0034] The main surface insulating film 16 covers an inner portion of the device region 10 at a distance inward from the peripheral edge of the device region 10 and exposes the first main surface 3 (first region 7) from the peripheral edge portion of the device region 10. That is, the main surface insulating film 16 exposes a boundary portion (the plurality of target cutting lines 12) of the plurality of device regions 10. Of course, the main surface insulating film 16 may cover the boundary portion (the plurality of target cutting lines 12) of the plurality of device regions 10.

[0035] The wafer structure 1A includes a first electrode 18 covering the first main surface 3 in the device region 10. In this embodiment, the first electrode 18 is formed as an anode electrode. The first electrode 18 is arranged at a distance inward from the peripheral edge of the device region 10. The first electrode 18 is formed in a polygonal shape (a quadrangular shape in this embodiment) along the peripheral edge of the device region 10 in plan view. The first electrode 18 enters the contact opening 17 from above the main surface insulating film 16 and is electrically connected to inner edge portions of the diode region 14 and the protection region 15. In particular, the first electrode 18 forms a Schottky junction with the diode region 14.

[0036] The first electrode 18 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the first main surface 3 side. The Ti-based metal film may include at least one of a Ti film and a Ti alloy film. The Al-based metal film is preferably thicker than the Ti-based metal film. The Al-based metal film includes at least one of an Al film and an Al alloy film. For example, the Al-based metal film may include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0037] The wafer structure 1A includes an insulating film 19 covering the first electrode 18 in the device region 10. The insulating film 19 covers a peripheral edge portion of the first electrode 18 at a distance inward from the peripheral edge of the device region 10. The insulating film 19 defines a pad opening 20 in an inward portion of the device region 10 and defines a street opening 21 at the peripheral edge portion of the device region 10. The pad opening 20 exposes an inward portion of the first electrode 18. The pad opening 20 is formed in a polygonal shape (a quadrangular shape in this embodiment) along a peripheral edge of the first electrode 18 in plan view.

[0038] The road opening 21 extends along the peripheral edge of the device portion 10 and exposes the first main surface 3. Specifically, the road opening 21 is defined by the plurality of insulating films 19 adjacent to each other in the first direction X and the second direction Y in a lattice shape extending in the first direction X and the second direction Y, and exposes the boundary portion (the plurality of target cutting lines 12) of the plurality of device portions 10. Of course, if the main surface insulating film 16 covering the first main surface 3 is formed at the boundary portion of the plurality of device portions 10, the road opening 21 can expose the main surface insulating film 16 at the boundary portion of the plurality of device portions 10.

[0039] The insulating film 19 is preferably thicker than the first electrode 18. The thickness of the insulating film 19 is preferably less than the thickness of the wafer 2. The thickness of the insulating film 19 may be no less than 3 µm and no more than 35 µm. The thickness of the insulating film 19 is preferably no more than 25 µm.

[0040] In this embodiment, the insulating film 19 has a laminated structure including an inorganic insulating film 22 (inorganic film) and an organic insulating film 23 (organic film) laminated in this order from the first electrode 18 side. The inorganic insulating film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the inorganic insulating film 22 includes an insulating material different from that of the main surface insulating film 16. In this embodiment, the inorganic insulating film 22 has a single-layer structure including a silicon nitride film. A thickness of the inorganic insulating film 22 may be not less than 0.1 μm and not more than 5 μm, if desired.

[0041] The organic insulating film 23 is thicker than the inorganic insulating film 22 and covers the inorganic insulating film 22. The organic insulating film 23 is preferably made of a photosensitive resin film. The organic insulating film 23 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. A thickness of the organic insulating film 23 may optionally be not less than 3 µm and not more than 30 µm. The thickness of the organic insulating film 23 is preferably not more than 20 µm.

[0042] The organic insulating film 23 may expose one or both of an inner edge portion and an outer edge portion of the inorganic insulating film 22. In this embodiment, the organic insulating film 23 exposes both the inner edge portion and the outer edge portion of the inorganic insulating film 22 and, together with the inorganic insulating film 22, defines the pad opening 20 and the street opening 21. Of course, the organic insulating film 23 may cover an entire area of ​​the inorganic insulating film 22.

[0043] The wafer structure 1A includes the second electrode 24 covering the second main surface 4. In this embodiment, the second electrode 24 is formed as a cathode electrode and is electrically connected to the second region 8 exposed from the second main surface 4. The second electrode 24 has a plating reaction rate that is faster than a plating reaction rate of the wafer 2. That is, the second electrode 24 includes an electrode material whose oxidation-reduction reaction proceeds faster than that of the wafer 2.

[0044] The second electrode 24 exposes at least a part of a peripheral edge portion of the wafer 2 as a plating reaction inhibiting portion 25. In other words, the plating reaction inhibiting portion 25 is an exposed portion exposed from the second electrode 24 in the second main surface 4. In this embodiment, the second electrode 24 exposes an entire periphery of the peripheral edge portion of the wafer 2 as the plating reaction inhibiting portion 25.

[0045] That is, the plating reaction inhibiting portion 25 exposes the SiC single crystal (in this embodiment, the carbon plane of the SiC single crystal) exposed from the peripheral edge portion of the second main surface 4. Furthermore, the plating reaction inhibiting portion 25 exposes the grinding marks formed on the peripheral edge portion of the second main surface 4. A portion of the second main surface 4 forming the plating reaction inhibiting portion 25 is shaped to be flush with a portion of the second main surface 4 hidden by the second electrode 24. That is, the plating reaction inhibiting portion 25 extends in the horizontal direction and does not form a step portion hollowed toward the first main surface 3 in the second main surface 4.

[0046] The plating reaction inhibiting portion 25 has, in plan view, a portion extending in a circular arc shape in a region outside the mark 6 and a portion extending linearly in a region along the mark 6. The plating reaction inhibiting portion 25 is formed in a region outside the plurality of device regions 10 in plan view and faces the space 11 in the thickness direction of the wafer 2. That is, the plating reaction inhibiting portion 25 is formed in an annular shape that collectively surrounds the plurality of device regions 10 in plan view.

[0047] An exposure width W of the plating reaction inhibiting portion 25 is preferably larger than a thickness of the second electrode 24. The exposure width W is preferably larger than a thickness of the first electrode 18. The exposure width W is preferably larger than a thickness of the insulating film 19. In particular, the exposure width W is preferably larger than the thickness of the wafer 2.

[0048] The exposure width W may be not less than 0.5 mm and not more than 5 mm. The exposure width W is preferably not less than 1 mm and not more than 2 mm. In particular, the exposure width W is preferably smaller than a length of one side of the device region 10. According to this configuration, it is possible to suppress a reduction in the number of the plurality of device regions 10 (that is, the number of semiconductor devices) due to insertion of the plating reaction inhibiting portion 25.

[0049] The second electrode 24 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film. The Al-based metal film may include at least one of an Al film and an Al alloy film. For example, the Al-based metal film may include at least one of an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

[0050] The Ti-based metal film may include at least one of a Ti film and a Ti alloy film. The Ni-based metal film may include at least one of a Ni film and a Ni alloy film. The Pd-based metal film may include at least one of a Pd film and a Pd alloy film. The Au-based metal film may include at least one of an Au film and an Au alloy film. The Ag-based metal film may include at least one of an Ag film and an Ag alloy film.

[0051] Referring to Fig. 6, in this embodiment, the second electrode 24 has a laminated structure including a Ti film 31, a Ni film 32, and an Au film 33 laminated in this order from the second main surface 4 side. The Ti film 31 directly covers the second main surface 4. In this embodiment, the Ti film 31 does not form a silicide layer (TiSi layer) on the surface layer portion of the second main surface 4. Of course, the Ti film 31 may form a silicide layer on the surface layer portion of the second main surface 4. The Ti film 31 may have a thickness of not less than 500 Å and not more than 1000 Å.

[0052] The Ni film 32 is thicker than the Ti film 31 and covers the Ti film 31. A thickness of the Ni film 32 may be not less than 5000 Å and not more than 20000 Å. The Au film 33 is thinner than the Ni film 32 and covers the Ni film 32. A thickness of the Au film 33 may be not less than 500 Å and not more than 1000 Å.

[0053] Referring to Fig. 7A, the second electrode 24 may have a laminated structure including an AlSi alloy film 34, a Ti film 35, a Ni film 36, and an Au film 37 laminated in this order from the second main surface 4 side. The AlSi alloy film 34 directly covers the second main surface 4. In this embodiment, the AlSi alloy film 34 does not form a silicide layer (AlSi layer) on the surface layer portion of the second main surface 4. Of course, the AlSi alloy film 34 may form a silicide layer on the surface layer portion of the second main surface 4. The AlSi alloy film 34 may have a thickness of not less than 500 Å and not more than 2000 Å.

[0054] The Ti film 35 is thinner than the AlSi alloy film 34 and covers the AlSi alloy film 34. A thickness of the Ti film 35 may be not less than 500 Å and not more than 1000 Å. The Ni film 36 is thicker than the Ti film 35 and covers the Ti film 35. The Ni film 36 may have a thickness of not less than 5000 Å and not more than 20000 Å. The Au film 37 is thinner than the Ni film 36 and covers the Ni film 36. The Au film 37 may have a thickness of not less than 500 Å and not more than 1000 Å.

[0055] Referring to Fig. 7B, the second electrode 24 may have a laminated structure including a Ti film 38, a Ni film 39, an Au film 40, and an Ag film 41 laminated in this order from the second main surface 4 side. The Ti film 38 directly covers the second main surface 4. In this embodiment, the Ti film 38 does not form a silicide layer (TiSi layer) on the surface layer portion of the second main surface 4. Of course, the Ti film 38 may form a silicide layer on the surface layer portion of the second main surface 4. The Ti film 38 may have a thickness of not less than 500 Å and not more than 1000 Å.

[0056] The Ni film 39 is thicker than the Ti film 38 and covers the Ti film 38. A thickness of the Ni film 39 may be not less than 5000 Å and not more than 20000 Å. The Au film 40 is thinner than the Ni film 39 and covers the Ni film 39. A thickness of the Au film 33 may be not less than 500 Å and not more than 1000 Å. The Ag film 41 is thicker than the Au film 40 and covers the Au film 40. A thickness of the Ag film 41 may be not less than 1000 Å and not more than 3000 Å.

[0057] The wafer structure 1A includes a protective tape 45 adhered to the second electrode 24 of the wafer 2. The protective tape 45 may be referred to as a "protective film," "support tape," "support film," etc. The protective tape 45 is preferably thicker than the second electrode 24. A thickness of the protective tape 45 is preferably greater than the thickness of the first electrode 18. The thickness of the protective tape 45 is preferably greater than the thickness of the insulating film 19. The thickness of the protective tape 45 is preferably less than the thickness of the wafer 2. Of course, the thickness of the protective tape 45 may not be less than the thickness of the wafer 2.

[0058] The protective tape 45 includes a base film 46 and an adhesive layer 47. The base film 46 is made of an optically transparent organic film. The base film 46 preferably has a planar shape corresponding to a planar shape of the wafer 2. In this embodiment, the base film 46 is formed in a circular shape in plan view. When a wafer 2 with a rectangular parallelepiped shape is used, the base film 46 is preferably formed in a quadrangular shape in plan view.

[0059] The base film 46 is preferably thicker than the second electrode 24. A thickness of the base film 46 is preferably greater than the thickness of the first electrode 18. The thickness of the base film 46 is preferably greater than the thickness of the insulating film 19. The thickness of the base film 46 is preferably less than the thickness of the wafer 2. Of course, the thickness of the base film 46 may not be less than the thickness of the wafer 2 if necessary. The thickness of the base film 46 may be not less than 10 µm and not more than 100 µm if necessary. The thickness of the base film 46 is preferably not less than 20 µm and not more than 50 µm.

[0060] The adhesive layer 47 is provided on one surface side of the base film 46. The adhesive layer 47 is preferably provided on an entire area of ​​the base film 46 on the one surface side. The adhesive layer 47 is preferably thicker than the second electrode 24. A thickness of the adhesive layer 47 is preferably greater than the thickness of the first electrode 18.

[0061] The thickness of the adhesive layer 47 is preferably greater than the thickness of the insulating film 19. The thickness of the adhesive layer 47 is preferably less than the thickness of the wafer 2. Of course, the thickness of the adhesive layer 47 may not be less than the thickness of the wafer 2. The thickness of the adhesive layer 47 may not be less than 10 µm and not more than 100 µm. The thickness of the adhesive layer 47 is preferably not less than 20 µm and not more than 50 µm.

[0062] The adhesive layer 47 may contain a light-curable adhesive whose adhesive strength is reduced, for example, by irradiation with ultraviolet rays. The adhesive layer 47 has properties such that adhesion (adhesion strength) to the wafer 2 is higher than adhesion (adhesion strength) to the second electrode 24. That is, the protective tape 45 has properties such that adhesion to the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4) is higher than adhesion to the second electrode 24.

[0063] The adhesive strength of the protective tape 45 (adhesive layer 47) to the wafer 2 is preferably greater than 14.1 N / 25 mm. For example, the adhesive strength of the protective tape 45 to a SiC wafer is preferably greater than 14.4 N / 25 mm. The adhesive strength of the protective tape 45 to the second electrode 24 is not less than 8 N / 25 mm and less than 14 N / 25 mm. The adhesive strength of the protective tape 45 to the Au film 33 is, for example, about 8.9 N / 25 mm. The adhesive strength of the protective tape 45 to the Ag film 41 is, for example, about 10 N / 25 mm.

[0064] The protective tape 45 is adhered to the second main surface 4 side of the wafer 2 by bonding the adhesive layer 47 to the second electrode 24 and the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4). The protective tape 45 covers an entire area of ​​the second electrode 24 and extends from the second electrode 24 onto the plating reaction inhibiting portion 25 in a film form. In this embodiment, the protective tape 45 covers the plating reaction inhibiting portion 25 over an entire circumference of the peripheral edge portion of the wafer 2.

[0065] That is, the protective tape 45 covers the SiC single crystal (in this embodiment, the carbon plane of the SiC single crystal) exposed as the plating reaction inhibiting portion 25. Furthermore, the protective tape 45 covers the grinding marks formed on the plating reaction inhibiting portion 25. In this case, the grinding marks are preferably filled with the adhesive layer 47.

[0066] According to this configuration, the bonding area of ​​the protective tape 45 (adhesive layer 47) with respect to the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4) is increased due to the grinding track. Therefore, the adhesion of the protective tape 45 to the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4) is increased. That is, the grinding track also functions as an anchor hole for the protective tape 45.

[0067] The bonding portion of the protective tape 45 to the plating reaction inhibiting portion 25 includes, in plan view, a portion extending in a circular arc shape in a region outside the mark 6 and a portion extending linearly in a region along the mark 6. Specifically, the bonding portion of the protective tape 45 is formed in a region outside the plurality of device regions 10 in plan view and faces the space 11 on the other side of the wafer 2. That is, the bonding portion of the protective tape 45 is formed in an annular shape that collectively surrounds the plurality of device regions 10 in plan view.

[0068] The protective tape 45 may form a gap 48 between the second main surface 4 and an edge portion of the second electrode 24. That is, the protective tape 45 may be adhered to the second electrode 24 and the plating reaction inhibiting portion 25 such that an edge portion of the second electrode 24 is exposed. The gap 48 may be partially formed at the edge portion of the second electrode 24 or at an entire periphery thereof. Of course, the protective tape 45 may partially cover the edge portion of the second electrode 24 or the entire periphery thereof, so that no gap 48 is formed at the edge portion of the second electrode 24.

[0069] An edge portion of the protective tape 45, in plan view, includes a portion extending in a circular arc shape in a region outside the mark 6 and a portion extending linearly in a region along the mark 6. The protective tape 45 preferably protrudes from a region above the second main surface 4 to a region outside the second main surface 4 along a horizontal direction. According to this configuration, an entire area of ​​the second main surface 4 can be covered by the protective tape 45. In this case, a portion of the adhesive layer 47 covering a peripheral edge portion of the base film 46 can be exposed from the wafer 2.

[0070] The protective tape 45 preferably exposes the side surface 5 of the wafer 2. It is particularly preferable that the protective tape 45 exposes an entire area of ​​the side surface 5. The fact that the protective tape 45 exposes an entire area of ​​the side surface 5 means that the base film 46 is not adhered to the side surface 5 of the wafer 2 via the adhesive layer 47. Therefore, in a configuration where the adhesive layer 47 partially overlaps a lower end portion of the side surface 5, when the base film 46 does not face the side surface 5 via the adhesive layer 47, the protective tape 45 must expose the entire area of ​​the side surface 5.

[0071] A projection width Wo of the protective tape 45 may be larger than the thickness of the wafer 2. The projection width Wo may be larger than the thickness of the second electrode 24. The projection width Wo may be larger than the thickness of the first electrode 18. The projection width Wo may be larger than the thickness of the insulating film 19. The projection width Wo is preferably smaller than the exposure width W of the plating reaction inhibiting portion 25. The projection width Wo may be not less than 0.1 mm and not more than 2 mm, if desired. The projection width Wo is preferably not less than 0.5 mm and not more than 1 mm.

[0072] The Fig. 8A to Fig. 8F are each a cross-sectional view showing a manufacturing method for a semiconductor device SD1. The Fig. 9A to Fig. 9C are each a cross-sectional view showing a step of forming the second electrode 24. The Fig. 8A to Fig. 8F ( Fig. 9F to Fig. 9C) are also some of the manufacturing steps of the wafer structure 1A.

[0073] Referring to Fig. 8A, the wafer structure 1A is first prepared before the step of forming the second electrode 24. In each of the device regions 10, the wafer structure 1A includes the diode region 14, the protection region 15, the main surface insulating film 16, the first electrode 18, and the insulating film 19. The wafer structure 1A includes the wafer 2 with a thickness of not less than 200 µm before the step of forming the second electrode 24. The wafer 2 may have a thickness of not less than 200 µm and not more than 1000 µm. The wafer 2 preferably has a thickness of not less than 250 µm and not more than 500 µm.

[0074] Next, with reference to Fig. 8B, a step of thinning the wafer 2 is performed. The wafer 2 can be thinned from the second main surface 4 side by at least one of a grinding process and an etching process. In this embodiment, the wafer 2 is thinned by a grinding process for the second main surface 4. In this embodiment, the wafer 2 is ground until it reaches a thickness of less than 200 µm. This thins the wafer 2, and at the same time, a grinding track is formed in the second main surface 4.

[0075] Next, with reference to Fig. 8C, a step of forming the second electrode 24 is carried out. Referring to Fig. 9A, in this step, a masking jig 50 is fabricated as a mask for the peripheral edge portion of the second main surface 4. The masking jig 50 may be constructed of an inorganic substance such as metal (e.g., stainless steel, etc.), glass, ceramic, etc., or may be constructed of an organic substance such as resin, etc. The masking jig 50 is configured to cover at least a part of the peripheral edge portion of the second main surface 4 and expose an inner portion of the second main surface 4.

[0076] That is, the masking jig 50 is configured to cover an area to be formed as the plating reaction inhibiting portion 25 in the peripheral edge portion of the second main surface 4. In this embodiment, the masking jig 50 is formed in a ring-shaped shape (specifically, a circular ring-shaped shape) in plan view, so that it covers an entire periphery of the peripheral edge portion of the second main surface 4 and exposes the inner portion of the second main surface 4.

[0077] The masking jig 50 may have a portion extending in a circular arc shape in a plan view in an area outside the mark 6, and a portion extending linearly in a plan view in an area along the mark 6. The masking jig 50 is preferably thicker than the second electrode 24 to be formed as a film.

[0078] Next, with reference to Fig. 9B, the masking jig 50 is brought into contact with the peripheral edge portion of the second main surface 4. The masking jig 50 is brought into contact with the SiC single crystal (in this embodiment, the carbon plane of the SiC single crystal) exposed from the peripheral edge portion of the second main surface 4. The masking jig 50 is arranged in a region outside the plurality of device regions 10 in plan view and faces the space 11 on the other side of the wafer 2. That is, the plating reaction inhibiting portion 25 is arranged to collectively surround the plurality of device regions 10 in plan view. A covering width (contact width) of the masking jig 50 with respect to the peripheral edge portion of the second main surface 4 corresponds to the exposure width W of the plating reaction inhibiting portion 25.

[0079] Next, the second electrode 24 is deposited on the second main surface 4 and the masking jig 50 by a sputtering method in a state where the masking jig 50 is in contact with the second main surface 4. The thickness of the second electrode 24 is less than the thickness of the masking jig 50. The second electrode 24 may include at least one of an Al-based metal film, a Ti-based metal film, a Ni-based metal film, a Pd-based metal film, an Au-based metal film, and an Ag-based metal film.

[0080] The Al-based metal film, the Ti-based metal film, the Ni-based metal film, the Pd-based metal film, the Au-based metal film, and the Ag-based metal film can all be formed into films by a sputtering method. The second electrodes 24 according to the first to third configuration examples (see Fig. 6, Fig. 7A and Fig. 7B) are formed by adjusting a film formation order of these metal films as needed.

[0081] Next, with reference to Fig. 9C, the masking jig 50 is removed from the second main surface 4. This simultaneously removes a portion of the second electrode 24 covering the masking jig 50, and the plating reaction inhibiting portion 25 having a layout corresponding to a layout of the masking jig 50 is formed on the peripheral edge portion of the second main surface 4.

[0082] Next, with reference to Fig. 8D, the protective tape 45 is bonded to the second electrode 24 and the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4). Fig. 1 to Fig. 6 is manufactured. The wafer structure 1A is handled in a state in which the protective tape 45 is adhered.

[0083] Next, with reference to Fig. 8E, a plating film 51 is formed on the first electrode 18 by a plating process. The plating film 51 can be considered a component of the wafer structure 1A. In this step, an entire surface of the wafer structure 1A is immersed in a plating solution, and the plating film 51 is formed on the first electrode 18. This step may include a step of rocking the wafer structure 1A in the plating solution. The rocking step includes a stirring step in which bubbles generated by a plating reaction are dispersed in the solution. According to this step, film formation failure of the plating film 51 due to bubbles is suppressed.

[0084] In the case of a wafer 2 with a thickness of less than 200 µm, the wafer 2 is deformed in the pivoting step due to being subjected to stress from the plating solution. The protective tape 45 protects the second electrode 24 from the plating solution and simultaneously prevents deformation of the wafer 2 in the plating solution. This prevents abnormal film formation of the plating film 51 with respect to the second electrode 24 and simultaneously prevents cracks in the wafer 2.

[0085] Further, the second electrode 24 exposes the peripheral edge portion of the second main surface 4, and the protective tape 45 covers the peripheral edge portion of the second main surface 4. In this configuration, the protective tape 45 has properties such that adhesion to the peripheral edge portion of the second main surface 4 is higher than adhesion to the second electrode 24. According to this configuration, the protective tape 45 is prevented from peeling off from the peripheral edge portion of the second main surface 4.

[0086] This prevents abnormal formation of a plating film on the second electrode 24 due to peeling of the protective tape 45. Furthermore, the adhesion of the protective tape 45 to the peripheral edge portion of the second main surface 4 is improved, and therefore, a plating solution is prevented from penetrating into a region between the second main surface 4 and the protective tape 45. This prevents abnormal formation of the plating film with respect to the second electrode 24.

[0087] Furthermore, the peripheral edge portion of the second main surface 4 is exposed as a plating reaction inhibiting portion 25, whose reaction rate with respect to a plating solution is slow. The film formation of the plating film 51 is prevented in the plating reaction inhibiting portion 25. Therefore, even if the plating solution penetrates into a region between the second main surface 4 and the protective tape 45, abnormal formation of the plating film is prevented by the plating reaction inhibiting portion 25.

[0088] In this embodiment, the step of forming the plating film 51 includes a step of forming a Ni plating film 52, a Pd plating film 53, and an Au plating film 54 in this order from the first electrode 18 side. The step of forming the Ni plating film 52 includes a step of forming the Ni plating film 52 on the first electrode 18 by an electroless plating method. The step of forming the Ni plating film 52 includes a step of immersing the wafer structure 1A in a Ni plating solution. Further, the step of forming the Ni plating film 52 includes a step of rocking the wafer structure 1A in the Ni plating solution.

[0089] The peripheral edge portion of the second main surface 4 is preferably exposed as a plating reaction inhibiting portion 25 whose reaction rate is slow with respect to at least the Ni plating solution. By preventing abnormal film formation of the Ni plating film 52 on the second main surface 4 side, it is possible to also prevent abnormal film formation of the Pd plating film 53 and the Au plating film 54 on the second main surface 4 side in subsequent steps.

[0090] The Ni plating film 52 is preferably thicker than the inorganic insulating film 22. In this case, the Ni plating film 52 is preferably formed on the first electrode 18 so as to slide over an edge portion of the inorganic insulating film 22 within the pad opening 20. The Ni plating film 52 is preferably formed at a distance to the vertical Z-direction side from an opening end of the pad opening 20 toward the first electrode 18.

[0091] In this embodiment, the Ni plating film 52 covers the first electrode 18 and the inorganic insulating film 22 within the pad opening 20 and is in contact with the organic insulating film 23. Of course, the Ni plating film 52 is formed within the pad opening 20 at a distance from the organic insulating film 23 and may cover edge portions of the first electrode 18 and the inorganic insulating film 22.

[0092] The Ni plating film 52 may have a thickness of not less than 0.1 μm and not more than 15 μm. The thickness of the Ni plating film 52 may optionally be not less than 0.1 μm and not more than 1 μm, not less than 1 μm and not more than 3 μm, not less than 3 μm and not more than 6 μm, not less than 6 μm and not more than 9 μm, not less than 9 μm and not more than 12 μm, or not less than 12 μm and not more than 15 μm. The thickness of the Ni plating film 52 is preferably not less than 2 μm and not more than 8 μm.

[0093] The step of forming the Pd plating film 53 includes a step of forming the Pd plating film 53 on the Ni plating film 52 by an electroless plating method. The step of forming the Pd plating film 53 includes a step of immersing the wafer structure 1A in the Pd plating solution. Furthermore, the step of forming the Pd plating film 53 includes a step of rocking the wafer structure 1A in the Pd plating solution.

[0094] The peripheral edge portion of the second main surface 4 is preferably exposed as a plating reaction inhibiting portion 25 whose reaction rate is slow with respect to the Pd plating solution. By preventing abnormal film formation of the Pd plating film 53 on the second main surface 4 side, it is possible to also prevent abnormal film formation of the Au plating film 54 on the second main surface 4 side in subsequent steps.

[0095] The Pd plating film 53 is formed in a film shape along an outer surface of the Ni plating film 52. The Pd plating film 53 is preferably formed at a distance from an opening end of the pad opening 20 to the Ni plating film 52 side. The Pd plating film 53 is in contact with the organic insulating film 23 inside the pad opening 20 with respect to the vertical direction Z. Of course, when the Ni plating film 52 is separated from the organic insulating film 23, the Pd plating film 53 may cover the Ni plating film 52 at a distance from the organic insulating film 23. In this case, the Pd plating film 53 may cover an edge portion of the inorganic insulating film 22.

[0096] The Pd plating film 53 preferably has a thickness less than the thickness of the Ni plating film 52. The thickness of the Pd plating film 53 may be not less than 0.01 μm and not more than 1 μm, as appropriate. The thickness of the Pd plating film 53 may be not less than 0.01 μm and not more than 0.1 μm, not less than 0.1 μm and not more than 0.2 μm, not less than 0.2 μm and not more than 0.4 μm, not less than 0.4 μm and not more than 0.6 μm, not less than 0.6 μm and not more than 0.8 μm, or not less than 0.8 μm and not more than 1 μm.

[0097] The step of forming the Au plating film 54 includes a step of forming the Au plating film 54 on the Pd plating film 53 by an electroless plating method. The step of forming the Au plating film 54 includes a step of immersing the wafer structure 1A in an Au plating solution. The step of forming the Au plating film 54 also includes a step of rocking the wafer structure 1A in the Au plating solution. The peripheral edge portion of the second main surface 4 is preferably exposed as a plating reaction inhibiting portion 25 whose reaction rate is slow with respect to the Au plating solution.

[0098] The Au plating film 54 is formed in a film shape along an outer surface of the Pd plating film 53. The Au plating film 54 is preferably formed at a distance from the vertical direction Z side from an opening end of the pad opening 20 toward the Pd plating film 53 side. The Au plating film 54 is in contact with the organic insulating film 23 within the pad opening 20. Of course, when the Ni plating film 52 and the Pd plating film 53 are separated from the organic insulating film 23, the Au plating film 54 may cover the Pd plating film 53 at a distance from the organic insulating film 23. In this case, the Au plating film 54 may cover an edge portion of the inorganic insulating film 22.

[0099] The Au plating film 54 preferably has a thickness less than the thickness of the Ni plating film 52. The thickness of the Au plating film 54 may be not less than 0.01 μm and not more than 1 μm, as appropriate. The thickness of the Au plating film 54 may be not less than 0.01 μm and not more than 0.1 μm, not less than 0.1 μm and not more than 0.2 μm, not less than 0.2 μm and not more than 0.4 μm, not less than 0.4 μm and not more than 0.6 μm, not less than 0.6 μm and not more than 0.8 μm, or not less than 0.8 μm and not more than 1 μm.

[0100] In this embodiment, an example is shown in which the plating film 51 includes the Ni plating film 52, the Pd plating film 53, and the Au plating film 54. However, the plating film 51 may have a laminated structure including only the Ni plating film 52 and the Au plating film 54, which are laminated in this order from the first electrode 18 side. Of course, the plating film 51 may have a single-layer structure made of the Ni plating film 52, the Pd plating film 53, or the Au plating film 54.

[0101] Next, with reference to Fig. 8F, the protective tape 45 is peeled off from the second main surface 4 and the second electrode 24. This step includes a step of irradiating the adhesive layer 47 of the protective tape 45 with ultraviolet rays and reducing an adhesive force of the adhesive layer 47. This step also includes a step of peeling off the base film 46 from the second electrode 24 together with the adhesive layer 47.

[0102] Next, with reference to Fig. 8G, the wafer 2 is cut along the plurality of predetermined cutting lines 12. The wafer 2 may be cut (sliced) in the vertical direction Z by a dicing blade, or may be cut (cleaved) in the vertical direction Z by a cleaving process using a laser light irradiation step. In the cleaving process, a modified layer in which a crystal structure is partially modified by laser light irradiation is formed inside the wafer 2, and with the modified layer as a starting point, the wafer 2 is cleaved in the vertical direction Z. Through the steps including the above, the semiconductor device SD1 (in this embodiment, the SiC semiconductor device) is manufactured.

[0103] As described above, the wafer structure 1A includes the wafer 2, the first electrode 18, the second electrode 24, and the protective tape 45. The wafer 2 has the first main surface 3 on one side and the second main surface 4 on the other side. The first electrode 18 covers the first main surface 3. The second electrode 24 covers the inner portion of the second main surface 4 such that the peripheral edge portion of the second main surface 4 is exposed. The protective tape 45 is adhered to the peripheral edge portion of the second main surface 4 and the second electrode 24. The protective tape 45 has properties such that adhesion to the peripheral edge portion of the second main surface 4 is higher than adhesion to the second electrode 24.

[0104] According to this configuration, it is possible to prevent peeling of the protective tape 45 from the second main surface 4 and the second electrode 24. Therefore, when the wafer structure 1A undergoes a manufacturing process for the semiconductor device SD1, it is possible to prevent a manufacturing defect due to peeling of the protective tape 45. Thus, it is possible to provide the wafer structure 1A that contributes to the manufacture of the semiconductor device SD1 with high reliability. For example, when the wafer structure 1A is immersed in a plating solution, it is possible to prevent the plating solution from penetrating into a region between the second main surface 4 and the protective tape 45. This prevents abnormal formation of the plating film with respect to the second electrode 24.

[0105] When the second electrode 24 has a plating reaction rate higher than the plating reaction rate of the wafer 2, the second electrode 24 preferably exposes a peripheral edge portion of the wafer 2 as the plating reaction inhibiting portion 25. That is, the peripheral edge portion of the wafer 2 is preferably made of a material that inhibits the formation of a plating film.

[0106] In this case, the protective tape 45 is preferably adhered to the plating reaction inhibiting portion 25. According to this configuration, it is possible to prevent a plating solution from penetrating into a region between the plating reaction inhibiting portion 25 and the protective tape 45. Even if the plating solution penetrates into a region between the second main surface 4 and the protective tape 45, abnormal formation of the plating film can be suppressed by the plating reaction inhibiting portion 25.

[0107] The wafer 2 preferably encloses the SiC single crystal. In this case, the second electrode 24 preferably exposes the SiC single crystal from the peripheral edge portion of the second main surface 4. The protective tape 45 is also preferably bonded to the SiC single crystal at the peripheral edge portion of the second main surface 4. The SiC single crystal has such physical properties that the probability of metal deposition by a plating process is lower. Therefore, even if a plating solution penetrates into a region between the second main surface 4 and the protective tape 45, it is possible to prevent abnormal formation of the plating film by the SiC single crystal.

[0108] The wafer 2 preferably has a thickness of less than 200 µm. According to this configuration, it is possible to reduce the on-resistance due to the thickness of the wafer 2. Furthermore, the wafer 2 can be handled accordingly with the protective tape 45 while preventing deformation of the relatively thin wafer 2.

[0109] The second electrode 24 preferably exposes an entire periphery of the peripheral edge portion of the second main surface 4. In this case, the protective tape 45 is preferably adhered to the entire periphery of the peripheral edge portion of the second main surface 4. According to this configuration, peeling of the protective tape 45 from the second main surface 4 can be prevented at the entire periphery of the peripheral edge portion of the second main surface 4. At the entire periphery of the peripheral edge portion of the second main surface 4, it is also possible to prevent a plating solution from penetrating into a region between the second main surface 4 and the protective tape 45.

[0110] The exposure width W of the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4) is preferably larger than the thickness of the second electrode 24. The exposure width W is preferably larger than the thickness of the wafer 2. According to these configurations, it is possible to appropriately reduce a risk of contact of a plating solution with respect to the second electrode 24.

[0111] The second main surface 4 preferably has the grinding track. In this case, the second electrode 24 preferably exposes the grinding track at the peripheral edge portion of the second main surface 4. Furthermore, the protective tape 45 is preferably adhered to the peripheral edge portion with the grinding track. According to this configuration, it is possible to increase the adhesion of the protective tape 45 to the peripheral edge portion of the second main surface 4 through the grinding track.

[0112] The second main surface 4 is preferably formed from a flat surface. That is, the second main surface 4 preferably does not have a step portion that is hollowed toward the first main surface 3 side. According to this configuration, it is possible to adequately prevent the formation of a fragile portion of the wafer 2 in the second main surface 4. In particular, this configuration is preferably applied to the wafer 2 with a thickness of less than 200 μm.

[0113] The wafer structure 1A may include the plating film 51 covering the first electrode 18. In this case, the second electrode 24 preferably exposes the peripheral edge portion of the wafer 2 as the plating reaction inhibiting portion 25 that inhibits the film formation of the plating film 51. The plating film 51 may include at least one of the Ni plating film 52, the Pd plating film 53, and the Au plating film 54.

[0114] The wafer structure 1A may include the plurality of device regions 10 arranged in an inner portion of the first main surface 3. In this case, the second electrode 24 preferably exposes the area outside the plurality of device regions 10 in plan view. According to this configuration, it is possible to properly manufacture the semiconductor device SD1 having the second electrode 24.

[0115] In another aspect, the manufacturing method for the semiconductor device SD1 includes the step of preparing the wafer structure 1A, the step of forming the second electrode 24, and the step of adhering the protective tape 45. In the step of preparing the wafer structure 1A, the wafer structure 1A is manufactured, which includes the wafer 2 having the first surface on one side and the second main surface 4 on the other side, as well as the first electrode 18 covering the first surface.

[0116] In the step of forming the second electrode 24, the second electrode 24 covering the inner portion of the second main surface 4 is formed so that the peripheral edge portion of the second main surface 4 is exposed. In the step of adhering the protective tape 45, the protective tape 45, which has properties such that adhesion to the peripheral edge portion of the second main surface 4 is higher than adhesion to the second electrode 24, is adhered to the peripheral edge portion of the second main surface 4 and the second electrode 24.

[0117] According to this manufacturing method, it is possible to prevent the protective tape 45 from peeling off the second main surface 4 and the second electrode 24. This makes it possible to prevent a manufacturing defect due to the peeling off of the protective tape 45. Therefore, it is possible to provide the method that contributes to the manufacture of the semiconductor device SD1 with high reliability. For example, when the wafer 2 is immersed in a plating solution in a state where the protective tape 45 is adhered, it is possible to prevent the plating solution from penetrating into a region between the second main surface 4 and the protective tape 45. This prevents abnormal formation of the plating film with respect to the second electrode 24.

[0118] When the second electrode 24 has a plating reaction rate higher than the plating reaction rate of the wafer 2, the second electrode 24 preferably exposes the peripheral edge portion of the wafer 2 as the plating reaction inhibiting portion 25. That is, the peripheral edge portion of the wafer 2 is preferably made of a material that inhibits the formation of a plating film.

[0119] In this case, the protective tape 45 is preferably adhered to the plating reaction inhibiting portion 25. According to the manufacturing method, it is possible to prevent a plating solution from penetrating into a region between the plating reaction inhibiting portion 25 and the protective tape 45. Furthermore, even if the plating solution penetrates into a region between the second main surface 4 and the protective tape 45, it is possible to prevent abnormal formation of the plating film by the plating reaction inhibiting portion 25.

[0120] It is preferable that the manufacturing method for the semiconductor device SD1 also includes a step of immersing the wafer structure 1A in a plating solution in a state where the protective tape 45 is adhered, and forming the plating film 51 on the first electrode 18. According to the manufacturing method, it is possible to prevent a plating solution from penetrating into a region between the second main surface 4 and the protective tape 45. This makes it possible to suppress abnormal formation of the plating film with respect to the second electrode 24.

[0121] The step of forming the plating film 51 preferably includes a step of rocking the wafer structure 1A in a plating solution. According to this manufacturing method, bubbles generated in connection with plating reactions can be dispersed in the solution. This makes it possible to prevent a defect in the film formation of the plating film 51 caused by the bubbles. Furthermore, according to this manufacturing method, it is possible to protect the second electrode 24 from the plating solution by the protective tape 45, while simultaneously preventing deformation of the wafer 2 in the plating solution by the protective tape 45.

[0122] This prevents abnormal film formation of the plating film 51 with respect to the second electrode 24, and at the same time, cracks in the wafer 2 are prevented. In particular, the relatively thin wafer 2, which is smaller than 200 μm, is likely to be deformed by a stress from the plating solution in the rocking step, but it is possible to adequately prevent the deformation of the relatively thin wafer 2 by the protective tape 45.

[0123] The step of forming the plating film 51 may include at least one of the step of immersing the wafer structure 1A in the Ni plating solution and forming the Ni plating film 52, the step of immersing the wafer structure 1A in the Pd plating solution and forming the Pd plating film 53, and the step of immersing the wafer structure 1A in the Au plating solution and forming the Au plating film 54. According to this manufacturing method, it is possible to suppress at least one of abnormal film formation of the Ni plating film 52, abnormal film formation of the Pd plating film 53, and abnormal film formation of the Au plating film 54 on the second main surface 4 side by the protective tape 45.

[0124] The wafer 2 preferably encloses the SiC single crystal. In this case, the second electrode 24 is preferably formed so as to expose the SiC single crystal from the peripheral edge portion of the second main surface 4. The protective tape 45 is also preferably bonded to the SiC single crystal at the peripheral edge portion of the second main surface 4. The SiC single crystal has such a physical property that the probability of metal deposition by a plating process is lower. Therefore, even if a plating solution penetrates into a region between the second main surface 4 and the protective tape 45, it is possible to suppress abnormal formation of the plating film by the SiC single crystal.

[0125] In the step of manufacturing the wafer structure 1A, it is preferable that the wafer structure 1A including the wafer 2 be manufactured with a thickness of not less than 200 µm. In this case, the manufacturing method for the semiconductor device SD1 preferably includes a step of thinning the wafer 2 until the wafer 2 reaches a thickness of less than 200 µm before the step of forming the second electrode 24.

[0126] According to the manufacturing method, the wafer 2 can be handled while preventing deformation of the wafer 2 by keeping the wafer 2 relatively thick until the wafer 2 thinning step. Then, an on-resistance due to the thickness of the wafer 2 can be reduced in the wafer 2 thinning step. Then, the wafer 2 can be handled after the protective tape 45 bonding step by preventing deformation of the relatively thin wafer 2 by the protective tape 45.

[0127] The step of thinning the wafer 2 may include a step of grinding an entire surface of the second main surface 4 by a grinding process. In this case, the second electrode 24 is preferably formed to expose a grinding track on the peripheral edge portion of the second main surface 4. The protective tape 45 is also preferably adhered to the peripheral edge portion with the grinding track. According to the manufacturing method, it is possible to increase adhesion of the protective tape 45 to the peripheral edge portion of the second main surface 4 through the grinding track.

[0128] Fig. 10 is a plan view in which a wafer structure 1B according to a second embodiment is viewed from the first main surface 3 side. Fig. 11 is a cross-sectional view taken along the Fig. Line XI-XI shown in Figure 10. Fig. 12 is an enlarged cross-sectional view showing a main portion of the Fig. 11 shows the functional device 13. Fig. 13 is a schematic cross-sectional view of the Fig. 10 shown wafer structure 1B.

[0129] With reference to the Fig. 10 to Fig. 12, the wafer structure 1B has a configuration that differs from the aforementioned wafer structure 1A in that the functional device 13 includes a MISFET instead of the SBD. In Fig. 11, the functional device 13 is shown in simplified form by a dashed line.

[0130] In this embodiment, the MISFET is of the trench gate type. Other configurations of wafer structure 1B are substantially the same as those of wafer structure 1A. A point in wafer structure 1B that differs from that of wafer structure 1A will be described below. Furthermore, a configuration of the single device region 10 will be described below.

[0131] The wafer structure 1B includes a p-type body region 60 formed on the surface layer portion of the first main surface 3 in the device region 10. The body region 60 is formed at a distance from a bottom portion of the first region 7 to the first main surface 3 side and extends in a layered shape on the surface layer portion of the first main surface 3. The body region 60 may be formed in an entire area of ​​the first main surface 3.

[0132] The wafer structure 1B includes an n-type source region 61 formed at the surface layer portion of the body region 60 in the device region 10. The source region 61 may be formed at a distance from the peripheral edge of the device region 10 at an inner portion of the device region 10. The source region 61 has a higher n-type impurity concentration than the first region 7. The source region 61 is formed at a distance from a bottom portion of the body region 60 to the first main surface 3 side and extends in a layered shape at the surface layer portion of the first main surface 3. The source region 61 forms a channel with the first region 7 within the body region 60.

[0133] The wafer structure 1B includes a plurality of first trench structures 62 formed on the first main surface 3 in the device region 10. The first trench structure 62 may be referred to as a "trench-gate structure." The plurality of first trench structures 62 control the inversion and non-inversion of the channel. The plurality of first trench structures 62 extend through the body region 60 and the source region 61 and reach the first region 7. The plurality of first trench structures 62 may be arrayed at a pitch in the first direction X in plan view and each formed in a band shape extending in the second direction Y. The plurality of first trench structures 62 are formed at a pitch from a bottom portion of the first region 7 to the first main surface 3 side.

[0134] Each of the first trench structures 62 includes a first trench 63, a first insulating film 64, and a first embedded electrode 65. The first trench 63 is formed in the first main surface 3 and defines a wall surface of the first trench 63. The first insulating film 64 covers the wall surface of the first trench 63. The first embedded electrode 65 is embedded in the first trench 63 via the first insulating film 64. The first embedded electrode 65 faces the channel via the first insulating film 64.

[0135] The wafer structure 1B includes a plurality of second trench structures 66 formed on the first main surface 3 in the device region 10. The second trench structure 66 may be referred to as a "trench source structure." The plurality of second trench structures 66 are each formed in a region between two adjacent first trench structures 62.

[0136] The plurality of second trench structures 66 may each be formed in a band shape extending in the second direction Y in plan view. The plurality of second trench structures 66 extend through the body region 60 and the source region 61 and reach the first region 7. The plurality of second trench structures 66 are formed at a distance to the first main surface 3 side from a bottom portion of the first region 7 and are formed deeper than the first trench structure 62.

[0137] Each of the second trench structures 66 includes a second trench 67, a second insulating film 68, and a second embedded electrode 69. The second trench 67 is formed in the first main surface 3 and defines a wall surface of the second trench 67. The second insulating film 68 covers the wall surface of the second trench 67. The second embedded electrode 69 is embedded in the second trench 67 via the second insulating film 68.

[0138] The wafer structure 1B includes a plurality of p-type contact regions 70, each formed in a region along the plurality of second trench structures 66 within the wafer 2 in the device region 10. The plurality of contact regions 70 have a higher p-type impurity concentration than the body region 60. Each of the contact regions 70 covers a sidewall and a bottom wall of each second trench structure 66 and is electrically connected to the body region 60.

[0139] The wafer structure 1B includes a plurality of p-type well regions 71, each formed in a region along the plurality of second trench structures 66 within the wafer 2 in the device region 10. Each of the well regions 71 has a p-type impurity concentration higher than that of the body region 60 and lower than that of the contact region 70. Each of the well regions 71 covers a corresponding second trench structure 66 via a corresponding contact region 70. Each of the well regions 71 covers a sidewall and a bottom wall of the corresponding second trench structure 66 and is electrically connected to the body region 60.

[0140] The wafer structure 1B includes the main surface insulating film 16 covering the first main surface 3 in the device region 10. The main surface insulating film 16 extends to the first insulating film 64 and the second insulating film 68, exposing the first embedded electrode 65 and the second embedded electrode 69. In this embodiment, the main surface insulating film 16 covers a peripheral edge portion of the device region 10 (boundary portion of the plurality of device regions 10). That is, the main surface insulating film 16 covers an entire area of ​​the first main surface 3. Of course, the main surface insulating film 16 may expose the peripheral edge portion of the device region 10 (boundary portion of the plurality of device regions 10).

[0141] The wafer structure 1B includes an interlayer insulating film 72 covering the main surface insulating film 16 in the device region 10. The interlayer insulating film 72 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 72 covers the plurality of first trench structures 62 and the plurality of second trench structures 66.

[0142] In this embodiment, the interlayer insulating film 72 covers the peripheral edge portion of the device region 10 (boundary portion of the plurality of device regions 10) via the main surface insulating film 16. The interlayer insulating film 72 may cover an entire area of ​​the first main surface 3. Of course, if the main surface insulating film 16 exposes the first main surface 3 at the peripheral edge portion of the device region 10, the interlayer insulating film 72 may expose the first main surface 3 at the peripheral edge portion of the device region 10.

[0143] As in the first embodiment, the wafer structure 1B includes a first embedded electrode 65 disposed on the interlayer insulating film 72 in the device region 10. The first electrode 18 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the first main surface 3 side.

[0144] In this embodiment, the first electrode 18 includes a gate electrode 73 and a source electrode 74. In this embodiment, the gate electrode 73 is arranged in a region near a central portion of one side of the device region 10 in plan view. The gate electrode 73 may be arranged at a corner portion of the device region 10 in plan view. In this embodiment, the gate electrode 73 is formed in a quadrangular shape in plan view.

[0145] The source electrode 74 is arranged at a distance from the gate electrode 73 on the interlayer insulating film 72. In this embodiment, the source electrode 74 is formed in a polygonal shape having a concave portion hollowed out along the gate electrode 73 in plan view. Of course, the source electrode 74 may be formed in a quadrangular shape in plan view. The source electrode 74 extends through the interlayer insulating film 72 and the main surface insulating film 16 and is electrically connected to the body region 60, the source region 61, and the plurality of second trench structures 66.

[0146] The wafer structure 1B includes a gate wiring electrode 75 that extends from the gate electrode 73 in the device region 10 onto the interlayer insulating film 72. As with the gate electrode 73 (first electrode 18), the gate wiring electrode 75 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the first main surface 3 side. The gate wiring electrode 75 is formed in a band shape that extends along the peripheral edge of the device region 10 so as to intersect (specifically, intersect perpendicularly) end portions of the plurality of first trench structures 62 in plan view. The gate wiring electrode 75 penetrates the interlayer insulating film 72 and is electrically connected to the plurality of first trench structures 62.

[0147] The wafer structure 1B includes an insulating film 19 covering the first electrode 18 in the device region 10. As in the first embodiment, the insulating film 19 has a laminated structure including the inorganic insulating film 22 and the organic insulating film 23 laminated in this order from the first electrode 18 side. In this embodiment, the insulating film 19 covers a peripheral edge portion of the gate electrode 73 and a peripheral edge portion of the source electrode 74 at a distance inward from the peripheral edge of the device region 10. The insulating film 19 covers an entire area of ​​the first gate wiring electrode 75.

[0148] The insulating film 19 defines the plurality of pad openings 20 that expose an inner portion of the gate electrode 73 and an inner portion of the source electrode 74, and defines the street opening 21 that exposes the interlayer insulating film 72 at the peripheral edge portion of the device region 10. In this embodiment, the plurality of pad openings 20 include a gate pad opening 76 that exposes the inner portion of the gate electrode 73 and a source pad opening 77 that exposes the inner portion of the source electrode 74.

[0149] In this embodiment, the gate pad opening 76 is defined in a quadrangular shape in plan view along the peripheral edge of the gate electrode 73. In this embodiment, the source pad opening 77 is formed in a polygonal shape in plan view along the peripheral edge of the source electrode 74. The street opening 21 is formed in the same manner as in the first embodiment.

[0150] The organic insulating film 23 may expose an edge portion of the inorganic insulating film 22 in the gate pad opening 76. The organic insulating film 23 may expose an edge portion of the inorganic insulating film 22 in the source pad opening 77. The organic insulating film 23 may expose an edge portion of the inorganic insulating film 22 in the street opening 21. Of course, the organic insulating film 23 may cover an entire area of ​​the inorganic insulating film 22.

[0151] The wafer structure 1B includes a second electrode 24 covering the second main surface 4. In this embodiment, the second electrode 24 is formed as a drain electrode and is electrically connected to the second region 8 exposed from the second main surface 4. The second electrode 24 is formed in the same manner as that of the first embodiment. Descriptions of the first embodiment also apply to further descriptions of the second electrode 24.

[0152] The Fig. 14A to Fig. 14G are each a cross-sectional view showing a manufacturing method for a semiconductor device SD2 according to the Fig. 10 shows the wafer structure 1B. The Fig. 14A to Fig. 14G are also some of the manufacturing steps of the wafer structure 1B.

[0153] Referring to Fig. 14A, a wafer structure 1B is manufactured before a step of forming the second electrode 24. The wafer structure 1B includes the body region 60, the source region 61, the first trench structure 62, the second trench structure 66, the contact region 70, the well region 71, the main surface insulating film 16, the interlayer insulating film 72, the gate electrode 73 (first electrode 18), the source electrode 74 (first electrode 18), the gate wiring electrode 75, and the insulating film 19 in each of the device regions 10. The wafer structure 1A includes the wafer 2 with a thickness of not less than 200 μm before the step of forming the second electrode 24. The wafer 2 may have a thickness of not less than 200 µm and not more than 1000 µm. The wafer 2 preferably has a thickness of not less than 250 µm and not more than 500 µm.

[0154] Next, with reference to Fig. 14B, a step of thinning the wafer 2 is performed. The wafer 2 can be thinned from the second main surface 4 side by at least one of a grinding process and an etching process. In this embodiment, the wafer 2 is thinned by applying the grinding process to the second main surface 4. In this embodiment, the wafer 2 is ground until the thickness of less than 200 µm is reached. As a result, a grinding track is formed in the second main surface 4.

[0155] Next, with reference to Fig. 14C, a step of forming the second electrode 24 is carried out. The step of forming the second electrode 24 is carried out by the same steps as those in the aforementioned Fig. 9A to Fig. 9C. Thereby, the plating reaction inhibiting portion 25 having a layout corresponding to a layout of the masking jig 50 is formed at a peripheral edge portion of the second main surface 4.

[0156] Next, with reference to Fig. 14D, the protective tape 45 is bonded to the second electrode 24 and the plating reaction inhibiting portion 25 (peripheral edge portion of the second main surface 4). Fig. 10 to Fig. 13 is manufactured. The wafer structure 1B is handled in a state in which the protective tape 45 is adhered.

[0157] Next, with reference to Fig. 14E, the plating film 51 is formed on the first electrode 18 by a plating process. In this embodiment, the step of forming the plating film 51 includes a step of forming a gate plating film 78 on the gate electrode 73 and a step of forming a source plating film 79. The plating film 51 (gate plating film 78 and source plating film 79) can be considered a component of the wafer structure 1B.

[0158] As in the first embodiment, the step of forming the plating film 51 includes a step of forming the Ni plating film 52, the Pd plating film 53, and the Au plating film 54 in this order from the first electrode 18 side. The Ni plating film 52, the Pd plating film 53, and the Au plating film 54 are formed within the pad opening 20 (gate pad opening 76 and source pad opening 77) in the same manner as that of the first embodiment.

[0159] Of course, the plating film 51 may have a laminated structure including only the Ni plating film 52 and the Au plating film 54, which are laminated in this order from the first electrode 18 side. Furthermore, the plating film 51 may have a single-layer structure made of the Ni plating film 52, the Pd plating film 53, or the Au plating film 54.

[0160] Next, with reference to Fig. 14F, the protective tape 45 is peeled off from the second main surface 4 and the second electrode 24. This step includes a step of irradiating the adhesive layer 47 of the protective tape 45 with ultraviolet rays and reducing an adhesive force of the adhesive layer 47. This step also includes a step of peeling off the base film 46 from the second electrode 24 together with the adhesive layer 47.

[0161] Next, with reference to Fig. 14G, the wafer 2 is cut along the plurality of predetermined cutting lines 12. The wafer 2 can be cut (sliced) by a dicing blade or can be cut (cleaved) by a cleaving method using a laser light irradiation step. Through the steps including the above, the semiconductor device SD2 (in this embodiment, the SiC semiconductor device) is manufactured.

[0162] As described so far, the same effects as those described in the wafer structure 1A can also be achieved by the wafer structure 1B. Furthermore, the manufacturing method for the semiconductor device SD2 according to the wafer structure 1B can achieve the same effects as those described in the manufacturing method for the semiconductor device SD2 according to the wafer structure 1A.

[0163] Fig. Fig. 15 is a plan view showing the wafer 2 according to a modified example applied to each of the aforementioned embodiments. The mark 6 of the wafer 2 according to each of the aforementioned embodiments includes an alignment flat. In contrast, with reference to Fig. 15, the mark 6 of the wafer 2 according to the modified example includes an alignment notch hollowed toward the central portion of the first main surface 3 in the side surface 5 in a spindle shape (conical shape or triangular shape).

[0164] The alignment notch may be hollowed in the first direction X or the second direction Y (a-axis direction or m-axis direction) in plan view. Of course, the mark 6 may include a first alignment notch hollowed in the first direction X and a first alignment notch hollowed in the second direction Y. Furthermore, the mark 6 may include at least one alignment flat and at least one alignment notch.

[0165] The second electrode 24 does not need to have a linearly extending portion at a portion along the alignment notch. The second electrode 24 covers the second main surface 4 at a distance inward from the alignment notch so that the alignment notch is exposed. The second electrode 24 may expose the peripheral edge portion of the second main surface 4 in a circular annular shape. That is, the plating reaction inhibiting portion 25 may expose the peripheral edge portion of the second main surface 4 in a circular annular shape in a region along the mark 6 and in a region outside the mark 6.

[0166] The edge portion of the protective band 45 need not have a linearly extending portion at a portion along the alignment notch. The edge portion of the protective band 45 may be formed in a circular shape over an entire circumference of the peripheral edge of the second main surface 4 in plan view.

[0167] Fig. 16 is a schematic cross-sectional view showing the step of forming the second electrode 24 according to a first modified example applied to each of the aforementioned embodiments. Fig. 17 is a schematic cross-sectional view showing the step of forming the second electrode 24 according to a second modified example applied to each of the aforementioned embodiments. Fig. 18 is a schematic cross-sectional view showing the step of forming the second electrode 24 according to a third modified example applied to each of the above embodiments. In each of the above embodiments, the step of forming the second electrode 24 using the masking jig 50 has been described.

[0168] Referring to Fig. 16, however, the second electrode 24 may be formed on the second main surface 4 by a lift-off process. In this case, a resist mask 81 is formed on the second main surface 4 instead of the masking jig 50, and the resist mask 81 may be removed after the film formation of the second electrode 24. Considering the manpower and the stress on the wafer 2, a step of using the masking jig 50 is preferable.

[0169] Of course, with reference to Fig. 17, the second electrode 24 may be formed in a predetermined layout by an etching process. In this case, after the film formation of the second electrode 24 on the second main surface 4, a resist mask 82 having a predetermined layout is formed on the second electrode 24, and the second electrode 24 is formed in the predetermined layout by an etching process over the resist mask 82. After removing unnecessary portions of the second electrode 24, the resist mask 82 is removed. Considering the manpower and the load on the wafer 2, the step of using the masking jig 50 is preferable.

[0170] In addition, with reference to Fig.18, the second electrode 24 may be formed in a predetermined layout by a grinding process. In this case, unnecessary portions of the second electrode 24 may be removed by a chamfer grinding process applied to the peripheral edge portion of the second electrode 24 (peripheral edge portion of the second main surface 4). In this case, the wafer 2 may be partially removed together with a part of the second electrode 24. That is, the plating reaction inhibiting portion 25 may have a step portion 83 extending downward toward the first main surface 3 at the peripheral edge portion of the second main surface 4. In view of the man-hours and the loads on the wafer 2, the step of using the masking jig 50 is preferable.

[0171] Although the embodiments have been described above, each of the embodiments can be implemented in still other ways. For example, in the step of thinning the wafer 2 according to each of the aforementioned embodiments, the second region 8 may be removed until a thickness less than the thickness of the first region 7 is reached. Of course, in the step of thinning the wafer 2 according to each of the aforementioned embodiments, the second region 8 may be completely removed. That is, the wafer 2 may be formed with a single-layer structure made of the first region 7 (SiC epitaxial layer).

[0172] In the above cases, in the step of adhering the protective tape 45, the protective tape 45 having a thickness greater than that of the wafer 2 may be adhered to the second main surface 4 side. When a member that reinforces or supports the wafer 2 is provided on the first main surface 3 side, the protective tape 45 having a thickness smaller than that of the wafer 2 may be adhered to the second main surface 4 side.

[0173] In each of the aforementioned embodiments, an example was shown in which the functional device 13 includes one of an SBD or a MISFET. However, the functional device 13 may include both the SBD and the MISFET. That is, both the SBD and the MISFET may be formed within the same device region 10. Of course, in each of the aforementioned embodiments, the functional device 13 including the SBD and the functional device 13 including the MISFET may be formed in a different device region 10 on the same wafer 2.

[0174] In the aforementioned second embodiment, an example was described in which a trench-gate type MISFET is formed as an example of the functional device 13. However, the functional device 13 may include a planar-gate type MISFET instead of the trench-gate type.

[0175] In the aforementioned second embodiment, a p-type second region 8 may be used instead of the n-type second region 8. In this case, the functional device 13 includes an IGBT (Insulated Gate Bipolar Transistor) instead of the MISFET. In this case, a specific configuration is obtained by replacing a "source" of the MISFET with an "emitter" of the IGBT and replacing a "drain" of the MISFET with a "collector" of the IGBT in the previous description.

[0176] In each of the above embodiments, a configuration was explained in which the first conductivity type is an n-type and the second conductivity type is a p-type. However, in each of the above embodiments, a configuration in which the first conductivity type is a p-type and the second conductivity type is an n-type may be used. In this case, a specific configuration can be obtained by replacing the n-type region with the p-type region and replacing the p-type region with the n-type region in the above description and the accompanying drawings.

[0177] The following shows features extracted from this description and the drawings. Hereinafter, alphanumeric characters in parentheses represent corresponding components, etc., in each of the above-mentioned embodiments, but this representation does not imply that the scope of each clause is limited to the embodiments. The "wafer structure" according to the following clauses may be replaced with a "wide bandgap semiconductor wafer structure," a "SiC wafer structure," etc., as needed. In addition, the "semiconductor device" according to the following clauses may be replaced with a "wide bandgap semiconductor device," a "SiC semiconductor device," etc., as needed.

[0178] [A1] A wafer structure (1A, 1B) comprising: a wafer (2) having a first surface (3) on one side and a second surface (4) on the other side; a first electrode (18) covering the first surface (3); a second electrode (24) covering an inner portion of the second surface (4) so ​​as to expose a peripheral edge portion of the second surface (4); and a protective tape (45) having properties such that adhesion to the peripheral edge portion of the second surface (4) is higher than adhesion to the second electrode (24), and which is adhered to the peripheral edge portion of the second surface (4) and the second electrode (24).

[0179] [A2] The wafer structure (1A, 1B) according to A1, wherein the second electrode (24) has a plating reaction speed higher than a plating reaction speed of the wafer (2) and exposes the peripheral edge portion of the wafer (2) as a plating reaction inhibiting portion (25), and the protective tape (45) is adhered to the plating reaction inhibiting portion (25).

[0180] [A3] The wafer structure (1A, 1B) according to A1 or A2, wherein the wafer (2) includes a SiC single crystal, the second electrode (24) exposes the SiC single crystal from the peripheral edge portion of the second surface (4), and the protective tape (45) is bonded to the SiC single crystal at the peripheral edge portion of the second surface (4).

[0181] [A4] Wafer structure (1A, 1B) according to one of A1 to A3, wherein the wafer (2) has a thickness of less than 200 µm.

[0182] [A5] The wafer structure (1A, 1B) according to any one of A1 to A4, wherein the second electrode (24) exposes an entire periphery of the peripheral edge portion and the protective tape (45) is adhered to the entire periphery of the peripheral edge portion.

[0183] [A6] The wafer structure (1A, 1B) according to any one of A1 to A5, wherein an exposure width (W) of the peripheral edge portion is greater than a thickness of the second electrode (24).

[0184] [A7] Wafer structure (1A, 1B) according to A6, wherein the exposure width (W) is greater than a thickness of the wafer (2).

[0185] [A8] Wafer structure (1A, 1B) according to one of A1 to A7, wherein the wafer (2) has a second surface (4) having a grinding mark, the second electrode (24) exposes the peripheral edge portion having the grinding mark, and the protective tape (45) is adhered to the peripheral edge portion having the grinding mark.

[0186] [A9] Wafer structure (1A, 1B) according to one of A1 to A8, wherein the second surface (4) is made of a flat surface or as a flat surface.

[0187] [A10] The wafer structure (1A, 1B) according to any one of A1 to A9, further comprising: a plating film (51) covering the first electrode (18).

[0188] [A11] The wafer structure (1A, 1B) according to A10, wherein the plating film (51) includes at least one of a Ni plating film (52), a Pd plating film (53), and an Au plating film (54).

[0189] [A12] The wafer structure (1A, 1B) according to any one of A1 to A11, further comprising: device regions (10) arranged in an inner portion of the first surface (3); and wherein the second electrode (24) exposes a region outside the device regions (10) in plan view.

[0190] [A13] A manufacturing method for a semiconductor device (SD1, SD2), comprising: a step of preparing a wafer structure (1A, 1B) including a wafer (2) having a first surface (3) on one side and a second surface (4) on the other side, and a first electrode (18) covering the first surface (3); a step of forming a second electrode (24) covering an inner portion of the second surface (4) so ​​as to expose a peripheral edge portion of the second surface (4); and a step of adhering a protective tape (45) having properties that adhesion to the peripheral edge portion of the second surface (4) is higher than adhesion to the second electrode (24), to the peripheral edge portion of the second surface (4) and to the second electrode (24).

[0191] [A14] A manufacturing method for the semiconductor device (SD1, SD2) according to A13, wherein the second electrode (24) has a plating reaction speed higher than a plating reaction speed of the wafer (2) and exposes the peripheral edge portion of the wafer (2) as a plating reaction inhibiting portion (25).

[0192] [A15] A manufacturing method for the semiconductor device (SD1, SD2) according to A13 or A14, further comprising: a step of immersing the wafer structure (1A, 1B) in a plating solution in a state where the protective tape (45) is adhered, and forming a plating film (51) on the first electrode (18).

[0193] [A16] A manufacturing method for the semiconductor device (SD1, SD2) according to A15, wherein the step of forming the plating film (51) includes a step of rocking the wafer structure (1A, 1B) in the plating solution.

[0194] [A17] A manufacturing method for the semiconductor device (SD1, SD2) according to A15 or A16, wherein the step of forming the plating film (51) includes at least one of a step of immersing the wafer structure (1A, 1B) in a Ni plating solution and forming a Ni plating film (52), a step of immersing the wafer structure (1A, 1B) in a Pd plating solution and forming a Pd plating film (53), and a step of immersing the wafer structure (1A, 1B) in an Au plating solution and forming an Au plating film (54).

[0195] [A18] A manufacturing method for the semiconductor device (SD1, SD2) according to any one of A13 to A17, wherein the wafer (2) includes a SiC single crystal, the second electrode (24) exposes the SiC single crystal from the peripheral edge portion of the second surface (4), and the protective tape (45) is bonded to the SiC single crystal at the peripheral edge portion of the second surface (4).

[0196] [A19] A manufacturing method for the semiconductor device (SD1, SD2) according to any one of A13 to A18, further comprising: a step of manufacturing the wafer structure (1A, 1B) including the wafer (2) having a thickness of not less than 200 µm, and a step of thinning the wafer (2) until the wafer (2) reaches a thickness of less than 200 µm, before the step of forming the second electrode (24).

[0197] [A20] A manufacturing method for the semiconductor device (SD1, SD2) according to A19, wherein the step of thinning the wafer (2) includes a step of grinding the second surface (4) by a grinding process.

[0198] Although embodiments of the present invention have been described in detail above, these are merely specific examples used to clarify the technical content. The various technical ideas extracted from this description are not limited by the order of description, the order of embodiments, etc. in the description, and can be combined with each other at will. List of reference symbols 1A wafer structure 1B wafer structure 2 wafers 3 first main interface 4 second main interface 10 Fixture area 18 first electrode 24 second electrode 25 section inhibiting the plating reaction 45 protective tape 51 Plating film 52 Ni plating film or layer 53 Pd plating film 54 Au plating film W Exposed width SD1 semiconductor device SD2 semiconductor device QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-095664

[0001] US 2022-0020628

[0003]

Claims

[1] Wafer structure comprising: a wafer having a first surface on one side and a second surface on the other side; a first electrode covering the first surface; a second electrode covering an inner portion of the second surface such that a peripheral edge portion of the second surface is exposed; and a protective tape having properties such that adhesion to the peripheral edge portion of the second surface is higher than adhesion to the second electrode, and which is adhered to the peripheral edge portion of the second surface and the second electrode. [2] Wafer structure according to claim 1, wherein the second electrode has a plating reaction rate higher than a plating reaction rate of the wafer, and exposes the peripheral edge portion of the wafer as a plating reaction inhibiting portion, and the protective tape is glued to the section that inhibits the plating reaction. [3] Wafer structure according to claim 1 or 2, wherein the wafer includes a SiC single crystal, the second electrode exposes the SiC single crystal from the peripheral edge portion of the second surface, and the protective tape is bonded to the SiC single crystal at the peripheral edge portion of the second surface. [4] Wafer structure according to one of claims 1 to 3, wherein the wafer has a thickness of less than 200 µm. [5] Wafer structure according to one of claims 1 to 4, wherein the second electrode exposes an entire circumference of the peripheral edge portion, and the protective tape is glued to the entire circumference of the peripheral edge section. [6] The wafer structure according to any one of claims 1 to 5, wherein an exposure width of the peripheral edge portion is larger than a thickness of the second electrode. [7] The wafer structure of claim 6, wherein the exposure width is greater than a thickness of the wafer. [8] Wafer structure according to one of claims 1 to 7, wherein the wafer has the second surface having a grinding track, the second electrode exposes the peripheral edge section with the grinding track, and the protective tape is glued to the peripheral edge section with the grinding mark. [9] The wafer structure according to any one of claims 1 to 8, wherein the second surface is made of a flat surface. [10] Wafer structure according to one of claims 1 to 9, further comprising: a plating film covering the first electrode. [11] The wafer structure according to claim 10, wherein the plating film includes at least one of a Ni plating film, a Pd plating film, and an Au plating film. [12] Wafer structure according to one of claims 1 to 11, further comprising: Device regions arranged in an inner portion of the first surface; and wherein the second electrode exposes an area outside the device areas in plan view. [13] A manufacturing method for a semiconductor device, comprising: a step of manufacturing a wafer structure including a wafer having a first surface on one side and a second surface on the other side, and a first electrode covering the first surface; a step of forming a second electrode covering an inner portion of the second surface so as to expose a peripheral edge portion of the second surface; and a step of adhering a protective tape having properties such that adhesion to the peripheral edge portion of the second surface is higher than adhesion to the second electrode, to the peripheral edge portion of the second surface and to the second electrode. [14] The manufacturing method of the semiconductor device according to claim 13, wherein the second electrode has a plating reaction speed higher than a plating reaction speed of the wafer and exposes the peripheral edge portion of the wafer as a plating reaction inhibiting portion. [15] A manufacturing method for the semiconductor device according to claim 13 or 14, further comprising: a step of immersing the wafer structure in a plating solution in a state where the protective tape is adhered, and forming a plating film on the first electrode. [16] The manufacturing method for the semiconductor device according to claim 15, wherein the step of forming the plating film includes a step of rocking the wafer structure in the plating solution. [17] The manufacturing method for the semiconductor device according to claim 15 or 16, wherein the step of forming the plating film includes at least one of a step of immersing the wafer structure in a Ni plating solution and forming a Ni plating film, a step of immersing the wafer structure in a Pd plating solution and forming a Pd plating film, and a step of immersing the wafer structure in an Au plating solution and forming an Au plating film. [18] A manufacturing method for the semiconductor device according to any one of claims 13 to 17, wherein the wafer includes a SiC single crystal, the second electrode exposes the SiC single crystal from the peripheral edge portion of the second surface, and the protective tape is bonded to the SiC single crystal at the peripheral edge portion of the second surface. [19] A manufacturing method for the semiconductor device according to any one of claims 13 to 18, further comprising: a step of manufacturing the wafer structure, which includes the wafer having a thickness of not less than 200 µm, and a step of thinning the wafer until the wafer reaches a thickness of less than 200 µm, prior to the step of forming the second electrode. [20] The manufacturing method for the semiconductor device according to claim 19, wherein the step of thinning the wafer includes a step of grinding the second surface by a grinding process.

Images