Wideband LNA architectures with advanced impedance matching

Abstract

Circuits and methods for an amplifier (particularly LNAs) that achieve broadband output impedance matching and high gain while simultaneously suppressing out-of-band (OOB) harmonics. Some embodiments allow multiple operating modes to enable a choice of gain versus linearity characteristics. One aspect of the present invention is to improve the linearity and sensitivity of an entire RF front-end (RFFE) receiver chain by suppressing OOB gain within an LNA component at higher-order harmonic frequencies. Another aspect of the present invention is novel broadband and ultra-wideband LNA load circuits that maintain high in-band gain and broadband output impedance matching while achieving high-frequency OOB rejection.Another aspect of the present invention is novel ultra-wideband LNA output impedance matching circuits.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 17 / 855,386, filed June 30, 2022, the contents of which are incorporated herein by reference in their entirety. BACKGROUND(1) Technical field

[0002] The invention relates to electronic circuits, in particular to high-frequency amplifier circuits. (2) Background

[0003] Many modern electronic systems contain radio frequency (RF) receivers; examples include mobile phones, personal computers, tablet computers, wireless network components, televisions, cable system set-top boxes, and radar systems. Many RF receivers are connected to RF transmitters in the form of transceivers, which are often quite complex two-way radio devices. In some cases, RF transceivers can transmit and receive on multiple frequencies in multiple frequency bands.

[0004] Amplifiers are a common component in RF transmitters, receivers, and transceivers and are often used to amplify the energy of transmitted RF signals and provide low-noise amplification of received RF signals. For many RF systems, particularly those requiring low power and / or portability (e.g., mobile phones, Wi-Fi-enabled computers, cameras, and other devices), it has become common practice to use complementary metal-oxide-semiconductor (CMOS) manufacturing processes to create low-cost, low-power integrated circuits (ICs). CMOS devices include bulk CMOS, silicon-on-insulator (SOI) CMOS, and silicon-on-sapphire (SOS) CMOS (SOS is a type of SOI manufacturing technology).

[0005] Fig.1 is a simplified schematic diagram of a generalized embodiment of a prior art low noise amplifier (LNA) circuit 100. In the illustrated example, the LNA circuit 100 includes an amplifier block 102 with a stack of two series-connected FETs M CS , M CG in a cascode arrangement. An RF IN applied RF input signal can be passed through an input impedance matching circuit 104 and connected to the gate of the lower common-source FET M CS The source of the lower FET M CS is usually via an inductor L DEG connected to a reference potential, e.g. circuit ground.

[0006] The source of the upper common-gate FET M CG is connected to the drain of the lower FET M CS The drain of the upper FET M CGdelivers an amplified RF output signal via a DC blocking capacitor C to an RF output terminal RF OUT . The capacitor C can also help to adjust the output impedance. An inductor L is connected between a source voltage V DD and the drain of the upper FET M CG connected to assist impedance matching and provide bias voltage for the amplifier block 102. In the example shown, the RF output terminal RF OUT connected to a typical load known as resistance R L The value of R L is typically 50 ohms in many modern RF circuits.

[0007] A bias circuit 106 is configured to provide a suitable bias voltage CG_V BIAS to the upper common gate FET M CG and a suitable preload CS_V BIAS to the lower common-source FET M CSin a known manner. Additional known circuit elements that may be included in some applications, such as bypass capacitors, have been omitted for clarity.

[0008] Important desired properties of an LNA are high gain with low noise, wide bandwidth, good linearity, and a good output impedance match. Accordingly, four important design parameters for LNAs are gain, noise figure (NF), input-referred third intercept point (IIP3), and output reflection coefficient. NF is a measure of the signal-to-noise ratio (SNR) degradation caused by components in a signal chain, with lower values ​​indicating better performance. IIP3 is a measure of the amplifier's linearity, with higher values ​​indicating better performance. In general, NF requirements are more stringent in high-gain modes than in low-gain modes, while IIP3 requirements are more stringent in low-gain modes than in high-gain modes. The output reflection coefficient is the S 22-Scatter parameter (or “S-parameter”) and is an indication of the output impedance match, with lower (more negative when viewed logarithmically) numbers indicating better impedance match.

[0009] The increase in the frequency of RF communication bands and channels, as well as the continuous growth in the number of bands and channels in use, has pushed current LNA architectures to their limits. For example, it is not possible to meet the stringent gain, percentage bandwidth, linearity, and output impedance matching requirements for some of the new 5G cellular bands with a conventional LNA architecture, particularly in the NR bands from 3 to 6 GHz, the upcoming 7-24 GHz bands, and the millimeter wave range (e.g., 24.25 GHz to 52.6 GHz).

[0010] In the Fig.For example, in the LNA architecture shown in Figure 1, output impedance matching is achieved by a single-stage LC output impedance matching circuit comprising L and C. However, this single-stage LC architecture has limitations depending on the choice of L and C values: either narrowband output impedance matching at high gain or broadband output impedance matching at lower gain (e.g., by reducing the Q factor of the LC architecture). Another limitation of the illustrated architecture is that it has essentially no high-frequency rejection outside of the band (OOB), since the L and C components form a high-pass filter.

[0011] One way to overcome some of the limitations mentioned above in Fig. 1 is to add a low-pass LC filter to achieve broadband matching and some high-frequency OOB rejection. Fig.For example, Figure 2 is a simplified schematic diagram of a generalized embodiment of a prior art LNA circuit 200 having a two-stage LC output impedance matching circuit 202. The LNA circuit 200 of Fig. 2 is similar in most aspects to the LNA circuit 100 of Fig. 1 and includes a two-stage LC output impedance matching circuit 202 including a second inductor L' connected between the terminal RF OUT and the first capacitor C, and a second capacitor C' connected between V DD and a node connected between C and L'. The added LC elements form a low-pass filter. Although the resulting LNA circuit 200 is smaller than the LNA circuit 100 of Fig.1 has a wider-bandwidth output impedance matching characteristic, it still does not achieve the high gain required for 5G mobile network bands and other high-frequency applications. Furthermore, the increased circuitry of the two-stage LC output impedance matching circuit 202 impairs linearity due to energy losses in the LC low-pass filter. Compared to the single-stage LC output impedance matching, the voltage swing at the drain of the common-gate FET M CG be larger to compensate for the loss in the two-stage LC output impedance matching, which reduces the linearity to achieve the same gain.

[0012] Another possible architecture is to limit the OOB frequencies by inserting a bandpass filter between the source of the RF INsignal (e.g. an antenna) and the LNA input, which, however, reduces the gain and the noise figure and thus degrades the sensitivity of the receiver.

[0013] Accordingly, there is a need for an LNA architecture that overcomes these limitations of conventional LNA architectures. SUMMARY

[0014] The present invention encompasses circuits and methods for an LNA that achieves broadband output impedance matching and high gain while suppressing out-of-band harmonic frequencies. Some embodiments allow multiple operating modes to enable the selection of gain versus linearity characteristics. The inventive circuits and methods can also be applied to other amplifier types, such as power amplifiers.

[0015] One aspect of the present invention is to improve the linearity and sensitivity of an entire RF front-end (RFFE) receiver chain by suppressing out-of-band gain within an LNA component at higher-order harmonic frequencies (such as second-, third-, and higher-order harmonic frequencies). Otherwise, these higher-order OOB harmonic frequencies may be downconverted by circuits downstream of the LNA circuit and degrade receiver performance.

[0016] Another aspect of the present invention is novel wideband and ultra-wideband LNA load circuits that provide high in-band gain and wideband output impedance matching while achieving high-frequency OOB rejection.

[0017] Another aspect of the present invention is novel ultra-wideband LNA output impedance matching circuits.

[0018] Some embodiments include a load circuit configured to be connected between a high-frequency amplifier core and an output terminal, the load circuit comprising: a first LC resonator connected between the high-frequency amplifier core and a node, the first LC resonator including a first inductor and a first capacitor connected in parallel; a matching and biasing circuit connected to the node and configured to be connected to a power supply, the matching and biasing circuit including a second inductor and a second capacitor connected in parallel;and a second LC resonator connected between the node and the output terminal, the second LC resonator including a capacitor connected to the output terminal, and a third inductor and a third capacitor connected in parallel with each other and in series with the capacitor.;

[0019] Some embodiments include a load circuit configured to be connected between a high-frequency amplifier core and an output terminal, the load circuit comprising: a first inductor connected between the high-frequency amplifier core and a node; a first resistor connected in parallel with the first inductor between the high-frequency amplifier core and the node; a second inductor connected to the node and configured to be connected to a power supply; a second resistor connected in parallel with the second inductor and connected to the node and configured to be connected to the power supply; and a capacitor connected between the node and the output terminal.

[0020] Some embodiments include a load circuit configured to be connected between a high-frequency amplifier core and an output terminal, the load circuit comprising: a first inductor connected between the high-frequency amplifier core and a node; a second inductor connected to the node and configured to be connected to a power supply; a capacitor connected between the node and the output terminal; and a feedback circuit connected between the input terminal and a feedback node in an output signal path of the amplifier core and selectively switchable between enabled and disabled, the feedback circuit comprising a capacitor, a resistor, and a switch connected in series.

[0021] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Further features, objects, and advantages of the invention will become apparent from the description and drawings, as well as from the claims. DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a simplified schematic diagram of a generalized embodiment of a prior art low noise amplifier (LNA) circuit. Fig. Figure 2 is a simplified schematic diagram of a generalized embodiment of a prior art LNA circuit with a two-stage LC output impedance matching circuit. Fig. Figure 3A is a simplified schematic diagram of a first embodiment of a wideband LNA circuit according to the present invention. Fig.Figure 3B is a graph showing an example of LNA gain / loss as a function of frequency for a modeled implementation of the Fig. 3A shows the LNA circuit. Fig. Figure 3C is a graph showing the LNA gain / loss as a function of frequency for a modeled implementation of the Fig. 3A with a modeled conventional broadband LNA. Fig. Figure 4 is a simplified schematic diagram of a second embodiment of a wideband LNA circuit according to the present invention. Fig. Figure 5A is a simplified schematic diagram of an LNA circuit with broadband output impedance matching. Fig. Figure 5B is a representation of an equivalent circuit that Fig. 5A approximately replicates the LNA circuit shown. Fig.Figure 6 is a simplified schematic diagram of a first embodiment of an ultra-wideband LNA circuit with improved output impedance matching according to the present invention. Fig. Figure 7 is a simplified schematic diagram of a second embodiment of an ultra-wideband LNA circuit with improved output impedance matching according to the present invention. Fig. Figure 8A is a simplified schematic diagram of a first combined embodiment of an ultra-wideband LNA circuit with improved output impedance matching according to the present invention. Fig. 8B is a simplified schematic diagram of a second combined embodiment of an ultra-wideband LNA circuit with improved output impedance matching according to the present invention Fig. Figure 9 is a schematic diagram of an improved input impedance matching circuit. Fig. 10 is a plan view of a substrate, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin film tile). Fig. 11 shows an exemplary prior art wireless communication environment that includes various wireless communication systems and may include one or more mobile wireless devices. Fig. 12 is a block diagram of a transceiver that could be used in a wireless device, such as a cellular phone, and in which an embodiment of the present invention may be advantageously employed to improve performance. Fig. 13 is a process flow diagram showing a method for achieving broadband output impedance matching and high gain for a high-frequency amplifier having an amplifier core and an output terminal.

[0022] Like reference numbers and designations in the different drawings indicate like elements unless the context requires otherwise. DETAILED DESCRIPTION

[0023] The present invention encompasses circuits and methods for an LNA that achieves broadband output impedance matching and high gain while suppressing out-of-band harmonic frequencies. Some embodiments allow multiple operating modes to facilitate the selection of gain versus linearity characteristics. The inventive circuits and methods can also be applied to other amplifier types, such as power amplifiers. General concepts

[0024] One aspect of the present invention is to improve the linearity and sensitivity of an entire RF front-end (RFFE) receiver chain by suppressing out-of-band gain within an LNA component at higher-order harmonic frequencies (such as second-, third-, and higher-order harmonic frequencies). Otherwise, these higher-order OOB frequencies may be downconverted by circuitry downstream of the LNA, degrading receiver performance.

[0025] Another aspect of the present invention is novel wideband and ultra-wideband LNA load circuits that provide high in-band gain and wideband output impedance matching while achieving high-frequency OOB rejection.

[0026] Another aspect of the present invention is novel ultra-wideband LNA output impedance matching circuits.

[0027] For the purposes of this disclosure, “narrowband”, “wideband”, and “ultra-wideband” can be characterized as a percentage of bandwidth that is equal to (stop frequency f STOP minus starting frequency f START ) divided by the center frequency f CENTER a volume or (f STOP - f START ) / f CENTER (expressed in percent), where f CENTER = (f STOP + f (START) ) / 2. TABLE 1 below shows typical guidelines (not strict definitions) for characterizing typical percentage bandwidths. TABLE 1 Nominal band name % bandwidth range narrowband < 7,5% Extended narrowband 7,5%~15% Broadband 15%~25% Ultra-broadband > 25%

[0028] TABLE 2 provides examples of common mobile bands and their classification as broadband or ultra-wideband using the guidelines in TABLE 1 TABLE 2 Typical application f START (GHz) f STOP (GHz) f CENTER (GHz) % Bandwidth Broadband (N77) 3,3 4,2 3,75 24,00% Broadband (N96) 5,925 7,125 6,525 18,39% Ultra Wideband (UWB) 6,2 9 7,6 36,84% First embodiment

[0029] Fig.Figure 3A is a simplified schematic diagram of a first embodiment of a wideband LNA circuit 300 according to the present invention. The circuit below demarcation line 302 may be substantially the same as the corresponding circuit in Figures Fig. 1 and Fig. 2. Accordingly, the LNA circuit 300 includes an amplification core 102 comprising a common-source FET M CS and a common-gate FET M CG in a cascode configuration. The gate of the common-source FET M CS can be considered as an input terminal INT of the amplification core 102, the source of the common-source FET M CS can be considered as a degeneration terminal DT of the amplification core 102, and the drain of the common-gate FET M CGcan be considered as an amplified signal terminal AST of the amplification core 102. Below the demarcation line 302 there are also an input impedance matching circuit 104, a bias circuit 106 and a degeneration inductor L connected to a reference potential. DEG .

[0030] Although the reinforcement core 102 in Fig. 3A is shown with only a pair of series-connected FET devices, additional FET devices may be included. For example, in some embodiments, to overcome a relatively low breakdown voltage per CMOS FET, multiple common-gate FETs in a FET stack may be connected in series between the drain of the lowest common-gate FET M CG and the amplified signal terminal AST, ie, the amplification core 102 may comprise several common-gate FETs connected in series in a cascode configuration. An example of such a configuration is shown in Fig.4 and is described below.

[0031] Above the demarcation line 302 there is an improved load circuit comprising a first LC resonator 304 connected between the amplified signal terminal AST of the amplifier core 102 and a node X, a matching and biasing circuit 306 connected between a power supply V DD and the node X, and comprises a second LC resonator 308 connected between the node X and the output terminal RF OUT In the example shown, the RF output connector RF OUT connected to a typical load known as resistance R L is shown.

[0032] The first LC resonator 304 includes an inductor L1 and a capacitor C1 connected in parallel between the node X and the amplified signal terminal AST. The matching and biasing circuit 306 includes an inductor L2 and a capacitor C2 connected in parallel between V DD and the node X. The second LC resonator 308 comprises an inductor L3 and a capacitor C3 connected in parallel and between the node X and a DC blocking capacitor C BLK which in turn is connected to RF OUT In alternative embodiments, C BLK be arranged between the node X and the second LC resonator 308. Note that the capacitor C BLK , which is a DC blocking capacitor, is not essential for the broadband performance of the invention. Rather, the capacitor C BLKor an equivalent is required, since L1 and L3 otherwise form a DC path from the amplifier block 102 to RF OUT In some embodiments, the capacitor C BLK However, this may be unnecessary if the DC loss in the resistor R L is acceptable or if the RF OUT connected circuit contains a DC blocking capacitor or equivalent.

[0033] In integrated circuit embodiments, C1, C2 and C3 may be partially implemented as the parasitic capacitor of their respective on-chip inductors L1, L2, L3 due to the finite self-resonant frequency (SRF) of the inductors.

[0034] Note that C2 and L3 form a low-loss low-pass filter (LPF), while L1 and C1 in the first LC resonator 304 and L3 and C3 in the second LC resonator 308 act as low-loss band-stop filters, respectively.

[0035] At a frequency of interest (e.g. fo = 3.75 GHz), the combination of L1, L2, C2 and L3 forms a second-order output impedance matching circuit that achieves a wider bandwidth than the circuits of the Fig. 1 and Fig. 2. This topology also has higher gain because the inductors L1 and L3 are connected in series, which increases the load impedance at the AST node.

[0036] The improved load circuit achieves high OOB suppression of at least the second to fifth harmonic frequencies (2fo, 3fo, 4fo and 5fo) as follows: • In the first LC resonator 304, L1 and C1 create a very high impedance (almost an “open” circuit) in the signal path to achieve OOB rejection at ~2fo; • The LPF formed by C2 and L3 improves OOB suppression at 3fo and 4fo; and • In the second LC resonator 308, L3 and C3 improve the OOB suppression to ~5fo.

[0037] Fig. 3B is a graph 350 illustrating an example of LNA gain / loss as a function of frequency for a modeled implementation of the Fig. 3A. For the modeled circuit, the inductance and capacitance values ​​given in TABLE 3 below and a value of approximately 3.75 GHz for fo were used. TABLE 3 Example of implementation L1 5 nH SRF = 7.1 GHz C1 100 fF L2 2.4 nH SRF = 3.4 GHz C2 920 fF L3 1.9 nH SRF = 23.1 GHz C3 25 fF

[0038] Referring to diagram line 352, the combination of L1, L2, C2 and L3 results in an impedance match of the LNA output RF OUT to the load R L(e.g., 50 ohms) and provides high gain at the frequency of interest fo. L1 and C1 resonate at about 2fo, thereby suppressing this OOB harmonic frequency; the location of the corresponding dip can be adjusted by changing the value of C1. C2 and L3 improve OOB suppression at 3fo and 4fo; C2 has a particular effect on OOB gain at 3fo and 4fo (the larger C2, the more gain, but larger C2 values ​​can reduce in-band gain flatness). L3 and C3 resonate at about 5fo, thereby suppressing this OOB harmonic frequency.

[0039] Fig. Figure 3C is a graph 360 showing the LNA gain / loss as a function of frequency for a modeled implementation of the Fig. 3A with a modeled conventional broadband LNA. Graph line 362 shows the gain / loss for the modeled implementation of the LNA shown in Fig.3A, while the graph line 364 shows the gain / loss for the modeled conventional broadband LNA, such as the LNA circuit 100 of Fig. 1, shows (note that the values ​​of the LC components used to generate Fig. 3C differ from the values ​​of the LC components used to generate Fig. 3B, and that therefore the harmonic frequencies occur at different points). As the comparison shows, the modeled version of the Fig. The LNA circuit shown in Figure 3A exhibits significantly better suppression of OOB harmonic frequencies while achieving high broadband gain at fo. Second embodiment

[0040] Fig.Figure 4 is a simplified schematic diagram of a second embodiment of a wideband LNA circuit 400 according to the present invention. The illustrated embodiment demonstrates the addition of a number of switches and other components that provide flexibility in programmatically adapting the LNA circuit 400 to operate in a number of different modes, allowing for trade-offs between gain, bandwidth, and linearity.

[0041] The LNA circuit 400 includes an amplification core 402 which includes a common-source FET M CS and a common-gate FET M CG in a cascode configuration. Accordingly, the gate of the common-source FET M CS be considered as an input terminal INT of the amplification core 402, the source of the common-source FET M CS can be considered as a degeneration terminal DT of the gain core 402, and the drain of the common-gate FET M CGcan be considered as an amplified signal terminal AST of the gain core 402. In some embodiments, to overcome a relatively low breakdown voltage per CMOS FET, multiple common-gate FETs in a FET stack 404 can be connected between the drain of the lowest common-gate FET M CG and the amplified signal terminal AST, i.e., the amplification core 402 can have multiple common-gate FETs connected in series in a cascode configuration. The amplified signal terminal AST would then be the drain of the topmost common-gate FET in the amplifier core 402.

[0042] The degeneration terminal DT is typically connected to a reference potential, e.g., circuit ground, via a degeneration circuit 406. In some embodiments, the degeneration circuit 406 may include an adjustable degeneration inductance L DEGinclude, for example, an induction coil in an integrated multi-channel circuit. An adjustable inductor L DEG can be used to improve linearity in low-gain modes. For example, a smaller value for the inductor L DEG in higher gain modes and a larger value for the inductor L DEG used in lower gain modes. Some embodiments of the degeneration circuit 406 may include a bypass switch Sw BP which is parallel to the degeneration inductance L DEG is switched on.

[0043] An RF input signal connected to an RF input terminal RF IN can be passed through an input impedance matching circuit 104 and connected to the gate of the lower common-source FET M CS A bias circuit 106 is configured to provide a suitable bias voltage CG_V BIAS to the common gate FET M CGand a suitable preload CS_V BIAS to the common-source FET M CS to deliver as described above.

[0044] Some embodiments may include an input matching feedback circuit 408. The feedback circuit 408 is shown connected between the input terminal INT and the amplified signal terminal AST. More generally, the input matching feedback circuit 408 may be connected to a feedback node in the output signal path of the gain core 402, which may be the drain of any FET in the gain core 402. The choice of the feedback node for connection to the input matching feedback circuit 408 may be based, for example, on different desired feedback strengths and different desired input impedances.

[0045] In the illustrated embodiment, the input matching feedback circuit 408 includes a DC blocking capacitor C0 connected in series with a switch Sw0, which in turn is connected in series with a resistor R0. In some embodiments, C0 and / or R0 may be adjustable or have fixed values, as shown. In alternative embodiments, the input matching feedback circuit 408 may include one or more parallel switches Sw01, ..., Sw0 n (general Sw0 x ), which in turn are connected to corresponding parallel resistors R01, ..., R0 n (general R0 x ) are connected in series. With n parallel branches of switches / resistors, the tunability of the resistors R0 x equals 2 n (the total number of switching combinations). Note that the values ​​of the resistors R0 xdo not have to be identical. The input matching feedback circuit 408 can be activated by opening all feedback switches Sw0 x be deactivated.

[0046] In alternative embodiments, the capacitor C0, the set of one or more switches Sw0 x and the set of one or more resistors R0 x connected in series in any order. In other alternative embodiments, a single switch Sw0 may be used in combination with an adjustable or fixed resistor R0. In still other embodiments, the switch Sw0 may be omitted, thereby reducing the set of one or more resistors R0 x is permanently connected between the input terminal INT and a feedback node in the output signal path of the gain core 402.

[0047] In different amplification modes, the presence of one or more resistors R0x in the circuit a reduction of the Q factor of the input impedance matching, thereby increasing the bandwidth of the extended LNA circuit 400 at the expense of gain and NF.

[0048] An advantage of using a variable or multi-stage input matching feedback circuit 408 is that multiple resistor values ​​allow for multiple gain modes. For example, LNAs in mobile RF receivers require multiple gain modes depending on the range of input signal strength at the receiver. In addition, by using variable or multi-stage feedback resistors R0 x the need for an output attenuator (as is common with conventional receiver LNAs) is eliminated.

[0049] Further information on the input matching feedback circuit 408 can be found in U.S. Patent Application No. 17 / 337,227, filed June 2, 2021, entitled "Wideband Multi Gain LNA Architecture," which was assigned to the assignee of the present invention and is hereby incorporated by reference.

[0050] The LNA circuit 400 includes a modified, improved load circuit including a modified first LC resonator 414 connected between the amplified signal terminal AST of the amplifier core 402 and a terminal X, a modified matching and biasing circuit 416 connected between a power supply V DD and the terminal X, and comprises a modified second LC resonator 418 connected between the terminal X and the output terminal RF OUT In the example shown, the RF output connector RF OUTconnected to a typical load known as resistance R L is shown.

[0051] The modified first LC resonator 414 includes an inductor L1, a capacitor C1, and an additional switch Sw1 connected in parallel between node X and the amplified signal terminal AST. Both L1 and C1 can be adjustable components or have fixed values, as shown. The switch Sw1 allows L1 and C1 to be bypassed, e.g., programmatically or when adjusting performance characteristics of the LNA circuit 400 (e.g., at the time of manufacture or incorporation into a larger circuit or system).

[0052] The modified matching and biasing circuit 416 includes an inductor L2 connected between V DD and node X. A capacitor C2 is connected between V DDand node X (and thus parallel to L2), optionally via a switch Sw2a. A resistor R2 is connected between V DDand node X (and thus in parallel with L2), optionally via a switch Sw2b. L2, C2 and / or R2 can be adjustable components as shown or have fixed values. Switches Sw2a, Sw2b allow C2 and / or R2 to be configured as selectively enabled or in-circuit (i.e., switch closed) or selectively disabled or out-of-circuit (i.e., switch open). The state of switches Sw2a, Sw2b can be set, for example, programmatically or when setting the performance characteristics of LNA circuit 400. When switch Sw2b is set to switch R2 into circuit, or when switch Sw2b is omitted (and R2 is thus permanently connected in circuit), then R2 "de-Qs" inductor L2 (i.e., it reduces the Q of inductor L2), thereby decreasing gain but increasing bandwidth.The tunability of resistor R2 allows for variable gain reduction, with a smaller resistor providing wider bandwidth by further de-Qing inductor L2. The tunability of capacitor C2 allows for better matching of the output impedance in low-gain modes.

[0053] The modified second LC resonator 418 includes a DC blocking capacitor C in parallel and between the nodes X and BLK connected an inductor L3, a capacitor C3 and a switch Sw3, which in turn is connected to RF OUT Both L3 and C3 can be adjustable components, as shown, or have fixed values. Switch Sw3 can be used to bridge L3 and C3, e.g., programmatically or when setting the performance characteristics of the LNA circuit 400.

[0054] As described above, C2 and L3 form a low-loss low-pass filter (LPF), while L1 and C1 in the modified first LC resonator 414 and L3 and C3 in the modified second LC resonator 418 act as low-loss band-stop filters, respectively. In integrated circuit embodiments, C1, C2, and C3 can be partially implemented as a parasitic capacitor of their respective on-chip inductors L1, L2, and L3 due to the finite natural resonant frequency (SRF) of the inductors.

[0055] The Fig.The architecture exemplified in Figure 4 provides programmability that includes switching between different modes of component configurations and component values ​​to achieve a trade-off between gain, bandwidth, and linearity while ensuring broadband output matching and high OOB rejection. For example, in a low-gain mode, L1 and C1 are bypassed by closing switch Sw1, and R2 is connected in parallel with L2 and C2 by closing switch Sw2b, resulting in a reduction in gain and de-Q'ing of the output network to increase bandwidth. Since the losses in the load circuit are lower when L1 and C1 are bypassed, a smaller voltage swing results at the drain of the upper common-gate FET M for the same gain. CG, resulting in better linearity. As described above, broadband output impedance matching is achieved by the LC network formed by C2 and L3, which also acts as a low-pass filter to achieve OOB rejection even in the low-gain sample mode. C2 is tunable to achieve better output matching in the low-gain sample mode.

[0056] In a high gain mode, switch Sw1 is opened, switching L1 and C1, and R2 is turned off by opening switch Sw2b, resulting in an increase in gain and no de-Q'ing of the output network, but slightly reducing the bandwidth.

[0057] Other operating modes can be achieved by selectively opening and closing the switches Sw0, Sw1, Sw2a, Sw2b, Sw3 and Sw BPcan be achieved, allowing trade-offs between gain, bandwidth, and linearity by calling up different gain modes. Furthermore, if some or all of the inductors L1, L2, L3, the capacitors C0, C1, C2, C3, and / or the resistors R0, R2 are adjustable—particularly dynamically, e.g., programmatically, adjustable—trade-offs between gain, bandwidth, and linearity can be achieved by calling up different gain modes. Improvements in ultra-wideband output impedance matching

[0058] For applications that use a standalone RFFE configured to interface with other circuits, such as LNAs at antenna sites, the LNA should have a good output impedance match to these other circuits—typically 50 ohms for many modern RF circuits—across the operating frequency. In ultra-wideband applications, achieving this design goal with high gain is difficult.

[0059] For a single-stage LNA, wideband output impedance matching can be achieved by the LNA architectures described above and by an LNA architecture as described in the aforementioned U.S. Patent Application No. 17 / 337,227. To achieve even wider output impedance matching for ultra-wideband LNAs, the Q of the output impedance matching network can be lowered by de-Qing the output network's inductors, resulting in lower gain but better output impedance matching. One aspect of the present invention is a novel LNA architecture implementing a new de-Qing technique that lowers the Q of the output impedance matching network while achieving a better gain-to-bandwidth tradeoff to achieve the required performance for ultra-wideband applications.

[0060] An overview of a basic broadband LNA architecture can be useful to better understand the challenge of designing good output impedance matching. Fig. Figure 5A is a simplified schematic diagram of an LNA circuit 500 with broadband output impedance matching. The circuit below demarcation line 502 may be substantially the same as the corresponding circuit in Figures Fig. 1 and Fig. 2. The impedance at the drain of the upper common-gate FET M CG of the reinforcement core 102, Z DRAIN , is shown by a dashed line. The inductors L1 and L2 and the DC blocking capacitor C BLK are as shown with a load resistance R LA bypass switch Sw1, connected in parallel with L1, allows L1 to be bypassed (switched out of the circuit) or connected (switched into the circuit). Switching the inductor L1 (i.e., switching Sw1 to the OPEN state) extends the bandwidth of the output impedance matching network.

[0061] Fig. 5B is a drawing of an equivalent circuit 550 that approximates the Fig. 5A is modeled. The circuit in Fig. 5A, which includes the input impedance matching network 104 and the amplifier block 102, can be approximately considered as a current source I S parallel to a resistor R D and a capacitor C D The impedance Z DRAIN of the upper common-gate FET M CG of the amplifier core 102 is shown by a dashed line, ie the resistance R D and the capacitor C Dhave the same output impedance as the impedance towards the drain of the FET M CG . The combination of C D , L1, L2 and C BLK forms a second-order output impedance matching network for broadband matching. (The inductor L2, which is Fig. 5A than with V DD connected, can be modeled as connected to the circuit ground at the operating frequency, as shown in Fig. 5B).

[0062] The transformation Q of the output impedance matching network is proportional to R D / R L The higher the transformation Q, the smaller the impedance matching bandwidth. As soon as R D and R L are specified, the bandwidth of the impedance matching is the same as the Fig. 5A shown architecture is limited.

[0063] For ultra-wideband LNAs, where even wider output matching is required, the present invention includes two architectures that can be used alone or in combination.

[0064] Fig. Figure 6 is a simplified schematic diagram of a first embodiment of an ultra-wideband LNA circuit 600 with improved output impedance matching according to the present invention. Although the circuit is partially similar to that shown in Fig.5A, but additional elements have been added, including a resistor R1 connected in parallel with inductor L1 and a resistor R2 connected in parallel with inductor L2. Resistors R1 and R2 may have fixed values, but may also be adjustable, as shown. The values ​​of R1 and R2 may be adjusted programmatically or when tuning the performance characteristics of the LNA circuit 600 (e.g., at the time of manufacture or incorporation into a larger circuit or system).

[0065] Resistors R1 and R2 act as de-Q'ing resistors to selectively lower the Q value of the output impedance matching network, thereby achieving a wider bandwidth, with the trade-off being lower gain.

[0066] In an alternative architecture, instead of lowering Q within the output impedance matching network as in the circuit of Fig.6 a resistor parallel to the equivalent resistance R D be added to lower the transformation Q of the output impedance matching network. Fig. For example, Figure 7 is a simplified schematic diagram of a second embodiment of an ultra-wideband LNA circuit 700 with improved output impedance matching according to the present invention. While the circuit is somewhat similar to that shown in Fig. 5A, but additional elements have been added, including an output adjustment feedback circuit 702 connected between the amplified signal terminal AST and the gate of the common-gate FET M CG The output matching feedback circuit 702 in the illustrated embodiment includes a capacitor C FB , which is connected to the switch Sw FB connected in series, which in turn is connected to a resistor R FB connected in series. In some embodiments, C FBand / or R FB have fixed values ​​or, as shown, be adjustable. In alternative embodiments, the capacitor C FB , the switch Sw FB and the resistance R FB can be connected in series in any order.

[0067] Switching from R FB into the circuit or out of the circuit allows two modes of operation, a first mode with a wider bandwidth of output impedance matching and a second mode with a narrower bandwidth of output impedance matching but with higher gain than the first mode.

[0068] If the switch Sw FB CLOSED, connects R FB the amplified signal terminal AST with the gate of the common-gate FET M CG , whereby R FB in the equivalent circuit parallel to R Dswitched (this assumes that there is ultimately an AC path to circuit ground via the CG_V BIAS line of the bias circuit 106). The presence of R FB in the circuit lowers Z DRAIN and reduces the transformation Q of the output impedance matching network, where Q is approximately equal to the real part of Z DRAIN divided by R L or Re(Z DRAIN) / R L Accordingly, the transformation Q is lowered, thereby increasing the impedance matching bandwidth of the LNA circuit 700. This architecture exhibits a better gain-to-bandwidth ratio compared to other known circuits in a variety of applications.

[0069] Conversely, if the switch Sw FB OPEN is R FB with respect to R D in the equivalent circuit is out of order, and the transformation Q of the output impedance matching network is not reduced.

[0070] Embodiments of the Fig. 7 have an advantage over integrated circuit embodiments of the type shown in Fig. 6: The output matching feedback circuit 702, the R FB results in significantly less physical routing relative to inductors L1 and L2, resulting in fewer parasitic inductances and capacitances that could limit bandwidth. Combinations of embodiments

[0071] The circuits according to the invention described above can be combined in various ways as required for particular applications. Fig.For example, Figure 8A is a simplified schematic diagram of a first combined embodiment of an ultra-wideband LNA circuit 800 with improved output impedance matching according to the present invention. The illustrated LNA circuit 800 is similar in most respects to the LNA circuit 400 of Fig. 4, but additionally includes two circuit modifications to improve output impedance matching (note that some embodiments may not include both circuit modifications). The first circuit is an output matching feedback circuit 702 (see Fig. 7) connected between the amplified signal terminal AST and the gate of the common-gate FET M CGThe second addition is a modified first LC resonator circuit 414' that adds a resistor R1 connected in series with an optional deactivation switch Sw1R, the resistor and switch being connected in parallel with the inductor L1 (see Fig. 6).

[0072] Several operating modes can be selected by selectively opening and closing the switches Sw FB (within the output matching feedback circuit 702), Sw0 (within the input matching feedback circuit 408), Sw1, Sw1R, Sw2a, Sw2b, Sw3 and Sw BP as desired, allowing compromises between gain, bandwidth, and linearity by calling different amplification modes. If some or all of the inductors L1, L2, L3, the capacitors C FB (in the output matching feedback circuit 702), C0 (in the input matching feedback circuit 408), C1, C2, C3 and / or the resistors RFB (in the output matching feedback circuit 702), R0 (in the input matching feedback circuit 408), R1, R2 are adjustable - in particular dynamically, e.g. program-controlled, adjustable -, compromises between gain, bandwidth and linearity can also be made by calling up different gain modes.

[0073] As another example, Fig. 8B is a simplified schematic diagram of a second combined embodiment of an ultra-wideband LNA circuit 850 with improved output impedance matching according to the present invention. The LNA circuit 850 is similar in most aspects to the Fig.8A and implements the inductors L1 and L2 as an asymmetric T-coil, as indicated by the dots next to L1 and L2 connected by a dashed arrow k. An asymmetric T-coil is an inductive peaking circuit that can expand the bandwidth of an amplifier and accelerate the rise time of the output signal. As is well known, an asymmetric T-coil contains series-connected inductors (corresponding to the discrete inductors L1 and L2) and an inherent bypass capacitance (not shown) between the inductors. Since a T-coil inherently contains bypass capacitance, the value of the DC-blocking capacitor C BLK possibly compared to the value of C BLK in the LNA circuit 800 of Fig. 8A can be adjusted.

[0074] The implementation of the asymmetric T-coil in an integrated circuit can be in the form of a spiral inductor structure with three taps, in which a first section of the spiral (e.g. from an input tap to a middle tap) corresponds to L1 and a second section of the spiral (e.g. from the middle tap to an output tap) corresponds to L2.

[0075] An advantage of using an asymmetric T-coil instead of the discrete inductors L1 and L2 is that the IC design (e.g. as a spiral inductor structure with three taps) generally saves chip area compared to discrete inductors. Input impedance matching circuit

[0076] The inventive embodiments described above may be further improved by improving certain subcircuits and / or adding additional circuits. For example, while a variety of circuits may be used for the input impedance matching circuit 104 in the various embodiments described above, it may be desirable to use an improved input impedance matching circuit. Fig. For example, Figure 9 is a schematic diagram of an improved input impedance matching circuit 104'. The improved input impedance matching circuit 104' includes a series inductor L SER , which is connected between the RF connector IN and the input terminal INT of the amplification core 102, 402, and a shunt inductor L SH , which is between L SER and a reference potential (e.g. circuit ground). In alternative embodiments, L SHwith L SER on the other side of L SER instead of on the side of the RF IN -connector (note that changing the order of the connections may result in different compromises in input matching bandwidth and noise figure). Both L SER as well as L SH may, as shown, be adjustable components or have fixed values. In embodiments including a degeneration circuit 406, the series shunt inductors L SER , L SH the improved input impedance matching circuit 104' together with the common-source FET M connected to the degeneration circuit 406 CS a double-terminated bandpass filter that increases the input bandwidth of an LNA circuit. Circuit embodiments

[0077] Circuits and devices according to the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be housed in IC packages and / or in modules for ease of handling, manufacturing, and / or improved performance. In particular, IC embodiments of the present invention are often used in modules in which one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) in a package.The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of a final product such as a mobile phone, laptop, or electronic tablet, or to form a higher-level module that can be used in a variety of products such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0078] As an example of further integration of embodiments of the present invention with other components, Fig.10 is a top view of a substrate 1000, which may be, for example, a printed circuit board or a chip module substrate (e.g., a thin-film tile). In the example shown, the substrate 1000 includes a plurality of ICs 1002a-1002d with connection pads 1004 interconnected by vias and / or traces on and / or within the substrate 1000 or on the opposite (rear) surface of the substrate 1000 (to avoid confusion, the surface traces are not shown and not all connection pads are labeled). The ICs 1002a-1002d may include, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuits. IC 1002b may, for example, include one or more instances of an LNA circuit, such as those shown in the Fig. 3A, Fig. 4, Fig. 6, Fig. 7 and Fig. 8 shown circuits 300, 400, 600, 700 and / or 800.

[0079] The substrate 1000 may also include one or more passive devices 1006 embedded in, formed on, and / or attached to the substrate 1000. The passive devices 1006, depicted as general rectangles, may include, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., connected to other passive devices 1006 and / or the individual ICs 1002a-1002d by conductive traces on or in the substrate 1000.

[0080] The front or back surface of substrate 1000 can be used as a site for forming other structures. For example, one or more antennas can be formed on or attached to the front or back surface of substrate 1000; an example of a front-surface antenna 1008 is shown, connected to an IC chip 1002b, which may include RF front-end circuitry. Thus, by incorporating one or more antennas on substrate 1000, a complete radio device can be created. System aspects

[0081] Embodiments of the present invention are useful in a variety of larger radio frequency (RF) circuits and systems, such as radio systems (particularly including cellular radio systems), personal computers, tablet computers, wireless network components, televisions, cable system set-top boxes, radar systems (including phased array and vehicle radar systems), and test equipment.

[0082] Radio system use includes wireless radio frequency systems (including base stations, relay stations, and portable transceivers) that use various technologies and protocols, including various types of orthogonal frequency division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), code-division multiple access (“CDMA”), time-division multiple access (“TDMA”), wide band code division multiple access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.11a, b, g, ac, ax), as well as other radio communication standards and protocols.

[0083] As an example of the use of a wireless RF system, Fig. 11 illustrates an exemplary wireless communication environment 1100 that includes various wireless communication systems 1102 and 1104 and may include one or more mobile wireless devices 1106.

[0084] A wireless device 1106 may be capable of communicating with multiple wireless communication systems 1102, 1104 using one or more of the above-mentioned telecommunications protocols. A wireless device 1106 may also be capable of communicating with one or more satellites 1108, such as navigation satellites (e.g., GPS) and / or telecommunications satellites. The wireless device 1106 may be equipped with multiple external and / or internal antennas to operate at different frequencies and / or to provide diversity against harmful path effects such as fading and multipath interference. A wireless device 1106 may be a cellular phone, a personal digital assistant (PDA), a wireless-enabled computer or tablet, or other wireless communication unit or device. A wireless device 1106 may also be referred to as a mobile station, user equipment, terminal, or other terminology.

[0085] For example, the wireless system 1102 may be a CDMA-based system that includes one or more base station transceivers (BSTs) 1110 and at least one central switching center (SC) 1112. Each BST 1110 provides wireless radio communications to the devices 1106 within its coverage area. The SC 1112 is connected to one or more BSTs in the wireless system 1102 and provides coordination and control of these BSTs.

[0086] For example, the wireless system 1104 may be a TDMA-based system that includes one or more transceiver nodes 1114 and a network center (NC) 1116. Each transceiver node 1114 enables wireless radio communication for the devices 1106 within its coverage area. The NC 1116 connects to one or more transceiver nodes 1114 in the wireless system 1104 and coordinates and controls these transceiver nodes 1114.

[0087] In general, each BST 1110 and each transceiver node 1114 is a fixed station that provides communication coverage for wireless devices 1106 and may also be referred to as a base station or by other terms. The SC 1112 and the NC 1116 are network entities that coordinate and control the base stations and may also be referred to by other terms.

[0088] An important aspect of any wireless system lies in the details of how the system's component elements function. Fig.12 is a block diagram of a transceiver 1200 that could be used in a wireless device, such as a cellular phone, and that may advantageously incorporate an embodiment of the present invention to improve performance. As illustrated, the transceiver 1200 includes a mix of analog RF circuitry for directly transmitting and / or converting signals on an RF signal path, non-RF analog circuitry for operational requirements outside the RF signal path (e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, a receiver path Rx includes the RF front-end, intermediate frequency (IF) block, back-end, and baseband sections (although the distinction between the sections may be different in some implementations). The various sections and circuit elements illustrated may be packaged on one chip or multiple IC chips.For example, in the example shown, the RF front-end may comprise an RFFE module and a mixing block, which may be housed in (or as part of) different IC chips or modules. The different chips and / or modules may be interconnected by transmission lines T. IN and T OUT (e.g. microstrip, coplanar waveguide or an equivalent structure or circuit), one or both of which may have an impedance of e.g. 50 Ω.

[0089] The receiver path Rx receives RF signals over the air via at least one antenna 1202 and a switching unit 1204, which can be implemented with active switching devices (e.g., field-effect transistors or FETs) and / or with passive devices implementing frequency-domain multiplexing, such as a diplexer or duplexer. An RF filter 1206 forwards the desired received RF signals to at least one low-noise amplifier (LNA) 1208a, whose output is coupled via the RFFE module to at least one LNA 1208b in the mixer block (in this example, via the transmission line T IN). The LNA(s) 1208b may provide buffering, input matching, and reverse isolation. The output of the LNA(s) 1208b is combined in a corresponding mixer 1210 with the output of a first local oscillator 1212 to generate an IF signal. The IF signal may be amplified by an IF amplifier 1214 and subjected to an IF filter 1216 before being fed to a demodulator 1218, which may be connected to a second local oscillator 1220. The demodulated output signal of the demodulator 1218 is converted to a digital signal by an analog-to-digital converter 1222 and fed to one or more system components 1224 (e.g., a video graphics circuit, a sound circuit, storage devices, etc.). The converted digital signal may represent, for example, video or still images, sounds, or symbols such as text or other characters.

[0090] In the example shown, a transmitter path Tx comprises the baseband, back-end, IF block, and RF front-end sections (again, the distinction between the sections may be different in some implementations). Digital data from one or more system components 1224 is converted into an analog signal by a digital-to-analog converter 1226, the output of which is applied to a modulator 1228, which may also be connected to the second local oscillator 1220. The modulated output signal of the modulator 1228 may be subjected to an IF filter 1230 before being amplified by an IF amplifier 1232. The output of the IF amplifier 1232 is then combined with the output of the first local oscillator 1212 in a mixer 1234 to generate an RF signal. The RF signal can be amplified by a driver 1236, the output of which is fed to a power amplifier (PA) 1238 (in this example via the transmission line T OUT). The amplified RF signal can be connected to an RF filter 1240, the output of which is connected to at least one antenna 1202 via the switching unit 1204.

[0091] The operation of the transceiver 1200 is controlled in a known manner by a microprocessor 1242, which interacts with system control components 1244 (e.g., user interfaces, storage devices, application programs, operating system software, power management, etc.). In addition, the transceiver 1200 generally includes other circuitry, such as a bias circuit 1246 (which may be distributed throughout the transceiver 1200 near transistor devices), ESD (electrostatic discharge) protection circuitry, test circuitry (not shown), factory programming interfaces (not shown), etc.

[0092] In modern transceivers, there is often more than one receiver path (Rx) and one transmitter path (Tx), for example, to accommodate multiple frequencies and / or signaling modalities. Furthermore, some components of the transceiver 1200 may be arranged in a different order (e.g., filters) or omitted, as should be apparent to one skilled in the art. Other components may be (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.

[0093] As one skilled in the art will understand, an RF system architecture is critically impacted by the current invention, including the selection of a first mode of operation that provides high gain with wide output impedance matching with trade-offs in current, NF, and linearity, and a second mode of operation that provides broadband output impedance matching with improved NF and linearity at lower current and moderate gain. These system-level improvements are specifically enabled by the present invention and allow embodiments of the invention to meet stringent customer performance specifications and a range of RF standards. The present invention is therefore critical to embodiments of the Fig. 12 shown overall system. Proceedings

[0094] Fig.13 is a process flow diagram 1300 illustrating a method for achieving wideband output impedance matching and high gain for a high-frequency amplifier having an amplifier core and a terminal. The method includes: connecting a first LC resonator between the amplifier core and a node, the first LC resonator including a first inductor and a first capacitor connected in parallel (block 1302); connecting a matching and biasing circuit to the node and a power supply, the matching and biasing circuit including a second inductor and a second capacitor connected in parallel (block 1304); and connecting a second LC resonator between the node and the output terminal, the second LC resonator including a third inductor and a third capacitor connected in parallel (block 1306).

[0095] Further aspects of the above method may include modifying the circuit components that implement the method as described above and in the Fig. 3A, Fig. 4, Fig. 6, Fig. 7, Fig. 8 and Fig. 9 shown. Technologies and manufacturing options

[0096] In the Fig. 3A, Fig. 4, Fig. 6, Fig. 7 and Fig. Although the embodiments shown in Figure 8 are LNAs, the circuits and methods according to the invention can also be applied to other types of amplifiers, such as power amplifiers.

[0097] Additional known circuit elements that may be included in some applications, such as DC blocking capacitors, additional impedance matching circuits, and additional filters, have been omitted for clarity. Note also that the value of a circuit component described as "adjustable" may be selected from a range of possible component value settings and fixed during manufacturing, upon assembly in a circuit module, during factory testing, or in the field (e.g., by burning or "blowing" fuses), or its value may be dynamically varied, tuned, or set programmatically, e.g., in response to other circuitry (e.g., temperature compensation and / or power control circuitry) or in response to generated or received command signals.

[0098] The operating modes of the LNA circuits according to the invention can be set by a control circuit (not shown) in a known manner. The circuit can also be connected to the adjustable components to select different component values ​​(e.g., capacitance, resistance, inductance) for different gain states, e.g., to assist input and / or output impedance matching or to vary the gain relative to linearity in some operating modes.

[0099] The switches shown in the embodiments of the present invention can be implemented as FETs, in particular MOSFETs. The term "MOSFET" as used in this disclosure encompasses any field-effect transistor (FET) with an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates with a metal or metal-like, insulator, and / or semiconductor structure. The terms "metal" or "metal-like" encompass at least one electrically conductive material (such as aluminum, copper, or another metal, or highly doped polysilicon, graphene, or another electrical conductor), "insulator" encompasses at least one insulating material (such as silicon oxide or another dielectric material), and "semiconductor" encompasses at least one semiconductor material.

[0100] The term "radio frequency" (RF), as used in this disclosure, refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or an alternating voltage or current in a circuit.

[0101] In the figures referred to in this disclosure, the dimensions of the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. Furthermore, references to orientations and directions (e.g., "top," "bottom," "upper," "lower," "side," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0102] Various embodiments of the invention can be implemented to meet a variety of specifications. Unless otherwise noted above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the invention can be implemented in any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments can be fabricated using any suitable substrates and processes, including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention can also be implemented in other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies.However, embodiments of the invention are particularly useful when fabricated using an SOI- or SOS-based process, or processes with similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and above 300 GHz). A monolithic IC implementation is particularly useful because parasitic capacitances can generally be kept low through careful design (or at least distributed evenly across all devices so that they can be compensated).

[0103] Depending on the specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS transistor elements, enhancement-mode or depletion-mode transistors), the voltage levels may be adjusted and / or the voltage and / or logic signal polarities may be reversed. The voltage, current, and energy handling capabilities of the components may be adjusted as needed, e.g., by adjusting the device size, serially stacking components (particularly FETs) to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional features without substantially altering the functionality of the disclosed circuits. conclusion

[0104] A number of embodiments of the invention have been described. It should be understood that various changes may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequence independent and may therefore be performed in a different order than that described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the above methods may be performed repeatedly, serially, and / or in parallel.

[0105] It should be understood that the foregoing description is illustrative and not limiting, with respect to the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes all possible combinations of one or more of the methods, machines, manufacturing processes, or compositions of matter recited in the following claims. (It should be noted that the parentheses surrounding claim elements are provided to facilitate reference to those elements and do not, in themselves, indicate any particular required order or enumeration of elements; further, these terms may be reused in dependent claims as references to additional elements without being considered to initiate a conflicting sequence of terms.) QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 17 / 855,386

[0001] US 17 / 337,227 [0049, 0059]

Claims

[1] A load circuit configured to be connected between a high-frequency amplifier core and an output terminal, the load circuit comprising: (a) a first LC resonator connected between the high-frequency amplifier core and a node, the first LC resonator including a first inductor and a first capacitor connected in parallel; (b) a matching and biasing circuit connected to the node and configured to be connected to a power supply, the matching and biasing circuit including a second inductor and a second capacitor connected in parallel; and (c) a second LC resonator connected between the node and the output terminal, the second LC resonator including a third inductor and a third capacitor connected in parallel with each other. [2] The invention of claim 1, further comprising a fourth capacitor connected in series with the third inductor and a third capacitor connected in parallel. [3] The invention of claim 1, wherein the first LC resonator further comprises a bypass switch connected in parallel with the first inductor and the first capacitor. [4] The invention of claim 1, wherein the second LC resonator further comprises a bypass switch connected in parallel with the third inductor and the third capacitor. [5] The invention of claim 1, wherein the matching and biasing circuit further comprises a switch connected in series with the second capacitor and configured to selectively deactivate the second capacitor. [6] The invention of claim 1, wherein at least one of the first inductor and the first capacitor is adjustable. [7] The invention of claim 1, wherein at least one of the third inductor and the third capacitor is adjustable. [8] The invention of claim 1, wherein at least one of the second inductor and the second capacitor is adjustable. [9] The invention of claim 1, wherein the matching and biasing circuit further comprises a second resistor connected in parallel with the second inductor and the second capacitor. [10] The invention of claim 9, wherein the second resistor is adjustable. [11] The invention of claim 9, wherein the matching and biasing circuit further comprises a first switch connected in series with the second resistor and configured to selectively deactivate the second resistor. [12] The invention of claim 9, wherein the first LC resonator further comprises a first resistor connected in parallel with the first inductor and the first capacitor. [13] The invention of claim 12, wherein the first LC resonator further comprises a second switch connected in series with the first resistor and configured to selectively deactivate the first resistor. [14] The invention of claim 12, wherein the first resistor is adjustable. [15] Amplifier comprising: (a) an amplifier core including: (1) an input port configured to receive radio frequency (RF) signals; and (2) an amplified signal port; (b) an output terminal; (c) a load circuit configured to be connected between the amplified signal terminal and the output terminal, the load circuit comprising: (1) a first LC resonator connected between the amplified signal terminal and a node, the first LC resonator including a first inductor and a first capacitor connected in parallel; (2) a matching and biasing circuit connected to the node and configured to be connected to a power supply, the matching and biasing circuit including a second inductor and a second capacitor connected in parallel; and (3) a second LC resonator connected between the node and the output terminal, the second LC resonator including a third inductor and a third capacitor connected in parallel with each other. [16] The invention of claim 15, further comprising a fourth capacitor connected in series with the third inductor and a third capacitor connected in parallel. [17] The invention of claim 15, wherein the first LC resonator further comprises a first bypass switch connected in parallel with the first inductor and the first capacitor. [18] The invention of claim 15, wherein the second LC resonator further comprises a second bypass switch connected in parallel with the third inductor and the third capacitor. [19] The invention of claim 15, wherein the matching and biasing circuit further comprises a switch connected in series with the second capacitor and configured to selectively deactivate the second capacitor. [20] The invention of claim 15, wherein at least one of the first inductor and the first capacitor is adjustable. [21] The invention of claim 15, wherein at least one of the third inductor and the third capacitor is adjustable. [22] The invention of claim 15, wherein at least one of the second inductor and the second capacitor is adjustable. [23] The invention of claim 15, wherein the matching and biasing circuit further comprises a second resistor connected in parallel with the second inductor and the second capacitor. [24] The invention of claim 23, wherein the second resistor is adjustable. [25] The invention of claim 23, wherein the matching and biasing circuit further comprises a first switch connected in series with the second resistor and configured to selectively deactivate the second resistor. [26] The invention of claim 23, wherein the first LC resonator further comprises a first resistor connected in parallel with the first inductor and the first capacitor. [27] The invention of claim 26, wherein the first LC resonator further comprises a second switch connected in series with the first resistor and configured to selectively deactivate the first resistor. [28] The invention of claim 26, wherein the first resistor is adjustable. [29] The invention of claim 15, further comprising an input impedance matching circuit connected to the input terminal and configured to receive the RF signal. [30] The invention of claim 29, wherein the input impedance matching circuit comprises a series inductor connected to the input terminal and configured to receive the RF signal, and a shunt inductor connected between the series inductor and a reference potential. [31] The invention of claim 30, wherein at least one of the series inductor and the shunt inductor is adjustable. [32] The invention of claim 15, wherein the amplifier core includes a degeneration terminal and further comprising a degeneration circuit connected to the degeneration terminal and configured to be connected to a reference potential, the degeneration circuit including a degeneration inductor. [33] The invention of claim 32, further comprising a bypass switch connected in parallel with the degeneration inductor. [34] The invention of claim 15, wherein the amplifier core further comprises a feedback node in an output signal path of the amplifier core and further comprises a feedback circuit connected between the input terminal and the feedback node, the feedback circuit being selectively switchable between enabled and disabled. [35] The invention of claim 34, wherein the feedback circuit comprises a capacitor, a resistor and a switch connected in series. [36] The invention of claim 35, wherein at least one of the resistor or the capacitor is adjustable. [37] The invention of claim 15, wherein the amplifier core further comprises a feedback node in an output signal path of the amplifier core and further comprises a feedback circuit connected between the feedback node and a gate of an upper common-gate FET within the amplifier core, the feedback circuit being selectively switchable between enabled and disabled. [38] The invention of claim 37, wherein the feedback circuit comprises a capacitor, a resistor and a switch connected in series. [39] The invention of claim 38, wherein at least one of the resistor or the capacitor is adjustable. [40] The invention of claim 15, wherein the amplifier is a low noise amplifier. [41] The invention of claim 15, wherein the amplifier is implemented as an integrated circuit implemented in silicon-on-insulator technology and including MOS devices. [42] The invention according to claim 15, wherein the amplifier is implemented as an integrated circuit assembled in a circuit module. [43] The invention of claim 15, wherein the amplifier is implemented as an integrated circuit that is part of a communication device. [44] The invention of claim 15, wherein the amplifier core further comprises: (a) a common-source FET having a gate connected to the input signal terminal, a source, and a drain; (b) a stack comprising at least one common-gate FET, each common-gate FET having a gate, a source, and a drain that outputs an amplified version of the received RF signal, wherein the source of one of the at least one common-gate FET is connected to the drain of the common-source FET, and wherein the drain of one of the at least one common-gate FET is connected to the amplified signal terminal for the stack. [45] A load circuit configured to be connected between a high-frequency amplifier core and an output terminal, the load circuit comprising: (a) a first inductor connected between the core of the high-frequency amplifier and the output terminal; (b) a first resistor connected in parallel with the first inductor between the high-frequency amplifier core and the output terminal; (c) a second inductor connected to the output terminal and configured to be connected to a power supply; and (d) a second resistor connected in parallel with the second inductor and connected to the output terminal and configured to be connected to the power supply. [46] A load circuit configured to be connected between a high-frequency amplifier core and an output terminal, the load circuit comprising: (a) a first inductor connected between the core of the high-frequency amplifier and the output terminal; (b) a second inductor connected to the output terminal and configured to be connected to a power supply; (c) a capacitor connected between the node and the output terminal; and (d) a feedback circuit connected between the input terminal and a feedback node in an output signal path of the amplifier core and selectively switchable between enabled and disabled, the feedback circuit comprising a capacitor, a resistor and a switch connected in series. [47] A method for achieving broadband output impedance matching and high gain for a high-frequency amplifier having an amplifier core and an output terminal, the method comprising: (a) connecting a first LC resonator between the amplifier core and a node, the first LC resonator including a first inductor and a first capacitor connected in parallel; (b) connecting a matching and biasing circuit to the node and a power supply, the matching and biasing circuit including a second inductor and a second capacitor connected in parallel; and (c) connecting a second LC resonator between the node and the output terminal, the second LC resonator including a third inductor and a third capacitor connected in parallel with each other.

Images