SETTING A POWER MODE OF AN RF RECEIVER FRONTEND

Abstract

Examples relate to setting a power mode of an RF receiver front end. One exemplary procedure involves determining a power state of an input signal to an RF receiver front end and setting a power mode of the RF receiver front end to one of at least three different power modes offered by the RF receiver front end, at least partially in response to the determined input signal power state.

Description

PRIORITY CLAIM

[0001] This application claims the benefit under 35 USC §119(e) of U.S. Provisional Patent Application Serial No. 63 / 373,171, filed August 22, 2022, entitled “CHANGING A POWER MODE OF A RECEIVER FRONTEND TO A LOWER POWER MODE IN RESPONSE TO A RADIO FREQUENCY (RF) INPUT SIGNAL LEVEL BELOW A THRESHOLD,” the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0002] Examples generally refer to receivers and radio-frequency receiver front ends. Some examples refer to the power setting of a receiver front end based on an input signal power condition. In some examples, the power includes sensitivity, blocker tolerance, or both. Some examples refer to the operation of an RF receiver front end in a default, lower-power mode until the input signal power condition indicates a higher-power mode. BACKGROUND

[0003] Wireless and wired receivers are used for electronic communication in a variety of operational contexts. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] To make it easier to identify the discussion of a particular element or action, the main number(s) in a reference number refer to the figure number in which that element is first introduced. Fig. 1 is a diagram 100 illustrating information about input signal power and power modes for an RF receiver according to one or more examples. Fig. 2 is a block diagram illustrating a device including power modes each adjustable at least in part in response to an input signal power condition, according to one or more examples. Fig. 3 is a block diagram of an apparatus for determining power settings according to one or more examples. Fig. 4 is a flowchart illustrating a process for setting a power mode of an RF receiver front end based on an input signal power state according to one or more examples. Fig. 5 is a flowchart illustrating a process for operating an RF receiver front end in a default power mode until an input signal power condition indicates a transition to a different power mode, according to one or more examples. Fig. 6 is a flowchart illustrating a process for operating an RF receiver front end in a default power mode when an input signal power state indicates a transition from another, higher power mode, according to one or more examples. Fig. 7 is a flowchart illustrating a process for determining an input signal power state, the input signal power state of an input signal to an RF receiver front end, according to one or more examples. Fig. 8 is a flowchart illustrating a process for setting a power mode of the RF receiver front end to one of at least three different power modes offered by the RF receiver front end at least in part in response to a particular input signal power condition, according to one or more examples. Fig. 9 is a block diagram illustrating a signal processing chain, including performance-defining blocks that are adjustable, according to one or more examples. Fig. 10 is a block diagram illustrating a signal processing chain including a bypass, according to one or more examples. Fig. 11 is a block diagram illustrating a control register with fields used to store values ​​of performance-defining settings, according to one or more examples. Fig. 12 is a block diagram of circuit logic that may be used in some examples to implement various functions, operations, actions, processes, or methods disclosed herein. MODE(S) FOR CARRYING OUT THE INVENTION

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which is shown, by way of illustration, specific examples of examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other examples may be utilized, and structural, material, and procedural changes may be made without departing from the scope of the disclosure.

[0006] The illustrations presented herein are not intended to be actual views of any particular method or system, device, or structure, but are merely idealized representations used to describe the examples of the present disclosure. The drawings presented herein are not necessarily to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, similarity in numbering does not imply that the structures or components are necessarily identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to enable those skilled in the art to practice the disclosed examples. The use of the terms "exemplary," "as an example," and "for example" means that the accompanying description is illustrative, and while the scope of the disclosure is intended to include the examples and their legal equivalents, the use of these terms is not intended to limit the scope of any example or this disclosure to the specified components, steps, features, functions, or the like.

[0008] It will be readily appreciated that the components of the examples generally described herein and illustrated in the drawings may be arranged and configured in a variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. While the various aspects of the examples may be illustrated in the drawings, the drawings are not necessarily drawn to scale unless expressly indicated.

[0009] Furthermore, the specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Elements, circuits, and functions may be shown in block diagram form in order not to obscure the present disclosure with unnecessary detail. Conversely, specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless otherwise stated herein. Furthermore, block definitions and the partitioning of logic between different blocks are exemplary of a specific implementation. It will be readily apparent to those skilled in the art that the present disclosure may be practiced using numerous other partitioning solutions.Details of timing considerations and the like have largely been omitted to the extent that such details are not necessary for a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0010] Those skilled in the art would understand that information and signals may be represented using a variety of different technologies and techniques. Some drawings may illustrate signals as a single signal for clarity of illustration and description. Those skilled in the art will understand that the signal may represent a bus of signals, where the bus may have a variety of bit widths, and the present disclosure may be implemented with any number of data signals, including a single data signal.

[0011] The various illustrative logic blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof configured to perform the functions described herein.A general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, it may be any conventional processor, control unit, microcontroller, or state machine. A processor may also be implemented as a combination of data processing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, while the general-purpose computer is configured to execute computational instructions (e.g., software code) related to examples of the present disclosure.

[0012] The examples may be described with respect to a process represented as a flowchart, a flow sheet, a structural diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different sequence, in parallel, or substantially concurrently. Furthermore, the order of the acts may be changed. A process may correspond, without limitation, to a method, a thread, a function, a procedure, a subroutine, or a subprogram. Further, the methods disclosed herein may be implemented in hardware, software, or both. When implemented in software, the functions may be stored or dispatched as one or more instructions or as code on computer-readable media.Computer-readable media includes both computer storage media and communications media, including any media that supports the transfer of a computer program from one location to another.

[0013] Any reference to an element herein using a label such as "first," "second," etc., does not limit the quantity or order of those elements unless such a limitation is expressly stated. Rather, these labels may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, a reference to a first and a second element does not imply that only two elements may be employed or that the first element must precede the second element in any way. Furthermore, unless otherwise stated, a set of elements may include one or more elements.

[0014] As used herein, the term "substantially" with respect to a given parameter, property, or condition means, and includes, to the extent understood by one skilled in the art, that the given parameter, property, or condition is satisfied with a small degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be at least 90% satisfied, at least 95% satisfied, or even at least 99% satisfied.

[0015] As used herein, relational terms such as "over," "under," "upon," "underlying," "above," "beneath" are used without limitation for clarity and convenience in understanding the disclosure and the accompanying drawings and are not associated with or dependent upon any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0016] In this description, the term "coupled" and derivatives thereof may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. Conversely, when an element is described as being "directly coupled" to another element, no intervening elements or layers are present. The term "connected" may be used interchangeably with the term "coupled" in this description and has the same meaning unless expressly stated otherwise or the context would indicate otherwise to one of ordinary skill in the art.

[0017] The sensitivity of a receiver is the threshold at which the receiver reliably detects a signal. For an RF receiver, the sensitivity is the threshold at which the RF receiver reliably detects an RF signal. Sensitivity defines a lowest signal strength (usually measured in decibels relative to one milliwatt (dBm)) at which the RF receiver is expected to be able to reliably detect and process it. The sensitivity of an RF receiver depends on the various signal processing blocks of an RF receiver's signal processing chain, including, as non-limiting examples: filtering, amplification, and other signal processing.Sensitivity-defining parameters of such processes can be adjusted and changed, including, without limitation, during operation, and thus the sensitivity of an RF receiver can be adjusted or changed, including, without limitation, during operation. A particular configuration for a sensitivity setting is referred to herein as a "sensitivity mode" of an RF receiver. The exemplary RF receivers discussed herein may provide multiple sensitivity modes, each associated with predetermined sensitivity settings.

[0018] "Blocker power" is a magnitude of interference from an interfering signal (a signal other than a target signal / signal under consideration); such an interfering signal is also referred to herein as a "blocker signal." Interference is the extent to which a blocker signal reduces reception of a target signal. In the context of an RF receiver, "blocker tolerance" refers to the amount of interference that an RF receiver can reliably tolerate (e.g., without limitation, filter out) without significant performance degradation. Blocker tolerance is based at least in part on a filter bandwidth of the RF receiver, and thus, filter bandwidth is a non-limiting example of a parameter defining blocker tolerance. A particular configuration for blocker tolerance is referred to herein as a "blocker tolerance mode" of an RF receiver. The example RF receivers discussed herein may offer multiple blocker tolerance modes.

[0019] Blocker tolerance and sensitivity of an RF receiver are collectively referred to herein as the “performance” of the RF receiver, and blocker tolerance modes and sensitivity modes are collectively referred to herein as “performance modes.”

[0020] A typical radio frequency (RF) receiver (such as an RF receiver used for BLUETOOTH® communication, without limitation) is configured to operate with maximum sensitivity, blocker tolerance, or both over a wide input signal power range. However, in practical scenarios, an RF receiver encounters a narrower band of input signal levels. By assigning a probability curve to the entire operating range of an RF receiver, it becomes clear that much of the increased sensitivity, blocker tolerance, or both is over-engineered for the commonly encountered input signal levels.

[0021] The probability curve for an RF receiver exhibits a pronounced peak corresponding to the narrowband input signal level typically encountered. The probability decreases sharply on either side of the peak. The probability curve exhibits the pronounced peak at moderate input signal levels that do not require the highest power setting (e.g., sensitivity adjustment, blocker tolerance adjustment, or both, without limitation), so a moderate power setting should theoretically be sufficient. Selecting the moderate power setting meets the input signal requirements and consumes less power than the highest power setting.

[0022] One or more examples refer to an RF receiver front-end and an RF receiver including it, operating at a moderate power setting, optionally by default, and switching to a higher or highest power setting only when the input signal requires it, and switching to a lower or lowest power setting when the input signal permits it. "Default" refers to a default setting that the RF receiver front-end uses when no other instructions are given. In one or more examples, a default power mode setting may be used when a device is first powered on or when no other specific power setting has been selected (e.g., by a user or application layer, without limitation).

[0023] While some of the example RF receiver front ends discussed herein offer three distinct power modes (e.g., lowest, moderate, and highest, without limitation), the scope of this disclosure is not limited to offering only three sensitivity modes, and offering more than three modes is expressly contemplated. Furthermore, sensitivity adjustment is not limited to three or more distinct modes. One or more examples relate to an RF receiver that offers continuous sensitivity adjustment and adapts seamlessly in response to the input signal power state.

[0024] Fig. 1 is a graph 100 illustrating information about input signal power and sensitivity modes for an RF receiver according to one or more examples. The graph 100 includes an x-axis, a y-axis, a line 102, a line 104, a line 106, and a line 108.

[0025] The y-axis of the graph corresponds to the input signal power, with values ​​of the input signal level increasing from the bottom to the top of the y-axis. In this example, the RF receiver's input signal power range (also called the RF receiver's "dynamic range") is defined between SP0 and SP2. The signal power is expressed in decibels relative to one milliwatt (dBm). Markers for several intermediate signal power levels, namely dBm1 and dBm2, are shown on the right side of the page, and these are discussed below.

[0026] The positive side of the x-axis corresponds to the blocker power and increases from left to right. It also identifies subranges of blocker power that the RF receiver can tolerate in certain power modes (represented by line 104, line 106, and line 108, discussed below). "Blocker power" is a measure of interference from a jamming signal (a signal other than a target signal). Interference is the extent to which an interfering signal reduces reception of a target signal. In the context of an RF receiver front-end, "blocker power" refers to the amount of interference that the RF receiver front-end can reliably tolerate (e.g., filter out without restriction) without significant performance degradation. The negative side of the x-axis corresponds to the receiver (RX) current, which increases from right to left.Adjacent to the y-axis are rectangular boxes, each vertically aligned to the negative side of the x-axis, to indicate the power consumption (here expressed as power consumption) for a respective performance mode.

[0027] Line 102 is a curve representing the probability that the RF receiver front-end (or more generally, the RF receiver) will encounter a given input signal level on the y-axis. For a given input signal level on the y-axis, the point on line 102 that is horizontally aligned with the given input signal level corresponds to a probability that the given input signal level will occur. The greater the distance between the point on line 102 and the y-axis, the higher the probability. For example, a point 110 is closer to the y-axis than a point 112, so the probability curve represented by line 102 indicates that the probability that the input signal level associated with point 110 will occur is lower (in this example, much lower) than the probability that the input signal level associated with point 112 will occur.

[0028] While through Fig. 1 only shows a single probability curve, probability curves can be obtained that represent the probability of encountering a target signal at given signal levels, and probability curves can be obtained that represent the probability of encountering blocker signals at given signal levels. The probability curve represented by line 102 is a probability of encountering a target signal at given signal levels.

[0029] Line 104, line 106, and line 108 represent signal power ranges and blocker power ranges of three exemplary different power modes of an RF receiver front-end. As discussed below, respective power modes may be characterized by different filter bandwidths, gains, DC bias levels, and clock rates chosen to strike a balance between sensitivity, blocking tolerance, or both, and power consumption.

[0030] Line 104 represents a power mode suitable for a target signal power less than signal power SP2, for which a highest sensitivity setting meets the target signal requirement, and provides appropriate blocker tolerance for a blocker power less than blocker power BP0. In this example, line 104 indicates that the highest sensitivity setting meets the full dynamic range requirements of the RF receiver front-end and provides appropriate blocker tolerance at blocker powers BP0 and lower.

[0031] As mentioned above, not all input signal levels require the highest sensitivity or blocker tolerance. Line 106 represents a power mode suitable for signal power lower than signal power SP2 and greater than signal power SP0, and provides appropriate blocker tolerance for blocker power lower than blocker power BP1. In this example, the sensitivity setting associated with the power mode represented by line 106 meets the requirements of a target signal with signal power greater than signal power SP0. Line 108 represents a power mode suitable for signal power less than signal power SP2 and greater than signal power SP1, and provides appropriate blocker tolerance for blocker power less than BP2.In this example, the sensitivity setting associated with the mode represented by line 108 meets the requirements of a target signal having a signal power greater than the signal power SP1.

[0032] The dynamic range of the RF receiver front-end is divided into specific (different) signal power subranges or "power states" of the target signal. Respective power states correspond to respective power modes. In one or more examples, power modes may be associated with sensitivity modes, blocker tolerance modes, or both sensitivity modes and blocker tolerance modes. A sensitivity mode may be associated with a sensitivity setting. A blocker tolerance mode may be associated with a blocker tolerance setting. A power setting may be associated with a sensitivity setting, a blocker tolerance setting, or both a sensitivity setting and a blocker tolerance setting. A power mode should reliably provide an associated power setting.A sensitivity setting associated with a power mode may be determined based on the highest sensitivity required for the range of target signal power levels within a power state or states for which the sensitivity mode is used. A blocker tolerance setting associated with a power mode may be determined based on a highest blocker tolerance required for the range of blocker signal power levels within a power state or states for which the blocker tolerance mode is used.

[0033] In one or more examples, input signal power sub-ranges (e.g., target signal power sub-ranges and blocker signal power sub-ranges, without limitation) may be determined based at least in part on the probability that the RF receiver front-end encounters signals within those sub-ranges. The probability may be defined, without limitation, by a probability curve, such as the probability curve represented by line 102. Any suitable technique may be used to determine the probability curve, including, as a non-limiting example, by observing power states of input signals in environments representative of operating conditions for which an RF receiver front-end may be used; or utilizing public or private databases that contain information about input signal power levels (e.g.,Target signal power levels and blocker signal power levels, without limitation) that may occur in various environments and that include probabilistic information or information based on which probabilistic information may be determined.

[0034] In one or more examples, thresholds defining the input signal power subranges and thus the power states may be determined using the probabilistic information and other relevant information or criteria. As a non-limiting example, a cost function may be used that aims to minimize the potential cost of failing to achieve the required sensitivity and maximize the potential benefit of reducing power consumption by the RF receiver front-end. Such a cost function may be weighted by the probability that signals occur within a respective subrange. In this way, the values ​​of the thresholds defining the power states may be influenced by probabilistic information.Determining the values ​​of thresholds is based at least in part on probabilistic information (such as the probability of occurrence of input signals (target signals, blocker signals, or both) at certain power levels, without limitation) or may be referred to herein as a "probabilistic determination," and such a threshold may be referred to herein as a "probabilistic threshold."

[0035] As a further non-limiting example, a calibration process may be used that searches a range of input signal powers (e.g., corresponding to a dynamic range of the RF receiver front-end) for respective power modes (sensitivity modes, blocker tolerance modes, or both) offered by an RF receiver front-end, observes the error rate exhibited for the range of input signal powers for respective power modes, and adjusts the thresholds to exhibit the lowest error rates for the subrange of input power levels associated with respective power modes, and to reduce or eliminate error rate peaks (e.g., negligible or nonexistent, without limitation) at transitions between power modes.

[0036] In one or more examples, various operating conditions may affect one or more of: the sensitivity required by an input signal, the blocker tolerance required by an input signal, the range of input signal power levels for which a given power mode is sufficient, or the probability of a particular input signal power level occurring. The probability of a particular input signal power level occurring may include, as non-limiting examples, the probability of a target signal occurring at the particular power level, the probability of a blocker signal occurring at a particular blocker power, or both.

[0037] Non-limiting examples of operating conditions include other modes offered by the RF receiver front-end besides the power modes and environmental conditions discussed herein. Environmental conditions include, without limitation, ambient temperature, altitude (e.g., air pressure affects the propagation characteristics of RF signals in air, without limitation), humidity (e.g., humidity levels can cause signal attenuation, without limitation), terrain and physical obstructions (e.g., buildings, mountains, trees, without limitation, which cause, for example, reflection of RF signals, diffraction of RF signals, or absorption of RF signals, without limitation), the presence of blocker signals (e.g., environments saturated with RF sources, without limitation), congested frequency bands (e.g., many transmitters, without limitation), the distance of a receiver from a transmitter, the dynamic range of input signals (e.g.,a mixture of strong and weak input signals, without limitation), the mobility of an RF receiver or RF device, including the RF receiver front end, atmospheric conditions (e.g., weather, without limitation), or combinations and subcombinations thereof, without limitation.

[0038] Operating conditions may be specified in various ways, such as via a global setting used to set and / or specify other modes at the RF receiver front-end (modes other than the power modes discussed above) or via, without limitation, an environmental status. In one or more examples, a global setting may be set at an application layer of a receiver or device incorporating it. The global setting may be set by a user and / or based on, without limitation, an environmental status. Non-limiting examples of other RF receiver front-end modes set via global settings include: a short-range mode, a long-range mode, a low-power mode, a high-power mode, or a jammer-tolerant mode.A "short-range mode" is an operating mode specifically designed to receive signals over a relatively shorter distance (e.g., for certain applications that involve receiving signals over a relatively shorter distance, without limitation). A "long-range mode" is an operating mode specifically designed to receive signals over a relatively longer distance (e.g., for certain applications that involve receiving signals over a relatively longer distance, without limitation). A "low-power mode" is an operating mode specifically designed to consume a relatively smaller amount (e.g., the least amount, without limitation) of power (e.g.,A "high-performance mode" is an operating mode specifically designed to provide the highest level of sensitivity (e.g., for certain applications where power resources are limited, extending a device's battery life is a priority, or maintaining a device's operating time is a priority, or any combination or subcombination thereof, without limitation). A "high-performance mode" is an operating mode specifically designed to provide the highest level of blocker tolerance (e.g., for certain applications where sensitivity is a priority, without limitation). A "blocker tolerance mode" is an operating mode specifically designed to provide the highest level of blocker tolerance (e.g., for certain applications where blocker tolerance is a priority, without limitation).

[0039] In one or more examples, the environmental status consists of information about one or more environmental conditions. Such information may include, without limitation, a value representative of an environmental condition, an indication of an environmental condition, or statistical information. Non-limiting examples of values ​​representative of an environmental condition include: a temperature value, a humidity value, an altitude value, and a distance value.Non-limiting examples of environmental indications include, without limitation, indications generated by logic circuitry that determine (or detect the presence of) specific environmental conditions such as temperature, altitude, humidity, frequency band congestion, or the presence of physical obstructions greater than predefined thresholds, or indications set by users to indicate predefined environmental conditions (whether or not those environmental conditions actually exist) such as temperature, altitude, humidity, frequency band congestion, or the presence of physical obstructions greater than predefined thresholds.

[0040] Statistical information is information about, or useful for determining, the effect of an environmental condition (or cumulative effects of multiple environmental conditions) on transmitted RF signals and / or on the reception of RF signals. As a non-limiting example, statistical information may include, or be useful for determining, information about the noise level of an environment or the suitability of an environment for transmitting RF signals and / or receiving RF signals at any frequency, a specific frequency, or in a specific frequency range or band. Statistical information may be provided by a user or determined dynamically (e.g., by a digital signal processor (DSP) of the RF receiver front-end (e.g.,a DSP implementing automatic radio control (discussed below), or another DSP, without limitation; or an RF receiver or device incorporating the same, without limitation. Non-limiting examples of statistical information include: Packet Error Rate (PER), Received Signal Strength Indicator (RSSI), Noise Level Frequency Range A, Noise Level Frequency Range B, or combinations and sub-combinations thereof. Range A and Range B are different, predetermined frequency ranges. Determining interference over fewer or more than two frequency ranges does not exceed the scope of this disclosure.

[0041] In one or more examples, various parameters used to determine power states, thresholds, and sensitivity settings may be based at least in part on operating conditions of the RF receiver front end, including global settings or environmental status, as discussed above.

[0042] As non-limiting examples, one or more of the following elements may be based at least in part on a set of predetermined operating conditions of the RF receiver front-end: an input signal power range of the RF receiver front-end, a probability curve, a required sensitivity for given power levels, and a required blocker tolerance.

[0043] As a non-limiting example, specified operating conditions may be associated with a scenario requiring lower or higher sensitivity or blocker tolerance than under average operating conditions. To account for the higher probability of signals requiring higher sensitivity or blocker tolerance, the peak exhibited by a probability curve used to determine thresholds, subranges, performance states, sensitivity settings, and blocker tolerance settings may be shifted downward or broadened relative to a probability curve representing average operating conditions.

[0044] In one or more examples, respective sets of parameters, such as thresholds, subranges, power states, sensitivity settings, and blocker tolerance settings, without limitation, may be determined for respective ones of the set of predetermined operating conditions of the RF receiver front-end. These respective parameter sets and their mapping to respective predetermined operating conditions of the RF receiver front-end may be stored, for example, in non-volatile memory. Certain ones of the respective parameter sets may be referenced based at least in part on an indication of the operating condition, the input signal power level, or both. A parameter set associated with the indication of the operating condition may be selected.The information in the selected parameter set can be used to determine an input signal power condition, a sensitivity setting, or a blocker tolerance setting, as discussed herein.

[0045] One or more examples relate to an RF receiver front-end that offers at least three power modes. The three power modes provide different power settings, including different sensitivity settings and / or blocker tolerance settings. The RF receiver front-end can operate (optionally by default) in a power mode that is lower (in terms of power settings) than a highest power mode offered by the RF receiver front-end. In one or more examples, the RF receiver front-end sets the power mode at least in part in response to a power condition of an input signal to the RF receiver front-end. For example, the RF receiver front-end transitions to a higher power mode (i.e.,, offering higher sensitivity and / or higher blocker tolerance than a current performance mode, without limitation) and, in response to an input signal power condition indicating this, transitions to a lower performance mode (i.e., offering lower sensitivity and / or lower blocker tolerance than a current performance mode, without limitation).

[0046] Logic circuitry determines the input signal power state and sets the power mode of the RF receiver front-end at least in part in response to the determined input signal power state. In one or more examples, the logic circuitry determines the input signal power state and dynamically determines a power setting (e.g., a sensitivity setting and / or a blocker tolerance setting, without limitation) based at least in part on the determined input signal power state. The logic circuitry provides the power setting to an automatic radio controller. The automatic radio controller determines values ​​of parameters defining the sensitivity and / or blocker tolerance of the RF receiver according to the power setting and provides the power-defining parameters to the signal processing chain of the RF receiver to set the power mode.

[0047] Fig. 2 is a block diagram illustrating a device 200 including power modes, each adjustable at least in part in response to an input signal power condition, according to one or more examples. Device 200 may also be referred to herein as an RF receiver front-end 200.

[0048] The device 200 includes a signal processing chain 202, an automatic radio control 206 and a logic circuit 208.

[0049] The signal processing chain 202 is a series of signal processing blocks that convert the input signal 210 into an output signal 212 in a form suitable for further processing or output. The input signal 210 may include a target signal and may optionally include a blocker signal.

[0050] The specific signal processing blocks of the signal processing chain 202 may, as a non-limiting example, be selected at least in part based on specific operating conditions. The signal processing chain 202 includes, as a non-limiting example, the Fig. 9 and Fig. 10. The signal processing chain 202 may include at least three different performance modes 204 responsive to the performance-defining setting 216, and an RF receiver front end 200 and an RF receiver including it may be considered to provide the at least three different performance modes 204 that the signal processing chain 202 may include. Respective performance modes provide respective sensitivity settings, blocker tolerances, or both sensitivity settings and blocker tolerances.

[0051] The automatic radio controller 206 is logic circuitry or software, or a combination thereof, that determines the performance-defining setting 216 for the signal processing chain 202. Generally speaking, the automatic radio controller 206 determines the respective performance-defining setting 216 for respective blocks of the signal processing chain 202 to achieve a balance between performance (e.g., sensitivity and / or blocker tolerance, without limitation) and power consumption. The automatic radio controller 206 observes the performance of the signal processing chain 202 and attempts to adjust the observed performance to a target performance by controlling various settings of the signal processing chain 202 or blocks thereof via the performance-defining setting 216.In one or more examples, a target power used by the automatic radio controller 206 to determine the power-defining setting 216 is based at least in part on the power setting 214 provided by the logic circuit 208. The power-defining setting 216 may include one or more of: gain, DC bias current, filter bandwidth, or clock rate.

[0052] Logic circuitry 208 receives input signal 210 and specifies power setting 214 at least in part in response thereto. Logic circuitry 208 determines an input signal power state of input signal 210 and determines power setting 214 based at least in part on the determined input signal power state. Logic circuitry 208 specifies one of the three different power modes by providing power setting 214 corresponding to one of the three different power modes at least in part in response to an input signal power state.

[0053] As discussed above, certain input signal power states of input signal 210 may correspond to different input signal power subranges. For example, a first input signal power subrange may include input signal levels requiring the highest sensitivity setting and / or the lowest blocker tolerance setting, a second input signal power subrange may include input signal levels requiring a moderate sensitivity setting and / or blocker tolerance setting, and a third input signal power subrange may include input signal levels requiring a lowest sensitivity setting and / or highest blocker tolerance setting.Information about input signal power states, input signal power sub-ranges, thresholds associated with these sub-ranges, and mappings to power settings corresponding to power modes may be stored in a memory of logic circuit 208 (memory not shown) or configured at logic circuit 208 (e.g., implemented in combinational logic circuits of logic circuit 208).In one or more examples, information about power settings and power modes stored in a memory of logic circuit 208 or configured on logic circuit 208, as applicable, may include information about sensitivity settings corresponding to sensitivity modes of power modes, information about blocker tolerance settings corresponding to blocker tolerance modes of power modes, or information about both sensitivity settings and blocker tolerance settings corresponding to power modes.

[0054] Power setting values ​​pre-mapped to specific power states of input signal 210 may be provided to logic circuit 208. As non-limiting examples, the pre-map may take the form of a look-up table (LUT), a rule engine, or a function that relates power setting values ​​to input signal power states.

[0055] Fig. 3 is a block diagram of a device 300 for determining power settings according to one or more examples. Logic circuit 302 is a non-limiting example of logic circuit 208 of Fig. 2.

[0056] Logic circuitry 302 includes input signal power state definitions 304 and power setting definitions 308. Input signal power state definitions 304 include the conditions or criteria for determining an input signal power state based on input signal power level 306, as discussed herein. Input signal power state definitions 304 may include one or more of the probability-based thresholds discussed herein.

[0057] The power setting definitions 308 include sensitivity setting definitions 314, blocker tolerance setting definitions 316, and mappings of respective power settings (or modes) to respective input signal power states. The sensitivity setting definitions 314 include sensitivity settings for respective sensitivity modes of respective power modes of the RF receiver front-end and further include mappings of the respective sensitivity modes to respective input signal power states included in the input signal power state definitions 304. The blocker tolerance setting definitions 316 include blocker tolerance settings for respective blocker tolerance modes of respective power modes of an RF receiver front-end and further include mappings of respective blocker tolerance modes to respective input signal power states.

[0058] In one or more examples, logic circuitry 302 determines an input signal power state based on input signal power level 306 and input signal power state definitions 304, and determines a power setting 312 based at least in part on a determined input signal power state and power setting definitions 308.

[0059] As discussed above, operating conditions may affect input signal power states and respective associated power settings. In one or more examples, logic circuitry 302 optionally receives an indication of an operating state 310 that includes information about one or more of the operating states discussed above. In one or more examples, the indication of the operating state 310 may indicate or include indications of a global setting or environmental status. In one or more examples, the source of an indication of the operating state 310 may be, without limitation, an application layer or DSP of the RF receiver front-end or RF receiver including it. In one or more examples, the indication of the operating state 310 may indicate or include indications of a power-up, power-up reset, or reset.

[0060] Input signal power state definitions 304 may include one or more sets of input signal power state definitions, each associated with one or more predetermined operating conditions. Definitions may include information about power states, input signal power levels associated with power states, and thresholds each associated with a first set of input signal power definitions associated with a first of the operating conditions may be different from those associated with a second set of input signal power definitions associated with a second of the operating conditions. Power setting definitions 308 may include one or more sets of power setting definitions, each associated with one or more operating conditions.The power settings and associated power states in a first set of power setting definitions 308 associated with a first operating condition may differ from those in a second set of power setting definitions 308 associated with a second operating condition.

[0061] In one or more examples, the logic circuit 302 selects one of the sets of input signal power state definitions 304 and one of the sets of sensitivity setting definitions 314 based at least in part on the indication of the operating condition 310, and determines an input signal power state and a power setting 312 based at least in part on the selected sets.

[0062] In particular, providing an indication of the operating condition 310 to, or using the indication of the operating condition 310 by, logic circuitry 302 is optional. In one or more examples, logic circuitry 302 may determine the power setting 312 with or without consideration of operating conditions. As a non-limiting example, an operating condition could include a high-sensitivity or blocker-tolerance mode set at an application layer through a global setting; nevertheless, logic circuitry 302 may determine the power setting 312, corresponding to a moderate power mode at power-on, as the default setting.

[0063] Fig. 4 is a flowchart illustrating a process 400 for setting a power mode of an RF receiver front-end at least in part in response to an input signal power condition, according to one or more examples. Some or all of the acts of process 400 may be performed by device 200 or device 300, as a non-limiting example.

[0064] While the example process 400 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 400. In other examples, various components of an example device or system implementing the process 400 may perform functions at substantially the same time or in a particular sequence.

[0065] In one or more examples, process 400 includes determining an input signal power state, the input signal power state of an input signal to an RF receiver front-end at operation 402. An input signal may include, without limitation, a target signal, a blocker signal, or both.

[0066] In one or more examples, process 400 includes setting a power mode of the RF receiver front end to one of at least three different power modes offered by the RF receiver front end, at least in part in response to the determined input signal power condition at operation 404.

[0067] Fig. 5 is a flowchart illustrating a process 500 for operating an RF receiver front-end in a default power mode until an input signal power condition indicates a transition to another power mode, according to one or more examples. Some or all of the acts of process 500 may be performed by device 200 or device 300, as a non-limiting example.

[0068] While the example process 500 depicts a particular sequence of operations, the sequence may be changed without departing from the scope of the present disclosure. For example, some of the depicted operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 500. In other examples, various components of an example device or system implementing the process 500 may perform functions at substantially the same time or in a particular sequence.

[0069] In one or more examples, process 500 includes setting a power mode of a radio frequency (RF) receiver front-end to a default power mode at operation 502. A power setting associated with the default power mode is lower than a power setting associated with another power mode offered by the RF receiver front-end. In one or more examples, other power modes offered by the RF receiver front-end may include a power mode associated with a higher power setting than the default power mode and may include a power mode associated with a lower power setting than the default power mode.In one or more examples, the process 500 may set the power mode of the RF receiver front-end to the default power mode at least in part in response to an indication of power-on, power-on reset, or reset. In one or more examples, the process 500 may set the power mode of the RF receiver front-end to the default power mode at least in part in response to both: an indication of power-on, power-on reset, or reset and a determination that there are no instructions (e.g., a lack of instructions, without limitation) to use a particular power mode or power setting. In one or more examples, the process 500 may set the power mode of the RF receiver front-end to the default power mode regardless of an instruction to use a higher power mode.In one or more examples, the process 500 may set the power mode of the RF receiver front end to the default power mode in response to a power-on, power-on reset, or reset indication, regardless of an instruction to use a higher power mode or an indication of an operating condition associated with a higher power setting.

[0070] In one or more examples, process 500 includes determining an input signal power state, the input signal power state of an input signal to the RF receiver front-end at operation 504. An input signal may include, without limitation, a target signal, a blocker signal, or both.

[0071] In one or more examples, process 500 includes setting the power mode of the RF receiver front-end to one of the additional power modes offered by the RF receiver front-end, at least in part in response to the determined input signal power condition at operation 506. In one or more examples, the one of the additional power modes offered by the RF receiver front-end may be a higher power mode, that is, associated with a higher power setting than the power setting associated with the default power mode.

[0072] Fig. 6 is a flowchart illustrating a process 600 for operating an RF receiver front-end in a default power mode when an input signal power condition indicates a transition from another, higher power mode, according to one or more examples. Some or all of the acts of process 500 may be performed by device 200 or device 300, as a non-limiting example.

[0073] While the example process 600 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 600. In other examples, various components of an example device or system implementing the process 600 may perform functions at substantially the same time or in a particular sequence.

[0074] In one or more examples, process 600 includes setting a power mode of a radio frequency (RF) receiver front-end to a higher power mode at operation 602. The higher power mode may be associated with a higher power setting than the default power mode. Other power modes offered by the RF receiver front-end may include a power mode associated with a lower power setting than the default power mode and the higher power mode.

[0075] In one or more examples, process 600 includes determining an input signal power state, the input signal power state of an input signal to the RF receiver front-end at operation 604. An input signal may include, without limitation, a target signal, a blocker signal, or both.

[0076] In one or more examples, process 600 includes setting the power mode of the RF receiver front-end to a default power mode at least in part in response to the determined input signal power condition at operation 606. A power setting associated with the default power mode is lower than the power setting associated with the higher (previous) power mode. In this manner, the RF receiver front-end operates only in the higher power mode (higher than the default power mode) until the input signal power condition indicates that the higher power mode is not required (or no longer indicates that the higher power mode is required), and then transitions to the default power mode. In one or more examples, the power mode of the RF receiver front-end may be set to the default power mode by applying a power setting to an input of a logic circuit (e.g.,logic circuit 208 or logic circuit 302, without limitation), by providing a power setting associated with the default power setting, or both.

[0077] In one or more examples, process 600 may set the power mode of the RF receiver front-end to the default power mode in response at least in part to both the determined input signal power condition and a determination that there are no instructions (e.g., a lack of instructions, without limitation) to use a particular power mode or power setting. In one or more examples, process 600 may set the power mode of the RF receiver front-end to the default power mode regardless of an instruction to use the higher power mode or an indication of an operating condition associated with the higher power setting.

[0078] Fig. 7 is a flowchart illustrating a process 700 for determining an input signal power state of an input signal to an RF receiver front-end according to one or more examples. Some or all of the acts of process 500 may be performed by device 200 or device 300, as a non-limiting example.

[0079] While the example process 700 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 700. In other examples, various components of an example device or system implementing the process 700 may perform functions at substantially the same time or in a particular sequence.

[0080] In one or more examples, process 700 includes obtaining a value representative of a power level of an input signal to an RF receiver front end at operation 702.

[0081] In one or more examples, at operation 704, process 700 optionally includes selecting one or more thresholds based at least in part on an indication of the operating condition, wherein the one or more thresholds are probability-based thresholds. In one or more examples, the indication of the RF receiver front-end mode may be a global setting in an application layer set by a user or set based on environmental status.

[0082] In one or more examples, process 700 includes comparing the power level representative value to one or more thresholds, where the one or more thresholds are probability-based thresholds, at operation 706.

[0083] In one or more examples, process 700 includes determining the input signal power state at least in part in response to the comparison at operation 708.

[0084] Fig. 8 is a flowchart illustrating a process 800 for setting a power mode of the RF receiver front-end to one of at least three different power modes offered by the RF receiver front-end at least in part in response to a particular input signal power condition, according to one or more examples. Some or all of the acts of process 800 may be performed by device 200 or device 300, as a non-limiting example.

[0085] While the example process 800 illustrates a particular sequence of operations, the sequence may be modified without departing from the scope of the present disclosure. For example, some of the illustrated operations may be performed in parallel or in a different sequence that does not significantly affect the function of the process 800. In other examples, various components of an example device or system implementing the process 800 may perform functions at substantially the same time or in a particular sequence.

[0086] In one or more examples, process 800 includes obtaining an input signal power state, the input signal power state of an input signal to an RF receiver front end, at operation 802.

[0087] In one or more examples, process 800 includes determining a power setting based at least in part on the input signal power state, wherein the determined power setting is associated with a power mode that is one of at least three power modes offered by the RF receiver front end, at operation 804.

[0088] According to one or more examples, at operation 806, process 800 optionally includes the particular power setting being a sensitivity setting or a blocker tolerance setting.

[0089] In one or more examples, process 800 includes determining a performance-defining setting based at least in part on the determined performance setting at operation 808. In one or more examples, the performance-defining setting includes a sensitivity-defining setting, a blocker tolerance-defining setting, or both a sensitivity-defining setting and a blocker tolerance-defining setting.

[0090] In one or more examples, process 800 optionally includes performance-defining adjustment for gain, direct current (DC) bias, filter bandwidth, or clock rate of a performance-defining block of a signal processing chain of the RF receiver front-end at operation 810.

[0091] In one or more examples, process 800 includes applying the determined performance-defining setting to the RF receiver front-end at operation 812. Applying the determined performance-defining setting to the RF receiver front-end may include setting respective knobs (e.g., knobs set via fields of a control register, such as control register 1100, without limitation) of one or more blocks of a signal processing chain of the RF receiver front-end. By setting knobs to the values ​​of the determined performance-defining setting, the performance of the RF receiver front-end is set to the power setting.

[0092] Any suitable technique may be used to adjust the performance modes or power of a signal processing chain. In one or more examples, performance modes or power are adjusted via a register (a "control register"), as shown in Fig. 11. Values ​​stored in the control register fields set certain performance-defining properties of the signal processing chain.

[0093] Fig. 9 is a block diagram illustrating a signal processing chain 900, including performance-defining blocks (discussed below) that are adjustable, according to one or more examples. The signal processing chain 900 is a non-limiting example of the signal processing chain 202 of Fig. 2.

[0094] In one or more examples, respective performance-defining blocks of the signal processing chain 900 may be directly adjustable and / or indirectly adjustable. If directly adjustable, then bits in a control register (e.g., the control register 1100 of Fig. 11, without limitation) directly adjust parameters of a respective performance-defining block. If they are indirectly adjustable, then directly adjusting a parameter of another performance-defining block via bits of the control register affects the performance-defining block.

[0095] Examples of parameters of respective blocks of the signal processing chain 900 that affect performance include: power consumption, gain, DC bias current, filter bandwidth, and clock rate.

[0096] For each of these performance-defining parameters, arc defines a performance value, i.e., the range of filter rejection and the amount of gain.

[0097] Power consumption is the amount of receiver current consumed by a block. Gain is a measure of how much a block amplifies or attenuates the signal it is processing. Bias current is the direct current (DC) operating point current of a block and sets the DC level under bias current.

[0098] The signal processing chain 900 includes an antenna 902, a low noise amplifier (LNA) 904, a mixer 906, a baseband amplifier (BB) 908, a transimpedance amplifier (TIA) 910, an analog-to-digital converter (ADC) 912, an automatic radio controller (ARC) 914, and a signal level detector 916.

[0099] Antenna 902 receives a radio signal from the air and converts it into an electrical signal, e.g., an analog voltage signal. Antenna 902 detects electromagnetic waves in the air and converts them into electrical voltages. If the electromagnetic waves in the air correspond to a radio signal, the electrical voltages generated by antenna 902 are an electrical signal.

[0100] The LNA 904 amplifies the weak electrical signal received by the antenna 902 and adds limited noise to the signal. By amplifying the received signal at the beginning of the receiver chain, the signal-to-noise ratio (SNR) of the received signal is improved. The power consumption of the LNA 904 can be adjusted via the gain or bias current, or a combination thereof.

[0101] Mixer 906 converts the frequency of the received signal to a lower frequency for further processing. Mixer 906 is a nonlinear device that mixes the amplified signal from LNA 904 with a local oscillator (LO) signal to generate an intermediate frequency (IF) signal, which may be a current signal having a lower frequency than the received signal. The power consumption of mixer 906 can be adjusted via gain, bias current, or clock rate (or a rise and fall time of the clock received at mixer 906), or a combination thereof.

[0102] The BB 908 provides additional gain to the received IF current signal and filters out noise. The power consumption of the BB 908 can be adjusted via gain, bias current, or filter bandwidth, or a combination thereof.

[0103] The TIA 910 is an intermediate frequency amplifier (IF amplifier) ​​with a built-in low-pass filter. The TIA 910 converts the IF current signal from the mixer into an IF voltage signal that can be digitized by the ADC 912. The TIA 910's power consumption can be adjusted via gain, bias current, or bandwidth, or a combination thereof. Here, the bandwidth determines the frequency range the TIA can accurately amplify. When the amount of input current from the BB 908 changes rapidly, the TIA 910's ability to effectively track the changes depends, at least in part, on its bandwidth.

[0104] The ADC 912 converts the analog voltage signal from the TIA 910 into a digital signal that can be further processed by digital signal processing (DSP) algorithms. The power consumption of the ADC 912 can be adjusted via bias current or bandwidth, or a combination of both.

[0105] Clock sources for mixer 906 and ADC 912 may be the same or different. Different clock sources may have different clock rates. The rise time or fall time of a given clock signal may be adjusted, as a non-limiting example, via a supply voltage level, which can be adjusted to adjust the rise and fall times of a clock signal.

[0106] In one or more examples, the signal processing chain 900 may include one or more control registers, and values ​​in the fields of these control registers may directly or indirectly set the parameters of respective blocks used by the ARC 914 to adjust the performance of the signal processing chain 900 via performance-defining settings 920 in response to the performance setting 918.

[0107] In some examples, one or more of the sensitivity-defining blocks of signal processing chain 900 may provide both an asymmetric mode and a symmetric mode. The symmetric input mode utilizes more power than the asymmetric mode, so in some examples, the ARC 914 may set respective input modes of the various sensitivity-defining blocks of signal processing chain 900 as a power-defining setting 216.

[0108] Fig. 10 is a block diagram illustrating a signal processing chain 1000 including a bypass 1002, according to one or more examples. The bypass 1002 is a circuit for selectively bypassing the BB 908. The bypass 1002 provides another mechanism for the ARC 914 to adjust performance and control power consumption in the signal processing chain 1000. When high performance (high sensitivity or interferer rejection (i.e., blocker tolerance)) is not required, the ARC 914 can bypass the BB 908 via the power-defining settings 1004, effectively turning off the BB 908 to reduce power consumption by the BB 908 and the signal processing chain 1000 more generally.

[0109] Fig. 11 is a block diagram illustrating a control register 1100 having fields used to store values ​​of performance-defining settings, according to one or more examples.

[0110] Fields of the control register 1100 are referred to herein as "knobs," and the knobs are set by values ​​provided by an ARC (e.g., the ARC 914 or the automatic radio control 206, without limitation).

[0111] The control register 1100 includes LNA knobs 1102, mixer knobs 1108, TIA knobs 1116, BBamp knobs 1124, and ADC knobs 1132. The LNA knobs 1102 include a gain control knob 1104 and a DC bias control knob 1106. The mixer knobs 1108 include a clock rate control knob 1110, a gain control knob 1112, and a DC bias control knob 1114. The TIA knobs 1116 include a filter BW control knob 1118, a gain control knob 1120, and a DC bias control knob 1122. The BBamp knobs 1124 include a filter BW control knob 1126, a gain control knob 1128, and a DC bias control knob 1130. The ADC knobs 1132 include a clock rate control knob 1134 and a DC bias control knob 1136.

[0112] It will be understood by those skilled in the art that functional elements of examples disclosed herein (e.g., functions, operations, actions, processes, and / or methods) may be implemented in any suitable hardware, software, firmware, or combinations thereof. Fig. 12 illustrates non-limiting examples of implementations of functional elements disclosed herein. In some examples, some or all portions of the functional elements disclosed herein may be performed by hardware specifically configured to perform the functional elements.

[0113] Fig.12 is a block diagram of circuitry 1200 that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. Circuitry 1200 includes one or more processors 1202 (sometimes referred to herein as "processors 1202") operably coupled to one or more data storage devices 1204 (sometimes referred to herein as "memory 1204"). Memory 1204 includes machine-executable code 1206 stored therein, and processors 1202 include logic circuitry 1208. The machine-executable code 1206 information describes functional elements that may be implemented (e.g., performed) by logic circuitry 1208. The logic circuitry 1208 is adapted to implement (e.g., perform) the functional elements described by the machine-executable code 1206.When executing the functional elements described by machine-executable code 1206, circuit logic 1200 should be considered special-purpose hardware configured to execute functional elements disclosed herein. In some examples, processors 1202 may be configured to perform the functional elements described by machine-executable code 1206 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process streams.

[0114] When implemented by logic circuitry 1208 of processors 1202, machine-executable code 1206 is configured to adapt processors 1202 to perform operations of examples for adjusting the power of an RF receiver front end, as discussed herein. As a non-limiting example, machine-executable code 1206 may be configured to adapt processors 1202 to perform some or all of the operations of one or more of: process 400, process 500, process 600, process 700, or process 800.

[0115] Also as a non-limiting example, machine-executable code 1206 may be configured to adapt processors 1202 to perform some or all of the features, functions, or operations disclosed herein for one or more of: device 200, including signal processing chain 202, automatic radio controller 206, and logic circuitry 208; device 300, including logic circuitry 302; input signal power state definitions 304, power setting definitions 308, sensitivity setting definitions 314, and blocker tolerance setting definitions 316; signal processing chain 900, including antenna 902, LNA 904, mixer 906, BB 908, TIA 910, ADC 912, or ARC 914; the signal processing chain 1000, including the bypass 1002; the control register 1100.

[0116] Processors 1202 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, another programmable device, or any combination thereof configured to perform the functions disclosed herein. A general-purpose computer, including a processor, is considered a special-purpose computer, while the general-purpose computer is configured to execute functional elements according to machine-executable code 1206 (e.g., software code, firmware code, hardware descriptions) related to examples of the present disclosure.It should be noted that a general-purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, processors 1202 may include any conventional processor, controller, microcontroller, or state machine. Processors 1202 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0117] In some examples, memory 1204 includes volatile data storage (e.g., random access memory (RAM)), non-volatile data storage (e.g., flash memory, a hard disk drive, a solid-state drive, erasable programmable read-only memory (EPROM), without limitation). In some examples, processors 1202 and memory 1204 may be implemented in a single device (e.g., a semiconductor device product, a system-on-chip (SOC), without limitation). In some examples, processors 1202 and memory 1204 may be implemented in separate devices.

[0118] In some examples, machine-executable code 1206 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by memory 1204, which may be directly accessible by processors 1202, and executed by processors 1202 using at least logic circuitry 1208. Also as a non-limiting example, the computer-readable instructions may be stored in memory 1204, transferred to a storage device (not shown) for execution, and executed by processors 1202 using at least logic circuitry 1208. Accordingly, in some examples, logic circuitry 1208 includes electrically configurable logic circuitry 1208.

[0119] In some examples, machine-executable code 1206 may describe hardware (e.g., circuit logic) to be implemented in logic circuitry 1208 to perform the functional elements. This hardware may be described at a variety of abstraction levels, from low-level transistor layouts to high-level description languages. At a high abstraction level, a hardware description language (HDL), such as an IEEE standard hardware description language (HDL), may be used. As non-limiting examples, VERILOG™, SYSTEMVERILOG™, or Very Large Scale Integration (VLSI) hardware description languages ​​(VHDL) may be used.

[0120] HDL descriptions can be freely converted into descriptions at any of numerous other abstraction levels. As a non-limiting example, a high-level description can be converted into a logic-level description, such as a register transfer language (RTL), a gate-level description (GL), a layout-level description, or a mask-level description. As a non-limiting example, micro-operations performed by hardware logic circuits (e.g.,The operations to be performed (e.g., gates, flip-flops, registers, without limitation) of the logic circuitry 1208 may be described in an RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, corresponding to a physical layout of an integrated circuit, a programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Accordingly, in some examples, the machine-executable code 1206 may include an HDL, an RTL, a GL description, a mask-level description, another hardware description, or any combination thereof.

[0121] In examples where machine-executable code 1206 includes a hardware description (at any level of abstraction), a system (not shown, but including memory 1204) may be configured to implement the hardware description described by machine-executable code 1206. As a non-limiting example, processors 1202 may include a programmable logic device (e.g., an FPGA or a PLC), and logic circuitry 1208 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 1208. Also as a non-limiting example, logic circuitry 1208 may include hard-wired logic manufactured by a manufacturing system (not shown, but including memory 1204) according to the hardware description of machine-executable code 1206.

[0122] Regardless of whether the machine-executable code 1206 includes computer-readable instructions or a hardware description, the logic circuitry 1208 is adapted to perform the functional elements described by the machine-executable code 1206 when implementing the functional elements of the machine-executable code 1206. It should be noted that although a hardware description may not directly describe functional elements, a hardware description indirectly describes functional elements that the hardware elements described by the hardware description can perform.

[0123] As used in the present disclosure, the terms "module" or "component" may refer to specific hardware implementations configured to perform the actions of the module or component and / or software objects or software routines stored on and / or executed by general-purpose hardware (e.g., but not limited to, computer-readable media, processing devices) of the computing system. In some examples, the various components, modules, engines, and services described in the present disclosure may be implemented as objects or processes executing on the computing system (e.g., as separate threads).Although some of the systems and methods described in the present disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and are contemplated.

[0124] As used in the present disclosure, the term "combination" with reference to a plurality of elements may include a combination of all of the elements or any of various different subcombinations of some of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to one of A, B, C, or D; the combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0125] Terms used in the present disclosure, and particularly in the appended claims (e.g., without limitation, the body of the appended claims), are generally intended to be "open-ended" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "comprising" should be interpreted as "at least comprising," the term "includes" should be interpreted as "includes, but not limited to"). As used herein, the term "each" means "some or a whole." As used herein, the term "all" means a "whole."

[0126] Furthermore, if a specific number of introduced claim statements are intended, that intention will be expressly stated in the claim, and in the absence of such reciting, no such intention exists. As an aid to understanding, for example, the following accompanying claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim statements. However, the use of such phrases should not be construed to imply that the introduction of a claim statement by the indefinite articles "a" or "an" limits a particular claim containing such introduced claim statement to examples containing only one such statement, even if the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g.,"a" and / or "an" shall be interpreted to mean "at least one" or "one or more", without limitation; the same applies to the use of certain articles used to introduce claim particulars.

[0127] In addition, even if a particular number of an introduced claim statement is explicitly stated, one of ordinary skill in the art will recognize that such a statement should be interpreted to mean at least the stated number (e.g., simply stating "two statements" without other modifiers means at least two statements, or two or more statements, without limitation). Furthermore, where a convention analogous to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such construction is generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, without limitation.

[0128] Furthermore, any disjunctive word or phrase representing two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibility of including either term, one term or the other, or both. For example, the phrase "A or B" should be understood to include the possibilities "A" or "B" or "A and B." Other non-limiting examples include: Example 1: A device comprising: an RF receiver front-end offering at least three different power modes; logic circuitry for determining a power mode of the three different power modes at least in part in response to the input signal power condition; and an automatic radio controller for setting a power mode of the RF receiver front-end to the determined one of the three different power modes. Example 2: The device of Example 1, wherein the different power modes include different sensitivity settings and blocker tolerance settings. Example 3: The device according to one or more of examples 1 and 2, wherein the RF receiver front end offers one or more further different power modes, and wherein the respective power associated with the one or more further different power modes is between the highest sensitivity and the lowest sensitivity. Example 4: The device of one or more of Examples 1 to 3, wherein the logic circuit is to: obtain a value representative of a power level of an input signal to the RF receiver front-end; compare the value representative of the input signal power level to one or more thresholds, wherein the one or more thresholds are probability-based thresholds; and determine the input signal power state at least in part in response to the comparison. Example 5: The device of one or more of examples 1 to 4, wherein the logic circuit is to: select the one or more thresholds based at least in part on an indication of the RF receiver front-end mode. Example 6: The device of one or more of examples 1 to 5, wherein the logic circuit is to: determine a power setting based at least in part on the input signal power state, wherein the determined power setting is associated with the power mode. Example 7: The device of one or more of examples 1 to 6, wherein the performance-defining setting applies to one or more of: gain, DC bias current, bandwidth, or clock rate of a performance-defining block of a signal processing chain of the RF receiver front end. Example 8: The device of one or more of examples 1 to 7, comprising an automatic radio controller for: determining a power-defining setting based at least in part on the determined power setting; and applying the determined power-defining setting to the RF receiver front end. Example 9: The device of one or more of examples 1 to 8, wherein the logic circuit includes: input signal power state definitions including one or more threshold values ​​associated with input signal power states; and power setting definitions including one or more power settings associated with input signal power states. Example 10: The device of one or more of Examples 1 to 9, wherein the RF receiver front end includes a signal processing chain comprising: a low-noise amplifier; a mixer; a baseband amplifier; an intermediate frequency (IF) amplifier with a built-in low-pass filter; and an analog-to-digital converter (ADC). Example 11: The device according to one or more of examples 1 to 10, comprising: a circuit for selectively bypassing the baseband amplifier. Example 12: The device according to one or more of examples 1 to 11, comprising: an automatic radio controller for dynamically adjusting one or more parameters of power-defining blocks of the RF receiver front end in one of at least three different power modes. Example 13: The device of one or more of examples 1 to 12, wherein the logic circuit is to establish a default power mode, wherein a power setting associated with the default power mode is lower than a power setting associated with the established one of the three different power modes. Example 14: A method comprising: determining a power state of an input signal to an RF receiver front end; and setting a power mode of the RF receiver front end to one of at least three different power modes offered by the RF receiver front end, at least in part in response to the determined input signal power state. Example 15: The method of Example 14, comprising: obtaining a value representative of a power level of the input signal to the RF receiver front-end; comparing the value representative of the power level of the input signal to the RF receiver front-end to one or more thresholds, wherein the one or more thresholds are probability-based thresholds; and determining the power state of the input signal at least in part in response to the comparison. Example 16: The method of one or more of Examples 14 and 15, comprising: selecting the one or more thresholds based at least in part on an indication of the RF receiver front-end mode, wherein the one or more thresholds are probability-based thresholds. Example 17: The method of one or more of Examples 14 to 16, comprising: determining a power setting based at least in part on the input signal power state, wherein the determined power setting is associated with one of at least three power modes offered by the RF receiver front-end; and determining a power-defining setting based at least in part on the determined power setting. Example 18: The method of one or more of examples 14 to 17, wherein the power-defining setting applies to gain, DC bias current, bandwidth, or clock rate of a power block of a signal processing chain of the RF receiver front end. Example 19: The method of one or more of examples 14 to 18, comprising: applying the determined power-defining setting to the RF receiver front end. Example 20: The method of one or more of examples 14 to 19, wherein the determined power setting includes one or more of a sensitivity setting or a blocker tolerance setting. Example 21: The method of one or more of Examples 14 to 20, comprising: setting the power mode of the RF receiver front-end to a default power mode, wherein a power setting associated with the default power mode is lower than a power setting associated with the set power mode of at least three different power modes offered by the RF receiver front-end. Example 22: The method of one or more of Examples 14 to 21, wherein setting the power mode of the RF receiver front end to the default power mode comprises: setting the power mode of the RF receiver front end to the default power mode at least in part in response to an indication of: a power-up, a power-on reset, or a reset. Example 23: The method of one or more of examples 14 to 22, wherein the set one of at least three different power modes offered by the RF receiver front end is a default power mode.

[0129] Although the present disclosure has been described herein with reference to certain illustrated examples, those of ordinary skill in the art will recognize and understand that the present invention is not limited thereto. Rather, many additions, omissions, and modifications may be made to the illustrated and described examples without departing from the scope of the invention as claimed below, along with their legal equivalents. Furthermore, features of one example may be combined with features of another example and still be included within the scope of the invention contemplated by the inventor. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 373,171

[0001]

Claims

[1] Facility comprising: an RF receiver front end that offers at least three different power modes; a logic circuit for determining a power mode of the three different power modes at least in part in response to the input signal power state and an automatic radio control to set a power mode of the RF receiver front end to the specified one of the three different power modes. [2] The device of claim 1, wherein the different power modes include different sensitivity settings and blocker tolerance settings. [3] The device of claim 1, wherein the RF receiver front end offers one or more further different power modes, and wherein the respective power associated with the one or more further different power modes is between the highest sensitivity and the lowest sensitivity. [4] The device of claim 1, wherein the logic circuit is for: Obtaining a value representative of a power level of an input signal to the RF receiver front end; Comparing the value representative of the input signal power level with one or more threshold values, wherein the one or more threshold values ​​are probability-based threshold values; and Determining the input signal power state at least in part in response to the comparison. [5] The device of claim 4, wherein the logic circuit is for: Selecting the one or more thresholds based at least in part on an indication of the RF receiver front-end mode. [6] The device of claim 4, wherein the logic circuit is for: Determining a power setting based at least in part on the input signal power state, wherein the determined power setting is associated with the power mode. [7] The device of claim 6, wherein the performance defining setting is for one or more of a gain, a DC bias current, a bandwidth, or a clock rate of a power defining block of a signal processing chain of the RF receiver front end. [8] Device according to claim 6, comprising an automatic radio control for: Determining a performance-defining setting based at least in part on the determined performance setting and Apply the determined performance-defining setting to the RF receiver frontend. [9] The device of claim 1, wherein the logic circuit includes: Input signal power state definitions including one or more threshold values ​​associated with input signal power states; and Power setting definitions that include one or more power settings associated with input signal power states. [10] The device of claim 1, wherein the RF receiver front end includes a signal processing chain comprising: a low-noise amplifier; a mixer; a baseband amplifier; an intermediate frequency amplifier (IF amplifier) ​​with built-in low-pass filter and an analog-to-digital converter (ADC). [11] The device of claim 10, comprising: a circuit for selectively bypassing the baseband amplifier. [12] Device according to claim 1, comprising: an automatic radio control for dynamically adjusting one or more parameters of performance-defining blocks of the RF receiver front-end in one of at least three different performance modes. [13] The device of claim 1, wherein the logic circuit is to establish a default power mode, wherein a power setting associated with the default power mode is lower than a power setting associated with the specified power mode of the three different power modes. [14] Method comprising: Determining a power state of an input signal to an RF receiver front end and Setting a power mode of the RF receiver front end to one of at least three different power modes offered by the RF receiver front end, at least in part in response to the determined input signal power condition. [15] A method according to claim 14, comprising: Obtaining a value representative of a power level of the input signal to the RF receiver front end; Comparing the value representative of the power level of the input signal to the RF receiver front-end with one or more thresholds, wherein the one or more thresholds are probability-based thresholds; and Determining the power state of the input signal at least in part in response to the comparison. [16] A method according to claim 15, comprising: Selecting the one or more thresholds based at least in part on an indication of the RF receiver front-end mode, wherein the one or more thresholds are probability-based thresholds. [17] A method according to claim 14, comprising: Determining a power setting based at least in part on the input signal power state, wherein the determined power setting is associated with one of at least three power modes offered by the RF receiver front end; and Determining a performance-defining setting based at least in part on the determined performance setting. [18] The method of claim 17, wherein the performance-defining setting is for gain, DC bias current, bandwidth, or clock rate of a power block of a signal processing chain of the RF receiver front end. [19] A method according to claim 17, comprising: Apply the determined performance-defining setting to the RF receiver frontend. [20] The method of claim 17, wherein the determined power setting includes one or more of a sensitivity setting or a blocker tolerance setting. [21] A method according to claim 14, comprising: Setting the power mode of the RF receiver front end to a default power mode, wherein a power setting associated with the default power mode is lower than a power setting associated with the set power mode of at least three different power modes offered by the RF receiver front end. [22] The method of claim 21, wherein setting the power mode of the RF receiver front-end to the standard power mode comprises: Setting the power mode of the RF receiver front end to the default power mode at least in part in response to an indication of: a power-up, a power-up reset, or a reset. [23] The method of claim 14, wherein the set power mode of at least three different power modes offered by the RF receiver front end is a default power mode.

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