System and method for testing a non-volatile memory

Abstract

According to one embodiment, a method for characterizing a non-volatile memory comprises applying a first voltage to a wordline conductively coupled to a non-volatile memory cell, and measuring a current flowing through the non-volatile memory cell in response to applying the first voltage. Measuring the current comprises using a sense amplifier, comparing the current flowing through the non-volatile memory cell to a plurality of different first currents generated by an adjustable current source while applying the same first voltage to the wordline, and determining the measured current based on the comparison.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This international application claims priority to U.S. patent application No. 18 / 069,408, filed December 21, 2022, which application is hereby incorporated by reference. TECHNICAL FIELD

[0002] The present invention relates generally to an electronic system and method, and in certain embodiments, to a system and method for testing a non-volatile memory. BACKGROUND

[0003] Programmable non-volatile memories (NVMs) are useful in many applications because they retain stored information even when power is removed from the memory. There are many different types of programmable non-volatile memory, including but not limited to programmable read-only memory (PROM), electrically erasable ROM (EEPROM), and flash memory. These types of memory have multiple methods for storing charge, including but not limited to placing charge on a floating-gate or silicon oxide nitride oxide silicon (SONOS) memory material or node. Like other types of memory, programmable NVMs are typically constructed as an array of bitcells arranged in rows and columns. Each bitcell can comprise one transistor, one split-gate transistor, or two transistors (i.e., 1T, 1.5T, or 2T cells).During programming, charge is injected into the storage node of one of the transistors. During normal operation of the NVM, bit cells are read by selecting a row of bit cells via a word line (WL) and measuring the output currents of each bit cell via sense amplifiers coupled to bit lines.

[0004] In practical memory applications, the device characteristics of bitcells can vary with respect to semiconductor process parameters and can vary arbitrarily with respect to each other. Therefore, in some applications, the threshold value of each bitcell is measured to determine read parameters, write parameters, and sense amplifier threshold currents. Additionally, some bitcells may be defective and require replacement using redundant bitcells. However, given the large size of modern non-volatile memories, it can take a long time to measure and characterize each cell, resulting in increased test costs. OVERVIEW

[0005] According to one embodiment, a method for characterizing a non-volatile memory comprises applying a first voltage to a wordline conductively coupled to a non-volatile memory cell, and measuring a current flowing through the non-volatile memory cell in response to applying the first voltage. Measuring the current comprises using a sense amplifier, comparing the current flowing through the non-volatile memory cell to a plurality of different first currents generated by an adjustable current source while applying the same first voltage to the wordline, and determining the measured current based on the comparison.

[0006] According to another embodiment, a memory system comprises: an integrated circuit having: a memory array comprising non-volatile memory cells, a plurality of wordline drivers coupled to the memory array, a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus, an adjustable current source coupled to the plurality of sense amplifiers, a first control circuit, and a second control circuit.The first control circuit is configured to set the adjustable current source to a test current and apply a first address to the memory array to select a row of the non-volatile memory cells; and the second control circuit is configured to: read outputs of the sense amplifier and iteratively update the test current based on outputs of the sense amplifier to determine a current flowing through at least one non-volatile memory cell of the row of non-volatile memory cells.

[0007] According to another embodiment, a method for characterizing a non-volatile memory comprises: operating the non-volatile memory in a test mode, comprising: performing a test read operation of the non-volatile memory, comprising: applying a row address to the non-volatile memory to select a row of non-volatile memory cells, grounding word lines coupled to the selected row of non-volatile memory cells, measuring a current of at least one non-volatile memory cell of the row of non-volatile memory cells, the word lines being grounded, and incrementing the row address; and repeating performing the test read operation using the incremented row address. BRIEF DESCRIPTION OF THE CHARACTERS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings in which: Fig. 1A illustrates a block diagram of an embodiment memory system; and Fig. 1B illustrates a diagram showing an exemplary read current distribution for N memory cells; Fig. 2A and Fig. 2B illustrate flow diagrams of methods according to embodiments of the present invention; Fig. 3A illustrates a block diagram showing the operation of a sense amplifier according to one embodiment; Fig. 3B illustrates a schematic diagram of a wordline driver according to an embodiment; Fig. 3C illustrates a schematic diagram of a conventional wordline driver; Fig. 3D and Fig. 3E illustrate schematic diagrams of embodiment level shifters; and Fig. 3F illustrates a schematic representation of an embodiment reference power generator; Fig. 4 illustrates a timing diagram according to one embodiment; Fig. 5A, Fig. 5B and Fig. 5C illustrate exemplary memory cells that could be used to implement a non-volatile memory array according to embodiments of the present invention; and Fig. 5D is a cross-section illustrating one embodiment of an N-type SONOS transistor; and Fig. 6 illustrates a processing system that may be used to implement portions of embodiment systems.

[0009] Corresponding numbers and symbols in different figures generally refer to corresponding parts unless otherwise noted. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate particular embodiments, a letter indicating variations of the same structure, material, or process step may follow a figure number. DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0010] The making and using of the presently preferred embodiments are discussed in detail below. It should be understood, however, that the present invention provides many applicable inventive concepts that may be practiced in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

[0011] In one embodiment, a non-volatile memory array is characterized by grounding the word lines of each row of memory cells and measuring the output current of each non-volatile memory cell. The current measurement may be performed by iteratively comparing the output current of each memory cell to an adjustable reference current using a sense amplifier to estimate the output current of the non-volatile memory cells. In some embodiments, these measurements may be performed quickly on a row-by-row basis using the non-volatile memory's existing sense amplifiers, external data bus, and sense amplifier current reference circuitry used during normal memory read operation.

[0012] Grounding the wordlines in a non-volatile memory array during testing enables faster characterization of the memory cells compared to conventional systems that measure memory cell thresholds by applying a variable voltage to the wordlines. Conventional systems require additional time to charge and discharge the higher voltages applied to the wordlines before and after each measurement. Embodiment memory systems also have a size advantage over conventional systems because the wordline drivers do not need to include high-voltage circuitry for applying test voltages to the wordlines. The use of smaller wordline drivers reduces silicon area and lowers costs.

[0013] Fig. 1 illustrates an embodiment memory system including an integrated circuit 100 having non-volatile memory. As shown, the integrated circuit 100 includes a memory array 104, a row decoder 102, wordline drivers 103, a controller 106, sense amplifiers 112, a column decoder 110, I / O logic 114 coupled to an external data bus, a reference current generator 108, and a test controller 116. The reference current generator 108 may also be referred to as an adjustable current source. In some embodiments, the integrated circuit 100 may be coupled to an external tester 120 while the memory array 104 is being characterized. Alternatively or in addition to the tester 120, the integrated circuit 100 may also include a built-in self-test (BIST) circuit 118 that performs one or more characterization functions for the memory array 104.The BIST circuit 118 and tester 120 are shown in dashed lines to indicate that these blocks may or may not be present in some embodiments.

[0014] In various embodiments, the components of integrated circuit 100 may be arranged on a single monolithic semiconductor integrated circuit, such as a single semiconductor substrate, and / or on the same monolithic semiconductor integrated circuit as other disclosed system components.

[0015] As shown, memory array 104 includes an array of non-volatile memory cells 105. Each non-volatile memory cell 105 is connected to a respective word line (WL1...WLn) and to a respective bit line (BL1...BLm). During normal operation of the memory, row decoder 102 decodes a row address based on address data ADDR provided at the input of I / O logic 114. The decoded row address is used to select one of the word lines (WL1...WLn) via word line drivers 103, which activate a row of memory cells 105 that generate respective read currents on respective bit lines (BL1...BLm). The current of each bit line is compared using sense amplifiers 112 to a reference current produced by reference current generator 108.Column decoder 110 selects columns of memory array 104 to be routed to sense amplifiers 112, whose outputs are routed to data lines DATA via I / O logic 114. Controller 106 is a memory controller that controls the operation of the memory. In some embodiments, reference current generator 108 may be implemented using a current digital-to-analog converter (CDAC).

[0016] In various embodiments, non-volatile memory cells 105 of memory array 104 are measured to (1) characterize the thresholds of programmed and / or unprogrammed memory cells; (2) determine operating parameters of the memory, such as sense amplifier threshold and programming times, etc.; and / or (3) identify non-functional memory cells to be replaced with redundant memory cells.

[0017] As mentioned above, in various embodiments, the state of each memory is evaluated by determining whether or not a read current of each memory cell is greater than or less than a threshold current. Fig. 1B illustrates a diagram showing an example distribution for read currents for N memory cells, which may represent, for example, N memory cells 105 within a row of the non-volatile memory array 104.

[0018] As shown, each memory cell produces a first lower current when the memory cell is written to a "1" state 134 and produces a second higher current when the memory cell is written to a "0" state 132. In an alternative embodiment, the assignment of the binary states "0" and "1" can be reversed. Current I NOM0 represents an average or nominal current of the N memory cells when they are written to the “0” state, and current I NOM1represents an average or nominal current of the N memory cells when they are written to the "1" state. Current I THRESH represents a threshold current used by sense amplifiers 112 during a read operation to determine whether a particular bit is written to the "0" state or the "1" state. For example, during a read operation, the sense amplifier determines that a memory cell 105 is written to a "0" state if the current produced by the memory cell is greater than the threshold current I THRESH and determines that the memory cell 105 is written to a "1" state when the current produced by the memory cells is less than the threshold current I THRESH is.

[0019] In practical storage systems, the actual currents I NOM0 and I NOM1produced by each memory cell may vary during operation due to changes in temperature, mains voltage, aging of the memory cells, and operating memory parameters, including but not limited to write duration and write voltage. Thus, the memory is designed to provide a certain current reserve I MARG between the nominal current I written as “0” NOM0 and the threshold current I THRESH and between the nominal current I written as “1” NOM1 and the threshold current I THRESH The reserve current I MARG can be selected to ensure adequate noise margin and accurate operation over a specified range of temperatures and line voltages. This margin can be ensured by adjusting the threshold current I THRESH selected to meet predetermined reserve requirements and is in Fig. 1B as dashed lines, which are designated as I NOM0 - I THRESH for the bits written as “0” and I NOM1 + I MARG for the bits written as "1". In various embodiments, bits written as "0" that have a measured current greater than I NOM0 - I THRESH produce, and bits written as “1” that have a measured current less than I NOM0 + I THRESH produce, is considered to have an appropriate margin. For example, the outlier measurement 136 of the bits written as “0” lies within the current margin I MARG , because their corresponding current is greater than I NOM0 - I THRESH On the other hand, the outlier measurement 138 of the bits written as “1” lies outside the current reserve I MARG , because their corresponding current is greater than I NOM1 + I THRESH is.

[0020] In various embodiments, the measurements of the currents of one or more memory cells are determined by iteratively setting the current thresholds of the sense amplifiers 112 and reading the output of the sense amplifiers 112. For example, in one embodiment, the current generated by the reference current generator is set to a first current value for comparison with a particular current threshold. Next, a row of memory cells is read using the first current value. The resulting read values ​​provide an indication of which memory cells are producing current above and below the first current value. For example, with reference to Fig. 1B, if the first current value is set to I NOM1 + I MARGIf the current value were set to "1" after the row of memory cells was written to have "1" values, all measured memory cells would yield a "1" value except for bit 138, which would yield a "0" value, indicating that its current is greater than the first current value. This information could be used, for example, to replace bit 138 with a redundant memory cell or to replace the entire row with a redundant row of memory cells.

[0021] In various embodiments, the memory cells in the row of memory cells may be written to a "1" value, a "0" value, or a combination of "1" and "0" values ​​according to a particular pattern. For example, in one embodiment, all memory cells of a particular row are written to have "0" values. Next, the reference current generated by the reference current generator 108 is successively varied to determine one or more current levels of the written memory cells using a "linear search." For example, with reference to Fig. 1B the initial reference current is greater than the current I NOM0so that the initial measurement results in a set of measurements indicating that memory cells in the series have a current level lower than the initial reference current. During each subsequent measurement, the reference current is successively lowered so that the resulting measurements indicate a mixture of memory cells with currents above and below the reference current. For example, if the reference current is at I NOM0 is, the memory cells with currents above I NOM0 a value of “0”, while the memory cells with currents below I NOM1a value of "1". The current of a particular memory cell can be estimated as a current that lies between a first reference current, at which a "0" is represented, and a second reference current, at which a "1" is represented. These measurements can continue until the current for each memory cell is determined. For example, once the reference current is below the current for the outlier memory cell 136, all memory cells will yield a "0" value. In an alternative embodiment, the linear search could be performed at a lower current (e.g., below I NOM0 - I MARG ) and gradually increased.

[0022] In some embodiments, the currents of a subset of the memory cells may be estimated. For example, the current threshold may be adjusted iteratively to determine the worst-case memory cell (e.g., memory cell 136) written as "0" or to determine a predetermined number of worst-case memory cells with minimum currents and then complete the memory measurement.

[0023] In some embodiments of the present invention, other search techniques could be applied in addition to the linear search technique described above. For example, the current of a particular memory cell could be successively approximated using a binary search algorithm. In such an embodiment, where the reference current generator 108 is implemented using a CDAC, the CDAC is initialized to an initial DAC word in which the MSB of the DAC is set to "1" and the remaining least significant bits are set to "0." In the case where all bits are written to "0," if the measurement of the particular bit indicates a "0," meaning that the reference current is less than the current produced by the particular memory cell, the MSB and the second most significant bit of the CDAC are set to a "1" for the next measurement.On the other hand, if the measurement of the particular bit indicates a "1," meaning that the reference current is greater than the current produced by the particular memory cell, the MSB is set to "0," and the second most significant bit of the CDAC is set to "1" for the next measurement. Measurements continue on a bit-by-bit basis until all bits of the CDAC input word have been trained. In some embodiments, the CDAC word may be stored and modified using a successive approximation register according to known successive approximation techniques known in the art. In such embodiments, the final value stored in the successive approximation register at the end of the measurement represents the estimated value of the memory cell.

[0024] In some embodiments, the measurement results of a plurality of memory cells may be used to determine the reference current when performing a binary search to identify one or more outlier memory cells and / or to identify and measure a current of a worst-case memory cell. In such embodiments, the binary search may be performed to minimize the number of bits that produce a "1" value if bits are preprogrammed to the "0" state. For example, the current used for each successive approximation attempt may be determined by comparing the number of "1" values ​​produced between two successive cycles to converge on a current value at which a single memory cell (e.g., outlier 136) produces a "1" value while the remaining memory cells produce "0" values.In other words, the system is configured to find the cell (or cells) with the lowest erase current.

[0025] While the above current estimation techniques are described with respect to measuring memory cells written to the "0" value, it should be understood that similar measurement techniques could also be used to measure memory cells written to the "1" value. In such embodiments, the polarity of the measurements of the corresponding measurement sequences is reversed and adjusted to the reversed programmed polarity. For example, instead of determining a current of an outlier cell with a minimum current, the current of one or more outlier cells (e.g., cell 138) with a maximum current is determined.

[0026] Each measurement may be controlled, for example, using BIST 118, tester 120, controller 106, test controller 116, or a combination thereof. For example, one of these controllers provides a row address to row decoder 102, analyzes the resulting data output by sense amplifiers 112, and determines a next current to be produced by reference current generator 108. In embodiments where the test operation is controlled by external tester 120 during a test mode, the row address of the test row may be provided via address bits ADDR, and the measured bits may be read via data bus DATA coupled to I / O logic 114. Reference current generator 108 and the operation of embodiment test modes may be controlled by tester 120 via control bus CTL coupled to I / O logic 114.In some embodiments, the various test sequences may be partially controlled by test controller 116. For example, when tester 120 places integrated circuit 100 into a characterization test mode, test controller 116 may configure controller 106 to apply the required test control sequence and configure reference current generator 108 to adapt its reference current to a requested test current or sequence of test currents, as described above. In some embodiments, tester 120 may provide only an initial row address for characterization. In such embodiments, the row address may be incremented internally by test controller 116 and / or BIST 118 after each measurement on a row-by-row basis.

[0027] In some embodiments, tester 120 may analyze the output of each measurement iteration described above and determine a next current value to be provided by reference current generator 108. In alternative embodiments, the analysis of each measurement iteration and / or the determination of the next current value may be implemented internally by BIST 118. In some embodiments, the entire characterization process may be performed internally by BIST 118, and the characterization results may be made available externally via I / O logic 114.

[0028] In various embodiments, the characterization results may be tabulated in a variety of formats. In one embodiment, the characterization results may include a list of the memory cell address location and their associated current thresholds. This list may detail each memory cell in each or a subset of memory cells in each row, such as one or more "worst-case" memory cells and their associated current thresholds. These current thresholds may be expressed in terms of CDAC input words provided to the reference current generator 108 and / or may be converted to an equivalent current threshold and / or an equivalent threshold voltage value based on other physical measurements or characterization data.This conversion may be implemented, for example, using a database, a lookup table, or other data conversion techniques known in the art.

[0029] The memory systems described herein may be implemented in a variety of semiconductor processes, such as a standard CMOS process and / or a CMOS process modified to accommodate one or more particular types of non-volatile memory. While embodiments of the memory architecture are described herein with respect to silicon oxide nitride oxide silicon (SONOS) devices, developed, for example, according to Infineon's SONOS process technology, other embodiments of the invention are not so limited and may include substantially any type of memory cell developed according to substantially any non-volatile process technology.

[0030] Fig. 2A and Fig. 2B illustrate flow diagrams of methods according to embodiments of the present invention. In particular, Fig. 2A illustrates a method 200 for characterizing a non-volatile memory array in which each memory cell to be tested has been written with a “0,” and Fig. 2B illustrates a method 230 for characterizing a non-volatile memory array in which each memory cell to be tested has been written with a "1." In various embodiments, methods 200 and 230 may be performed under the control of test controller 116, BIST 118, and / or tester 120, depending on the implementation of the particular system and its specifications.

[0031] With reference to Fig. 2A, the method 200 begins when a "reserve mode" (e.g., a mode in which the memory cells are characterized) is entered in step 202. This reserve mode can be entered externally via a command sent via the control lines CTL to the Fig. 1A. Next, in step 204, a first row address is provided to the row decoder 102. As discussed above, this row address may be provided by the tester 120, the BIST 118, and / or the test controller 116.

[0032] In step 206, a first initial read current reference is set, for example, by providing a first CDAC input word to the reference current generator 108. This first initial read current may, for example, correspond to the first (e.g., MSB) estimate of a successive approximation by binary search.

[0033] Once the initial set current has been established, the wordline of the selected row is set to a reference voltage such as 0 V (e.g., ground voltage), and a first measurement of the selected row is taken in step 212 by performing a memory read operation. The resulting memory outputs (e.g., the output of sense amplifiers 112) for the selected row are analyzed to determine whether the read operation passes a first set of conditions. In some embodiments, a successful read operation is defined as a memory read operation that produces a "0" for each memory cell in the row of memory cells. If a successful read operation occurs in step 214, the reference current produced by reference current generator 108 is increased in step 210, and step 212 is repeated with an increased reference current.In some implementations, the reference current is increased by incrementing a digital word provided to a CDAC of the reference current generator 108. On the other hand, if a successful read operation does not occur in step 214 (e.g., one or more bits output by the memory read operation indicate a "1"), the reference current produced by the reference current generator 108 is decreased in step 208, and step 212 is repeated with the decreased reference current. The reference current may be decreased, for example, by decrementing a digital word provided to the CDAC of the reference current generator 108.

[0034] In various embodiments, steps 212, 214 and steps 208 and / or 210 are repeated until the measurement is completed in step 213. In some embodiments, the measurement is complete when all bits controlling the CDAC have been toggled and the current of the memory cell is determined (within the accuracy of the CDAC), at which time the method proceeds to step 216, in which the row address is incremented. If the measurement is not complete, the method proceeds to step 214, as described above. In embodiments that use column decoders such as the one in Fig. 1A, the current column decoder setting may be successively incremented in step 216 to read an entire row before the row address is incremented.

[0035] During step 218, a determination is made as to whether the incremented row address is greater than a predetermined maximum address. If the incremented row address is not greater than the maximum row address, the method proceeds to step 212, where the row corresponding to the incremented row address is measured. Conversely, if the incremented row address is greater than the maximum row address, the reserve mode is exited in step 218. The predetermined maximum address may be the maximum address for the non-volatile memory or may be a different address in embodiments where only a subset of memory rows is measured.

[0036] The Fig. The method 230 shown in Figure 2B is similar to that shown in Fig. 2A, except that the memory cells of a particular row are written to have a value of "1." As such, steps 212 and 214 are replaced by steps 232 and 234, respectively. In step 234, the wordline of the selected row is set to 0 V (e.g., ground voltage), and a first measurement of the selected row is taken in step 234 by performing a memory read operation. The resulting memory outputs (e.g., the output of sense amplifiers 112) for the selected row are analyzed to determine whether the read operation passes a first set of conditions. In some embodiments, a successful read operation is defined as a memory read operation that produces a "1" for each selected memory cell in the accessed row of memory cells.If a successful read operation occurs in step 234, the reference current produced by the reference current generator 108 is decreased in step 208, and step 232 is repeated with a decreased reference current. On the other hand, if a successful read operation does not occur in step 234 (e.g., one or more bits output by the memory read operation indicate a "0"), the reference current produced by the reference current generator 108 is increased in step 210, and step 234 is repeated with an increased reference current. The remaining steps of the method 230 proceed as described above with respect to the method 200 in FIG. Fig. 2A.

[0037] Fig. 3A, Fig. 3B, Fig. 3D, Fig. 3E and Fig. 3F illustrate circuits that may be used to implement memory systems according to embodiments of the present invention. Fig. 3A illustrates an embodiment memory detection system 300 comprising: a memory cell 105 corresponding to a memory cell in the Fig. 1A, a sense amplifier 302 corresponding to a sense amplifier selected from the plurality of sense amplifiers in the memory array 104 shown in Fig. 1A, and a reference current generator 108, which is connected to the reference current generator in Fig. 1A corresponds.

[0038] The memory cell 105 may be a non-volatile memory cell, such as a floating-gate memory cell or SONOS memory, configured to produce an output current Icell that depends on a memory state of the memory cell. For example, when the memory cell 105 is in a programmed state (e.g., a "1" state), a lower bitline current Icell is produced. On the other hand, when the memory cell 105 is in an erased or "0" state, a higher bitline current Icell is produced. Accordingly, the sense amplifier 302 may be used to determine the state of the memory cell 105 by comparing the output current Icell of the memory cell 105, which is provided to a sense input of the sense amplifier 302, with a reference current Isense generated by the current generator 108, which is provided to a reference current input of the sense amplifier 302.

[0039] During operation, sense amplifier 302 produces a first logic state with respect to output signal Dout when output current Icell of memory cell 105 is less than reference current Isense, and produces a second logic state when output current Icell is greater than reference current Isense. The first and second logic states could be referred to as a "low" state and a "high" state, or a "0" state and a "1" state, respectively. In some embodiments, this notation could be reversed, such that the first and second logic states are referred to as a "high" state and a "low" state, or a "1" state and a "0" state, respectively.

[0040] The memory cell 105 and the sense amplifier 302 may be constructed using memory cell and sense amplifier circuits known in the art. For example, the memory cell 105 could be a SONOS or charge trap memory cell or a floating gate memory cell, and the sense amplifier 302 may be implemented using a cross-coupled CMOS latch circuit. In alternative embodiments, other memory cell and sense amplifier circuits could be used. The reference current generator 108 may be implemented using a CDAC, such as the CDAC 360 described below with respect to Fig. 3F is described.

[0041] Fig. 3B illustrates one embodiment word line driver circuit 320 that could be used to drive any of the plurality of word line driver circuits within the Fig. 1A. As shown, the wordline driver 320 includes a p-channel MOS transistor P1 coupled between a positive bias node (also referred to as a "positive supply node") and a wordline driver node WLS, and an n-channel MOS transistor N1 coupled between the wordline driver node WLS and a negative bias node (also referred to as a "negative supply node"). The positive bias node and the negative bias node are each coupled to a positive and a negative power supply circuit (e.g., a positive charge pump and a negative charge pump). In some embodiments, the body connection NWELL of the p-channel MOS transistor P1 may be coupled to the positive bias node, and the body connection PWELL of the n-channel MOS transistor N1 may be coupled to the negative supply node.

[0042] A negative level shifter 322 and a positive level shifter 324 respectively provide gate drive signals to the gates of the p-channel MOS transistor P1 and the n-channel MOS transistor N1 based on signals received from the low-voltage series control block 326. In one embodiment, the low-voltage series control block 326 provides an output stage of the Fig. 1A. During normal memory read and write operations, the positive and negative bias nodes provide the required voltages to the word line WLS, as described below with respect to the Fig. 5A, Fig. 5B, Fig. 5C and Fig. 5D. However, during memory cell characterization operations of the embodiment described herein, the negative bias node is fixed to a ground voltage, so that the word line WLS is grounded.

[0043] Device characterization systems and methods of the embodiment that enable wordline grounding during memory cell characterization are advantageous because they enable the use of physically compact wordline drivers. This contrasts with voltage-mode characterization systems and methods that apply a variable voltage to the wordline and require additional circuitry to perform memory cell characterization. To determine the voltage thresholds of the memory cells, a wide range of voltages is applied to the measured memory cells. In some cases, devices designed to handle higher voltages are used to provide these voltages during characterization. In some embodiments, each of these devices may consist of multiple devices interconnected together, occupying a large amount of silicon area.. Fig. Figure 3C illustrates a conventional wordline driver including transistors P1 and N1 and level shifters 322 and 324, along with additional circuitry to support applying a wider positive voltage range to the wordline via p-channel MOS device P3. Additional circuitry further includes p-channel MOS devices P2, an n-channel MOS device N2, and level shifters 333 and 335 that receive input from low voltage row control reserve mode block 336. Conventional wordline driver 330 includes more devices than embodiment wordline driver 320. In various embodiments of the present invention, embodiment wordline drivers are physically smaller than conventional wordline drivers used in voltage mode device characterization.

[0044] Fig. 3D and Fig. 3E illustrate level shifter circuits 332 and 334, which can be used, respectively, to convert the negative and positive level shifter circuits 322 and 324 of the Fig. 3B shown word line driver 320. Fig. 3D shows a negative level shifter 332 configured to convert a low-level logic signal (e.g., 0 V to 1 V) to a high-level logic signal with a signal swing between the negative supply and the positive supply (e.g., -3 V to 0 / 1 V). In various embodiments, the voltage range at the output of the negative level shifter circuit 332 is sufficient to drive the gate of the n-channel MOS transistor N1 ( Fig. 3B), which serves as a high-side switching transistor. The negative level shifter 332 includes a cross-coupled latch including p-channel MOS transistors P4 and P5 and n-channel MOS transistors N4 and N5, and input p-channel MOS transistors P6 and P7, which serve as input transistors. During operation, a low-level logic input IN LV is applied to the gate of the p-channel MOS transistor P6, and an inverted low-level logic input Inb LV is applied to the gate of the p-channel MOS transistor P7. The resulting currents provided by the transistors P6 and P7 cause the cross-coupled latch circuit to provide a high-level logic signal at the output node Out HV and an inverted high-level logic signal OutB HV.

[0045] With reference to Fig. 3E shows a positive level shifter 334 configured to convert a low-level logic signal (e.g., 0 V to 1 V) into a high-level logic signal with a signal swing between the negative supply and the positive supply (e.g., 0 / 1 V to 4 V). In various embodiments, the voltage range at the output of the positive level shifter circuit 334 is sufficient to drive the gate of the p-channel MOS transistor P1 ( Fig. 3B), which serves as a low-side switching transistor. The positive level shifter 334 includes a cross-coupled latch including p-channel MOS transistors P4 and P5 and n-channel MOS transistors N4 and N5, and input n-channel MOS transistors N8 and N9, which serve as input transistors. During operation, a low-level logic input IN LV is applied to the gate of the n-channel MOS transistor N8, and an inverted low-level logic input Inb LV is applied to the gate of the n-channel MOS transistor N9. The resulting currents provided by the transistors N8 and N9 cause the cross-coupled latch circuit to provide a high-level logic signal at the output node Out HV and an inverted high-level logic signal OutB HV.

[0046] It is understood that the Fig. 3D and Fig. The level shifter circuits 332 and 334 shown in Figure 3E are two examples of many possible level shifter circuits that could be used to implement the level shifting functionality of wordline driver 320. In alternative embodiments of the present invention, other level shifting circuits known in the art could be used.

[0047] Fig. Figure 3F illustrates a CDAC circuit 360 that could be used to Fig. 1A. As shown, CDAC circuit 360 is configured to provide an output current Iout based on an n-bit digital input word CDAC[n:1]. In one embodiment of the present invention, CDAC 360 is an 8-bit CDAC; however, other bit resolutions may be used in other embodiments depending on the particular embodiment and its specifications.

[0048] As illustrated, the CDAC circuit 360 is implemented as binary-weighted with n binary-weighted output branches and a bias branch. The bias branch includes p-channel MOS transistors 362, 364, and 366 and a resistor RC1. Current source Iin provides a bias voltage P0_BIAS to transistor 366 in the input branch and transistors 372, 378, and 384 in the output branches. The output of resistor RC1 provides a bias voltage P1_BIAS to transistor 364 in the input branch and transistors 370, 376, and 382 in the output branches, and transistor 362 is used to adjust the on-resistance of select transistors 368, 374, and 380 in the output branches. As shown, transistors 362, 364, and 366 each have a relative size of one unit and are configured to receive the DC bias current Iin.A first output branch includes cascode transistor 372, current source transistor 370, and select transistor 368, which is activated when the LSB of the digital input word CDAC[n:1] is activated. As shown, transistors 368, 370, and 372 have the same sizes as transistors 362, 364, and 366 of the bias branch, so the first branch produces a current of 1·Iin when the branch is active. A second output branch includes cascode transistor 378, current source transistor 376, and select transistor 374, which is activated when the second least significant bit of the digital input word CDAC[n:1] is activated. As shown, transistors 374, 376, and 378 are twice the size of transistors 362, 364, and 366 of the bias branch, so that the second branch produces a current of 2·Iin when the branch is active.An nth output branch includes cascode transistor 384, current source transistor 382, ​​and select transistor 380, which is activated when the MSB of the digital input word CDAC[n:1] is activated. As shown, transistors 380, 382, ​​and 384 are n times the size of transistors 362, 364, and 366 of the bias branch, so the nth branch supplies a current of 2. n-1 ·Iin produced when the branch is active. Additional binary weighted branches, which may have weights between 4 and 2 n-2However, for simplicity of illustration, they are not shown. In some embodiments, CDAC circuitry 360 may be implemented using equally weighted segments or using a combination of equally weighted and binary weighted segments, depending on the specifications of the particular embodiment. In further alternative embodiments, other CDAC circuits and architectures known in the art may also be used.

[0049] Fig. Figure 4 illustrates a timing diagram showing the state of row address lines RADDR and data lines DATA associated with the I / O logic 114 of Fig. 1A, during one embodiment, a memory cell characterization procedure when reading memory array 104. The clock signal CLK, representing the system clock of the memory system, and the signal R_VALID, a control signal that is asserted when an initial row address is written to the test memory system, are also shown. At time t1, when R_VALID is asserted, an initial row address A1 is written to row address lines RADDR. This causes the first measurement, represented by data word D1, to appear on data lines DATA at time t2, with the length of each word corresponding to the width of the row or the width of the selected columns being measured.For example, in an embodiment where 128 sense amplifiers are coupled to the selected columns, and / or in an embodiment using 128 sense amplifiers coupled to a 128-bit wide row, the width of data words D1, D2, D4, and D4 would each be 128 bits. Five clock cycles later, the initial row address A1 is incremented to A2 and applied to row decoder 102, and the corresponding data word D2 appears on data lines DATA at time t3. This process is repeated until memory 104 is completely read. In embodiments using a column decoder such as the one shown in FIG. Fig. Using the column decoder 110 shown in Figure 1A, the separate read operations are performed for each selected column until an entire row is read before the row address RADDR is incremented.

[0050] The Fig. The timing scheme shown in Figure 4 is advantageous because it allows a large number of measurements to be output in a small number of clock cycles. This increases the speed of the characterization test and reduces the test cost per device. In contrast, conventional embodiments require a significant delay between each row measurement of the memory array to enable charging and discharging of the word lines with a built-in charge pump. Additionally, embodiments that provide measurement data over a wide external data bus are more efficient because the measurement data can be quickly clocked out in a parallel manner, which is faster than using narrower output buses or narrower specialty buses such as narrow test buses or control buses.

[0051] It is understood that the timing diagram of Fig. 4 is only one example of possible signal timing relationships in embodiment characterization systems. In alternative embodiments, different timing relationships may be implemented. For example, in an alternative embodiment, the data lines DATA may be updated every n clock cycles, where n is less than or greater than five.

[0052] Fig. 5A, Fig. 5B and Fig. 5C illustrate exemplary memory cells that could be used to implement memory cells 105 of a non-volatile memory array 104 according to embodiments of the present invention. For example, an embodiment of a single-transistor (1T) SONOS memory cell is shown in Fig. 5A, which includes an N-type SONOS transistor having gate, drain, and source terminals (see Fig. 5C). The gate of the SONOS transistor is coupled to receive a SONOS word line voltage (WLS voltage), the drain is coupled to receive a bit line voltage (BL voltage), and the source is coupled to receive a source line voltage (SL voltage). As shown in the cross section of Fig. As shown in Figure 5C, the substrate or well of the SONOS transistor is coupled to receive a well bias voltage (P-WELL). Example voltages for reading, erasing, and programming a 1T SONOS memory cell are shown in Fig. 5D and are discussed in more detail below.

[0053] An embodiment of a 2T SONOS memory cell is shown in Fig. 5B illustrates an N-type SONOS transistor and an N-type pass-through device (FNPASS) included to minimize leakage currents during read operations. The SONOS gate is coupled to receive the SONOS wordline voltage (WLS voltage), while the drain is coupled to receive the bitline voltage (BL voltage). The source of the SONOS transistor is coupled to the drain of the FNPASS device. The gate of the FNPASS device is coupled to receive the wordline voltage (WL voltage), while the source is coupled to receive the sourceline voltage (SL voltage). The SONOS and FNPASS devices may share a common substrate connection. Like the 1T cell, a well bias (P-WELL) is supplied to the substrate of the SONOS and FNPASS devices to facilitate read, erase, and program operations.Example voltages for reading, erasing, and programming a 2T SONOS memory cell are shown in . Fig. 5D and are discussed in more detail below.

[0054] Fig. Figure 5C is a cross-section illustrating one embodiment of an N-type SONOS transistor. Although N-type devices in the Fig. 5A to Fig. 5C, the memory architecture described herein is not so limited and may include p-type devices in other embodiments. One of ordinary skill in the art would understand how the memory architecture could be modified to accommodate such devices.

[0055] As in Fig. As shown in Figure 5C, the gate of the SONOS transistor is separated from the channel by a stack of dielectric layers. The dielectric stack (often referred to as an "ONO stack") may include a thin tunneling layer (typically an oxide) over the channel, a charge-trapping layer (typically a nitride) over the tunneling layer, and a barrier layer (typically an oxide) between the charge-trapping layer and the gate. The charge-trapping layer of the SONOS transistor is the storage node for the 1T and 2T memory cells used, for example, in the Fig. 5A and Fig. 5B. The charge-trapping layer can be "charged" to change the threshold voltage (Vt) of the SONOS transistor and change the value of the bit stored in the 1T or 2T memory cell (e.g., to a "0" or "1"). The threshold voltage (Vt) is defined as the threshold gate-source voltage for current to flow through the SONOS transistor.

[0056] A SONOS memory cell according to embodiments of the present invention can be programmed or erased by applying a voltage of the correct polarity, magnitude, and duration between the gate terminal and the source / drain / substrate terminals of the SONOS transistor. This voltage is referred to as the gate-to-channel voltage. For example, a SONOS memory cell can be programmed by increasing the gate-to-channel voltage of the SONOS transistor to a relatively high positive value (typically between 7 V and 12 V). This causes electrons to tunnel from the channel to the ONO stack, where they are trapped in the charge-trapping nitride layer. The trapped charge produces an energy barrier between the transistor drain and the transistor source, which increases the threshold voltage (Vt) of the SONOS transistor.In one embodiment, a "1" bit can be stored in the memory cell by raising the threshold voltage of a programmed SONOS transistor to a substantially positive Vt. The electrons trapped in the nitride layer can be removed by applying a negative gate-to-channel voltage (typically between -7 V and -12 V) to the SONOS transistor, thereby lowering the threshold voltage of the SONOS transistor and erasing the contents of the memory cell. In one embodiment, an erased SONOS transistor with a substantially negative Vt can be used to store a "0" bit in the memory cell. After programming or erasing, the contents of the SONOS memory cell can be read by applying nominal voltages to a specific combination of word, bit, and source lines and detecting whether or not current flows on the corresponding bit line.

[0057] An example biasing scheme for reading, erasing and programming 1T and 2T SONOS memory cells is shown in Fig. 5D. Some of the Fig. The bias voltages shown in Figure 5D include two entries separated by a prime ( / ). If two entries are included, the first entry corresponds to a "select bias voltage" and the second entry corresponds to a "deselect bias voltage." In some embodiments, the non-volatile memory array 104 may be divided into multiple "blocks" and / or multiple "sectors."

[0058] If a block or sector architecture is used, the Fig. 5D may be applied to an activated block(s) or an activated sector(s) in one embodiment. Deactivated blocks or sectors may also receive a deselect signal (typically 0 V), with the exception of the WL in the 2T cell block architecture (since the WL spans multiple blocks, a WL may not be deactivated in one embodiment if it is connected to an accessed memory cell in an activated block). If the memory array is not divided into blocks or sectors, the Fig. 5D are applied to the entire memory array. Some of the Fig. The bias voltages shown in Figure 5D are marked with an asterisk (*). These bias voltages are exemplary and may differ in other embodiments of the invention. For example, the SL may be floating instead of shorting the SL to the BL during programming and erasing.

[0059] As in Fig. As shown in Figure 5D, 1T and 2T SONOS memory cells can be read by applying a bias voltage (VLIM) to the bit line (BL) while grounding the source line (SL) and the SONOS word line (WLS) of the selected memory cell(s). The word line (WL) of a selected 2T cell can also receive an appropriate bias voltage during read operations. This allows current to flow (or not flow) on the bit line depending on the threshold voltage (V) of the SONOS device. As described in more detail below, bit line currents can be sensed or "seen" by a sense amplifier. In one embodiment, a current value close to zero may indicate the presence of a "1" bit, whereas a significantly higher current value may indicate the presence of a "0" bit in the selected cell. The opposite may be true in alternative embodiments of the invention.

[0060] As in Fig. As shown in Figure 5D, the bias voltage (VLIM) applied to selected BLs during read operations is limited to avoid disturbing other cells on the same BL. In one embodiment, a VLIM of approximately 1.2 V may be provided. As further shown in Fig. As shown in Figure 5D, a line voltage (VPWR) is supplied to the WL of selected 2T cells to activate the N-channel FNPASS devices during read operations. In one embodiment, a line voltage of approximately 2 V may be supplied to the WL of selected 2T cells. In other embodiments, read currents may be increased by supplying a pumped bias voltage above the power supply level to the WL of selected 2T cells. It is noted, however, that the voltages shown in Fig. 5D are exemplary and should not be considered as limiting the invention.

[0061] In some embodiments, select / deselect bias voltages (e.g., 1.2 V / 0 V) may be applied to the BLs of the 1T and 2T memory cells, as well as the word line (WL) connected to the pass device (FNPASS) within the 2T cell. A select / deselect bias voltage (e.g., 0 V / -2 V) may also be applied to the WLS line of the 1T cell to select / deselect the cells during read operations. The select / deselect bias voltage may be used on the WLS line of the 1T cell since it does not have a pass device. As shown in Fig. As shown in Figure 5D, the read bias voltage supplied to the P-well may be different for 1T and 2T cells. In one embodiment, 0 V may be applied to the substrate of the 2T cell. However, a slightly negative bias voltage (e.g., -2 V) may be applied to the substrate of a 1T cell. The negative bias voltage applied to the P-well results in a 0 V gate-to-channel voltage for deselected memory cells. It is noted, however, that the read bias voltages mentioned herein are exemplary and may differ in other embodiments of the invention.

[0062] As in Fig. As shown in Figure 5D, 1T SONOS memory cells can be erased by applying a negative voltage (VNEG) to the SONOS word line (WLS) and a positive voltage (VPOS) to the bit lines (BL), source lines (SL), and substrate (P-well) of targeted or "selected" memory cells. The SONOS word line (WLS) of unselected memory cells within the activated block or sector is biased with VPOS to prevent memory cells on unselected rows from being erased.

[0063] A similar prestressing scheme is shown in Fig. 5D for erasing 2T SONOS memory cells. However, the 2T scheme differs from the 1T scheme in that a select / deselection bias is applied to the word lines (WL) connected to the pass device (FNPASS) in the 2T cell. In one embodiment, VPWR may be applied to a selected WL, while 0 V is applied to all deselected WLs. The select / deselector biases applied to the WLs during erasure may be generated, for example, by word line drivers 103.

[0064] As in Fig. As shown in Figure 5D, 1T SONOS memory cells can be programmed by applying a positive voltage (VPOS) to the SONOS word line (WLS) and a negative voltage (VNEG) to the bit lines (BL), source lines (SL), and substrate (P-well) of selected memory cells. The SONOS word line (WLS) of unselected memory cells within the activated block or sector is biased with VNEG to prevent memory cells on unselected rows from being programmed.

[0065] In some embodiments, the BL and SL of unselected memory cells may be biased (VBL) to prevent programming of memory cells that should be left in the erased state. As described in more detail below, a VBL bias between 0 V and VPWR may be used to prevent programming of certain cells. In one embodiment, a VBL of approximately 1 V may be provided.

[0066] A similar prestressing scheme is shown in Fig. 5D for programming 2T SONOS memory cells. However, the 2T scheme differs from the 1T scheme in that a VWL bias (typically between 0 V and VNEG) is applied to the word line (WL) of all 2T cells to reduce HV damage to the SONOS device during programming operations.

[0067] As further stated in Fig. As shown in Figure 5D, a SONOS memory cell can be programmed and erased by applying positive (VPOS) and negative (VNEG) voltages to the gate, drain, source, and substrate terminals of the SONOS transistor. In various embodiments, the SONOS memory cell can be programmed or erased in the manner described above before applying embodiment characterization techniques.

[0068] The selection and biasing of memory cells during embodiment characterization operations is similar to the selection and biasing of memory cells during a read operation. For example, VPWR can be applied to the WL of the selected 2T cells to activate the FNPASS devices, while a ground voltage (0 V) is applied to the WLS of the selected 2T cells. For 1T cells, the ground voltage (0 V) is applied to the WLS of the selected 1T cells.

[0069] With reference to Fig. 6, a block diagram of a processing system 600 is provided according to an embodiment of the present invention. The processing system 600 represents a universal platform and the general components and functionalities that can be used to implement portions of embodiments described herein, such as the controller 106, the test controller 116, the BIST 118, and / or the tester 120 described above with respect to Fig. 1A. For example, the processing system 600 may be used to implement some or all of the processing used to analyze memory cell characterization results and determine which reference currents should be applied to the memory array under test. The processing system 600 may also be used to implement portions of the Fig. 2A and Fig. 2B described embodiment method.

[0070] The processing system 600 may, for example, include a central processing unit (CPU) 602 and memory 604 connected to a bus 608, and may be configured to perform the processes discussed above according to programmed instructions stored in the memory 604 or on other non-transitory computer-readable media. The processing system 600 may further include, if desired or required, a display adapter 610 to provide a connection to a local display 612 and an input / output (I / O) adapter 614 to provide an input / output interface for one or more input / output devices 616, such as a mouse, keyboard, flash drive, or the like.

[0071] The processing system 600 may also include a network interface 618, which may be implemented using a network adapter configured to couple to a wired connection, such as a network cable, a USB interface, or the like, and / or a wireless / cellular connection for communication with a network 620. The network interface 618 may also include a suitable receiver and transmitter for wireless communication. It should be noted that the processing system 600 may include other components. For example, the processing system 600 may include hardware components, power supplies, cables, a motherboard, removable storage media, enclosures, and the like if implemented externally. These other components, although not shown, are considered part of the processing system 600.In some embodiments, processing system 600 may be implemented on a single monolithic semiconductor integrated circuit and / or on the same monolithic semiconductor integrated circuit as other disclosed system components.

[0072] Embodiments of the present invention are summarized herein. Other embodiments may also be understood from the entirety of the description and claims filed herein.

[0073] Example 1. A method for characterizing a non-volatile memory, the method comprising: applying a first voltage to a wordline conductively coupled to a non-volatile memory cell; measuring a current flowing through the non-volatile memory cell in response to applying the first voltage, wherein the measuring comprises: using a sense amplifier, comparing the current flowing through the non-volatile memory cell to a plurality of different first currents generated by an adjustable current source while applying the same first voltage to the wordline; and determining the measured current based on the comparison.

[0074] Example 2. The method of Example 1, further comprising determining whether the measured current falls within a predetermined range.

[0075] Example 3. The method of any one of examples 1 or 2, further comprising replacing the non-volatile memory cell with a redundant cell if the measured current does not fall within the predetermined range.

[0076] Example 4. The method of any one of examples 1 to 3, further comprising setting a memory operating parameter based on the measured current, wherein the memory operating parameter comprises a write duration or a write voltage.

[0077] Example 5. The method according to any one of examples 1 to 4, wherein the first voltage is a ground voltage.

[0078] Example 6. The method of any one of examples 1 to 5, wherein measuring the current flowing through the non-volatile memory cell comprises iteratively adjusting a current generated by the adjustable current source.

[0079] Example 7. The method of example 6, wherein iteratively adjusting the current generated by the adjustable current source comprises performing a binary search.

[0080] Example 8. The method of any one of examples 6 or 7, wherein iteratively adjusting the current produced by the adjustable current source comprises: increasing the current produced by the adjustable current source when a result of the comparing indicates a first comparison result; and decreasing the current produced by the adjustable current source when the result of the comparing indicates a second comparison result opposite to the first comparison result.

[0081] Example 9. The method of any one of examples 6 to 8, wherein iteratively adjusting the adjustable current source comprises iteratively adjusting an input word provided to a current digital-to-analog converter (CDAC).

[0082] Example 10. The method of any one of Examples 1 to 9, wherein: the non-volatile memory comprises a plurality of non-volatile memory cells; and the sense amplifier comprises a plurality of sense amplifier circuits configured to determine memory states of the plurality of non-volatile memory cells.

[0083] Example 11. The method of Example 10, further comprising providing outputs of the plurality of sense amplifier circuits to an external data bus.

[0084] Example 12. The method of any one of examples 10 or 11, wherein: the plurality of non-volatile memory cells are arranged in a row within a memory array; and the method further comprises measuring the current flowing through the non-volatile memory cells in at least a portion of the row of the memory array.

[0085] Example 13. The method of Example 12, wherein measuring the current flowing through the non-volatile memory cells in at least a portion of the row of the memory array comprises selecting the non-volatile memory cells using a column decoder.

[0086] Example 14. A memory system comprising: an integrated circuit comprising: a memory array comprising non-volatile memory cells, a plurality of wordline drivers coupled to the memory array, a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus, an adjustable current source coupled to the plurality of sense amplifiers, and a first control circuit configured to: set the adjustable current source to a test current and apply a first address to the memory array to select a row of the non-volatile memory cells;and a second control circuit configured to: read outputs of the sense amplifier and iteratively update the test current based on outputs of the sense amplifier to determine a current flowing through at least one non-volatile memory cell of the row of non-volatile memory cells;

[0087] Example 15. The memory system of example 14, wherein the second control circuit is arranged on the integrated circuit.

[0088] Example 16. The memory system of example 15, wherein the second control circuit is external to the integrated circuit.

[0089] Example 17. The memory system of any one of examples 15 or 16, wherein the second control circuit is configured to read the outputs of the sense amplifiers via the external data bus.

[0090] Example 18. The memory system of any of Examples 14 to 17, wherein each wordline driver of the plurality of wordline drivers comprises: a first transistor coupled between a wordline and a positive supply node; and a second transistor coupled between the wordline and a negative supply node, wherein the wordline is coupleable via the first transistor and the second transistor only to the positive supply node and the negative supply node, respectively.

[0091] Example 19. The memory system of Example 18, further comprising: a first level shifter coupled to the first transistor; and a second level shifter coupled to the second transistor, wherein the wordline driver does not include any level shifting circuitry other than the first level shifter and the second level shifter.

[0092] Example 20. The memory system of any one of examples 14 to 19, wherein the adjustable current source comprises a current DAC.

[0093] Example 21. The memory system of any one of Examples 14 to 20, wherein the non-volatile memory cells comprise silicon oxide nitride oxide silicon (SONOS) memory cells.

[0094] Example 22. A method for characterizing a non-volatile memory, the method comprising: operating the non-volatile memory in a test mode comprising: performing a test read operation of the non-volatile memory, comprising: applying a row address to the non-volatile memory to select a row of non-volatile memory cells, grounding word lines coupled to the selected row of non-volatile memory cells, measuring a current of at least one non-volatile memory cell of the row of non-volatile memory cells with the word lines grounded, and incrementing the row address; and repeating performing the test read operation using the incremented row address.

[0095] Example 23. The method of Example 22, further comprising: applying a column address to select a subset of the row of selected non-volatile memory cells after applying the row address; incrementing the column address after measuring the current and before incrementing the row address; and repeating performing the test read operation using the incremented column address after incrementing the column address and before incrementing the row address if the selected row of non-volatile memory cells has not been completely read.

[0096] Example 24. The method of any one of examples 22 or 23, further comprising: determining non-functional non-volatile memory cells of the non-volatile memory based on measuring the current; or determining operational memory parameters based on measuring the current.

[0097] Example 25. The method of any one of Examples 22 to 24, wherein measuring the current of the at least one non-volatile memory cell comprises: applying a reference current to a sense amplifier coupled to the at least one non-volatile memory cell to produce a sense amplifier output; modifying the reference current based on the sense amplifier output; and repeating applying the reference current and modifying the reference current to estimate the current of the at least one non-volatile memory cell.

[0098] Example 26. The method of example 25, wherein repeating the applying of the reference current and the modifying of the reference current is performed according to a linear search or a binary search.

[0099] Example 27. The method of any one of examples 22 to 26, wherein the at least one non-volatile memory cell of the series of non-volatile memory cells comprises a non-volatile memory cell having a largest or smallest threshold value of the non-volatile memory cells of the series of non-volatile memory cells.

[0100] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will become apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass such modifications or embodiments. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 069,408

[0001]

Claims

[1] A method for characterizing a non-volatile memory, the method comprising: Applying a first voltage to a word line conductively coupled to a non-volatile memory cell; Measuring a current flowing through the non-volatile memory cell in response to the application of the first voltage, the measuring comprising: using a sense amplifier, comparing the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source while applying the same first voltage to the word line; and Determine the measured current based on the comparison. [2] The method of claim 1, further comprising determining whether the measured current falls within a predetermined range. [3] The method of claim 2, further comprising replacing the non-volatile memory cell with a redundant cell if the measured current does not fall within the predetermined range. [4] The method of claim 1, further comprising setting a memory operating parameter based on the measured current, wherein the memory operating parameter includes a write duration or a write voltage. [5] The method of claim 1, wherein the first voltage is a ground voltage. [6] The method of claim 1, wherein measuring the current flowing through the non-volatile memory cell includes iteratively adjusting a current generated by the adjustable current source. [7] The method of claim 6, wherein iteratively adjusting the current generated by the adjustable current source includes performing a binary search. [8] The method of claim 6, wherein iteratively adjusting the current generated by the adjustable current source comprises: Increasing the current produced by the adjustable current source when a result of the comparison indicates a first comparison result; and Reducing the current produced by the adjustable current source when the result of the comparison indicates a second comparison result that is opposite to the first comparison result. [9] The method of claim 6, wherein iteratively adjusting the adjustable current source includes iteratively adjusting an input word provided to a current digital-to-analog converter (CDAC). [10] A method according to claim 1, wherein: the non-volatile memory includes a plurality of non-volatile memory cells; and the sense amplifier includes a plurality of sense amplifier circuits configured to determine memory states of the plurality of non-volatile memory cells. [11] The method of claim 10, further comprising providing outputs of the plurality of sense amplifier circuits to an external data bus. [12] A method according to claim 10, wherein: the plurality of non-volatile memory cells are arranged in a row within a memory array; and the method further includes measuring the current flowing through the non-volatile memory cells in at least a portion of the row of the memory array. [13] The method of claim 12, wherein measuring the current flowing through the non-volatile memory cells in at least a portion of the row of the memory array includes selecting the non-volatile memory cells using a column decoder. [14] A storage system that includes: an integrated circuit that includes: a memory array containing non-volatile memory cells, a plurality of word line drivers coupled to the memory array, a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus, an adjustable current source coupled to the plurality of sense amplifiers, and a first control circuit configured to: Setting the adjustable current source to a test current and Applying a first address to the memory array to select a row of the non-volatile memory cells; and a second control circuit configured to: Reading outputs of the sense amplifier and iteratively updating the test current based on outputs of the sense amplifier to determine a current flowing through at least one non-volatile memory cell of the row of non-volatile memory cells. [15] The memory system of claim 14, wherein the second control circuit is disposed on the integrated circuit. [16] The memory system of claim 15, wherein the second control circuit is external to the integrated circuit. [17] The memory system of claim 16, wherein the second control circuit is configured to read the outputs of the sense amplifiers via the external data bus. [18] The memory system of claim 14, wherein each word line driver of the plurality of word line drivers includes: a first transistor coupled between a word line and a positive supply node; and a second transistor coupled between the word line and a negative supply node, wherein the word line is only coupleable to the positive supply node and the negative supply node, respectively, via the first transistor and the second transistor. [19] A storage system according to claim 18, further comprising: a first level shifter coupled to the first transistor; and a second level shifter coupled to the second transistor, wherein the wordline driver does not include any further level shifting circuitry other than the first level shifter and the second level shifter. [20] The memory system of claim 14, wherein the adjustable current source includes a current DAC. [21] The memory system of claim 14, wherein the non-volatile memory cells include silicon oxide nitride oxide silicon (SONOS) memory cells. [22] A method for characterising a non-volatile memory, the method comprising: Operating the non-volatile memory in a test mode that includes: Perform a test read of the non-volatile memory, which includes: Applying a row address to non-volatile memory to select a row of non-volatile memory cells, Grounding word lines coupled to the selected row of non-volatile memory cells, Measuring a current of at least one non-volatile memory cell of the series of non-volatile memory cells, wherein the word lines are grounded, and Incrementing the row address; and Repeat performing the test read operation using the incremented row address. [23] The method of claim 22, further comprising: Applying a column address to select a subset of the row of selected non-volatile memory cells after applying the row address; Incrementing the column address after measuring the current and before incrementing the row address; and Repeating the test read operation using the incremented column address after incrementing the column address and before incrementing the row address if the selected row of non-volatile memory cells has not yet been completely read. [24] A method according to claim 22, further comprising: Determining non-functional non-volatile memory cells of the non-volatile memory based on measuring the current; or Determine operating memory parameters based on measuring current. [25] The method of claim 22, wherein measuring the current of the at least one non-volatile memory cell comprises: Applying a reference current to a sense amplifier coupled to the at least one non-volatile memory cell to produce a sense amplifier output; Modifying the reference current based on the sense amplifier output; and Repeating the application of the reference current and the modification of the reference current to estimate the current of the at least one non-volatile memory cell. [26] The method of claim 25, wherein repeating the application of the reference current and the modification of the reference current is performed according to a linear search or a binary search. [27] The method of claim 22, wherein the at least one non-volatile memory cell of the series of non-volatile memory cells includes a non-volatile memory cell having a largest or smallest threshold value of the non-volatile memory cells of the series of non-volatile memory cells.

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