Control circuit, control method, control module and display device

Abstract

The present disclosure provides a control circuit, a control method, a control module and a display device.The control circuit comprises a first control signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit, and a first output circuit; and N is a positive integer; wherein the first gating circuit, under the control of a gating control signal, controls the writing of a gating input signal to the first first node; and the first output circuit, under the control of the potential of the first second node, controls the connection between the output control terminal of the Nth stage and the first voltage terminal, and, under the control of the potential of the first third control node, controls the connection between the output control terminal of the Nth stage and the second voltage terminal; wherein the first third control node and the first second control node are distinct nodes.Embodiments of the present disclosure enable the updating of a local image on a display screen by controlling the gating input signal, thereby reducing power consumption.

Description

Cross-references to related registrations

[0001] The present application claims the priorities of PCT application number PCT / CN2022 / 140042, PCT application number PCT / CN2022 / 140046, PCT application number PCT / CN2022 / 140044 and PCT application number PCT / CN2022 / 140045, which were filed on 19 December 2022, the disclosure of which is hereby cited in full as part of the present application. Technical field

[0002] The present disclosure relates to the field of display technology and in particular to a control circuit, a control method, a control module and a display device. State of the art

[0003] In related technologies, updating an image on an OLED (organic light-emitting diode) display requires initializing pixel voltages and writing them to all row pixel circuits within a frame time. However, for some special images (such as an always-on display (AOD) image, which controls local screen illumination without lighting the entire mobile phone screen, static images, or infrequently updated images), most pixel circuits across the entire screen do not need to update their pixel voltages. This means that most pixel circuits can maintain the original display brightness using low-leakage-current LTPO (low-temperature polycrystalline oxide) TFT (thin-film transistor) technology, and repeatedly flashing these pixel circuits results in wasted power consumption. Disclosure of the invention

[0004] In one aspect, an embodiment of the present disclosure provides a control circuit comprising a first control signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit, and a first output circuit; and N is a positive integer; wherein the first control signal generation circuit is electrically connected to a first first control node, a first second control node or a control signal output terminal of the N-th stage and is used to generate a control signal of the N-th stage under the control of a potential of the first first control node and a potential of the first second control node and to output it via the control signal output terminal of the N-th stage; wherein the first output control circuit is electrically connected to a first first node, the first first control node or a first second node and is used to control the connection between the first first control node and the first second node under the control of a potential of the first first node; wherein the first gating circuit is electrically connected to the first node, a gating input terminal or a gating control terminal, and is used to control the writing of a gating input signal provided by the gating input terminal to the first node under the control of a gating control signal provided by the gating control terminal; wherein the first energy storage circuit is electrically connected to the first node or the first second node and is used to control the potential of the first second node according to the potential of the first node; wherein the first second energy storage circuit is electrically connected to a first third control node or an output control terminal of the N-th stage and is used to control the potential of the first third control node according to a control output signal of the N-th stage provided by the output control terminal of the N-th stage; wherein the first output circuit is electrically connected to the first second node, the first third control node, a first voltage terminal, a second voltage terminal or the output control terminal of the Nth stage and is used to control the connection between the output control terminal of the Nth stage and the first voltage terminal under control of the potential of the first second node and to control the connection between the output control terminal of the Nth stage and the second voltage terminal under control of the potential of the first third control node; where the first third control node and the first second control node are different nodes.

[0005] Optionally, the first gating circuit is used to control the writing of a gating input signal provided by the gating input terminal to the first node when the potential of a first node of the N-1 stage is at a second voltage and the potential of the N-1 stage drive signal is at a second voltage.

[0006] Optionally, the first gating circuit includes a first first transistor; wherein a gate of the first first transistor is electrically connected to the gating control terminal, a first electrode of the first first transistor is electrically connected to the first first node, and a second electrode of the first first transistor is electrically connected to the gating input terminal.

[0007] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal; and the first gating circuit includes a first transistor and a first second transistor; wherein a gate of the first first transistor is electrically connected to the first gating control terminal, a first electrode of the first first transistor is electrically connected to the first first node, and a second electrode of the first first transistor is electrically connected to the first electrode of the first second transistor; wherein a gate of the first second transistor is electrically connected to the second gating control terminal, and a second electrode of the first second transistor is electrically connected to the gating input terminal; wherein the first gating control terminal is a drive signal output terminal of the N-th stage, the second gating control terminal is a first third node of the N-1-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a first third node of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a drive signal output terminal of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, the first transistor is an n-type transistor, and the first transistor is a p-type transistor; or wherein the first gating control terminal is a drive signal output terminal of the N-th stage, the second gating control terminal is a drive signal output terminal of the N-1-th stage, the first transistor is a p-type transistor, and the first transistor is an n-type transistor; or wherein the first gating control terminal accepts an inverted signal of the drive signal of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a drive signal output terminal of the N-th stage, the second gating control terminal receives an inverted signal of the drive signal of the N-1-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a drive signal terminal of the N-1th stage, the second gating control terminal accepts an inverted signal of the drive signal of the N-th stage, and the first first transistor and the first second transistor are each an n-type transistor; or wherein the first gating control terminal receives an inverted signal of the drive signal of the N-th stage, the second gating control terminal is a drive signal terminal of the N-1-th stage, and the first first transistor and the first second transistor are each an n-type transistor.

[0008] Optionally, the first energy storage circuit includes a first capacitor and the first energy storage circuit includes a first capacitor; wherein a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node; wherein a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the output control terminal of the Nth stage.

[0009] Optionally, the first output control circuit includes a first third transistor; wherein a gate of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node, and a second electrode of the first third transistor is electrically connected to the first second node.

[0010] Optionally, the control circuit according to at least one embodiment of the present disclosure further comprises a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the first second node or the first voltage terminal and is used to control the connection between the first second node and the first voltage terminal by controlling the potential of the first third control node.

[0011] Optionally, the control circuit according to at least one embodiment of the present disclosure further comprises a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the output control terminal of the N-th stage, the first second node or the first voltage terminal, and is used to control the connection between the first second node and the first voltage terminal by controlling the potential of the first third control node and the control output signal of the N-th stage provided by the output control terminal of the N-th stage.

[0012] Optionally, the first second node control circuit includes a first fourth transistor; wherein a gate of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal.

[0013] Optionally, the first second node control circuit includes a first fourth transistor and a first control transistor; wherein a gate of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; wherein a gate of the first control transistor is electrically connected to the output control terminal of the Nth stage, and a first electrode of the first control transistor is electrically connected to the first second node.

[0014] Optionally, the first output circuit includes a first fifth transistor, a first sixth transistor, and a first third capacitor; wherein a gate of the first fifth transistor is electrically connected to the first second node, a first electrode of the first fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the first fifth transistor is electrically connected to the output drive terminal of the Nth stage; wherein a gate of the first sixth transistor is electrically connected to the first third control node, a first electrode of the first sixth transistor is electrically connected to the output control terminal of the Nth stage, and a second electrode of the first sixth transistor is electrically connected to the second voltage terminal; wherein a first terminal of the first third capacitor is electrically connected to the first second node, and a second terminal of the first third capacitor is electrically connected to the first voltage terminal.

[0015] Optionally, the control circuit according to at least one embodiment of the present disclosure further comprises a first initialization circuit; wherein the first initialization circuit is electrically connected to an initial control terminal, the second voltage terminal or the first first node, and is used to control the connection between the first first node and the second voltage terminal under the control of an initial control signal provided by the initial control terminal.

[0016] Optionally, the control circuit according to at least one embodiment of the present disclosure further comprises a first first node control circuit; wherein the first first node control circuit is electrically connected to a first fourth node, the second voltage terminal or the first first node, and is used to control the connection between the first first node and the second voltage terminal by controlling the potential of the first fourth node.

[0017] Optionally, the first initialization circuit includes a first seventh transistor; wherein a gate of the first seventh transistor is electrically connected to the initial control terminal, a first electrode of the first seventh transistor is electrically connected to the first first node, and a second electrode of the first seventh transistor is electrically connected to the second voltage terminal.

[0018] Optionally, the first node control circuit includes a first eighth transistor; wherein a gate of the first eighth transistor is electrically connected to the first fourth node, a first electrode of the first eighth transistor is electrically connected to the first first node, and a second electrode of the first eighth transistor is electrically connected to the second voltage terminal.

[0019] Optionally, the control circuit according to at least one embodiment of the present disclosure further comprises a first third control node control circuit; wherein the first third control node control circuit is electrically connected to the first first node, a first fifth node, the first second control node, the first third control node and a first sixth node respectively, and is used to control the connection between the first fifth node and the first third control node under the control of the potential of the first first node, and to control the connection between the first second control node and the first sixth node and the connection between the first sixth node and the first third control node under the control of the potential of the first sixth node.

[0020] Optionally, the first third control node control circuit includes a first ninth transistor, a first tenth transistor, and a first eleventh transistor; wherein a gate of the first ninth transistor is electrically connected to the first first node, a first electrode of the first ninth transistor is electrically connected to the first fifth node, and a second electrode of the first ninth transistor is electrically connected to the first third control node; wherein a gate of the first tenth transistor and a second electrode of the first tenth transistor are each electrically connected to the first sixth node, and a first electrode of the first tenth transistor is electrically connected to the first second control node; wherein a gate of the first eleventh transistor and a first electrode of the first eleventh transistor are each electrically connected to the first sixth node, and a second electrode of the first eleventh transistor is electrically connected to the first third control node.

[0021] Optionally, the control circuit according to at least one embodiment of the present disclosure further comprises a first output pull-down circuit; wherein the first output pulldown circuit is electrically connected to the first control node, the control signal output terminal of the Nth stage or the second voltage terminal, and is used to control the connection between the control signal output terminal of the Nth stage and the second voltage terminal by controlling the potential of the first control node.

[0022] Optionally, the first control signal generation circuit includes a first first control output circuit, a first second control output circuit, a first first control node control circuit, and a first second control node control circuit; wherein the first control node control circuit is used to control the potential of the first control node; wherein the first second control node control circuit is used to control the potential of the first second control node; wherein the first first control output circuit is electrically connected to the first first control node, the first voltage terminal or the control signal output terminal of the Nth stage and is used to control the connection between the control signal output terminal of the Nth stage and the first voltage terminal by controlling the potential of the first first control node; wherein the first second control output circuit is electrically connected to the first second control node, the second voltage terminal or the control signal output terminal of the N-th stage and is used to control the connection between the control signal output terminal of the N-th stage and the second voltage terminal by controlling the potential of the first second control node.

[0023] Optionally, the first first control node control circuit includes a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit; wherein the first seventh node control circuit is electrically connected to a first seventh node, the second voltage terminal, a first clock signal terminal, and the first fifth node, respectively, and is used to control the connection between the first seventh node and the second voltage terminal under the control of a first clock signal provided by the first clock signal terminal, and to control the connection between the first seventh node and the first clock signal terminal under the control of the potential of the first fifth node; wherein the first eighth node control circuit is electrically connected to the second voltage terminal, the first seventh node or a first eighth node, and is used to control the connection between the first seventh node and the first eighth node under the control of a second voltage signal provided by the second voltage terminal; wherein the first third node control circuit is electrically connected to the first eighth node, a second clock signal terminal or the first third node and is used to control the electrical connection between the first third node and the second clock signal terminal by controlling the potential of the first eighth node, and to control the potential of the first third node according to the potential of the first eighth node; wherein the first first control circuit is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node or the first voltage terminal and is used to control the connection between the first third node and the first first control node under the control of a second clock signal provided by the second clock signal terminal, and to control the connection between the first first control node and the first voltage terminal under the control of the potential of the first fifth node.

[0024] Optionally, the first second control node control circuit includes a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit; wherein the first sixth node control circuit is electrically connected to the second voltage terminal, a first ninth node, the first sixth node or the first fourth node and is used to control the connection between the first ninth node and the first sixth node under the control of the second voltage signal provided by the second voltage terminal, and to control the potential of the first sixth node according to the potential of the first fourth node; wherein the first fifth node control circuit is electrically connected to the control signal output terminal of the N-1th stage, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, and is used to control the connection between the first fifth node and the control signal output terminal of the N-1th stage under control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first fifth node and the first voltage terminal under control of the initial control signal provided by the initial control terminal; wherein the first ninth node control circuit is electrically connected to the first clock signal terminal, the control signal output terminal of the N-1th stage or the first ninth node, and is used to control the connection between the first ninth node and the control signal output terminal of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal; wherein the first fourth node control circuit is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal, and the first sixth node, respectively, and is used to control the connection between the first fourth node and the first voltage terminal by controlling the potential of the first seventh node, and to control the connection between the first fourth node and the second clock signal terminal by controlling the potential of the first sixth node; wherein the first second control circuit is electrically connected to the second voltage terminal, the first fifth node or the first second control node, and is used to control the connection between the first fifth node and the first second control node under the control of the second voltage signal provided by the second voltage terminal.

[0025] Optionally, the first seventh node control circuit includes a first twelfth transistor and a first thirteenth transistor, the first eighth node control circuit includes a first fourteenth transistor, the first third node control circuit includes a first fifteenth transistor and a first fourth capacitor, and the first first control circuit includes a first sixteenth transistor and a first seventeenth transistor; wherein a gate of the first twelfth transistor is electrically connected to the first clock signal terminal, a first electrode of the first twelfth transistor is electrically connected to the second voltage terminal, and a second electrode of the first twelfth transistor is electrically connected to the first seventh node; wherein a gate of the first thirteenth transistor is electrically connected to the first fifth node, a first electrode of the first thirteenth transistor is electrically connected to the first seventh node, and a second electrode of the first thirteenth transistor is electrically connected to the first clock signal terminal; wherein a gate of the first fourteenth transistor is electrically connected to the second voltage terminal, a first electrode of the first fourteenth transistor is electrically connected to the first seventh node, and a second electrode of the first fourteenth transistor is electrically connected to the first eighth node; wherein a gate of the first fifteenth transistor is electrically connected to the first eighth node, a first electrode of the first fifteenth transistor is electrically connected to the second clock signal terminal, and a second electrode of the first fifteenth transistor is electrically connected to the first third node; wherein a first terminal of the first fourth capacitor is electrically connected to the first eighth node, and a second terminal of the first fourth capacitor is electrically connected to the first third node; wherein a gate of the first sixteenth transistor is electrically connected to the second clock signal terminal, a first electrode of the first sixteenth transistor is electrically connected to the first third node, and a second electrode of the first sixteenth transistor is electrically connected to the first first control node; wherein a gate of the first seventeenth transistor is electrically connected to the first fifth node, a first electrode of the first seventeenth transistor is electrically connected to the first first control node, and a second electrode of the first seventeenth transistor is electrically connected to the first voltage terminal.

[0026] Optionally, the first sixth node control circuit includes a first eighteenth transistor and a first fifth capacitor, the first fifth node control circuit includes a first nineteenth transistor and a first twentieth transistor, the first ninth node control circuit includes a first twenty-first transistor, the first fourth node control circuit includes a first twenty-second transistor and a first twenty-third transistor, and the first second control circuit includes a first twenty-fourth transistor; wherein a gate of the first eighteenth transistor is electrically connected to the second voltage terminal, a first electrode of the first eighteenth transistor is electrically connected to the first ninth node, and a second electrode of the first eighteenth transistor is electrically connected to the first sixth node; wherein a first terminal of the first fifth capacitor is electrically connected to the first fourth node, and a second terminal of the first fifth capacitor is electrically connected to the first sixth node; wherein a gate of the first nineteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the first nineteenth transistor is electrically connected to the drive signal output terminal of the N-1th stage, and a second electrode of the first nineteenth transistor is electrically connected to the first fifth node; wherein a gate of the first twentieth transistor is electrically connected to the initial control terminal, a first electrode of the first twentieth transistor is electrically connected to the first voltage terminal, and a second electrode of the first twentieth transistor is electrically connected to the first fifth node; wherein a gate of the first twenty-first transistor is electrically connected to the first clock signal terminal, a first electrode of the first twenty-first transistor is electrically connected to the drive signal output terminal of the N-1th stage, and a second electrode of the first twenty-first transistor is electrically connected to the first ninth node; wherein a gate of the first twenty-second transistor is electrically connected to the first seventh node, a first electrode of the first twenty-second transistor is electrically connected to the first voltage terminal, and a second electrode of the first twenty-second transistor is electrically connected to the first fourth node; wherein a gate of the first twenty-third transistor is electrically connected to the first sixth node, a first electrode of the first twenty-third transistor is electrically connected to the first fourth node, and a second electrode of the first twenty-third transistor is electrically connected to the second clock signal terminal; wherein a gate of the first twenty-fourth transistor is electrically connected to the second voltage terminal, a first electrode of the first twenty-fourth transistor is electrically connected to the first ninth node, and a second electrode of the first twenty-fourth transistor is electrically connected to the first second control node.

[0027] Optionally, the first first drive output circuit includes a first twenty-fifth transistor and a first sixth capacitor, and the first second drive output circuit includes a first twenty-sixth transistor and a first seventh capacitor; wherein a gate of the first twenty-fifth transistor is electrically connected to the first control node, a first electrode of the first twenty-fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the first twenty-fifth transistor is electrically connected to the drive signal output terminal of the Nth stage; wherein a first terminal of the first sixth capacitor is electrically connected to the first first control node, and a second terminal of the first sixth capacitor is electrically connected to the first voltage terminal; wherein a gate of the first twenty-sixth transistor is electrically connected to the first second control node, a first electrode of the first twenty-sixth transistor is electrically connected to the drive signal output terminal of the Nth stage, and a second electrode of the first twenty-sixth transistor is electrically connected to the second voltage terminal; wherein a first terminal of the first seventh capacitor is electrically connected to the control signal output terminal of the Nth stage, and a second terminal of the first seventh capacitor is electrically connected to the second voltage terminal.

[0028] Optionally, the first output pulldown circuit includes a first twenty-seventh transistor; wherein a gate of the first twenty-seventh transistor is electrically connected to the first control node, a first electrode of the first twenty-seventh transistor is electrically connected to the drive signal output terminal of the Nth stage, and a second electrode of the first twenty-seventh transistor is electrically connected to the second voltage terminal.

[0029] In a second aspect, an embodiment of the present disclosure provides a control method that is applied to a control circuit mentioned above, wherein the control method comprises: Generating and outputting a control signal of an N-th stage via a control signal output terminal of the N-th stage under the control of a potential of a first first control node and a potential of a first second control node by a first control signal generation circuit; Controlling the connection between the first control node and a first second node by controlling a potential of a first first node through the first output control circuit; Controlling the writing of a gating input signal to the first node under the control of a gating control signal by a first gating circuit; Controlling the potential of the first second node according to the potential of the first first node by a first first energy storage circuit; Control of the potential of a first third control node according to a control output signal of the Nth stage provided by an output control terminal of the Nth stage by a first second energy storage circuit; Controlling the connection between the output control terminal of the Nth stage and a first voltage terminal by controlling the potential of the first second node by a first output circuit, and controlling the connection between the output control terminal of the Nth stage and a second voltage terminal by controlling the potential of the first third control node by the first output circuit; where the first third control node and the first second control node are distinct nodes, and N is a positive integer.

[0030] In a third aspect, an embodiment of the present disclosure provides a control module comprising several stages of the above-mentioned control circuits; wherein the N-th stage control circuit and the N-1-th stage control circuit comprise control signal output terminals that are electrically connected to each other, and N is a positive integer.

[0031] In a fourth aspect, an embodiment of the present disclosure provides a display device comprising a control module mentioned above. Brief description of the drawings Fig. 1 is a structural diagram of a control circuit according to an embodiment of the present disclosure; Fig. 2 is a circuit diagram of a relevant pixel circuit; Fig. 3 is an operating time diagram of the in Fig. 2 relevant pixel circuits shown; Fig. 4 is a circuit diagram of a relevant pixel circuit; Fig. 5 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 6 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 7 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 8 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 9 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 10 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 11 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 12 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 13 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 14 is a circuit diagram of at least one embodiment of a first gating circuit in a control circuit according to an embodiment of the present disclosure; Fig. 15 is a circuit diagram of at least one embodiment of a first inverter; Fig. 16 is a circuit diagram of at least one embodiment of a second inverter; Fig. 17A is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 17B is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 18A is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 18B is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 18C is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 18D is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 19A is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 19B is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 19C is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 19D is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 20A is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 20B is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 20C is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 20D is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 21A is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 21B is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 21C is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 21D is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 22A is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 22B is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 22C is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 22D is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 23 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 24A is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 24B is a simulation operating time diagram of at least one embodiment of the in Fig. 24 control circuit shown; Fig. 25 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 26 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 27 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 28 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 29 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 30 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 31 is a structural diagram of a control circuit according to an embodiment of the present disclosure; Fig. 32 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 33 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 34 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 35 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 36 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 37 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 38 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 39 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 40 is an operating time diagram of at least one embodiment of the in Fig. 39 shown control circuit; Fig. 41 is a simulation operating time diagram of at least one embodiment of the in Fig. 39 shown control circuit; Fig. 42 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 43 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 44 is a structural diagram of a control circuit according to an embodiment of the present disclosure; Fig. 45 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 46 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 47 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 48 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 49 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 50 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 51 is a simulation operating time diagram of at least one embodiment of the in Fig. 50 control circuit shown; Fig. 52 is a simulation operating time diagram of at least one embodiment of the in Fig. 50 control circuit shown; Fig. 53 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 54 is a simulation operating time diagram of at least one embodiment of the in Fig. 53 shown control circuit; Fig. 55 is a structural diagram of a control circuit according to an embodiment of the present disclosure; Fig. 56 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 57 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 58 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 59 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 60 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 61 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 62 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 63 is a simulation operating time diagram of at least one embodiment of the in Fig. 62 control circuit shown; Fig. 64 is a simulation operating time diagram of at least one embodiment of the in Fig. 62 control circuit shown; Fig. 65 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 66 is a simulation operating time diagram of at least one embodiment of the in Fig. 65 shown control circuit; Fig. 67 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 68 is an operating time diagram of at least one embodiment of the in Fig. 67 shown control circuit; Fig. 69 is a structural diagram of a control circuit according to an embodiment of the present disclosure; Fig. 70 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 71 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 72 is a structural diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 73 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 74 is a simulation operating time diagram of at least one embodiment of the in Fig. 73 control circuit shown; Fig. 75 is a simulation operating time diagram of at least one embodiment of the in Fig. 73 control circuit shown; Fig. 76 is a circuit diagram of a control circuit according to at least one embodiment of the present disclosure; Fig. 77 is a simulation operating time diagram of at least one embodiment of the in Fig. 76 shown control circuit; Fig. Figure 78 is a structural diagram of a control module according to at least one embodiment of the present disclosure; Fig. 79 is an operating time diagram of at least one embodiment of the in Fig. 78 control module shown; Fig. Figure 80 is a waveform diagram of a first clock signal provided by GCK and a second clock signal provided by GCB. Detailed description of the embodiments

[0032] The technical solutions in the embodiments of this disclosure are clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments represent only some of the embodiments of this disclosure and not all of them. Based on the embodiments in this disclosure, all other embodiments that could be obtained by a person skilled in the art without inventive effort fall within the scope of protection of this disclosure.

[0033] The transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same properties. To distinguish the two electrodes of a transistor, with the exception of a gate, one electrode is referred to as the first electrode and the other as the second electrode in the embodiments of the present disclosure.

[0034] If the transistor is a thin-film transistor or a field-effect transistor, in actual operation the first electrode can be a drain and the second electrode a source; or the first electrode can be a source and the second electrode can be a drain.

[0035] As in Fig. Figure 1 shows that the control circuit according to an embodiment of the present disclosure comprises a first control signal generation circuit 110, a first gating circuit 111, a first output control circuit 112, a first output circuit 113, a first first energy storage circuit 114 and a first second energy storage circuit 115; and N is a positive integer; wherein the first control signal generation circuit 110 is electrically connected to a first control node NC1-1, a first second control node NC1-2 or a control signal output terminal NS (N) of the N-th stage and is used to generate a control signal of the N-th stage under the control of a potential of the first control node NC1-1 and a potential of the first second control node NC1-2 and to output it via the control signal output terminal NS (N) of the N-th stage; wherein the first gating circuit 111 is electrically connected to the first node N1-1, a gating input terminal VCT or a gating control terminal CX, and is used to control the writing of a gating input signal provided by the gating control terminal VCT to the first node N1-1 under the control of a gating control signal provided by the gating control terminal CX; wherein the first output control circuit 112 is electrically connected to a first first node N1-1, the first first control node NC1-1 or a first second node N1-2 and is used to control the connection between the first first control node NC1-1 and the first second node N1-2 under the control of a potential of the first first node N1-1; wherein the first energy storage circuit 114 is electrically connected to the first node N1-1 or the first second node N1-2 and is used to control the potential of the first second node N1-2 according to the potential of the first node N1-1; wherein the first second energy storage circuit 115 is electrically connected to a first third control node NC1-3 or an output control terminal NO (N) of the N-th stage and is used to control the potential of the first third control node NC1-3 according to a control output signal of the N-th stage provided by the output control terminal NO (N) of the N-th stage; wherein the first output circuit 113 is electrically connected to the first second node N1-2, the first third control node NC1-3, a first voltage terminal V1, a second voltage terminal V2 or the output control terminal NO (N) of the N-th stage and is used to control the connection between the output control terminal NO (N) of the N-th stage and the first voltage terminal V1 under control of the potential of the first second node N1-2 and to control the connection between the output control terminal NO (N) of the N-th stage and the second voltage terminal V2 under control of the potential of the first third control node NC1-3; where the first third control node NC1-3 and the first second control node NC1-2 are different nodes.

[0036] If the embodiment of the in Fig. In the control circuit shown in Figure 1 of the present disclosure, the first control signal generation circuit 110, controlled by a potential of the first first control node NC1-1 and a potential of the first second control node NC1-2, generates a control signal of the Nth stage and outputs it via the control signal output terminal NS(N) of the Nth stage; the first gating circuit 111, controlled by a gating control signal provided by the gating control terminal CX, controls the writing of a gating input signal provided by the gating input terminal VCT to the first first node N1-1; the first output control circuit 112, controlled by a potential of the first first node N1-1, controls the connection between the first first control node NC1-1 and the first second node N1-2;The first energy storage circuit 114 controls the potential of the first second node N1-2 according to the potential of the first first node N1-1; the first second energy storage circuit 115 controls the potential of the first third control node NC1-3 according to a control output signal of the Nth stage provided by the output control terminal NO (N) of the Nth stage; the first output circuit 113 controls the connection between the output control terminal NO (N) of the Nth stage and the first voltage terminal V1 under the control of the potential of the first second node N1-2 and controls the connection between the output control terminal NO (N) of the Nth stage and the second voltage terminal V2 under the control of the potential of the first third control node NC1-3.

[0037] Optionally, the first voltage connection can be a high-voltage connection, but it is not limited to this.

[0038] The embodiment of the in Fig. The control circuit shown in the present disclosure can be a control circuit of the Nth stage.

[0039] If the embodiment of the in Fig. When the control circuit shown in the present disclosure is functioning, the following occurs within one frame time:

[0040] Prior to a phase of providing the control signal of the Nth stage, the first gating circuit 111, under the control of the gating control signal, writes the gating input signal provided by the gating input terminal VCT to the first node N1-1; If the gating input signal is a high-voltage signal, during the phase of providing the drive signal to the Nth stage, the drive signal output terminal NS(N) of the Nth stage outputs a high-voltage signal, and the potential of the first node N1-1 is at high voltage. The first output control circuit 112, under the control of the potential of the first node N1-1, controls the separation between the first control node NC1-1 and the first second node N1-2. The first energy storage circuit 114, according to the potential of the first node N1-1, controls the potential of the first second node N1-2 to high voltage. The first output circuit 113 controls the output drive terminal NO(N) to maintain the output of a low-voltage signal, thereby controlling the corresponding line pixel circuit without updating the pixel voltage. If the gating input signal is a low-voltage signal, during the phase of providing the drive signal to the Nth stage, the drive signal output terminal NS(N) of the Nth stage outputs a high-voltage signal, and the potential of the first node N1-1 is at low voltage. The first output control circuit 112, under control of the potential of the first node N1-1, controls the connection between the first control node NC1-1 and the first second node N1-2, so that the potential of the first second node N1-2 is at low voltage. The first output circuit 113, under control of the potential of the first second node N1-2, controls the connection between the output drive terminal NO(N) and the first voltage terminal V1, so that NO(N) outputs a high-voltage signal, thereby controlling the corresponding line pixel circuit to update the pixel voltage.

[0041] If the embodiment of the in Fig. If the control circuit shown in Figure 1 of the present disclosure functions and the potential of the control output signal of the N-th stage provided by NO(N) is reduced from high voltage to low voltage, the potential of the first third control node NC1-3 can be lowered so that the transistor contained in the first output circuit 113, whose gate is electrically connected to the first third control node NC1-3, can be switched on more effectively to keep the potential of the control output signal of the N-th stage at low voltage.

[0042] Embodiments of the present disclosure can, by controlling the gating input signal provided by the gating input port VCT, achieve the updating of a local image on the display screen, thereby reducing power consumption, or can achieve ultra-low power consumption in OLED display products such as portable products, mobile devices, notebooks, or the like by locally updating the display image.

[0043] As in Fig. As shown in Figure 2, the relevant pixel circuit can include a first display control transistor M1, a second display control transistor M2, a drive transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst and an organic light-emitting diode O1; wherein the gate of M1 is electrically connected to a first reset terminal NR (N), the source of M1 is electrically connected to an initial voltage terminal I1 and the drain of M1 is electrically connected to the gate of M3; wherein the gate of M2 is electrically connected to a first sampling terminal NG (N), the source of M2 is electrically connected to the gate of M3 and the drain of M2 is electrically connected to the drain of M3; wherein the gate of M4 is electrically connected to a second sampling port PG (N), the source of M4 is electrically connected to a data line D1 and the drain of M4 is electrically connected to the source of M3; wherein the gate of M5 is electrically connected to a light emission control terminal E (N), the source of M5 is electrically connected to a power supply voltage terminal ELVDD and the drain of M5 is electrically connected to the source of M3; wherein the gate of M6 is electrically connected to the light emission control terminal E (N), the source of M6 is electrically connected to the drain of M3, and the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to a low-level terminal ELVSS; wherein the gate of M7 is electrically connected to the second sampling terminal PG (N), the source of M7 is electrically connected to the initial voltage terminal I1 and the drain of M7 is electrically connected to the anode of O1.

[0044] In a specific implementation, the first reset terminal NR(N) can be a first sample terminal NG(N) of the N-1th stage, but is not limited to this.

[0045] In the Fig. In the 2 relevant pixel circuits shown, M1 and M2 are n-type transistors, M3, M4, M5, M6 and M7 are p-type transistors, M1 and M2 are low leakage current IGZO-TFTs, and M3, M4, M5, M6 and M7 are LTPS-TFTs.

[0046] In the Fig. The two relevant pixel circuits shown are M1 and M2 IGZO-TFTs. When using a low-frequency display, IGZO-TFTs can ensure that Cst can maintain the gate voltage of M3 over a long period of time.

[0047] In the Fig. In the relevant pixel circuit shown in Figure 2, the second sampling terminal PG (N) is responsible for resetting the anode voltage of O1 and writing the data voltage on the data line to the source of the drive transistor, and the first sampling terminal NG (N) is responsible for resetting Cst, extracting Vth (Vth is the threshold voltage of the drive transistor) and writing the data voltage to the gate of the drive transistor.

[0048] In a specific implementation, the first sampling signal provided by the first sampling port NG(N) and the second sampling signal provided by the second sampling port PG(N) can be inverted relative to each other, but are not limited to doing so.

[0049] The control circuit described in at least one embodiment of the present disclosure can provide the first sampling signal for the first sampling port NG (N) via the output control port NO (N), but is not limited to this.

[0050] As in Fig. As shown in section 3, the display cycle can change during operation of the in Fig. The relevant pixel circuit shown in section 2 comprises a first display control phase t1, a second display control phase t2 and a third display control phase t3, which are set one after the other; In the first display control phase t1, E (N) outputs a high-voltage signal, NR (N) provides a high-voltage signal, PG (N) provides a high-voltage signal, NG (N) provides a low-voltage signal, M5 and M6 are switched to blocking, M1 is switched on, and the gate potential of M3 is lowered to the initial voltage Vinit; the initial voltage terminal I1 is used to provide the initial voltage Vinit; In the second display control phase t2, E(N) outputs a high-voltage signal, NR(N) provides a low-voltage signal, PG(N) provides a low-voltage signal, NG(N) provides a high-voltage signal, M5 and M6 are switched off, M1 is switched off, M2 is switched on, M4 is switched on, M2 and M3 form a diode structure, and the data voltage Vdata provided via data line D1 charges Cst until M3 is switched off, at which point the gate voltage of M3 is Vdata+Vth, and Vth is the threshold voltage of M3; M7 is switched on to reset the anode voltage of O1; In the third display control phase t3, E (N) outputs a low-voltage signal, NR (N) provides a low-voltage signal, PG (N) provides a high-voltage signal, NG (N) provides a low-voltage signal, M5 and M6 are switched on, and M3 controls O1 to emit light; O1 emits light according to the voltage setting of Vdata.

[0051] From the above-mentioned operating process of the relevant pixel circuit, it can be seen that NG (N) can control whether the data voltage Vdata (the data voltage Vdata can be the pixel voltage) is written to the gate of M3 in the second display control phase.

[0052] Fig. Figure 4 is a circuit diagram of a relevant pixel circuit.

[0053] As in Fig. As shown in Figure 4, the relevant pixel circuit can include a first display control transistor M1, a second display control transistor M2, a drive transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst and an organic light-emitting diode O1; wherein the gate of M1 is electrically connected to a third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3; wherein the gate of M2 is electrically connected to the first sampling terminal NG (N), the source of M2 is electrically connected to the gate of M3 and the drain of M2 is electrically connected to the drain of M3; wherein the gate of M4 is electrically connected to the second sampling port PG (N), the source of M4 is electrically connected to the data line D1 and the drain of M4 is electrically connected to the source of M3; wherein the gate of M5 is electrically connected to the light emission control terminal E (N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD and the drain of M5 is electrically connected to the source of M3; wherein the gate of M6 is electrically connected to the light emission control terminal E (N), the source of M6 is electrically connected to the drain of M3, and the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low-level terminal ELVSS; wherein the gate of M7 is electrically connected to the fourth reset terminal RST2, the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.

[0054] If the in Fig. 4. In the relevant pixel circuit shown, NG (N) can control whether the data voltage Vdata on the data line D1 is written to the gate of the control transistor M3.

[0055] In a specific implementation, the first sampling signal provided by NG(N) can be used to control the turning on or off of the first second transistor, in order to control whether the data voltage on the data line is written to the gate of the drive transistor, thereby controlling whether the brightness of the pixel circuit of that line is updated; if NG(N) outputs a high-voltage signal, the first second transistor is turned on, thus allowing the brightness of the pixel circuit of that line to be updated;When NG(N) outputs a low-voltage signal, the first second transistor is always off, changes in the data voltage on the data line are not written to the gate of the drive transistor, and the brightness of the organic light-emitting diode does not change; that is, the display brightness of the pixel circuit of the current row in the current frame remains unchanged. In summary, it is evident that the pixel brightness can be updated by controlling the on or off of the N-type transistor. To prevent some pixels from being updated, it is sufficient to ensure that the N-type transistor is switched off.

[0056] In at least one embodiment of the present disclosure, the first gating circuit is used to control the writing of the gating input signal provided by the gating input terminal to the first node when the potential of the first node of the N-th stage is a second voltage and the potential of the drive signal of the N-th stage is a second voltage.

[0057] Optionally, the second voltage can be a low voltage, but is not limited to this.

[0058] Optionally, the first gating circuit includes a first first transistor; wherein the gate of the first first transistor is electrically connected to the gating control terminal, the first electrode of the first first transistor is electrically connected to the first first node, and the second electrode of the first first transistor is electrically connected to the gating input terminal.

[0059] As in Fig. As shown in Figure 5, the first gating circuit can include a first transistor T1-1; wherein the gate of the first transistor T1-1 is electrically connected to the gating control terminal S0, the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the gating input terminal VCT; where T1-1 is a p-type transistor.

[0060] As in Fig. As shown in Figure 6, the first gating circuit can include a first transistor T1-1; wherein the gate of the first transistor T1-1 is electrically connected to the gating control terminal S0, the source of the first transistor T1-1 is electrically connected to the first node N1-1, and the drain of the first transistor T1-1 is electrically connected to the gating input terminal VCT; where T1-1 is an n-type transistor.

[0061] Optionally, the gating control terminal includes a first gating control terminal and a second gating control terminal; the first gating circuit includes a first transistor and a first second transistor; wherein the gate of the first first transistor is electrically connected to the first gating control terminal, the first electrode of the first first transistor is electrically connected to the first first node, and the second electrode of the first first transistor is electrically connected to the first electrode of the first second transistor; wherein the gate of the first second transistor is electrically connected to the second gating control terminal, and the second electrode of the first second transistor is electrically connected to the gating input terminal; wherein the first gating control terminal is a drive signal output terminal of the N-th stage, the second gating control terminal is a first third node of the N-1-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a first third node of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a drive signal output terminal of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, the first transistor is an n-type transistor, and the first transistor is a p-type transistor; or wherein the first gating control terminal is a drive signal output terminal of the N-th stage, the second gating control terminal is a drive signal output terminal of the N-1-th stage, the first transistor is a p-type transistor and the first transistor is an n-type transistor; or wherein the first gating control terminal receives the inverted signal of the drive signal of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a drive signal output terminal of the N-th stage, and the second gating control terminal receives the inverted signal of the drive signal of the N-1-th stage; the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a drive signal terminal of the N-1th stage, the second gating control terminal receives the inverted signal of the drive signal of the N-th stage, and the first first transistor and the first second transistor are each an n-type transistor; or wherein the first gating control terminal receives the inverted signal of the drive signal of the N-th stage, the second gating control terminal is a drive signal terminal of the N-1-th stage, and the first first transistor and the first second transistor are each an n-type transistor.

[0062] As in Fig. As shown in Figure 7, the first gating circuit can include a first transistor T1-1 and a first transistor T1-2; wherein the gate of the first transistor T1-1 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, the source of the first transistor T1-1 is electrically connected to the first node N1-1, and the drain of the first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2; wherein the gate of the first second transistor T1-2 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; where T1-1 is an n-type transistor and T1-2 is a p-type transistor.

[0063] As in Fig. As shown in Figure 8, the first gating circuit can include a first transistor T1-1 and a first transistor T1-2; wherein the gate of the first transistor T1-1 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the source of the first transistor T1-2; wherein the gate of the first second transistor T1-2 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; where T1-1 is a p-type transistor and T1-2 is an n-type transistor.

[0064] As in Fig. As shown in Figure 9, the first gating circuit can include a first transistor T1-1 and a first transistor T1-2; wherein the gate of the first first transistor T1-1 is electrically connected to the first third node N1-3 (N-1) of the N-1th stage, the drain of the first first transistor T1-1 is electrically connected to the first first node N1-1, and the source of the first first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2; wherein the gate of the first second transistor T1-2 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; where T1-1 is a p-type transistor and T1-2 is a p-type transistor.

[0065] In at least one embodiment of the present disclosure, the first third node N1-3 (N-1) of the N-1th stage can be a first third node in the control circuit of the N-1th stage.

[0066] As in Fig. As shown in Figure 10, the first gating circuit can include a first transistor T1-1 and a first transistor T1-2; wherein the gate of the first transistor T1-1 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first transistor T1-2; wherein the gate of the first second transistor T1-2 is electrically connected to the first third node N1-3 (N-1) of the N-1th stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; where T1-1 is a p-type transistor and T1-2 is a p-type transistor.

[0067] As in Fig. As shown in Figure 11, the first gating circuit can include a first transistor T1-1 and a first transistor T1-2; wherein the gate of the first transistor T1-1 is electrically connected to a first inverted drive signal terminal NGI1, the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first second transistor T1-2; wherein the first inverted drive signal provided by the first inverted drive signal terminal NGI1 is inverted to the drive signal of the N-1th stage provided by the drive signal output terminal NS (N-1) of the N-1th stage; wherein the gate of the first second transistor T1-2 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; where T1-1 is a p-type transistor and T1-2 is a p-type transistor.

[0068] As in Fig. As shown in Figure 12, the first gating circuit can include a first transistor T1-1 and a first transistor T1-2; wherein the gate of the first transistor T1-1 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first transistor T1-2; wherein the gate of the first second transistor T1-2 is electrically connected to the first inverted drive signal terminal NGI1, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; wherein the first inverted drive signal provided by the first inverted drive signal terminal NGI1 is inverted to the drive signal of the N-1th stage provided by the drive signal output terminal NS (N-1) of the N-1th stage; where T1-1 is a p-type transistor and T1-2 is a p-type transistor.

[0069] As in Fig. As shown in Figure 13, the first gating circuit can include a first transistor T1-1 and a first transistor T1-2; wherein the gate of the first transistor T1-1 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, the source of the first transistor T1-1 is electrically connected to the first node N1-1, and the drain of the first transistor T1-1 is electrically connected to the source of the first second transistor T1-2; wherein the gate of the first second transistor T1-2 is electrically connected to the second inverted drive signal terminal NGI2, and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; wherein the second inverted drive signal provided by the second inverted drive signal terminal NGI2 is inverted to the drive signal of the N-th stage provided by the drive signal output terminal NS (N) of the N-th stage; where T1-1 is an n-type transistor and T1-2 is an n-type transistor.

[0070] As in Fig. As shown in Figure 14, the first gating circuit can include a first transistor T1-1 and a first transistor T1-2; wherein the gate of the first transistor T1-1 is electrically connected to the second inverted drive signal terminal NGI2, the source of the first transistor T1-1 is electrically connected to the first node N1-1, and the drain of the first transistor T1-1 is electrically connected to the source of the first transistor T1-2; wherein the second inverted drive signal provided by the second inverted drive signal terminal NGI2 is inverted to the drive signal of the N-th stage provided by the drive signal output terminal NS(N) of the N-th stage; wherein the gate of the first second transistor T1-2 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, and the drain of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; where T1-1 is an n-type transistor and T1-2 is an n-type transistor.

[0071] As in Fig. As shown in Figure 15, the control signal of the N-1 stage provided by the control signal output terminal NS (N-1) of the N-1 stage can be inverted by the first inverter to obtain the first inverted control signal provided by the first inverted control signal terminal NGI1; wherein the first inverter comprises a first inversion control transistor T01 and a second inversion control transistor T02; where T01 is a p-type transistor and T02 is an n-type transistor.

[0072] As in Fig. As shown in Figure 16, the control signal of the Nth stage provided by the control signal output terminal NS (N) of the Nth stage can be inverted by the second inverter to obtain the second inverted control signal provided by the second inverted control signal terminal NGI2; wherein the second inverter comprises a third inversion control transistor T03 and a fourth inversion control transistor T04; where T03 is a p-type transistor and T04 is an n-type transistor.

[0073] In at least one embodiment of the present disclosure, the first energy storage circuit comprises a first first capacitor, and the first second energy storage circuit comprises a first second capacitor; wherein the first terminal of the first first capacitor is electrically connected to the first first node, and the second terminal of the first first capacitor is electrically connected to the first second node; wherein the first terminal of the first second capacitor is electrically connected to the first third control node, and the second terminal of the first second capacitor is electrically connected to the output control terminal of the Nth stage.

[0074] Optionally, the first output control circuit includes a first third transistor; wherein the gate of the first third transistor is electrically connected to the first first node, the first electrode of the first third transistor is electrically connected to the first first control node, and the second electrode of the first third transistor is electrically connected to the first second node.

[0075] The control circuit according to at least one embodiment of the present disclosure may further comprise a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the first second node or the first voltage terminal and is used to control the connection between the first second node and the first voltage terminal by controlling the potential of the first third control node.

[0076] In a specific implementation, the control circuit may further include a first second node control circuit; wherein the first second node control circuit, under the control of the potential of the first third control node, controls the connection between the first second node and the first voltage terminal.

[0077] As in Fig. Shown in 17A, the control circuit is based on the embodiment of the one shown in Fig. 1 shown control circuit further a first second node control circuit 120; wherein the first second node control circuit 120 is electrically connected to the first third control node NC1-3, the first second node N1-2 or the first voltage terminal V1 and is used to control the connection between the first second node N1-2 and the first voltage terminal V1 under the control of the potential of the first third control node NC1-3.

[0078] If at least one embodiment of the in Fig. If the control circuit shown in 17A works and the potential of the first third control node NC1-3 is an effective voltage, the potential of the first second node N1-2 can be a first voltage.

[0079] Optionally, the first second node control circuit includes a first fourth transistor; wherein the gate of the first fourth transistor is electrically connected to the first third control node, the first electrode of the first fourth transistor is electrically connected to the first second node, and the second electrode of the first fourth transistor is electrically connected to the first voltage terminal.

[0080] The control circuit according to at least one embodiment of the present disclosure may further comprise a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the output control terminal of the N-th stage, the first second node or the first voltage terminal, and is used to control the connection between the first second node and the first voltage terminal by controlling the potential of the first third control node and the control output signal of the N-th stage provided by the output control terminal of the N-th stage.

[0081] In a specific implementation, the control circuit may further include a first second node control circuit; wherein the first second node control circuit, under the control of the potential of the first third control node and the control output signal of the N-th stage provided by the output control terminal of the N-th stage, controls the connection between the first second node and the first voltage terminal.

[0082] As in Fig. As shown in Figure 17B, the control circuit is based on the embodiment of the one shown in Fig. 1 shown control circuit further a first second node control circuit 120; wherein the first second node control circuit 120 is electrically connected to the first third control node NC1-3, the output control terminal NO (N) of the N-th stage, the first second node N1-2 or the first voltage terminal V1 and is used to control the connection between the first second node N1-2 and the first voltage terminal V1 by controlling the potential of the first third control node NC1-3 and the control output signal of the N-th stage provided by the output control terminal NO (N) of the N-th stage.

[0083] If at least one embodiment of the in Fig. If the control circuit shown in 17B works and the potential of the first third control node NC1-3 is at an effective voltage and the potential of the control output signal of the Nth stage is at an effective voltage, then the potential of the first second node N1-2 can be a first voltage.

[0084] Optionally, the first second node control circuit includes a first fourth transistor and a first control transistor; wherein the gate of the first fourth transistor is electrically connected to the first third control node, the first electrode of the first fourth transistor is electrically connected to the second electrode of the first control transistor, and the second electrode of the first fourth transistor is electrically connected to the first voltage terminal; wherein the gate of the first control transistor is electrically connected to the output control terminal of the Nth stage, and the first electrode of the first control transistor is electrically connected to the first second node.

[0085] Optionally, the first output circuit includes a first fifth transistor, a first sixth transistor, and a first third capacitor; wherein the gate of the first fifth transistor is electrically connected to the first second node, the first electrode of the first fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the first fifth transistor is electrically connected to the output drive terminal of the Nth stage; wherein the gate of the first sixth transistor is electrically connected to the first third control node, the first electrode of the first sixth transistor is electrically connected to the output control terminal of the Nth stage, and the second electrode of the first sixth transistor is electrically connected to the second voltage terminal; wherein the first terminal of the first third capacitor is electrically connected to the first second node, and the second terminal of the first third capacitor is electrically connected to the first voltage terminal.

[0086] The control circuit according to at least one embodiment of the present disclosure further comprises a first initialization circuit; wherein the first initialization circuit is electrically connected to an initial control terminal, the second voltage terminal or the first first node, and is used to control the connection between the first first node and the second voltage terminal under the control of an initial control signal provided by the initial control terminal.

[0087] In a specific implementation, the control circuit may further include a first initialization circuit. When the display device is switched on, the first initialization circuit controls the connection between the first first node and the second voltage terminal, under the control of the initial control signal, to set the potential of the first first node to a second voltage. The first output control circuit controls the connection between the first first control node and the first second node, under the control of the potential of the first first node.

[0088] The control circuit according to at least one embodiment of the present disclosure further comprises a first first node control circuit; wherein the first first node control circuit is electrically connected to a first fourth node, the second voltage terminal or the first first node, and is used to control the connection between the first first node and the second voltage terminal by controlling the potential of the first fourth node.

[0089] In a specific implementation, the drive circuit can further include a first first node control circuit, wherein the first first node control circuit, by controlling the potential of the first fourth node, controls the connection between the first first node and the second voltage terminal; after the N-th stage drive signal is provided, the first first node control circuit controls the connection between the first first node and the second voltage terminal when the potential of the first fourth node is an effective voltage, such that the potential of the first first node is a second voltage. The first output control circuit controls the connection between the first first control node and the first second node, by controlling the potential of the first first node.

[0090] In at least one embodiment of the present disclosure, the effective voltage can be a low voltage if the transistor included in the first first node control circuit is a p-type transistor, and the effective voltage can be a high voltage if the transistor included in the first first node control circuit is an n-type transistor.

[0091] As in Fig. As shown in 18A, the control circuit can be based on at least one embodiment of the one shown in Fig. The control circuit shown in 17A further comprises a first node control circuit 122; wherein the first first node control circuit 122 is electrically connected to the first fourth node N1-4, the first first node N1-1 or the second voltage terminal V2 and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 by controlling the potential of the first fourth node N1-4.

[0092] As in Fig. As shown in 18B, the control circuit can be based on at least one embodiment of the one shown in Fig. The control circuit shown in 17B further comprises a first node control circuit 122; wherein the first first node control circuit 122 is electrically connected to the first fourth node N1-4, the first first node N1-1 or the second voltage terminal V2 and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 by controlling the potential of the first fourth node N1-4.

[0093] As in Fig. As shown in 18C, the control circuit can be based on at least one embodiment of the one shown in Fig. The control circuit shown in 17A further comprises a first initialization circuit 121 and a first node control circuit 122; wherein the first initialization circuit 121 is electrically connected to the initial control terminal NCX, the first first node N1-1 or the second voltage terminal V2 and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 under the control of the initial control signal provided by the initial control terminal NCX; wherein the first first node control circuit 122 is electrically connected to the first fourth node N1-4, the first first node N1-1 or the second voltage terminal V2 and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 by controlling the potential of the first fourth node N1-4.

[0094] As in Fig. As shown in 18D, the control circuit can be based on at least one embodiment of the one shown in Fig. The control circuit shown in 17B further comprises a first initialization circuit 121 and a first node control circuit 122; wherein the first initialization circuit 121 is electrically connected to the initial control terminal NCX, the first first node N1-1 or the second voltage terminal V2 and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 under the control of the initial control signal provided by the initial control terminal NCX; wherein the first first node control circuit 122 is electrically connected to the first fourth node N1-4, the first first node N1-1 or the second voltage terminal V2 and is used to control the connection between the first first node N1-1 and the second voltage terminal V2 by controlling the potential of the first fourth node N1-4.

[0095] Optionally, the first initialization circuit includes a first seventh transistor; wherein the gate of the first seventh transistor is electrically connected to the initial control terminal, the first electrode of the first seventh transistor is electrically connected to the first first node, and the second electrode of the first seventh transistor is electrically connected to the second voltage terminal.

[0096] Optionally, the first node control circuit includes a first eighth transistor; wherein the gate of the first eighth transistor is electrically connected to the first fourth node, the first electrode of the first eighth transistor is electrically connected to the first first node, and the second electrode of the first eighth transistor is electrically connected to the second voltage terminal.

[0097] The control circuit according to at least one embodiment of the present disclosure further comprises a first third control node control circuit; wherein the first third control node control circuit is electrically connected to the first first node, a first fifth node, the first second control node, the first third control node and a first sixth node respectively, and is used to control the connection between the first fifth node and the first third control node under the control of the potential of the first first node, and to control the connection between the first second control node and the first sixth node and the connection between the first sixth node and the first third control node under the control of the potential of the first sixth node.

[0098] In a specific implementation, the control circuit can include a first third control node control circuit, wherein the first third control node control circuit controls the potential of the first third control node under the control of the potential of the first first node and the potential of the first sixth node.

[0099] As in Fig. As shown in 19A, the control circuit comprises at least one embodiment of the one shown in Fig. 18A shown control circuit further includes a first third control node control circuit 130; wherein the first third control node control circuit 130 is electrically connected to the first first node N1-1, a first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3 or a first sixth node N1-6 and is used to control the connection between the first fifth node N1-5 and the first third control node NC1-3 under the control of the potential of the first first node N1-1, and to control the connection between the first second control node NC1-2 and the first sixth node N1-6 as well as the connection between the first sixth node N1-6 and the first third control node NC1-3 under the control of the potential of the first sixth node N1-6

[0100] As in Fig. As shown in 19B, the control circuit, based on at least one embodiment of the one shown in Fig. The control circuit shown in 18B further includes a first third control node control circuit 130; wherein the first third control node control circuit 130 is electrically connected to the first first node N1-1, a first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3 or a first sixth node N1-6 and is used to control the connection between the first fifth node N1-5 and the first third control node NC1-3 under the control of the potential of the first first node N1-1, and to control the connection between the first second control node NC1-2 and the first sixth node N1-6 as well as the connection between the first sixth node N1-6 and the first third control node NC1-3 under the control of the potential of the first sixth node N1-6

[0101] As in Fig. As shown in Figure 19C, the control circuit, based on at least one embodiment of the one shown in Figure 19C, comprises the control circuit based on at least one embodiment of the one shown in Fig. 18C shown control circuit further includes a first third control node control circuit 130; wherein the first third control node control circuit 130 is electrically connected to the first first node N1-1, a first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3 or a first sixth node N1-6 and is used to control the connection between the first fifth node N1-5 and the first third control node NC1-3 under the control of the potential of the first first node N1-1, and to control the connection between the first second control node NC1-2 and the first sixth node N1-6 as well as the connection between the first sixth node N1-6 and the first third control node NC1-3 under the control of the potential of the first sixth node N1-6

[0102] As in Fig. As shown in 19D, the control circuit based on at least one embodiment of the in Fig. The control circuit shown in 18D further includes a first third control node control circuit 130; wherein the first third control node control circuit 130 is electrically connected to the first first node N1-1, a first fifth node N1-5, the first second control node NC1-2, the first third control node NC1-3 or a first sixth node N1-6 and is used to control the connection between the first fifth node N1-5 and the first third control node NC1-3 under the control of the potential of the first first node N1-1, and to control the connection between the first second control node NC1-2 and the first sixth node N1-6 as well as the connection between the first sixth node N1-6 and the first third control node NC1-3 under the control of the potential of the first sixth node N1-6

[0103] Optionally, the first third control node control circuit includes a first ninth transistor, a first tenth transistor, and a first eleventh transistor; wherein the gate of the first ninth transistor is electrically connected to the first first node, the first electrode of the first ninth transistor is electrically connected to the first fifth node, and the second electrode of the first ninth transistor is electrically connected to the first third control node; wherein the gate of the first tenth transistor and the second electrode of the first tenth transistor are each electrically connected to the first sixth node, and the first electrode of the first tenth transistor is electrically connected to the first second control node; wherein the gate of the first eleventh transistor and the first electrode of the first eleventh transistor are each electrically connected to the first sixth node, and the second electrode of the first eleventh transistor is electrically connected to the first third control node.

[0104] In at least one embodiment of the present disclosure, the first control signal generation circuit comprises a first first control output circuit, a first second control output circuit, a first first control node control circuit and a first second control node control circuit; wherein the first control node control circuit is used to control the potential of the first control node; wherein the first second control node control circuit is used to control the potential of the second control node; wherein the first first control output circuit is electrically connected to the first first control node, the first voltage terminal or the control signal output terminal of the Nth stage and is used to control the connection between the control signal output terminal of the Nth stage and the first voltage terminal by controlling the potential of the first first control node; wherein the first second control output circuit is electrically connected to the first second control node, the second voltage terminal or the control signal output terminal of the N-th stage and is used to control the connection between the control signal output terminal of the N-th stage and the second voltage terminal by controlling the potential of the first second control node.

[0105] As in Fig. 20A shows the control circuit based on at least one embodiment of the one shown. Fig. The control circuit shown in 19A further comprises a first first control node control circuit 131, a first second control node control circuit 132, a first first control output circuit 133 and a first second control output circuit 134; wherein the first control node control circuit 131 is electrically connected to the first control node NC1-1 and is used to control the potential of the first control node NC1-1; wherein the first second control node control circuit 132 is electrically connected to the first second control node NC1-2 and is used to control the potential of the first second control node NC1-2; wherein the first first control output circuit 133 is electrically connected to the first first control node NC1-1, the first voltage terminal V1 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the first voltage terminal V1 under control of the potential of the first first control node NC1-1; wherein the first second control output circuit 134 is electrically connected to the first second control node NC1-2, the control signal output terminal NS (N) of the N-th stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the second voltage terminal V2 by controlling the potential of the first second control node NC1-2

[0106] As in Fig. As shown in 20B, the control circuit comprises at least one embodiment of the one shown in Fig. The control circuit shown in 19B further comprises a first first control node control circuit 131, a first second control node control circuit 132, a first first control output circuit 133 and a first second control output circuit 134; wherein the first control node control circuit 131 is electrically connected to the first control node NC1-1 and is used to control the potential of the first control node NC1-1; wherein the first second control node control circuit 132 is electrically connected to the first second control node NC1-2 and is used to control the potential of the first second control node NC1-2; wherein the first first control output circuit 133 is electrically connected to the first first control node NC1-1, the first voltage terminal V1 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the first voltage terminal V1 under control of the potential of the first first control node NC1-1; wherein the first second control output circuit 134 is electrically connected to the first second control node NC1-2, the control signal output terminal NS (N) of the N-th stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the second voltage terminal V2 by controlling the potential of the first second control node NC1-2

[0107] As in Fig. As shown in 20C, the control circuit comprises at least one embodiment of the one shown in Fig. The control circuit shown in 19C further comprises a first first control node control circuit 131, a first second control node control circuit 132, a first first control output circuit 133 and a first second control output circuit 134; wherein the first control node control circuit 131 is electrically connected to the first control node NC1-1 and is used to control the potential of the first control node NC1-1; wherein the first second control node control circuit 132 is electrically connected to the first second control node NC1-2 and is used to control the potential of the first second control node NC1-2; wherein the first first control output circuit 133 is electrically connected to the first first control node NC1-1, the first voltage terminal V1 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the first voltage terminal V1 under control of the potential of the first first control node NC1-1; wherein the first second control output circuit 134 is electrically connected to the first second control node NC1-2, the control signal output terminal NS (N) of the N-th stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the second voltage terminal V2 by controlling the potential of the first second control node NC1-2

[0108] As in Fig. As shown in 20D, the control circuit is based on at least one embodiment of the one shown in Fig. The control circuit shown in 19D further comprises a first first control node control circuit 131, a first second control node control circuit 132, a first first control output circuit 133 and a first second control output circuit 134; wherein the first control node control circuit 131 is electrically connected to the first control node NC1-1 and is used to control the potential of the first control node NC1-1; wherein the first second control node control circuit 132 is electrically connected to the first second control node NC1-2 and is used to control the potential of the first second control node NC1-2; wherein the first first control output circuit 133 is electrically connected to the first first control node NC1-1, the first voltage terminal V1 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the first voltage terminal V1 under control of the potential of the first first control node NC1-1; wherein the first second control output circuit 134 is electrically connected to the first second control node NC1-2, the control signal output terminal NS (N) of the N-th stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the second voltage terminal V2 by controlling the potential of the first second control node NC1-2

[0109] In at least one embodiment of the present disclosure, the first first control node control circuit comprises a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit and a first first control circuit; wherein the first seventh node control circuit is electrically connected to a first seventh node, the second voltage terminal, a first clock signal terminal, and the first fifth node, respectively, and is used to control the connection between the first seventh node and the second voltage terminal under the control of a first clock signal provided by the first clock signal terminal, and to control the connection between the first seventh node and the first clock signal terminal under the control of the potential of the first fifth node; wherein the first eighth node control circuit is electrically connected to the second voltage terminal, the first seventh node or a first eighth node, and is used to control the connection between the first seventh node and the first eighth node under the control of a second voltage signal provided by the second voltage terminal; wherein the first third node control circuit is electrically connected to the first eighth node, a second clock signal terminal or the first third node and is used to control the electrical connection between the first third node and the second clock signal terminal by controlling the potential of the first eighth node, and to control the potential of the first third node according to the potential of the first eighth node; wherein the first first control circuit is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node or the first voltage terminal and is used to control the connection between the first third node and the first first control node under the control of a second clock signal provided by the second clock signal terminal, and to control the connection between the first first control node and the first voltage terminal under the control of the potential of the first fifth node.

[0110] In a specific implementation, the first first control node control circuit may comprise a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit, and a first first control circuit; wherein the first seventh node control circuit, under the control of the first clock signal and the potential of the first fifth node, controls the potential of the first seventh node; wherein the first eighth node control circuit, under the control of the second voltage signal, controls the connection between the first seventh node and the first eighth node; wherein the first third node control circuit, under the control of the potential of the first eighth node, controls the electrical connection between the first third node and the second clock signal terminal, and, according to the potential of the first eighth node, controls the potential of the first third node;wherein the first control circuit, under the control of the second clock signal, controls the connection between the first third node and the first control node, and, under the control of the potential of the first fifth node, controls the connection between the first control node and the first voltage terminal.

[0111] In at least one embodiment of the present disclosure, the first second control node control circuit comprises a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit and a first second control circuit; wherein the first sixth node control circuit is electrically connected to the second voltage terminal, a first ninth node, the first sixth node or the first fourth node and is used to control the connection between the first ninth node and the first sixth node under the control of the second voltage signal provided by the second voltage terminal, and to control the potential of the first sixth node according to the potential of the first fourth node; wherein the first fifth node control circuit is electrically connected to the control signal output terminal of the N-1th stage, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, and is used to control the connection between the first fifth node and the control signal output terminal of the N-1th stage under control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first fifth node and the first voltage terminal under control of the initial control signal provided by the initial control terminal; wherein the first ninth node control circuit is electrically connected to the first clock signal terminal, the control signal output terminal of the N-1th stage or the first ninth node, and is used to control the connection between the first ninth node and the control signal output terminal of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal; wherein the first fourth node control circuit is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal, and the first sixth node, respectively, and is used to control the connection between the first fourth node and the first voltage terminal by controlling the potential of the first seventh node, and to control the connection between the first fourth node and the second clock signal terminal by controlling the potential of the first sixth node; wherein the first second control circuit is electrically connected to the second voltage terminal, the first fifth node or the first second control node, and is used to control the connection between the first fifth node and the first second control node under the control of the second voltage signal provided by the second voltage terminal.

[0112] In a specific implementation, the first second control node control circuit can comprise a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit, and a first second control circuit; wherein the first fourth node control circuit, under the control of the potential of the first seventh node and the potential of the first sixth node, controls the potential of the first fourth node; wherein the first sixth node control circuit, under the control of the second voltage signal, controls the connection between the first ninth node and the first sixth node and, according to the potential of the first fourth node, controls the potential of the first sixth node;wherein the first fifth node control circuit, under the control of the first clock signal, controls the connection between the first fifth node and the control signal output terminal of the N-1th stage, and, under the control of the initial control signal, controls the connection between the first fifth node and the first voltage terminal; wherein the first ninth node control circuit, under the control of the first clock signal, controls the connection between the first ninth node and the control signal output terminal of the N-1th stage; wherein the first fourth node control circuit, under the control of the potential of the first seventh node, controls the connection between the first fourth node and the first voltage terminal, and, under the control of the potential of the first sixth node, controls the connection between the first fourth node and the second clock signal terminal;wherein the first second control circuit, under the control of the second voltage signal, controls the connection between the first fifth node and the first second control node;

[0113] As in Fig. 21A shows the first control node control circuit based on at least one embodiment of the Fig. 20A shown control circuit a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143 and a first first control circuit 144; wherein the first seventh node control circuit 141 is electrically connected to a first seventh node N1-7, the second voltage terminal V2, a first clock signal terminal GCK or the first fifth node N1-5 and is used to control the connection between the first seventh node N1-7 and the second voltage terminal V2 under the control of a first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first seventh node N1-7 and the first clock signal terminal GCK under the control of the potential of the first fifth node N1-5; wherein the first eighth node control circuit 142 is electrically connected to the second voltage terminal V2, the first seventh node N1-7 or a first eighth node N1-8 and is used to control the connection between the first seventh node N1-7 and the first eighth node N1-8 under the control of a second voltage signal provided by the second voltage terminal V2; wherein the first third node control circuit 143 is electrically connected to the first eighth node N1-8, a second clock signal terminal GCB or the first third node N1-3 and is used to control the electrical connection between the first third node N1-3 and the second clock signal terminal GCB by controlling the potential of the first eighth node N1-8, and to control the potential of the first third node N1-3 according to the potential of the first eighth node N1-8; wherein the first first control circuit 144 is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5 or the first voltage terminal V1 and is used to control the connection between the first third node N1-3 and the first first control node NC1-1 under the control of a second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first first control node NC1-1 and the first voltage terminal V1 under the control of the potential of the first fifth node N1-5; the first second control node control circuit comprises a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154 and a first second control circuit 155; wherein the first sixth node control circuit 151 is electrically connected to the second voltage terminal V2, a first ninth node N1-9, the first sixth node N1-6 or the first fourth node N1-4 and is used to control the connection between the first ninth node N1-9 and the first sixth node N1-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the first sixth node N1-6 according to the potential of the first fourth node N1-4; wherein the first fifth node control circuit 152 is electrically connected to the control signal output terminal NS (N-1) of the N-1th stage, the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX or the first voltage terminal V1 and is used to control the connection between the first fifth node N1-5 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first fifth node N1-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX; wherein the first ninth node control circuit 153 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage or the first ninth node N1-9 and is used to control the connection between the first ninth node N1-9 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK; wherein the first fourth node control circuit 154 is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4 and the second clock signal terminal GCB respectively, and is used to control the connection between the first fourth node N1-4 and the first voltage terminal V1 under control of the potential of the first seventh node N1-7, and to control the connection between the first fourth node N1-4 and the second clock signal terminal GCB under control of the potential of the first sixth node N1-6; wherein the first second control circuit 155 is electrically connected to the second voltage terminal V2, the first fifth node N1-5 or the first second control node NC1-2 and is used to control the connection between the first fifth node N1-5 and the first second control node NC1-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0114] As in Fig. As shown in 21B, the first control node control circuit comprises at least one embodiment of the one shown in Fig. 20B shown control circuit a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143 and a first first control circuit 144; wherein the first seventh node control circuit 141 is electrically connected to a first seventh node N1-7, the second voltage terminal V2, a first clock signal terminal GCK or the first fifth node N1-5 and is used to control the connection between the first seventh node N1-7 and the second voltage terminal V2 under the control of a first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first seventh node N1-7 and the first clock signal terminal GCK under the control of the potential of the first fifth node N1-5; wherein the first eighth node control circuit 142 is electrically connected to the second voltage terminal V2, the first seventh node N1-7 or a first eighth node N1-8 and is used to control the connection between the first seventh node N1-7 and the first eighth node N1-8 under the control of a second voltage signal provided by the second voltage terminal V2; wherein the first third node control circuit 143 is electrically connected to the first eighth node N1-8, a second clock signal terminal GCB or the first third node N1-3 and is used to control the electrical connection between the first third node N1-3 and the second clock signal terminal GCB by controlling the potential of the first eighth node N1-8, and to control the potential of the first third node N1-3 according to the potential of the first eighth node N1-8; wherein the first first control circuit 144 is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5 or the first voltage terminal V1 and is used to control the connection between the first third node N1-3 and the first first control node NC1-1 under the control of a second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first first control node NC1-1 and the first voltage terminal V1 under the control of the potential of the first fifth node N1-5; the first second control node control circuit comprises a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154 and a first second control circuit 155; wherein the first sixth node control circuit 151 is electrically connected to the second voltage terminal V2, a first ninth node N1-9, the first sixth node N1-6 or the first fourth node N1-4 and is used to control the connection between the first ninth node N1-9 and the first sixth node N1-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the first sixth node N1-6 according to the potential of the first fourth node N1-4; wherein the first fifth node control circuit 152 is electrically connected to the control signal output terminal NS (N-1) of the N-1th stage, the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX or the first voltage terminal V1 and is used to control the connection between the first fifth node N1-5 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first fifth node N1-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX; wherein the first ninth node control circuit 153 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage or the first ninth node N1-9 and is used to control the connection between the first ninth node N1-9 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK; wherein the first fourth node control circuit 154 is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4 and the second clock signal terminal GCB respectively, and is used to control the connection between the first fourth node N1-4 and the first voltage terminal V1 under control of the potential of the first seventh node N1-7, and to control the connection between the first fourth node N1-4 and the second clock signal terminal GCB under control of the potential of the first sixth node N1-6; wherein the first second control circuit 155 is electrically connected to the second voltage terminal V2, the first fifth node N1-5 or the first second control node NC1-2 and is used to control the connection between the first fifth node N1-5 and the first second control node NC1-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0115] As in Fig. 21C shows the first control node control circuit based on at least one embodiment of the Fig. 20C shown control circuit a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143 and a first first control circuit 144; wherein the first seventh node control circuit 141 is electrically connected to a first seventh node N1-7, the second voltage terminal V2, a first clock signal terminal GCK or the first fifth node N1-5 and is used to control the connection between the first seventh node N1-7 and the second voltage terminal V2 under the control of a first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first seventh node N1-7 and the first clock signal terminal GCK under the control of the potential of the first fifth node N1-5; wherein the first eighth node control circuit 142 is electrically connected to the second voltage terminal V2, the first seventh node N1-7 or a first eighth node N1-8 and is used to control the connection between the first seventh node N1-7 and the first eighth node N1-8 under the control of a second voltage signal provided by the second voltage terminal V2; wherein the first third node control circuit 143 is electrically connected to the first eighth node N1-8, a second clock signal terminal GCB or the first third node N1-3 and is used to control the electrical connection between the first third node N1-3 and the second clock signal terminal GCB by controlling the potential of the first eighth node N1-8, and to control the potential of the first third node N1-3 according to the potential of the first eighth node N1-8; wherein the first first control circuit 144 is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5 or the first voltage terminal V1 and is used to control the connection between the first third node N1-3 and the first first control node NC1-1 under the control of a second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first first control node NC1-1 and the first voltage terminal V1 under the control of the potential of the first fifth node N1-5; the first second control node control circuit comprises a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154 and a first second control circuit 155; wherein the first sixth node control circuit 151 is electrically connected to the second voltage terminal V2, a first ninth node N1-9, the first sixth node N1-6 or the first fourth node N1-4 and is used to control the connection between the first ninth node N1-9 and the first sixth node N1-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the first sixth node N1-6 according to the potential of the first fourth node N1-4; wherein the first fifth node control circuit 152 is electrically connected to the control signal output terminal NS (N-1) of the N-1th stage, the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX or the first voltage terminal V1 and is used to control the connection between the first fifth node N1-5 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first fifth node N1-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX; wherein the first ninth node control circuit 153 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage or the first ninth node N1-9 and is used to control the connection between the first ninth node N1-9 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK; wherein the first fourth node control circuit 154 is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4 and the second clock signal terminal GCB respectively, and is used to control the connection between the first fourth node N1-4 and the first voltage terminal V1 under control of the potential of the first seventh node N1-7, and to control the connection between the first fourth node N1-4 and the second clock signal terminal GCB under control of the potential of the first sixth node N1-6; wherein the first second control circuit 155 is electrically connected to the second voltage terminal V2, the first fifth node N1-5 or the first second control node NC1-2 and is used to control the connection between the first fifth node N1-5 and the first second control node NC1-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0116] As in Fig. As shown in 21D, the first control node control circuit comprises at least one embodiment of the one shown in Fig. The control circuit shown in 20D includes a first seventh node control circuit 141, a first eighth node control circuit 142, a first third node control circuit 143 and a first first control circuit 144; wherein the first seventh node control circuit 141 is electrically connected to a first seventh node N1-7, the second voltage terminal V2, a first clock signal terminal GCK or the first fifth node N1-5 and is used to control the connection between the first seventh node N1-7 and the second voltage terminal V2 under the control of a first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first seventh node N1-7 and the first clock signal terminal GCK under the control of the potential of the first fifth node N1-5; wherein the first eighth node control circuit 142 is electrically connected to the second voltage terminal V2, the first seventh node N1-7 or a first eighth node N1-8 and is used to control the connection between the first seventh node N1-7 and the first eighth node N1-8 under the control of a second voltage signal provided by the second voltage terminal V2; wherein the first third node control circuit 143 is electrically connected to the first eighth node N1-8, a second clock signal terminal GCB or the first third node N1-3 and is used to control the electrical connection between the first third node N1-3 and the second clock signal terminal GCB by controlling the potential of the first eighth node N1-8, and to control the potential of the first third node N1-3 according to the potential of the first eighth node N1-8; wherein the first first control circuit 144 is electrically connected to the second clock signal terminal GCB, the first third node N1-3, the first first control node NC1-1, the first fifth node N1-5 or the first voltage terminal V1 and is used to control the connection between the first third node N1-3 and the first first control node NC1-1 under the control of a second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first first control node NC1-1 and the first voltage terminal V1 under the control of the potential of the first fifth node N1-5; the first second control node control circuit comprises a first sixth node control circuit 151, a first fifth node control circuit 152, a first ninth node control circuit 153, a first fourth node control circuit 154 and a first second control circuit 155; wherein the first sixth node control circuit 151 is electrically connected to the second voltage terminal V2, a first ninth node N1-9, the first sixth node N1-6 or the first fourth node N1-4 and is used to control the connection between the first ninth node N1-9 and the first sixth node N1-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the first sixth node N1-6 according to the potential of the first fourth node N1-4; wherein the first fifth node control circuit 152 is electrically connected to the control signal output terminal NS (N-1) of the N-1th stage, the first clock signal terminal GCK, the first fifth node N1-5, the initial control terminal NCX or the first voltage terminal V1 and is used to control the connection between the first fifth node N1-5 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the first fifth node N1-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX; wherein the first ninth node control circuit 153 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage or the first ninth node N1-9 and is used to control the connection between the first ninth node N1-9 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK; wherein the first fourth node control circuit 154 is electrically connected to the first seventh node N1-7, the first voltage terminal V1, the first sixth node N1-6, the first fourth node N1-4 and the second clock signal terminal GCB respectively, and is used to control the connection between the first fourth node N1-4 and the first voltage terminal V1 under control of the potential of the first seventh node N1-7, and to control the connection between the first fourth node N1-4 and the second clock signal terminal GCB under control of the potential of the first sixth node N1-6; wherein the first second control circuit 155 is electrically connected to the second voltage terminal V2, the first fifth node N1-5 or the first second control node NC1-2 and is used to control the connection between the first fifth node N1-5 and the first second control node NC1-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0117] Optionally, the first seventh node control circuit includes a first twelfth transistor and a first thirteenth transistor, the first eighth node control circuit includes a first fourteenth transistor, the first third node control circuit includes a first fifteenth transistor and a first fourth capacitor, and the first first control circuit includes a first sixteenth transistor and a first seventeenth transistor; wherein the gate of the first twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the first twelfth transistor is electrically connected to the second voltage terminal, and the second electrode of the first twelfth transistor is electrically connected to the first seventh node; wherein the gate of the first thirteenth transistor is electrically connected to the first fifth node, the first electrode of the first thirteenth transistor is electrically connected to the first seventh node, and the second electrode of the first thirteenth transistor is electrically connected to the first clock signal terminal; wherein the gate of the first fourteenth transistor is electrically connected to the second voltage terminal, the first electrode of the first fourteenth transistor is electrically connected to the first seventh node, and the second electrode of the first fourteenth transistor is electrically connected to the first eighth node; wherein the gate of the first fifteenth transistor is electrically connected to the first eighth node, the first electrode of the first fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the first fifteenth transistor is electrically connected to the first third node; wherein a first terminal of the first fourth capacitor is electrically connected to the first eighth node, and a second terminal of the first fourth capacitor is electrically connected to the first third node; wherein the gate of the first sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the first sixteenth transistor is electrically connected to the first third node, and the second electrode of the first sixteenth transistor is electrically connected to the first first control node; wherein the gate of the first seventeenth transistor is electrically connected to the first fifth node, the first electrode of the first seventeenth transistor is electrically connected to the first first control node, and the second electrode of the first seventeenth transistor is electrically connected to the first voltage terminal.

[0118] Optionally, the first sixth node control circuit includes a first eighteenth transistor and a first fifth capacitor, the first fifth node control circuit includes a first nineteenth transistor and a first twentieth transistor, the first ninth node control circuit includes a first twenty-first transistor, the first fourth node control circuit includes a first twenty-second transistor and a first twenty-third transistor, and the first second control circuit includes a first twenty-fourth transistor; wherein the gate of the first eighteenth transistor is electrically connected to the second voltage terminal, the first electrode of the first eighteenth transistor is electrically connected to the first ninth node, and the second electrode of the first eighteenth transistor is electrically connected to the first sixth node; wherein a first terminal of the first fifth capacitor is electrically connected to the first fourth node, and a second terminal of the first fifth capacitor is electrically connected to the first sixth node; wherein the gate of the first nineteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the first nineteenth transistor is electrically connected to the drive signal output terminal of the N-1th stage, and the second electrode of the first nineteenth transistor is electrically connected to the first fifth node; wherein the gate of the first twentieth transistor is electrically connected to the initial control terminal, the first electrode of the first twentieth transistor is electrically connected to the first voltage terminal, and the second electrode of the first twentieth transistor is electrically connected to the first fifth node; wherein the gate of the first twenty-first transistor is electrically connected to the first clock signal terminal, the first electrode of the first twenty-first transistor is electrically connected to the drive signal output terminal of the N-1th stage, and the second electrode of the first twenty-first transistor is electrically connected to the first ninth node; wherein the gate of the first twenty-second transistor is electrically connected to the first seventh node, the first electrode of the first twenty-second transistor is electrically connected to the first voltage terminal, and the second electrode of the first twenty-second transistor is electrically connected to the first fourth node; wherein the gate of the first twenty-third transistor is electrically connected to the first sixth node, the first electrode of the first twenty-third transistor is electrically connected to the first fourth node, and the second electrode of the first twenty-third transistor is electrically connected to the second clock signal terminal; wherein the gate of the first twenty-fourth transistor is electrically connected to the second voltage terminal, the first electrode of the first twenty-fourth transistor is electrically connected to the first ninth node, and the second electrode of the first twenty-fourth transistor is electrically connected to the first second control node.

[0119] Optionally, the first first drive output circuit includes a first twenty-fifth transistor and a first sixth capacitor, and the first second drive output circuit includes a first twenty-sixth transistor and a first seventh capacitor; wherein the gate of the first twenty-fifth transistor is electrically connected to the first control node, the first electrode of the first twenty-fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the first twenty-fifth transistor is electrically connected to the drive signal output terminal of the Nth stage; wherein a first terminal of the first sixth capacitor is electrically connected to the first first control node, and a second terminal of the first sixth capacitor is electrically connected to the first voltage terminal; wherein the gate of the first twenty-sixth transistor is electrically connected to the first second control node, the first electrode of the first twenty-sixth transistor is electrically connected to the drive signal output terminal of the Nth stage, and the second electrode of the first twenty-sixth transistor is electrically connected to the second voltage terminal; wherein a first terminal of the first seventh capacitor is electrically connected to the control signal output terminal of the Nth stage, and a second terminal of the first seventh capacitor is electrically connected to the second voltage terminal.

[0120] The control circuit according to at least one embodiment of the present disclosure further comprises a first output pull-down circuit; wherein the first output pulldown circuit is electrically connected to the first control node, the control signal output terminal of the Nth stage or the second voltage terminal, and is used to control the connection between the control signal output terminal of the Nth stage and the second voltage terminal by controlling the potential of the first control node.

[0121] In a specific implementation, the control circuit may further include a first output pulldown circuit which, under control of the potential of the first control node, can control the connection between the control signal output terminal of the Nth stage and the second voltage terminal in order to improve the output capability of the second voltage signal of the control signal output terminal of the Nth stage.

[0122] As in Fig. As shown in 22A, the control circuit according to at least one embodiment of the present disclosure, based on at least one embodiment of the Fig. The control circuit shown in 21A also includes a first output pulldown circuit 1220; wherein the first output pulldown circuit 1220 is electrically connected to the first control node NC1-1, the control signal output terminal NS (N) of the Nth stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS (N) of the Nth stage and the second voltage terminal V2 under control of the potential of the first control node NC1-1.

[0123] As in Fig. As shown in 22B, the control circuit according to at least one embodiment of the present disclosure, based on at least one embodiment of the Fig. The control circuit shown in 21B also includes a first output pulldown circuit 1220; wherein the first output pulldown circuit 1220 is electrically connected to the first control node NC1-1, the control signal output terminal NS (N) of the N-th stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS of the N-th stage and the second voltage terminal V2 under control of the potential of the first control node NC1-1.

[0124] As in Fig. As shown in 22C, the control circuit according to at least one embodiment of the present disclosure, based on at least one embodiment of the Fig. The control circuit shown in 21C also includes a first output pulldown circuit 1220; wherein the first output pulldown circuit 1220 is electrically connected to the first control node NC1-1, the control signal output terminal NS (N) of the N-th stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS of the N-th stage and the second voltage terminal V2 under control of the potential of the first control node NC1-1.

[0125] As in Fig. As shown in 22D, the control circuit according to at least one embodiment of the present disclosure, based on at least one embodiment of the in Fig. The control circuit shown in 21D also includes a first output pulldown circuit 1220; wherein the first output pulldown circuit 1220 is electrically connected to the first control node NC1-1, the control signal output terminal NS (N) of the N-th stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS of the N-th stage and the second voltage terminal V2 under control of the potential of the first control node NC1-1.

[0126] As in Fig. As shown in 23, the first gating circuit based on at least one embodiment of the one shown in Fig. The control circuit shown in 21A includes a first transistor T1-1 and a first second transistor T1-2; wherein the gate of the first transistor T1-1 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, the drain of the first transistor T1-1 is electrically connected to the first node N1-1, and the source of the first transistor T1-1 is electrically connected to the drain of the first transistor T1-2; wherein the gate of the first second transistor T1-2 is electrically connected to the first third node N1-3 (N-1) of the N-1th stage, and the source of the first second transistor T1-2 is electrically connected to the gating input terminal VCT; the first output control circuit includes a first third transistor T1-3; wherein the gate of the first third transistor T1-3 is electrically connected to the first first node N1-1, the source of the first third transistor T1-3 is electrically connected to the first first control node NC1-1 and the drain of the first third transistor T1-3 is electrically connected to the first second node N1-2; The first energy storage circuit includes a first capacitor C1-1; wherein a first terminal of the first first capacitor C1-1 is electrically connected to the first first node N1-1, and a second terminal of the first first capacitor C1-1 is electrically connected to the first second node N1-2; The first second energy storage circuit includes a first second capacitor C1-2; wherein a first terminal of the first second capacitor C1-2 is electrically connected to the first third control node NC1-3, and a second terminal of the first second capacitor C1-2 is electrically connected to the output control terminal NO (N) of the Nth stage; The first second node control circuit includes a first fourth transistor T1-4; wherein the gate of the first fourth transistor T1-4 is electrically connected to the first third control node NC1-3, the source of the first fourth transistor T1-4 is electrically connected to the first second node N1-2, and the drain of the first fourth transistor T1-4 is electrically connected to the high voltage terminal VGH; The first output circuit includes a first fifth transistor T1-5, a first sixth transistor and a first third capacitor C1-3; wherein the gate of the first fifth transistor T1-5 is electrically connected to the first second node N1-2, the source of the first fifth transistor T1-5 is electrically connected to the high voltage terminal VGH, and the drain of the first fifth transistor T1-5 is electrically connected to the output control terminal NO (N); wherein the gate of the first sixth transistor T1-6 is electrically connected to the first third control node NC1-3, the source of the first sixth transistor T1-6 is electrically connected to the output control terminal NO (N), and the drain of the first sixth transistor T1-6 is electrically connected to the low voltage terminal VGL; wherein a first terminal of the first third capacitor C1-3 is electrically connected to the first second node N1-2, and a second terminal of the first third capacitor C1-3 is electrically connected to the high voltage terminal VGH; The first node control circuit includes a first eighth transistor T1-8; wherein the gate of the first eighth transistor T1-8 is electrically connected to the first fourth node N1-4, the source of the first eighth transistor T1-8 is electrically connected to the first first node N1-1, and the drain of the first eighth transistor T8 is electrically connected to the low voltage terminal VGL; The first third control node control circuit includes a first ninth transistor T1-9, a first tenth transistor T1-10 and a first eleventh transistor T1-11; wherein the gate of the first ninth transistor T1-9 is electrically connected to the first first node N1-1, the drain of the first ninth transistor T1-9 is electrically connected to the first fifth node N1-5, and the source of the first ninth transistor T1-9 is electrically connected to the first third control node NC1-3; wherein the gate of the first tenth transistor T1-10 and the source of the first tenth transistor T1-10 are each electrically connected to the first sixth node N1-6, and the drain of the first tenth transistor T1-10 is electrically connected to the first second control node NC1-2; wherein the gate of the first eleventh transistor T1-11 and the source of the first eleventh transistor T1-11 are each electrically connected to the first sixth node N1-6, and the drain of the first eleventh transistor T1-11 is electrically connected to the first third control node NC1-3; The first seventh node control circuit comprises a first twelfth transistor T1-12 and a first thirteenth transistor T1-13, the first eighth node control circuit comprises a first fourteenth transistor T1-14, the first third node control circuit comprises a first fifteenth transistor T1-15 and a first fourth capacitor C1-4, and the first first control circuit comprises a first sixteenth transistor T1-16 and a first seventeenth transistor T1-17; wherein the gate of the first twelfth transistor T1-12 is electrically connected to the first clock signal terminal GCK, the source of the first twelfth transistor T1-12 is electrically connected to the low voltage terminal VGL, and the drain of the first twelfth transistor T1-12 is electrically connected to the first seventh node N1-7; wherein the gate of the first thirteenth transistor T1-13 is electrically connected to the first fifth node N1-5, the source of the first thirteenth transistor T1-13 is electrically connected to the first seventh node N1-7, and the drain of the first thirteenth transistor T1-13 is electrically connected to the first clock signal terminal GCK; wherein the gate of the first fourteenth transistor T1-14 is electrically connected to the low voltage terminal VGL, the source of the first fourteenth transistor T1-14 is electrically connected to the first seventh node N1-7, and the drain of the first fourteenth transistor T1-14 is electrically connected to the first eighth node N1-8; wherein the gate of the first fifteenth transistor T1-15 is electrically connected to the first eighth node N1-8, the source of the first fifteenth transistor T1-15 is electrically connected to the second clock signal terminal GCB, and the drain of the first fifteenth transistor T1-15 is electrically connected to the first third node N1-3; wherein a first terminal of the first fourth capacitor C1-4 is electrically connected to the first eighth node N1-8, and a second terminal of the first fourth capacitor C1-4 is electrically connected to the first third node N1-3; wherein the gate of the first sixteenth transistor T1-16 is electrically connected to the second clock signal terminal GCB, the source of the first sixteenth transistor T1-16 is electrically connected to the first third node N1-3, and the drain of the first sixteenth transistor T1-16 is electrically connected to the first first control node NC1-1; wherein the gate of the first seventeenth transistor T1-17 is electrically connected to the first fifth node N1-5, the source of the first seventeenth transistor T1-17 is electrically connected to the first first control node NC1-1, and the drain of the first seventeenth transistor T1-17 is electrically connected to the high voltage terminal VGH; The first sixth node control circuit includes a first eighteenth transistor T1-18 and a first fifth capacitor C1-5, the first fifth node control circuit includes a first nineteenth transistor T1-19 and a first twentieth transistor T1-20, the first ninth node control circuit includes a first twenty-first transistor T1-21, the first fourth node control circuit includes a first twenty-second transistor T1-22 and a first twenty-third transistor T1-23, and the first second control circuit includes a first twenty-fourth transistor T1-24; wherein the gate of the first eighteenth transistor T1-18 is electrically connected to the low-voltage terminal VGL, the source of the first eighteenth transistor T1-18 is electrically connected to the first ninth node N1-9, and the drain of the first eighteenth transistor T1-18 is electrically connected to the first sixth node N1-6; wherein a first terminal of the first fifth capacitor C1-5 is electrically connected to the first fourth node N1-4, and a second terminal of the first fifth capacitor C1-5 is electrically connected to the first sixth node N1-6; wherein the gate of the first nineteenth transistor T1-19 is electrically connected to the first clock signal terminal GCK, the source of the first nineteenth transistor T1-19 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, and the drain of the first nineteenth transistor T1-19 is electrically connected to the first fifth node N1-5; wherein the gate of the first twentieth transistor T1-20 is electrically connected to the initial control terminal NCX, the source of the first twentieth transistor T1-20 is electrically connected to the high voltage terminal VGH, and the drain of the first twentieth transistor T1-20 is electrically connected to the first fifth node N1-5; wherein the gate of the first twenty-first transistor T1-21 is electrically connected to the first clock signal terminal GCK, the source of the first twenty-first transistor T1-21 is electrically connected to the drive signal output terminal NS (N-1) of the N-1 stage, and the drain of the first twenty-first transistor T1-21 is electrically connected to the first ninth node N1-9; wherein the gate of the first twenty-second transistor T1-22 is electrically connected to the first seventh node N1-7, the source of the first twenty-second transistor T1-22 is electrically connected to the high-voltage terminal VGH, and the drain of the first twenty-second transistor T1-22 is electrically connected to the first fourth node N1-4; wherein the gate of the first twenty-third transistor T1-23 is electrically connected to the first sixth node N1-6, the source of the first twenty-third transistor T1-23 is electrically connected to the first fourth node N1-4, and the drain of the first twenty-third transistor T1-23 is electrically connected to the second clock signal terminal GCB; wherein the gate of the first twenty-fourth transistor T1-24 is electrically connected to the low-voltage terminal VGL, the source of the first twenty-fourth transistor T1-24 is electrically connected to the first ninth node N1-9, and the drain of the first twenty-fourth transistor T1-24 is electrically connected to the first second control node NC1-2; The first first drive output circuit comprises a first twenty-fifth transistor T1-25 and a first sixth capacitor C1-6, and the first second drive output circuit comprises a first twenty-sixth transistor T1-26 and a first seventh capacitor C1-7; wherein the gate of the first twenty-fifth transistor T1-25 is electrically connected to the first control node NC1-1, the source of the first twenty-fifth transistor T1-25 is electrically connected to the high voltage terminal VGH, and the drain of the first twenty-fifth transistor T1-25 is electrically connected to the control signal output terminal NS (N) of the N-th stage; wherein a first terminal of the first sixth capacitor C1-6 is electrically connected to the first first control node NC1-1, and a second terminal of the first sixth capacitor C1-6 is electrically connected to the high voltage terminal VGH; wherein the gate of the first twenty-sixth transistor T1-26 is electrically connected to the first second control node NC1-2, the source of the first twenty-sixth transistor T1-26 is electrically connected to the drive signal output terminal NS (N) of the N-th stage, and the drain of the first twenty-sixth transistor T1-26 is electrically connected to the low voltage terminal VGL; wherein a first terminal of the first seventh capacitor C1-7 is electrically connected to the control signal output terminal NS (N) of the Nth stage, and a second terminal of the first seventh capacitor C1-7 is electrically connected to the low voltage terminal VGL.

[0127] In at least one embodiment of the Fig. In the control circuit shown in Figure 23, T1-3 is a double-gate transistor, but is not limited to this; however, in a specific implementation, T1-3 can also be replaced by a single-gate transistor.

[0128] In Fig. 23 is the node with the symbol N1-10, a first tenth node.

[0129] In at least one embodiment of the Fig. In the control circuit shown in 23, all transistors are p-type transistors, but are not limited to this.

[0130] In at least one embodiment of the Fig. In the control circuit shown in 23, the first voltage connection is a high-voltage connection and the second voltage connection is a low-voltage connection, but they are not limited to this.

[0131] In at least one embodiment of the Fig. In the control circuit shown in 23, all transistors are p-type transistors, but are not limited to this.

[0132] In at least one embodiment of the Fig. In the control circuit shown in section 23, N1-10 is the first tenth node.

[0133] In at least one embodiment of the present disclosure, the structure of the first control signal generation circuit is not based on the one described in Fig. The circuits shown in Figure 22 are limited. The first control signal generation circuit can be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, or a 10T3C circuit, etc., but is not limited to these.

[0134] If at least one embodiment of the in Fig. If the control circuit shown in Figure 23 of the present disclosure functions and the potential of the control output signal of the N-th stage provided by NO(N) is reduced from high voltage to low voltage, the potential of the first third control node NC1-3 can be lowered so that T1-6 can be switched on more effectively to keep the potential of the control output signal of the N-th stage at low voltage.

[0135] If at least one embodiment of the in Fig. If the control circuit shown in section 23 of the present disclosure functions, the following occurs: In a first phase, NS (N-1) outputs a low-voltage signal, GCK outputs a low-voltage signal, and GCB outputs a high-voltage signal. During this process, T1-19 and T1-21 are switched on to lower the potential of N1-5 and the potential of N1-9, T1-24 and T1-18 are switched on to lower the potential of NC1-2 and N1-6, and T1-26 is switched on. The potential of N1-6 is at low voltage to ensure that T1-23 is switched on, the potential of N1-5 is at low voltage to switch on T1-13, GCK provides a low-voltage signal to switch on T1-12, T1-14 is switched on, the potential of N1-7 and the potential of N1-8 are at low voltage, T1-15 is switched on to control the potential of N1-3 to high voltage, the potential of N1-5 is at low voltage to switch on T1-17, the potential of NC1-1 is at high voltage;T1-10 and T1-11 are switched on, the potential of NC1-2 and the potential of NC1-3 are at low voltage; In a second phase, NS (N-1) outputs a low-voltage signal, the potential of the first clock signal output by GCK jumps from low voltage to high voltage, GCB outputs a low-voltage signal, T1-19 and T1-21 are switched off, the potential of N1-5 is at low voltage, T1-12 is switched off, the potential of N1-5 is kept at low voltage, T1-13 is switched on, T1-14 is switched on, the potential of N1-7 and the potential of N1-8 are at high voltage, T1-15 is switched off, the potential of N1-3 is kept at high voltage in the previous phase, T1-16 is switched on to keep the potential of NC1-1 at high voltage and to switch off T1-25;Simultaneously, the potential of N1-6 is at low voltage to switch on T1-23, GCB writes the low-voltage signal to N1-4, the potential of N1-6 is reduced to a lower voltage via C1-4 (5V to 10V lower than the voltage value of the low-voltage signal provided by GCB), T1-10 and T1-11 are switched on to write low-voltage signals to NC1-2 and N1-6 (the potential of NC1-2 is 3V to 8V lower than the voltage value of the low-voltage signal provided by GCB) and to fully switch on T1-26, NS(N) outputs a low-voltage signal; the potential of NC1-3 is at low voltage, T1-6 is switched on, NO(N) outputs a low-voltage signal; the potential of N1-4 is at low voltage, T1-8 is switched on to reduce the potential of N1-1; T1-9 is switched on to control the potential of NC1-3 to low voltage, T1-6 is switched on, and NO (N) outputs a low voltage signal;Because the potential of N1-4 is at low voltage, T1-8 is switched on to control the potential of N1-1 at low voltage; T1-3 is switched on to control the connection between N1-1 and N1-2; the potential of N1-2 is at high voltage; T1-5 is switched to blocking; In a third phase, NS (N-1) outputs a high-voltage signal, GCK outputs a low-voltage signal, GCB outputs a high-voltage signal, T1-19 and T1-21 are switched on to raise the potential of N1-5 and the potential of N1-9, T1-24 and T1-18 are switched on, the potential of NC1-2 and the potential of N1-6 are at high voltage, T1-26 is switched off; The potential of N1-6 is at high voltage, T1-23 is switched off, the potential of N1-5 is at high voltage, T1-13 is switched off, GCK outputs a low-voltage signal to switch on T1-12, T1-14 is switched on to lower the potential of N1-7 and the potential of N1-8 and switch on T1-15, GCB writes the high-voltage signal to N1-3, T1-16 is switched off, the potential of N1-5 is at high voltage to switch off T1-17, the potential of NC1-1 is at high voltage; it is ensured that T1-25 is switched off;T1-22 is switched on, the potential of N1-4 is at high voltage, T1-8 is switched off; the potential of NC1-1 and the potential of NC1-2 are at high voltage, NS (N) continuously outputs a low voltage signal; T1-10 and T1-11 are switched off; In the third phase, N1-3 (N-1) and NS (N) output low-voltage signals, T1-1 and T1-2 are switched on, VCT and N1-1 are connected together; When VCT provides a high-voltage signal in the third phase, the potential of N1-1 is high voltage, T1-9 is switched off, T1-3 is switched off, the potential of N1-2 is held at high voltage; T1-9 is switched off, NC1-3 and N1-5 are disconnected from each other, the potential of N1-6 is high voltage, T1-10 and T1-11 are switched off, the potential of NC1-3 is held at low voltage, T1-6 is switched on, NO (N) outputs a low-voltage signal; When VCT provides a low-voltage signal in the third phase, the potential of N1-1 is at low voltage, T1-9 is switched on, T1-3 is switched on, NC1-1 and N1-2 are connected together, the potential of N1-2 is at high voltage, T1-5 is switched off, T1-9 is switched on to control the connection between NC1-3 and N1-5, the potential of NC1-3 is at high voltage, NO (N) continuously outputs a low-voltage signal; In a fourth phase, NS (N-1) outputs a high-voltage signal; the potential of the first clock signal output by GCK jumps from low voltage to high voltage; GCB outputs a low-voltage signal; T1-19 and T1-21 are switched off; the potential of N1-7 is held at low voltage; T1-14 is switched on; the potential of N1-8 is at low voltage; T1-15 is switched on; T1-16 is switched on to write low-voltage signals to N1-3 and NC1-1; T1-25 is switched on; NS (N) outputs a high-voltage signal; simultaneously, the potential of N1-6 is at high voltage; T1-23 is switched off; the potential of N1-4 is held at high voltage; and the potential of N1-6 is held at high voltage; T1-10 and T1-11 are switched off. In the fourth phase, N1-3 (N-1) outputs a high-voltage signal, T1-2 is switched to blocking mode, and T1-8 is switched to blocking mode; When the potential of N1-1 is at low voltage, T1-9 is switched on to control the connection between N1-5 and NC1-3; when the potential of N1-5 is at high voltage, the potential of NC1-3 is at high voltage, and T1-6 is switched off; when T1-3 is switched on to control the connection between NC1-1 and N1-2, when the potential of N1-2 is at low voltage, T1-5 is switched on, T1-6 is switched off, NO (N) outputs a high-voltage signal; When the potential of N1-1 is high voltage, T1-9 is switched off to control the isolation between N1-5 and NC1-3, the potential of NC1-3 is held at high voltage, the potential of NC1-3 remains at low voltage in the third phase, T1-6 remains on; T1-3 is switched off to control the isolation between NC1-1 and N1-2, the potential of N1-2 is held at high voltage, T1-5 is switched off, and NO(N) continuously outputs a low-voltage signal; In a fifth phase, the potential of the control signal of the N-1th stage output by NS (N-1) jumps from high voltage to low voltage, GCK outputs a high voltage signal, GCB outputs a low voltage signal, T1-19 and T1-21 are switched to blocking, the potential of N1-5 and the potential of N1-9 are held at high voltage and the potential of other nodes remains unchanged to ensure that NS (N) outputs a high voltage signal; In a sixth phase, NS (N-1) outputs a low-voltage signal. The potential of the first clock signal output by GCK jumps from high voltage to low voltage. GCB outputs a high-voltage signal. T1-19 and T1-21 are switched on to control the potential of N1-5 and N1-9 to low voltage. T1-24 and T1-18 are switched on. The potential of NC1-2 and N1-6 is at low voltage to switch on T1-26. The potential of N1-6 is at low voltage to ensure that T1-23 is switched on. The potential of N1-5 is at low voltage to switch on T1-13. T1-12 is switched on to lower the potential of N1-7 and N1-8 and switch on T1-15. GCB writes the high-voltage signal to N1-3. The potential of N1-5 is at low voltage to switch on T1-17. To switch on, the potential of NC1-1 is raised to high voltage to ensure that T1-25 is switched off.

[0136] The difference between at least one embodiment of the in Fig. 24A shown control circuit and at least one embodiment of the Fig. The control circuit shown in section 23 consists of the following: The first second node control circuit includes a first fourth transistor T1-4 and a first control transistor TC1; wherein the gate of the first fourth transistor T1-4 is electrically connected to the first third control node NC1-3, the source of the first fourth transistor T1-4 is electrically connected to the drain of the first control transistor TC1, and the drain of the first fourth transistor T1-4 is electrically connected to the high voltage terminal VGH; wherein the gate of the first control transistor TC1 is electrically connected to the output control terminal NO (N) of the N-th stage, and the source of the first control transistor TC1 is electrically connected to the first second node N1-2.

[0137] If at least one embodiment of the in Fig. In the control circuit shown in Figure 24A of the present disclosure, when NO (N) outputs a low voltage signal and the potential of NC1-3 is at low voltage, T1-4 and TC1 are switched on so that N1-2 and VGH are connected to each other and the potential of N1-2 is at high voltage, ensuring that T1-5 is switched off and NO (N) outputs a low voltage signal.

[0138] In Fig. 24A represents the symbol N1-11 as the first eleventh node.

[0139] Fig. 24B is a simulation operating time diagram of at least one embodiment of the in Fig. 24A control circuit shown in the present disclosure.

[0140] The difference between at least one embodiment of the in Fig. 25 shown control circuit and at least one embodiment of the in Fig. The control circuit shown in section 24 consists of the following:

[0141] At least one embodiment of the in Fig. The control circuit shown in section 25 of the present disclosure further comprises a first initialization circuit; wherein the first initialization circuit includes a first seventh transistor T1-7; wherein the gate of the first seventh transistor T1-7 is electrically connected to the initial control terminal NCX, the source of the first seventh transistor T1-7 is electrically connected to the first node N1-1, and the drain of the first seventh transistor T1-7 is electrically connected to the low voltage terminal VGL.

[0142] In at least one embodiment of the Fig. In the control circuit shown in Figure 25, T 1-7 is a p-type transistor.

[0143] If at least one embodiment of the in Fig. If the control circuit shown in section 25 of the present disclosure functions as follows:

[0144] When the display starts (i.e., when the display device is switched on), NCX outputs a low-voltage signal in a reset phase prior to the first phase; T1-7 is switched on to control the potential of N1-1 to low voltage; T1-3 is switched on to control the connection between NC1-1 and N1-2; T1-9 is switched on to control the connection between NC1-3 and N1-5; T1-20 is switched on to control the potential of N1-5 and NC1-3 to high voltage; at this point, NC1-1 and N1-2 are at low potential; T1-25 is switched on; T1-5 is switched on; both NS(N) and NO(N) output high-voltage signals, which allows a second display control transistor M2, included in all pixel circuits in the effective display area, to switch on in order to clear the residual charge in the storage capacitor Cst and to eliminate the screen flickering problem at startup; If subsequently NS (N) and N1-3 (N-1) each output low voltage signals, T1-1 and T1-2 are switched to conduct in order to control the connection between VCT and N1-1; When VCT provides a low-voltage signal, the potential of N1-1 is at low voltage, and C1-1 maintains the potential of N1-1; T1-3 is switched on to control the connection between NC1-1 and N1-2, at this time the potential of NC1-1 is at high voltage, the potential of N1-2 is at high voltage, T1-5 is switched off, and T1-9 is switched on to control the connection between NC1-3 and N1-5, the potential of NC1-3 is at high voltage, NO (N) continuously outputs a low-voltage signal; When VCT provides a high-voltage signal, the potential of N1-1 is at high voltage, T1-3 is switched off, NC1-1 and N1-2 are disconnected, C1-1 controls the potential of N1-2 to high voltage, T1-9 is switched off, NC1-3 and N1-5 are disconnected, the potential of N1-6 is at high voltage, T1-10 and T1-11 are switched off, the potential of NC1-3 is kept at low voltage, T1-6 is switched on, NO (N) outputs a low-voltage signal; Subsequently, NS(N) outputs a high-voltage signal during the phase of providing the control signal for the N-th stage; at this point, the potential of NC1-1 is at low voltage and the potential of NC1-2 is at high voltage; when the potential of N1-1 is at low voltage, T1-3 is switched on, NC1-1 and N1-2 are connected together, the potential of N1-2 is at low voltage, T1-9 is switched on to control the connection between N1-5 and NC1-3, the potential of N1-5 is at high voltage, the potential of NC1-3 is at high voltage, T1-6 is switched off; T1-5 is switched on, T1-6 is switched off, and NO(N) outputs a high-voltage signal; When the potential of N1-1 is high voltage, T1-3 is switched off, NC1-1 and N1-2 are disconnected, the potential of N1-2 is held at high voltage, T1-9 is switched off to control the disconnection between N1-5 and NC1-3, the potential of NC1-3 is held at low voltage, T1-6 is switched on; T1-5 is switched off and NO (N) continuously outputs a low voltage signal; After the phase of providing the control signal for the N-th stage, T1-8 is switched on when the potential of N1-4 is at low voltage to control the connection between N1-1 and VGL. When the potential of N1-1 is at low voltage, T1-3 is switched on to control the connection between NC1-1 and N1-2. At this point, the potential of NC1-1 is at high voltage and the potential of NC1-2 is at low voltage. When the potential of N1-2 is at high voltage, T1-9 is switched on to control the connection between NC1-3 and N1-5. When the potential of N1-5 and the potential of N1-6 are at low voltage, T1-10 and T1-11 are switched on. When the potential of NC1-3 is at low voltage, NO(N) outputs a low-voltage signal.

[0145] If at least one embodiment of the in Fig. In the control circuit shown in Figure 25 of the present disclosure, when N1-3 (N-1) outputs a low-voltage signal and NS (N) outputs a low-voltage signal, T1-1 and T1-2 are switched on, whereby a gating input signal status can be obtained within one high- and low-frequency switching cycle by simultaneously gating the two aforementioned signals and written to N1-1. T1-1 and T1-2 are not switched on simultaneously at other times to prevent the potential of N1-1 from being affected by a gating input signal provided by VCT.

[0146] If at least one embodiment of the in Fig. In the control circuit shown in Figure 25 of the present disclosure, when both NS (N) and N3 (N-1) output low-voltage signals and VCT outputs a low-voltage signal, the potential of N1-1 is at low voltage, T1-3 is switched on, the potential of N1-2 and the potential of NC1-1 are equal, NC1-3 switches off T1-6 and N1-2 switches on T1-5, thus ensuring a normal output of NO (N); When both NS (N) and N1-3 (N-1) output low-voltage signals and VCT outputs a high-voltage signal, the potential of N1-1 is at high voltage, T1-3 is switched off, T1-9 is switched off, the potential of N1-2 is at high voltage, T1-5 is switched off, the potential of N1-6 is at high voltage, T1-11 is in a reverse-switching state, and the potential of NC1-3 is held at low voltage to switch on T1-6, thus ensuring that NO (N) always outputs a low-voltage signal; the potential of NC1-3 is at low voltage to switch on T1-4, the potential of N1-2 is held at high voltage to prevent current leakage from T1-5, and after NO (N) has finished outputting, the potential of N1-4 is at low voltage to switch on T1-8, and the potential of N1-1 is lowered to low voltage.

[0147] The difference between at least one embodiment of the in Fig. 26 shown control circuit and at least one embodiment of the in Fig. The control circuit shown in section 24 of the present disclosure consists of the following:

[0148] At least one embodiment of the in Fig. The control circuit shown in Figure 26 of the present disclosure further comprises a first output pull-down circuit; wherein the first output pulldown circuit comprises a first twenty-seventh transistor T1-27; wherein the gate of the first twenty-seventh transistor T1-27 is electrically connected to the first control node NC1-1, the source of the first twenty-seventh transistor T1-27 is electrically connected to the control signal output terminal NS (N) of the N-th stage, and the drain of the first twenty-seventh transistor T1-27 is electrically connected to the low voltage terminal VGL.

[0149] In at least one embodiment of the Fig. In the control circuit shown in Figure 26, T1-27 is an n-type transistor.

[0150] If at least one embodiment of the in Fig. When the control circuit shown in Figure 26 is functioning and the potential of NC1-1 is at high voltage, T1-27 is switched on, NS (N) and VGL are connected together, and NS (N) outputs a low voltage signal.

[0151] The difference between at least one embodiment of the in Fig. 27 shown control circuit and at least one embodiment of the in Fig. The difference in the control circuit shown in Figure 23 is that the first fourth transistor T1-4 is not included.

[0152] The difference between at least one embodiment of the in Fig. 28 shown control circuit and at least one embodiment of the in Fig. The difference in the control circuit shown in Figure 23 is that the first eighth transistor T1-8 is not included.

[0153] The difference between at least one embodiment of the in Fig. 29 shown control circuit and at least one embodiment of the in Fig. The difference in the control circuit shown in Figure 24 is that the first eighth transistor T1-8 is not included.

[0154] The difference between at least one embodiment of the in Fig. 30 shown control circuit and at least one embodiment of the in Fig. The control circuit shown in Figure 23 consists in the fact that T1-3 is a single-gate transistor.

[0155] As in Fig. As shown in Figure 31, the control circuit according to an embodiment of the present disclosure comprises a second control signal generation circuit 210, a second gating circuit 211, a second output control circuit 212 and a second output circuit 213; wherein the second control signal generation circuit 210 is electrically connected to the control signal output terminal NS (N) of the N-th stage and is used to generate a control signal of the N-th stage and output it via the control signal output terminal NS (N) of the N-th stage; wherein the second gating circuit 211 is electrically connected to the second first node N2-1, a gating input terminal VCT or a gating control terminal CX, and is used to control the writing of a gating input signal provided by the gating control terminal VCT to the second first node N2-1 under the control of a gating control signal provided by the gating control terminal CX; wherein a first terminal of the second output control circuit 212 is electrically connected to the control signal output terminal NS (N) of the N-th stage and a second terminal of the second output control circuit 212 is electrically connected to the second first node N2-1 and is used to perform a NAND operation on the control signal of the N-th stage and the potential of the second terminal of the second output control circuit 212 to obtain the first output signal; wherein the second output circuit 213 is electrically connected to the second output control circuit 212 or the output control terminal NO (N) and is used to invert the first output signal in order to obtain the output control signal and to provide it via the output control terminal NO (N); where N is a positive integer.

[0156] If an embodiment of the in Fig. In the control circuit shown in Figure 31 of the present disclosure, the second control signal generation circuit 210 generates a control signal of the Nth stage and outputs it via the control signal output terminal NS(N) of the Nth stage, and the second gating circuit 211 writes the gating input signal to the second first node N2-1 under control of the gating control signal; the second output control circuit 212 performs a NAND operation on the control signal of the Nth stage and the potential of the second terminal of the second output control circuit 212 to obtain the first output signal, and the second output circuit 213 inverts the first output signal to obtain the output control signal and provide it via the output control terminal NO(N).

[0157] The embodiment of the in Fig. The control circuit shown in section 31 of the present disclosure can be a control circuit of the Nth stage.

[0158] If the embodiment of the in Fig. When the control circuit shown in section 31 of the present disclosure functions, the following occurs within one frame time:

[0159] Before a phase of providing the control signal of the Nth stage, the second gating circuit 211, under the control of the gating control signal, writes the gating input signal provided by the gating input terminal VCT to the second first node N2-1; If the gating input signal is a high-voltage signal, then during the phase of providing the N-th stage's drive signal, the N-th stage's drive signal output terminal NS(N) outputs a high-voltage signal, and then the first output signal output by the second output control circuit 212 is a low-voltage signal, and the second output circuit 213 provides a high-voltage signal via the output drive terminal NO(N) that can control the corresponding line pixel circuit to update the pixel voltage; If the gating input signal is a low-voltage signal, then during the phase of providing the control signal to the N-th stage, the control signal output terminal NS(N) of the N-th stage outputs a high-voltage signal, and then the first output signal output by the second output control circuit 212 is a high-voltage signal, and the second output circuit 213 provides a low-voltage signal via the output control terminal NO(N) that can control the corresponding line pixel circuit without updating the pixel voltage.

[0160] Embodiments of the present disclosure can, by controlling the gating input signal provided by the gating input port VCT, achieve the updating of a local image on the display screen, thereby reducing power consumption, or can achieve ultra-low power consumption in OLED display products such as portable products, mobile devices, notebooks, or the like by locally updating the display image.

[0161] The control circuit according to at least one embodiment of the present disclosure may further comprise a second initialization circuit and a second first voltage maintenance circuit; wherein the second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal or the second first node and is used to control the connection between the second first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal; wherein a first terminal of the second first voltage maintenance circuit is electrically connected to the second first node, and a second terminal of the second first voltage maintenance circuit is electrically connected to a DC terminal or a second third node, and the second first voltage maintenance circuit is used to maintain the potential of the second first node.

[0162] In a specific implementation, the control circuit may further include a second initialization circuit and a second first voltage maintenance circuit; wherein the second initialization circuit, under the control of the initial control signal, controls the connection between the second first node and the first voltage terminal, and wherein a first potential maintenance circuit maintains the potential of the second first node.

[0163] As in Fig. As shown in 32, the control circuit according to at least one embodiment of the present disclosure can be based on at least one embodiment of the Fig. The control circuit shown in Figure 31 further comprises a second initialization circuit 221 and a second first voltage maintenance circuit 222; wherein the second initialization circuit 221 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 or the second first node N2-1 and is used to control the connection between the second first node N2-1 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX; wherein the first terminal of the second first voltage maintenance circuit 222 is electrically connected to the second first node N2-1, and the second terminal of the second first voltage maintenance circuit 222 is electrically connected to the first voltage terminal V1, and the second first voltage maintenance circuit 222 is used to maintain the potential of the second first node N2-1.

[0164] If at least one embodiment of the in Fig. The control circuit shown in Figure 32 works, NCX provides an effective voltage signal at the beginning of a frame time, and the second initialization circuit 221 controls the connection between the second first node N2-1 and the first voltage terminal V1.

[0165] In at least one embodiment of the present disclosure, the first voltage connection can be a high-voltage connection, but is not limited to that.

[0166] The control circuit according to at least one embodiment of the present disclosure may further comprise a second second voltage maintenance circuit, wherein the second second voltage maintenance circuit comprises a second first inverter, a second second inverter and a second maintenance control circuit; wherein the input terminal of the second first inverter is electrically connected to the second first node, the output terminal of the second first inverter is electrically connected to the second third node, the input terminal of the second second inverter is electrically connected to the second third node, and the output terminal of the second second inverter is electrically connected to the second fourth node; wherein the second first inverter is used to invert the potential of the second first node and output the inverted potential of the second first node via the output terminal of the second first inverter; wherein the second inverter is used to invert the potential of its input terminal and output the inverted potential via the output terminal of the second inverter; wherein the second maintenance control circuit is electrically connected to a maintenance control terminal, the second fourth node or the second first node, and is used to control the connection or disconnection between the second fourth node and the second first node under the control of a maintenance control signal provided by the maintenance control terminal.

[0167] In a specific implementation, the drive circuit may further comprise a second second voltage maintenance circuit, wherein the second second voltage maintenance circuit comprises a second first inverter, a second second inverter and a second maintenance control circuit, wherein the second first inverter inverts the potential of the second first node, the second second inverter inverts the potential of its input terminal, and the second maintenance control circuit, under the control of a maintenance control signal, controls the connection or disconnection between the second fourth node and the second first node; wherein the second maintenance control circuit can control the separation between the second fourth node and the second first node when the second gating circuit controls the writing of the gating input signal to the second first node in order not to affect the potential of the second first node.

[0168] If the control circuit operates according to at least one embodiment of the present disclosure, a second voltage maintenance circuit can be added.The second second voltage maintenance circuit comprises a second first inverter and a second second inverter, which can control the connection between the output terminal of the second second inverter and the high-voltage terminal when the potential of the second first node is at high voltage, so that the potential of the output terminal of the second second inverter can be higher than the potential of the second first node, and which can control the connection between the output terminal of the second second inverter and the low-voltage terminal when the potential of the second first node is at low voltage, so that the potential of the output terminal of the second second inverter can be lower than the potential of the second first node.And the second second voltage maintenance circuit includes a second maintenance control circuit which, during the output phase of the drive signal of the Nth stage, can control the connection between the output terminal of the second second inverter and the second first node, thereby increasing the absolute value of the potential of the second first node, so that the second first node can better control a transistor included in the second output control circuit, whose gate is electrically connected to the second first node.

[0169] As in Fig. As shown in 33, the control circuit according to at least one embodiment of the present disclosure can be based on at least one embodiment of the Fig. 32 The control circuit shown further comprises a second second voltage maintenance circuit, wherein the second second voltage maintenance circuit comprises a second first inverter F21, a second second inverter F22 and a second maintenance control circuit W21; wherein the maintenance control terminal comprises the control signal output terminal NS (N-1) of the N-1th stage and the first clock signal terminal GCK; wherein the input terminal of the second first inverter F21 is electrically connected to the second first node N2-1, and the output terminal of the second first inverter F21 is electrically connected to the second third node N2-3; wherein the input terminal of the second second inverter F22 is electrically connected to the second third node N2-3, and the output terminal of the second second inverter F22 is electrically connected to the second fourth node N2-4; wherein the second first inverter F21 is used to invert the potential of the second first node N2-1 and output the inverted potential of the second first node via the output terminal of the second first inverter F21; wherein the second inverter F22 is used to invert the potential of its input terminal and output the inverted potential via the output terminal of the second inverter F22; wherein the second maintenance control circuit W21 is electrically connected to the control signal output terminal NS (N-1) of the N-1 stage, the first clock signal terminal GCK, the second fourth node N2-4 or the second first node N2-1 and is used to control the connection or disconnection between the second fourth node N2-4 and the second first node N2-1 under control of the control signal of the N-1 stage provided by the control signal output terminal NS (N-1) of the N-1 stage, and to control the connection or disconnection between the second fourth node N2-4 and the second first node N2-1 under control of the first clock signal provided by the first clock signal terminal GCK.

[0170] In at least one in Fig. In the embodiment shown in 33, the control signal output terminal of the N-1th stage can be replaced by the second clock signal terminal, but is not limited to this.

[0171] In at least one embodiment of the present disclosure, the control circuit may further comprise a second voltage maintenance circuit; wherein the second first node is electrically connected to the second terminal of the second output control circuit via the second second voltage maintenance circuit; wherein the second second voltage maintenance circuit comprises a second first inverter, a second second inverter and a second maintenance control circuit; wherein the input terminal of the second first inverter is electrically connected to the second first node, the output terminal of the second first inverter is electrically connected to the second third node, the input terminal of the second second inverter is electrically connected to the second third node, and the output terminal of the second second inverter is electrically connected to the second fourth node and the second terminal of the second output control circuit; wherein the second first inverter is used to invert the potential of the second first node and output the inverted potential of the second first node via the output terminal of the second first inverter, and the second second inverter is used to invert the potential of its input terminal and output the inverted potential via the output terminal of the second second inverter; wherein the second maintenance control circuit is electrically connected to the maintenance control terminal, the second fourth node or the second first node, and is used to control the connection or disconnection between the second fourth node and the second first node under the control of the maintenance control signal provided by the maintenance control terminal.

[0172] In a specific implementation, the control circuit may further comprise a second second voltage maintenance circuit, wherein the second first node may be electrically connected to the second terminal of the second output control circuit via the second second voltage maintenance circuit, and the second second voltage maintenance circuit may comprise a second first inverter, a second second inverter, and a second maintenance control circuit; wherein the second first inverter inverts the potential of the second first node, and the second second inverter inverts the potential of its input terminal; wherein the second maintenance control circuit, under the control of the maintenance control signal provided by the maintenance control terminal, controls the connection or disconnection between the second fourth node and the second first node; where the second maintenance control circuit can control the separation between the second fourth node and the second first node when the second gating circuit controls the writing of the gating input signal to the second first node.

[0173] If the control circuit operates according to at least one embodiment of the present disclosure, a second voltage maintenance circuit can be added.The second voltage maintenance circuit comprises a second first inverter and a second second inverter, which can control the connection between the second fourth node and the high-voltage terminal when the potential of the second first node is at high voltage, so that the potential of the second fourth node can be higher than the potential of the second first node, and which can control the connection between the second fourth node and the low-voltage terminal when the potential of the second first node is at low voltage, so that the potential of the second fourth node can be lower than the potential of the second first node, so that the second fourth node can better control a transistor included in the second output control circuit, whose gate is electrically connected to the second fourth node.

[0174] As in Fig. As shown in 34, the control circuit can be based on at least one embodiment of the Fig. The control circuit shown in Figure 32 further comprises a second voltage maintenance circuit; wherein the maintenance control terminal comprises the control signal output terminal NS (N-1) of the N-1 stage and the first clock signal terminal GCK; wherein the second first node N2-1 is electrically connected to the second terminal of the second output control circuit 212 via the second second voltage maintenance circuit; wherein the second second voltage maintenance circuit comprises a second first inverter F21, a second second inverter F22 and a second maintenance control circuit W21; wherein the input terminal of the second first inverter F21 is electrically connected to the second first node N2-1, and the output terminal of the second first inverter F21 is electrically connected to the second third node N2-3; wherein the input terminal of the second second inverter F22 is electrically connected to the second third node N2-3, and the output terminal of the second second inverter F22 is electrically connected to the second fourth node N2-4 and the second terminal of the second output control circuit 12; wherein the second first inverter F21 is used to invert the potential of the second first node N2-1 and output the inverted potential of the second first node via the output terminal of the second first inverter F21; wherein the second inverter F22 is used to invert the potential of its input terminal and output the inverted potential via the output terminal of the second inverter F22; wherein the second maintenance control circuit W21 is electrically connected to the control signal output terminal NS (N-1) of the N-1 stage, the first clock signal terminal GCK, the second fourth node N2-4 or the second first node N2-1 and is used to control the connection or disconnection between the second fourth node N2-4 and the second first node N2-1 under control of the control signal of the N-1 stage provided by the control signal output terminal NS (N-1) of the N-1 stage, and to control the connection or disconnection between the second fourth node N2-4 and the second first node N2-1 under control of the first clock signal provided by the first clock signal terminal GCK.

[0175] In at least one in Fig. In the embodiment shown in 34, the control signal output terminal of the N-1th stage can be replaced by the second clock signal terminal, but is not limited to this.

[0176] Optionally, the maintenance control port includes a first maintenance control port and a second maintenance control port; The second maintenance control circuit includes a second third transistor and a second fourth transistor; wherein the gate of the second third transistor is electrically connected to the first maintenance control terminal, the first electrode of the second third transistor is electrically connected to the second first node, and the second electrode of the second third transistor is electrically connected to the second fourth node; wherein the gate of the second fourth transistor is electrically connected to the second maintenance control terminal, the first electrode of the second fourth transistor is electrically connected to the second fourth node, and the second electrode of the second fourth transistor is electrically connected to the second first node; where the second third transistor is a p-type transistor and the second fourth transistor is an n-type transistor; wherein the first maintenance control terminal is a drive signal terminal of the N-1th stage, and the second maintenance control terminal is a first clock signal terminal; or where the first maintenance control terminal is a second clock signal terminal, and the second maintenance control terminal is a first clock signal terminal.

[0177] Optionally, the second first inverter includes a second fifth transistor and a second sixth transistor, and the second second inverter includes a second seventh transistor and a second eighth transistor; wherein the gate of the second fifth transistor is electrically connected to the second first node, the first electrode of the second fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the second fifth transistor is electrically connected to the second third node; wherein the gate of the second sixth transistor is electrically connected to the second first node, the first electrode of the second sixth transistor is electrically connected to the second third node, and the second electrode of the second sixth transistor is electrically connected to the second voltage terminal; where the second fifth transistor is a p-type transistor and the second sixth transistor is an n-type transistor; wherein the gate of the second seventh transistor is electrically connected to the second third node, the first electrode of the second seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the second seventh transistor is electrically connected to the second fourth node; wherein the gate of the second eighth transistor is electrically connected to the second third node, the first electrode of the second eighth transistor is electrically connected to the second fourth node, and the second electrode of the second eighth transistor is electrically connected to the second voltage terminal; where the second seventh transistor is a p-type transistor and the second eighth transistor is an n-type transistor.

[0178] Optionally, the second initialization circuit includes a second ninth transistor and the second first voltage maintenance circuit includes a second first capacitor; wherein the gate of the second ninth transistor is electrically connected to the initial control terminal, the first electrode of the second ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the second ninth transistor is electrically connected to the second first node; wherein the first terminal of the second first capacitor is electrically connected to the second first node, and the second terminal of the second first capacitor is electrically connected to the DC terminal or the second third node.

[0179] Optionally, the second output control circuit includes a second tenth transistor, a second eleventh transistor, a second twelfth transistor, and a second thirteenth transistor; wherein the gate of the second tenth transistor is electrically connected to the drive signal output terminal of the Nth stage, the first electrode of the second tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the second tenth transistor is electrically connected to the second fifth node; wherein the gate of the second eleventh transistor is electrically connected to the second first node, the first electrode of the second eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the second eleventh transistor is electrically connected to the second fifth node; wherein the gate of the second twelfth transistor is electrically connected to the drive signal output terminal of the Nth stage, the first electrode of the second twelfth transistor is electrically connected to the second fifth node, and the second electrode of the second twelfth transistor is electrically connected to the second sixth node; wherein the gate of the second thirteenth transistor is electrically connected to the second first node, the first electrode of the second thirteenth transistor is electrically connected to the second sixth node, and the second electrode of the second thirteenth transistor is electrically connected to the second voltage terminal; where the second tenth transistor and the second eleventh transistor are p-type transistors, and the second twelfth transistor and the second thirteenth transistor are n-type transistors.

[0180] Optionally, the second output control circuit includes a second tenth transistor, a second eleventh transistor, a second twelfth transistor, and a second thirteenth transistor; wherein the gate of the second tenth transistor is electrically connected to the drive signal output terminal of the Nth stage, the first electrode of the second tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the second tenth transistor is electrically connected to the second fifth node; wherein the gate of the second eleventh transistor is electrically connected to the second fourth node, the first electrode of the second eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the second eleventh transistor is electrically connected to the second fifth node; wherein the gate of the second twelfth transistor is electrically connected to the drive signal output terminal of the Nth stage, the first electrode of the second twelfth transistor is electrically connected to the second fifth node, and the second electrode of the second twelfth transistor is electrically connected to the second sixth node; wherein the gate of the second thirteenth transistor is electrically connected to the second fourth node, the first electrode of the second thirteenth transistor is electrically connected to the second sixth node, and the second electrode of the second thirteenth transistor is electrically connected to the second voltage terminal; where the second tenth transistor and the second eleventh transistor are p-type transistors, and the second twelfth transistor and the second thirteenth transistor are n-type transistors.

[0181] Optionally, the second output circuit includes a second fourteenth transistor and a second fifteenth transistor; wherein the gate of the second fourteenth transistor is electrically connected to the second fifth node, the first electrode of the second fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the second fourteenth transistor is electrically connected to the output drive terminal; wherein the gate of the second fifteenth transistor is electrically connected to the second fifth node, the first electrode of the second fifteenth transistor is electrically connected to the output control terminal, and the second electrode of the second fifteenth transistor is electrically connected to the second voltage terminal.

[0182] In at least one embodiment of the present disclosure, the second control signal generation circuit can comprise a second first control node control circuit, a second second control node control circuit, a second first control output circuit and a second second control output circuit; wherein the second first control node control circuit is used to control the potential of the first control node; wherein the second control node control circuit is used to control the potential of the second control node; wherein the second first control output circuit is electrically connected to the first control node, the first voltage terminal or the control signal output terminal of the Nth stage and is used to control the connection between the control signal output terminal of the Nth stage and the first voltage terminal by controlling the potential of the first control node; wherein the second control output circuit is electrically connected to the second control node, the second voltage terminal or the control signal output terminal of the Nth stage and is used to control the connection between the control signal output terminal of the Nth stage and the second voltage terminal by controlling the potential of the second control node.

[0183] In a specific implementation, the second control signal generation circuit can comprise a second first control node control circuit, a second second control node control circuit, a second first control output circuit, and a second second control output circuit, wherein the second first control node control circuit is used to control the potential of the first control node; wherein the second second control node control circuit is used to control the potential of the second control node; wherein, under the control of the potential of the first control node, the second first control output circuit controls the connection between the control signal output terminal of the Nth stage and the first voltage terminal; and wherein, under the control of the potential of the second control node, the second second control output circuit controls the connection between the control signal output terminal of the Nth stage and the second voltage terminal.

[0184] Optionally, the first voltage connection can be a high-voltage connection and the second voltage connection can be a low-voltage connection, but is not limited to this.

[0185] As in Fig. As shown in Figure 35, the second control signal generation circuit can be based on at least one embodiment of the one shown in Figure 35. Fig. The control circuit shown in Figure 33 comprises a second first control node control circuit 231, a second second control node control circuit 232, a second first control output circuit 233 and a second second control output circuit 234; wherein the second first control node control circuit 231 is electrically connected to the first control node NC2-1 and is used to control the potential of the first control node NC2-1; wherein the second control node control circuit 232 is electrically connected to the second control node NC2-2 and is used to control the potential of the second control node NC2-2; wherein the second first control output circuit 233 is electrically connected to the first control node NC2-1, the first voltage terminal V1 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the first voltage terminal V12 under control of the potential of the first control node NC2-1; wherein the second control output circuit 234 is electrically connected to the second control node NC2-2, the second voltage terminal V2 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the second voltage terminal V2 under control of the potential of the second control node NC2-2.

[0186] As in Fig. As shown in Figure 36, the second control signal generation circuit can be based on at least one embodiment of the one shown in Figure 36. Fig. The control circuit shown in Figure 34 comprises a second first control node control circuit 231, a second second control node control circuit 232, a second first control output circuit 233 and a second second control output circuit 234; wherein the second first control node control circuit 231 is electrically connected to the first control node NC2-1 and is used to control the potential of the first control node NC2-1; wherein the second control node control circuit 232 is electrically connected to the second control node NC2-2 and is used to control the potential of the second control node NC2-2; wherein the second first control output circuit 233 is electrically connected to the first control node NC2-1, the first voltage terminal V1 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the first voltage terminal V12 under control of the potential of the first control node NC2-1; wherein the second control output circuit 234 is electrically connected to the second control node NC2-2, the second voltage terminal V2 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the second voltage terminal V2 under control of the potential of the second control node NC2-2.

[0187] In at least one embodiment of the present disclosure, the second first control node control circuit comprises a second seventh node control circuit, a second eighth node control circuit and a second first control circuit; wherein the second seventh node control circuit is electrically connected to the first clock signal terminal, the first voltage terminal, the second seventh node and the second ninth node respectively, and is used to control the connection between the second seventh node and the first voltage terminal under control of the first clock signal provided by the first clock signal terminal, and to control the connection between the second seventh node and the first clock signal terminal under control of the potential of the second ninth node; wherein the second eighth node control circuit is electrically connected to the second voltage terminal, the second seventh node or the second eighth node and is used to control the connection between the second seventh node and the second eighth node under the control of the second voltage signal provided by the second voltage terminal; wherein the second first control circuit is electrically connected to the second eighth node, the second second node, the second clock signal terminal, the second ninth node, the first voltage terminal, and the first control node, respectively, and is used to control the connection between the second second node and the second clock signal terminal under the control of the potential of the second eighth node, to control the potential of the second second node according to the potential of the second eighth node, to control the connection between the second second node and the first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the first control node and the first voltage terminal under the control of the potential of the second ninth node.

[0188] In a specific implementation, the second first control node control circuit may include a second seventh node control circuit, a second eighth node control circuit, and a second first control circuit, wherein the second seventh node control circuit controls the potential of the second seventh node, the second eighth node control circuit controls the potential of the second eighth node, and the second first control circuit controls the potential of the first control node.

[0189] In at least one embodiment of the present disclosure, the second second control node control circuit comprises a second ninth node control circuit, a second tenth node control circuit, a second eleventh node control circuit and a second second control circuit; wherein the second ninth node control circuit is electrically connected to the first clock signal terminal, the control signal output terminal of the N-1th stage, the initial control terminal, the first voltage terminal, and the second ninth node respectively, and is used to control, under control of the first clock signal provided by the first clock signal terminal, the connection between the control signal output terminal of the N-1th stage and the second ninth node, and, under control of the initial control signal provided by the initial control terminal, to control the connection between the second ninth node and the first voltage terminal; wherein the second tenth node control circuit is electrically connected to the first clock signal terminal, the control signal output terminal of the N-1th stage or the second tenth node, and is used to control the connection between the control signal output terminal of the N-1th stage and the second tenth node under the control of the first clock signal; wherein the second eleventh node control circuit is electrically connected to the second voltage terminal, the second tenth node, the second eleventh node, the second seventh node, the first voltage terminal, the second twelfth node and the second clock signal terminal respectively, and is used to control the connection between the second tenth node and the second eleventh node under the control of the second voltage signal provided by the second voltage terminal, and to control the electrical connection between the second twelfth node and the first voltage terminal under the control of the potential of the second seventh node, and to control the connection between the second twelfth node and the second clock signal terminal under the control of the potential of the second eleventh node, and to control the potential of the second eleventh node according to the potential of the second twelfth node; wherein the second control circuit is electrically connected to the second control node, the second eleventh node, the second voltage terminal or the second ninth node and is used to control the potential of the second control node under the control of the potential of the second eleventh node, and to control the connection between the second ninth node and the second control node under the control of the second voltage signal provided by the second voltage terminal.

[0190] In a specific implementation, the second second control node control circuit may comprise a second ninth node control circuit, a second tenth node control circuit, a second eleventh node control circuit, and a second second control circuit, wherein the second ninth node control circuit controls the potential of the second ninth node, the second tenth node control circuit controls the potential of the second tenth node, the second eleventh node control circuit controls the potential of the second eleventh node, and the second second control circuit controls the potential of the second control node.

[0191] As in Fig. As shown in 37, the second first control node control circuit comprises at least one embodiment of the one shown in Fig. 35 control circuit shown a second seventh node control circuit 241, a second eighth node control circuit 242 and a second first control circuit 243; wherein the second seventh node control circuit 241 is electrically connected to the first clock signal terminal GCK, the second voltage terminal V2, the second seventh node N2-7 and the second ninth node N2-9 respectively, and is used to control the connection between the second seventh node N2-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the second seventh node N2-7 and the first clock signal terminal GCK under the control of the potential of the second ninth node N2-9; wherein the second eighth node control circuit 242 is electrically connected to the second voltage terminal V2, the second seventh node N2-7 or the second eighth node N2-8 and is used to control the connection between the second seventh node N2-7 and the second eighth node N2-8 under the control of the second voltage signal provided by the second voltage terminal V2; wherein the second first control circuit 243 is electrically connected to the second eighth node N2-8, the second second node N2-2, the second clock signal terminal GCB, the second ninth node N2-9, the first voltage terminal V1 and the first control node NC2-1 respectively, and is used to control the connection between the second second node N2-2 and the second clock signal terminal GCB by controlling the potential of the second eighth node N2-8, to control the potential of the second second node N2-2 according to the potential of the second eighth node N2-8, to control the connection between the second second node N2-2 and the first control node NC2-1 by controlling the second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first control node NC2-1 and the first voltage terminal V1 by controlling the potential of the second ninth node N2-9; The second second control node control circuit comprises a second ninth node control circuit 251, a second tenth node control circuit 252, a second eleventh node control circuit 253 and a second second control circuit 254; wherein the second ninth node control circuit 251 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage, the initial control terminal NCX, the first voltage terminal V1 or the second ninth node N2-9 and is used to control, under control of the first clock signal provided by the first clock signal terminal GCK, the connection between the control signal output terminal NS (N-1) of the N-1th stage and the second ninth node N2-9, and, under control of the initial control signal provided by the initial control terminal NCX, to control the connection between the second ninth node N2-9 and the first voltage terminal V1; wherein the second tenth node control circuit 252 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage or the second tenth node N2-10 and is used to control the connection between the control signal output terminal NS (N-1) of the N-1th stage and the second tenth node N2-10 under the control of the first clock signal; wherein the second eleventh node control circuit 253 is electrically connected to the second voltage connection V2, the second tenth node N2-10, the second eleventh node N2-11, the second seventh node N2-7, the first voltage connection V1, the second twelfth node N2-12 respectively.is connected to the second clock signal terminal GCB and is used to control, under the control of the second voltage signal provided by the second voltage terminal V2, the connection between the second tenth node N2-10 and the second eleventh node N2-11, and, under the control of the potential of the second seventh node N2-7, to control the electrical connection between the second twelfth node N2-12 and the first voltage terminal V1, under the control of the potential of the second eleventh node N2-11, to control the connection between the second twelfth node N2-12 and the second clock signal terminal GCB, and, according to the potential of the second twelfth node N2-12, to control the potential of the second eleventh node N2-11; wherein the second control circuit 254 is electrically connected to the second control node NC2-2, the second eleventh node N2-11, the second voltage terminal V2 or the second ninth node N2-9 and is used to control the potential of the second control node NC2-2 by controlling the potential of the second eleventh node N2-11, and to control the connection between the second ninth node N2-9 and the second control node NC2-2 by controlling the second voltage signal provided by the second voltage terminal V2.

[0192] As in Fig. As shown in 38, the second first control node control circuit comprises at least one embodiment of the one shown in Fig. 36 control circuit shown a second seventh node control circuit 241, a second eighth node control circuit 242 and a second first control circuit 243; wherein the second seventh node control circuit 241 is electrically connected to the first clock signal terminal GCK, the second voltage terminal V2, the second seventh node N2-7 and the second ninth node N2-9 respectively, and is used to control the connection between the second seventh node N2-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the second seventh node N2-7 and the first clock signal terminal GCK under the control of the potential of the second ninth node N2-9; wherein the second eighth node control circuit 242 is electrically connected to the second voltage terminal V2, the second seventh node N2-7 or the second eighth node N2-8 and is used to control the connection between the second seventh node N2-7 and the second eighth node N2-8 under the control of the second voltage signal provided by the second voltage terminal V2; wherein the second first control circuit 243 is electrically connected to the second eighth node N2-8, the second second node N2-2, the second clock signal terminal GCB, the second ninth node N2-9, the first voltage terminal V1 and the first control node NC2-1 respectively, and is used to control the connection between the second second node N2-2 and the second clock signal terminal GCB by controlling the potential of the second eighth node N2-8, to control the potential of the second second node N2-2 according to the potential of the second eighth node N2-8, to control the connection between the second second node N2-2 and the first control node NC2-1 by controlling the second clock signal provided by the second clock signal terminal GCB, and to control the connection between the first control node NC2-1 and the first voltage terminal V1 by controlling the potential of the second ninth node N2-9; The second second control node control circuit comprises a second ninth node control circuit 251, a second tenth node control circuit 252, a second eleventh node control circuit 253 and a second second control circuit 254; wherein the second ninth node control circuit 251 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage, the initial control terminal NCX, the first voltage terminal V1 or the second ninth node N2-9 and is used to control, under control of the first clock signal provided by the first clock signal terminal GCK, the connection between the control signal output terminal NS (N-1) of the N-1th stage and the second ninth node N2-9, and, under control of the initial control signal provided by the initial control terminal NCX, to control the connection between the second ninth node N2-9 and the first voltage terminal V1; wherein the second tenth node control circuit 252 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage or the second tenth node N2-10 and is used to control the connection between the control signal output terminal NS (N-1) of the N-1th stage and the second tenth node N2-10 under the control of the first clock signal; wherein the second eleventh node control circuit 253 is electrically connected to the second voltage connection V2, the second tenth node N2-10, the second eleventh node N2-11, the second seventh node N2-7, the first voltage connection V1, the second twelfth node N2-12 respectively.is connected to the second clock signal terminal GCB and is used to control, under the control of the second voltage signal provided by the second voltage terminal V2, the connection between the second tenth node N2-10 and the second eleventh node N2-11, and, under the control of the potential of the second seventh node N2-7, to control the electrical connection between the second twelfth node N2-12 and the first voltage terminal V1, under the control of the potential of the second eleventh node N2-11, to control the connection between the second twelfth node N2-12 and the second clock signal terminal GCB, and, according to the potential of the second twelfth node N2-12, to control the potential of the second eleventh node N2-11; wherein the second control circuit 254 is electrically connected to the second control node NC2-2, the second eleventh node N2-11, the second voltage terminal V2 or the second ninth node N2-9 and is used to control the potential of the second control node NC2-2 by controlling the potential of the second eleventh node N2-11, and to control the connection between the second ninth node N2-9 and the second control node NC2-2 by controlling the second voltage signal provided by the second voltage terminal V2.

[0193] Optionally, the second first drive output circuit includes a second sixteenth transistor and a second second capacitor; wherein the gate of the second sixteenth transistor is electrically connected to the first control node, the first electrode of the second sixteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the second sixteenth transistor is electrically connected to the control signal output terminal of the Nth stage; wherein the first terminal of the second second capacitor is electrically connected to the first control node, and the second terminal of the second second capacitor is electrically connected to the first voltage terminal; The second second control output circuit comprises a second seventeenth transistor and a second third capacitor; wherein the gate of the second seventeenth transistor is electrically connected to the second control node, the first electrode of the second seventeenth transistor is electrically connected to the drive signal output terminal of the Nth stage, and the second electrode of the second seventeenth transistor is electrically connected to the second voltage terminal; wherein the first terminal of the second third capacitor is electrically connected to the control signal output terminal of the Nth stage, and the second terminal of the second third capacitor is electrically connected to the second voltage terminal.

[0194] Optionally, the second seventh node control circuit includes a second eighteenth transistor and a second nineteenth transistor; wherein the gate of the second eighteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the second eighteenth transistor is electrically connected to the second voltage terminal, and the second electrode of the second eighteenth transistor is electrically connected to the second seventh node; wherein the gate of the second nineteenth transistor is electrically connected to the second ninth node, the first electrode of the second nineteenth transistor is electrically connected to the second seventh node, and the second electrode of the second nineteenth transistor is electrically connected to the first clock signal terminal; The second eighth node control circuit includes a second twentieth transistor; wherein the gate of the second twentieth transistor is electrically connected to the second voltage terminal, the first electrode of the second twentieth transistor is electrically connected to the second seventh node, and the second electrode of the second twentieth transistor is electrically connected to the second eighth node; The second first control circuit comprises a second twenty-first transistor, a second fourth capacitor, a second twenty-second transistor, and a second twenty-third transistor; wherein the gate of the second twenty-first transistor is electrically connected to the second eighth node, the first electrode of the second twenty-first transistor is electrically connected to the second clock signal terminal, and the second electrode of the second twenty-first transistor is electrically connected to the second second node; wherein the first terminal of the second fourth capacitor is electrically connected to the second eighth node, and the second terminal of the second fourth capacitor is electrically connected to the second second node; wherein the gate of the second twenty-second transistor is electrically connected to the second clock signal terminal, the first electrode of the second twenty-second transistor is electrically connected to the second second node, and the second electrode of the second twenty-second transistor is electrically connected to the first control node; wherein the gate of the second twenty-third transistor is electrically connected to the second ninth node, the first electrode of the second twenty-third transistor is electrically connected to the first control node, and the second electrode of the second twenty-third transistor is electrically connected to the first voltage terminal.

[0195] Optionally, the second ninth node control circuit includes a second twenty-fourth transistor and a second twenty-fifth transistor; wherein the gate of the second twenty-fourth transistor is electrically connected to the first clock signal terminal, the first electrode of the second twenty-fourth transistor is electrically connected to the drive signal output terminal of the N-1th stage, and the second electrode of the second twenty-fourth transistor is electrically connected to the second ninth node; wherein the gate of the second twenty-fifth transistor is electrically connected to the initial control terminal, the first electrode of the second twenty-fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the second twenty-fifth transistor is electrically connected to the second ninth node; The second tenth node control circuit includes a second twenty-sixth transistor; wherein the gate of the second twenty-sixth transistor is electrically connected to the first clock signal terminal, the first electrode of the second twenty-sixth transistor is electrically connected to the drive signal output terminal of the N-1th stage, and the second electrode of the second twenty-sixth transistor is electrically connected to the second tenth node; The second eleventh node control circuit comprises a second twenty-seventh transistor, a second twenty-eighth transistor, a second twenty-ninth transistor, and a second fifth capacitor; wherein the gate of the second twenty-seventh transistor is electrically connected to the second voltage terminal, the first electrode of the second twenty-seventh transistor is electrically connected to the second tenth node, and the second electrode of the second twenty-seventh transistor is electrically connected to the second eleventh node; wherein the gate of the second twenty-eighth transistor is electrically connected to the second seventh node, the first electrode of the second twenty-eighth transistor is electrically connected to the first voltage terminal, and the second electrode of the second twenty-eighth transistor is electrically connected to the second twelfth node; wherein the gate of the second twenty-ninth transistor is electrically connected to the second eleventh node, the first electrode of the second twenty-ninth transistor is electrically connected to the second twelfth node, and the second electrode of the second twenty-ninth transistor is electrically connected to the second clock signal terminal; wherein the first terminal of the second fifth capacitor is electrically connected to the second twelfth node, and the second terminal of the second fifth capacitor is electrically connected to the second eleventh node; The second control circuit comprises a second thirtieth transistor and a second thirtieth transistor; wherein the gate of the second thirtieth transistor and the first electrode of the second thirtieth transistor are each electrically connected to the second eleventh node, and the second electrode of the second thirtieth transistor is electrically connected to the second control node; wherein the gate of the second thirty-first transistor is electrically connected to the second voltage terminal, the first electrode of the second thirty-first transistor is electrically connected to the second ninth node, and the second electrode of the second thirty-first transistor is electrically connected to the second control node.

[0196] As in Fig. As shown in 39, the second gating circuit is based on at least one embodiment of the one shown in Fig. The control circuit shown in 37 includes a second first transistor T2-1 and a second second transistor T2-2; wherein the gate of the second first transistor T2-1 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, the source of the second first transistor T2-1 is electrically connected to the second first node N2-1, and the drain of the second first transistor T2-1 is electrically connected to the drain of the second second transistor T2-2; wherein the gate of the second second transistor T2-2 is electrically connected to the drive signal output terminal NS (N) of the N-th stage, and the source of the second second transistor T2-2 is electrically connected to the gating input terminal VCT; The second maintenance control circuit includes a second third transistor T2-3 and a second fourth transistor T2-4; wherein the gate of the second third transistor T2-3 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, the source of the second third transistor T2-3 is electrically connected to the second first node N2-1, and the drain of the second third transistor T2-3 is electrically connected to the second fourth node N2-4; wherein the gate of the second fourth transistor T2-4 is electrically connected to the first clock signal terminal GCK, the source of the second fourth transistor T2-4 is electrically connected to the second fourth node N2-4, and the drain of the second fourth transistor T2-4 is electrically connected to the second first node N2-1; The second first inverter includes a second fifth transistor T2-5 and a second sixth transistor T2-6, and the second second inverter includes a second seventh transistor T2-7 and a second eighth transistor T2-8; wherein the gate of the second fifth transistor T2-5 is electrically connected to the second first node N2-1, the source of the second fifth transistor T2-5 is electrically connected to the high voltage terminal VGH, and the drain of the second fifth transistor T2-5 is electrically connected to the second third node N2-3; wherein the gate of the second sixth transistor T2-6 is electrically connected to the second first node N2-1, the source of the second sixth transistor T2-6 is electrically connected to the second third node N2-3, and the drain of the second sixth transistor T2-6 is electrically connected to the low voltage terminal VGL; wherein the gate of the second seventh transistor T2-7 is electrically connected to the second third node N2-3, the source of the second seventh transistor T2-7 is electrically connected to the high voltage terminal VGH, and the drain of the second seventh transistor T2-7 is electrically connected to the second fourth node N2-4; wherein the gate of the second eighth transistor T2-8 is electrically connected to the second third node N2-3, the source of the second eighth transistor T2-8 is electrically connected to the second fourth node N2-4, and the drain of the second eighth transistor T2-8 is electrically connected to the low voltage terminal VGL; The second initialization circuit includes a second ninth transistor T2-9, and the second first voltage maintenance circuit includes a second first capacitor C2-1; wherein the gate of the second ninth transistor T2-9 is electrically connected to the initial control terminal NCX, the source of the second ninth transistor T2-9 is electrically connected to the high voltage terminal VGH, and the drain of the second ninth transistor T2-9 is electrically connected to the second first node N2-1; wherein the first terminal of the second first capacitor C2-1 is electrically connected to the second first node N2-1, and the second terminal of the second first capacitor C2-1 is electrically connected to the low voltage terminal VGL; The second output control circuit includes a second tenth transistor T2-10, a second eleventh transistor T2-11, a second twelfth transistor T2-12 and a second thirteenth transistor T2-13; wherein the gate of the second tenth transistor T2-10 is electrically connected to the drive signal output terminal NS (N) of the N-th stage, the source of the second tenth transistor T2-10 is electrically connected to the high voltage terminal VGH, and the drain of the second tenth transistor T2-10 is electrically connected to the second fifth node N2-5;

[0197] wherein the gate of the second eleventh transistor T2-11 is electrically connected to the second first node N2-1, the source of the second eleventh transistor T2-11 is electrically connected to the high voltage terminal VGH, and the drain of the second eleventh transistor T2-11 is electrically connected to the second fifth node N2-5; wherein the gate of the second twelfth transistor T2-12 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, the source of the second twelfth transistor T2-12 is electrically connected to the second fifth node N2-5, and the drain of the second twelfth transistor T2-12 is electrically connected to the second sixth node N2-6; wherein the gate of the second thirteenth transistor T2-13 is electrically connected to the second first node N2-1, the source of the second thirteenth transistor T2-13 is electrically connected to the second sixth node N2-6, and the drain of the second thirteenth transistor T2-13 is electrically connected to the low voltage terminal VGL; The second output circuit includes a second fourteenth transistor T2-14 and a second fifteenth transistor T2-15; wherein the gate of the second fourteenth transistor T2-14 is electrically connected to the second fifth node N2-5, the source of the second fourteenth transistor T2-14 is electrically connected to the high voltage terminal VGH, and the drain of the second fourteenth transistor T2-14 is electrically connected to the output control terminal NO (N); wherein the gate of the second fifteenth transistor T2-15 is electrically connected to the second fifth node N2-5, the source of the second fifteenth transistor T2-15 is electrically connected to the output drive terminal NO (N), and the drain of the second fifteenth transistor T2-15 is electrically connected to the low voltage terminal VGL; The second first control output circuit includes a second sixteenth transistor T2-16 and a second second capacitor C2-2; wherein the gate of the second sixteenth transistor T2-16 is electrically connected to the first control node NC2-1, the source of the second sixteenth transistor T2-16 is electrically connected to the high voltage terminal VGH, and the drain of the second sixteenth transistor T2-16 is electrically connected to the control signal output terminal NS (N) of the N-th stage; wherein the first terminal of the second second capacitor C2-2 is electrically connected to the first control node NC2-1, and the second terminal of the second second capacitor C2-2 is electrically connected to the high voltage terminal VGH; The second second control output circuit includes a second seventeenth transistor T2-17 and a second third capacitor C2-3; wherein the gate of the second seventeenth transistor T2-17 is electrically connected to the second control node NC2-2, the source of the second seventeenth transistor T2-17 is electrically connected to the drive signal output terminal NS (N) of the Nth stage, and the drain of the second seventeenth transistor T2-17 is electrically connected to the low voltage terminal VGL; wherein the first terminal of the second third capacitor C2-3 is electrically connected to the control signal output terminal NS (N) of the Nth stage, and the second terminal of the second third capacitor C2-3 is electrically connected to the low voltage terminal VGL; The second seventh node control circuit comprises a second eighteenth transistor T2-18 and a second nineteenth transistor T2-19; wherein the gate of the second eighteenth transistor T2-18 is electrically connected to the first clock signal terminal GCK, the source of the second eighteenth transistor T2-18 is electrically connected to the low voltage terminal VGL, and the drain of the second eighteenth transistor T2-18 is electrically connected to the second seventh node N2-7; wherein the gate of the second nineteenth transistor T2-19 is electrically connected to the second ninth node N2-9, the source of the second nineteenth transistor T2-19 is electrically connected to the second seventh node N2-7, and the drain of the second nineteenth transistor T2-19 is electrically connected to the first clock signal terminal GCK; The second eighth node control circuit includes a second twentieth transistor T2-20; wherein the gate of the second twentieth transistor T2-20 is electrically connected to the low voltage terminal VGL, the source of the second twentieth transistor T2-20 is electrically connected to the second seventh node N2-7, and the drain of the second twentieth transistor T2-20 is electrically connected to the second eighth node N2-8; The second first control circuit includes a second twenty-first transistor T2-21, a second fourth capacitor C2-4, a second twenty-second transistor T2-22 and a second twenty-third transistor T2-23; wherein the gate of the second twenty-first transistor T2-21 is electrically connected to the second eighth node N2-8, the source of the second twenty-first transistor T2-21 is electrically connected to the second clock signal terminal GCB, and the drain of the second twenty-first transistor T2-21 is electrically connected to the second second node N2-2; wherein the first terminal of the second fourth capacitor C2-4 is electrically connected to the second eighth node N2-8, and the second terminal of the second fourth capacitor C2-4 is electrically connected to the second second node N2-2; wherein the gate of the second twenty-second transistor T2-22 is electrically connected to the second clock signal terminal GCB, the source of the second twenty-second transistor T2-22 is electrically connected to the second second node N2-2, and the drain of the second twenty-second transistor T2-22 is electrically connected to the first control node NC2-1; wherein the gate of the second twenty-third transistor T2-23 is electrically connected to the second ninth node N2-9, the source of the second twenty-third transistor T2-23 is electrically connected to the first control node NC2-1, and the drain of the second twenty-third transistor T2-23 is electrically connected to the high voltage terminal VGH; The second ninth node control circuit comprises a second twenty-fourth transistor T2-24 and a second twenty-fifth transistor T2-25; wherein the gate of the second twenty-fourth transistor T2-24 is electrically connected to the first clock signal terminal GCK, the source of the second twenty-fourth transistor T2-24 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, and the drain of the second twenty-fourth transistor T2-24 is electrically connected to the second ninth node N2-9; wherein the gate of the second twenty-fifth transistor T2-25 is electrically connected to the initial control terminal NCX, the source of the second twenty-fifth transistor T2-25 is electrically connected to the high voltage terminal VGH, and the drain of the second twenty-fifth transistor T2-25 is electrically connected to the second ninth node N2-9; The second tenth node control circuit includes a second twenty-sixth transistor T2-26; wherein the gate of the second twenty-sixth transistor T2-26 is electrically connected to the first clock signal terminal GCK, the source of the second twenty-sixth transistor T2-26 is electrically connected to the drive signal output terminal NS (N-1) of the N-1th stage, and the drain of the second twenty-sixth transistor T2-26 is electrically connected to the second tenth node N2-10; The second eleventh node control circuit comprises a second twenty-seventh transistor T2-27, a second twenty-eighth transistor T2-28, a second twenty-ninth transistor T2-29 and a second fifth capacitor C2-5; wherein the gate of the second twenty-seventh transistor T2-27 is electrically connected to the low-voltage terminal VGL, the source of the second twenty-seventh transistor T2-27 is electrically connected to the second tenth node N2-10, and the drain of the second twenty-seventh transistor T2-27 is electrically connected to the second eleventh node N2-11; wherein the gate of the second twenty-eighth transistor T2-28 is electrically connected to the second seventh node N2-7, the source of the second twenty-eighth transistor T2-28 is electrically connected to the high-voltage terminal VGH, and the drain of the second twenty-eighth transistor T2-28 is electrically connected to the second twelfth node N2-12; wherein the gate of the second twenty-ninth transistor T2-29 is electrically connected to the second eleventh node N2-11, the source of the second twenty-ninth transistor T2-29 is electrically connected to the second twelfth node N2-12, and the drain of the second twenty-ninth transistor T2-29 is electrically connected to the second clock signal terminal GCB; wherein the first terminal of the second fifth capacitor C2-5 is electrically connected to the second twelfth node N2-12, and the second terminal of the second fifth capacitor C2-5 is electrically connected to the second eleventh node N2-11; The second control circuit comprises a second thirtieth transistor and a second thirtieth transistor; wherein the gate of the second thirtieth transistor T2-30 and the source of the second thirtieth transistor T2-31 are each electrically connected to the second eleventh node N2-11, and the drain of the second thirtieth transistor T2-31 is electrically connected to the second control node NC2-2; wherein the gate of the second thirty-first transistor T2-31 is electrically connected to the low voltage terminal VGL, the source of the second thirty-first transistor T2-31 is electrically connected to the second ninth node N2-9, and the drain of the second thirty-first transistor T2-31 is electrically connected to the second control node NC2-2.

[0198] In Fig. 39 represents the symbol N2-13 as a second thirteenth node.

[0199] In at least one embodiment of the Fig. In the control circuit shown in Figure 39, T2-1 is an n-type transistor, T2-2 is a p-type transistor, T2-3 is a p-type transistor, T2-4 is an n-type transistor, T2-5 is a p-type transistor, T2-6 is an n-type transistor, T2-7 is a p-type transistor, T2-8 is an n-type transistor, T2-9 is a p-type transistor, T2-10 and T2-11 are n-type transistors, T2-12 and T2-13 are n-type transistors, T2-14 is a p-type transistor, T2-15 is an n-type transistor, and T2-16 to T2-31 are p-type transistors.

[0200] In at least one embodiment of the present disclosure, the structure of the second control signal generation circuit is not based on the one described in Fig. The second control signal generation circuit shown in Figure 39 is limited. It can be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, or the like, but is not limited to these.

[0201] If at least one embodiment of the in Fig. If the control circuit shown in section 39 of the present disclosure functions as follows: In the first phase, NS (N-1) outputs a low-voltage signal, GCK outputs a low-voltage signal, when GCB provides a high-voltage signal, T2-24 and T2-26 are switched on, the potential of N2-9 and the potential of N2-10 are at low voltage, T2-27 and T2-31 are switched on to ensure that the potential of NC2-2 and the potential of N2-11 are at low voltage, T2-17 is switched on, NS (N) outputs a low-voltage signal; The potential of N2-11 is at low voltage to ensure that T2-29 is switched on, the potential of N2-9 is at low voltage to switch on T2-19, T2-18 is switched on to lower the potential of N2-7 and the potential of N2-8, and to switch on T2-21, GCB writes the high voltage signal to N2-2, the potential of N2-9 is at low voltage to switch on T2-23, to raise the potential of N2-1 to high voltage, and to ensure that T2-16 is switched off;In the second phase, NS (N-1) outputs a low-voltage signal, the potential of the first clock signal output by GCK jumps from low voltage to high voltage, T2-24 and T2-26 are switched off, the potential of N2-9 is at low voltage, T2-19 is switched on, T2-18 is switched off, T2-20 is switched on, the potential of N2-7 and the potential of N2-8 are at high voltage, T2-21 is switched off, the potential of N2-2 is held at high voltage, GCB outputs a low-voltage signal, T2-22 is switched on, the potential of NC2-1 is held at high voltage, T2-16 is switched off;Simultaneously, the potential of N2-11 is held at low voltage, T2-29 is switched on, GCB writes the low-voltage signal to N2-12, via C2-5 the potential of N2-11 is reduced to a lower voltage (5V to 10V lower than the voltage value of the low-voltage signal provided by GCB), T2-30 is switched on, the low-voltage signal is written to NC2-2 (the potential of NC2-2 is 3 to 8V lower than the voltage value of the low-voltage signal provided by GCB), T2-17 is fully switched on to ensure that NS (N) outputs a low-voltage signal; In the third phase, NS (N-1) outputs a high-voltage signal, GCK outputs a low-voltage signal, GCB outputs a high-voltage signal, T2-24 and T2-26 are switched on, the potential of N2-9 and the potential of N2-10 are controlled to high voltage, T2-27 and T2-31 are switched on, the potential of NC2-2 and the potential of N2-11 are at high voltage, T2-17 is switched off; The potential of N2-11 is at high voltage, T2-29 is switched off, the potential of N2-9 is at high voltage, T2-19 is switched off, T2-18 is switched on, T2-20 is switched on, the potential of N2-7 and the potential of N2-8 are lowered to switch on T2-21, GCB writes the high-voltage signal to N2-2, T2-22 is switched off, the potential of N2-9 is at high voltage to switch off T2-23, the potential of NC2-1 is held at high voltage to ensure that T2-16 is switched off; In the fourth phase, NS (N-1) outputs a high-voltage signal; the potential of the first clock signal output by GCK jumps from low voltage to high voltage; GCB outputs a low-voltage signal to switch off T2-24 and T2-26; the potential of N2-9 is high voltage to switch off T2-19; ​​T2-18 is switched off; T2-20 is switched on; the potential of N2-7 and the potential of N2-8 are kept at low voltage; T2-21 is switched on; T2-22 is switched on; the potential of N2-2 and the potential of NC2-1 are at low voltage; T2-16 is switched on; NS (N) outputs a high-voltage signal; simultaneously, the potential of N2-11 is at high voltage to switch off T2-29; the potential of N2-12 remains unchanged to ensure that the potential of N2-11 is at high voltage. In the fifth phase, the potential of the control signal of the N-1 stage output by NS (N-1) jumps from high voltage to low voltage, GCK outputs a high voltage signal, GCB outputs a low voltage signal, T2-24 and T2-26 are switched to blocking, the potential of N2-9 and the potential of N2-10 are held at high voltage, and the potential of other nodes remains unchanged to ensure that NS (N) outputs a high voltage signal; In the sixth phase, NS (N-1) outputs a low-voltage signal, the potential of the first clock signal output by GCK jumps from high voltage to low voltage, GCB outputs a high-voltage signal, T2-24 and T2-26 are switched on, the potential of N2-9 and the potential of N2-10 are at low voltage, T2-27 and T2-31 are switched on to ensure that the potential of NC2-2 and the potential of N2-11 are at low voltage in order to switch on T2-17, NS (N) outputs a low-voltage signal;The potential of N2-11 is at low voltage to ensure that T2-29 is switched on, the potential of N2-9 is at low voltage to switch on T2-19, T2-18 is switched on, T2-20 is switched on, the potential of N2-7 and the potential of N2-8 are lowered to switch on T2-21, GCB writes the high voltage signal to N2-2, the potential of N2-9 is at low voltage to switch on T2-23, the potential of N2-1 is raised to high voltage to ensure that T2-16 is switched off. Optionally, during the start-up phase (i.e., when the display device is switched on), NCX outputs a low-voltage signal before the first phase, and T2-9 is switched on to control the potential of N2-1 to high voltage, T2-25 is switched on, the potential of N2-9 is high voltage, T2-19 is switched off when GCK provides a low-voltage signal, the potential of N2-7 is low voltage, T2-20 is switched on, the potential of N2-8 is low voltage, T2-21 is switched on to control the connection between N2-2 and GCB; when GCB provides a low-voltage signal, T2-22 is switched on, the potential of NC2-1 is low voltage, T2-16 is switched on, NS(N) outputs a high-voltage signal;T2-12 is switched on, T2-13 is switched on, the potential of N2-5 is at low voltage, T2-14 is switched on, NO (N) outputs a high voltage signal, which allows a second display control transistor M2, which is included in all pixel circuits in the effective display area, to be switched on in order to clear the residual charge in the storage capacitor Cst and to eliminate the problem of screen flickering at startup; If subsequently NS (N-1) outputs a high-voltage signal and NS (N) outputs a low-voltage signal, T2-1 and T2-2 are switched on. When VCT provides a low-voltage signal, the potential of N2-1 is at the low-voltage signal, and C2-1 maintains the potential of N2-1; T2-11 is switched on, T2-10 is switched on, the potential of N2-5 is at high voltage, T2-15 is switched on, and NO (N) outputs a low-voltage signal; When VCT provides a high-voltage signal, the potential of N2-1 is at high voltage, C2-1 maintains the potential of N2-1, T2-11 is switched off, T2-10 is switched on, the potential of N2-5 is at high voltage, T2-15 is switched on, and NO (N) outputs a low-voltage signal; Subsequently, NS (N) outputs a high-voltage signal during the phase of providing the control signal for the N-th stage, When the potential of N2-1 is at low voltage, T2-10 is switched off, T2-11 is switched on; when the potential of N2-5 is at high voltage, T2-15 is switched on, and NO (N) outputs a low voltage signal; When the potential of N2-1 is high voltage, T2-10 is switched off, T2-11 is switched off, T2-12 and T2-13 are switched on, the potential of N2-5 is low voltage, T2-14 is switched on, and NO (N) outputs a high voltage signal; After the phase of providing the control signal for the Nth stage, NS (N) outputs a low-voltage signal. When the potential of N2-1 is at low voltage, T2-10 is switched on, T2-11 is switched on, the potential of N2-5 is at high voltage, and NO (N) outputs a low voltage signal; When the potential of N2-1 is at high voltage, T2-10 is switched to conducting, T2-11 is switched to blocking, the potential of N2-5 is at high voltage, and NO (N) outputs a low voltage signal.

[0202] If at least one embodiment of the in Fig. In the control circuit shown in Figure 39 of the present disclosure, when NS (N-1) outputs a high-voltage signal and NS (N) outputs a low-voltage signal, T2-1 and T2-2 are switched on, whereby a gating input signal status can be obtained within a high- and low-frequency switching cycle by simultaneously gating the two signals mentioned above.

[0203] In at least one embodiment of the Fig.In the control circuit shown in Figure 39 of the present disclosure, the absolute value of the potential of N2-1 will be lower because the p-type transistor exhibits a threshold voltage drop when transmitting low voltage, and the n-type transistor exhibits a threshold voltage drop when transmitting high voltage. Therefore, the second first inverter and the second second inverter can control the increase in the absolute value of the potential of N2-1, thus allowing better control of the conducting or blocking switching of the corresponding transistor in the second output circuit. When T2-1 and T2-2 are switched on, the second maintenance control circuit, controlled by them, controls the isolation between N2-1 and N2-4 in order not to interfere with the writing of the potential of N2-1.

[0204] Fig. 40 is an operating time diagram of at least one embodiment of the in Fig. 39 shown control circuit;

[0205] Fig. 41 is a simulation operating time diagram of at least one embodiment of the in Fig. Control circuit shown in 39.

[0206] The difference between at least one embodiment of the in Fig. 42 Control circuit shown in the present disclosure and at least one embodiment thereof Fig. The control circuit shown in Figure 39 of the present disclosure is as follows: The second voltage maintenance circuit is not provided (i.e., T2-3 to T2-8 are not provided).

[0207] The difference between at least one embodiment of the in Fig. 43 control circuit shown in the present disclosure and at least one embodiment thereof Fig. The control circuit shown in Figure 39 of the present disclosure is as follows: N2-4 is electrically connected to the gate of T2-11 and the gate of T2-13.

[0208] If at least one embodiment of the in Fig. In the control circuit shown in Figure 43 of the present disclosure, the absolute value of the potential of N2-1 will be lower because the p-type transistor exhibits a threshold voltage drop when transmitting low voltage, and the n-type transistor exhibits a threshold voltage drop when transmitting high voltage. This allows the second first inverter and the second second inverter to control the increase in the absolute value of the potential of N2-4, thereby improving control of the conducting or blocking switching of the corresponding transistor in the second output circuit. When T2-1 and T2-2 are switched on, the second maintenance control circuit, under their control, maintains the isolation between N2-1 and N2-4 to avoid interfering with the writing of the potential of N2-1.

[0209] As in Fig. As shown in Figure 44, the control circuit according to an embodiment of the present disclosure comprises a third control signal generation circuit 310, a third gating circuit 311, a third output control circuit 312, a third output circuit 313 and a third voltage control circuit 314; wherein the third control signal generation circuit 310 is electrically connected to the third first control node NC3-1, the third second control node NC3-2 or the control signal output terminal NS (N) of the N-th stage and is used to generate a control signal of the N-th stage under control of the potential of the third first control node NC3-1 and the potential of the third second control node NC3-2 and to output it via the control signal output terminal NS (N) of the N-th stage; wherein the third gating circuit 311 is electrically connected to the third first node N3-1, the gating input terminal VCT or the gating control terminal CX, and is used to control the writing of the gating input signal provided by the gating control terminal VCT to the third first node N3-1 under the control of the gating control signal provided by the gating control terminal CX; wherein the third output control circuit 312 is electrically connected to the third first node N3-1, the third first control node NC3-1 or the third second node N3-2 and is used to control the connection between the third first control node NC3-1 and the third second node N3-2 by controlling the potential of the third first node N3-1; wherein the third voltage control circuit 314 is electrically connected to the third first node N3-1 or the third second node N3-2 and is used to control the potential of the third second node N3-2 according to the potential of the third first node N3-1; wherein the third output circuit 313 is electrically connected to the third second node N3-2, the third third control node NC3-3, the first voltage terminal V1, the second voltage terminal V2 and the output control terminal NO (N) respectively, and is used to control the connection between the output control terminal NO (N) and the first voltage terminal V1 under control of the potential of the third second node N3-2, and to control the connection between the output control terminal NO (N) and the second voltage terminal V2 under control of the potential of the third third control node NC3-3; where the third second control node NC3-2 and the third third control node NC3-3 are distinct nodes; and N is a positive integer.

[0210] If an embodiment of the in Fig. In the control circuit shown in Figure 44 of the present disclosure, the third control signal generation circuit 310 generates a control signal of the Nth stage and outputs it via the control signal output terminal NS(N) of the Nth stage, and the third gating circuit 311 writes the gating input signal to the third first node N3-1 under control of the gating control signal; the third output control circuit 312 controls the connection between the third first control node NC3-1 and the third second node N3-2 under control of the potential of the third first node N3-1; the third voltage control circuit 314 controls the potential of the third second node N3-2 according to the potential of the third first node N3-1;The third output circuit 313 controls, under the control of the potential of the third second node N3-2, the connection between the output control terminal NO (N) and the first voltage terminal V1, and, under the control of the potential of the third third control node NC3-3, the connection between the output control terminal NO (N) and the second voltage terminal V2.

[0211] Optionally, the first voltage connection can be a high-voltage connection, but it is not limited to this.

[0212] The embodiment of the in Fig. The control circuit shown in section 44 of the present disclosure can be a control circuit of the Nth stage.

[0213] If the embodiment of the in Fig. In the control circuit shown in section 44 of the present disclosure, the following occurs within one frame time:

[0214] Before the phase of providing the control signal of the Nth stage, the third gating circuit 311, under the control of the gating control signal, writes the gating input signal provided by the gating input terminal VCT to the third first node N3-1; If the gating input signal is a high-voltage signal, during the phase of providing the drive signal to the N-th stage, the drive signal output terminal NS(N) of the N-th stage outputs a high-voltage signal; the potential of the third first node N3-1 is at high voltage; the third output control circuit 312, under control of the potential of the third first node N3-1, controls the separation between the third first control node NC3-1 and the third second node N3-2; the third voltage control circuit 314, according to the potential of the third first node N3-1, controls the potential of the third second node N3-2 to high voltage; the third output circuit controls the output drive terminal NO(N) to maintain the output of a low-voltage signal that can control the corresponding line pixel circuit without updating the pixel voltage; If the gating input signal is a low-voltage signal, during the phase of providing the drive signal to the Nth stage, the drive signal output terminal NS(N) of the Nth stage outputs a high-voltage signal. The potential of the third first node N3-1 is at low voltage. The third output control circuit 312, under control of the potential of the third first node N3-1, controls the connection between the third first control node NC3-1 and the third second node N3-2, so that the potential of the third second node N3-2 is at low voltage. The third output circuit 313, under control of the potential of the third second node N3-2, controls the connection between the output drive terminal NO(N) and the first voltage terminal V1, so that NO(N) outputs a high-voltage signal that can control the corresponding line pixel circuit to update the pixel voltage.

[0215] Embodiments of the present disclosure can, by controlling the gating input signal provided by the gating input port VCT, achieve the updating of a local image on the display screen, thereby reducing power consumption, or can achieve ultra-low power consumption in OLED display products such as portable products, mobile devices, notebooks, or the like by locally updating the display image.

[0216] Optionally, the third output control circuit includes a third transistor; wherein the gate of the third third transistor is electrically connected to the third first node, the first electrode of the third third transistor is electrically connected to the third first control node, and the second electrode of the third third transistor is electrically connected to the third second node.

[0217] Optionally, the third voltage control circuit includes a third first capacitor; wherein the first terminal of the third first capacitor is electrically connected to the third first node, and the second terminal of the third first capacitor is electrically connected to the third second node.

[0218] The control circuit according to at least one embodiment of the present disclosure further comprises a third second node control circuit; wherein the third second node control circuit is electrically connected to the third third control node, the third second node or the first voltage terminal and is used to control the connection between the third second node and the first voltage terminal by controlling the potential of the third third control node.

[0219] In a specific implementation, the control circuit may also include a third second node control circuit; wherein the third second node control circuit, under the control of the potential of the third third control node, controls the connection between the third second node and the first voltage terminal.

[0220] As in Fig. As shown in Figure 45, the control circuit comprises the embodiment of the design shown in Figure 45. Fig. 44 control circuit shown furthermore a third second node control circuit 320; wherein the third second node control circuit 320 is electrically connected to the third third control node NC3-3, the third second node N3-2 or the first voltage terminal V1 and is used to control the connection between the third second node N3-2 and the first voltage terminal V1 under the control of the potential of the third third control node NC3-3.

[0221] If at least one embodiment of the in Fig. If the control circuit shown in Figure 45 works and the potential of the third control node NC3-3 is at an effective voltage, the potential of the third second node N3-2 can be at a first voltage.

[0222] Optionally, the third second node control circuit includes a third fourth transistor; wherein the gate of the third fourth transistor is electrically connected to the third third control node, the first electrode of the third fourth transistor is electrically connected to the third second node, and the second electrode of the third fourth transistor is electrically connected to the first voltage terminal.

[0223] Optionally, the third output circuit includes a third fifth transistor, a third sixth transistor, and a third second capacitor; wherein the gate of the third fifth transistor is electrically connected to the third second node, the first electrode of the third fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the third fifth transistor is electrically connected to the output drive terminal; wherein the gate of the third sixth transistor is electrically connected to the third third control node, the first electrode of the third sixth transistor is electrically connected to the output control terminal, and the second electrode of the third sixth transistor is electrically connected to the second voltage terminal; wherein the first terminal of the third second capacitor is electrically connected to the third second node, and the second terminal of the third second capacitor is electrically connected to the first voltage terminal.

[0224] The control circuit according to at least one embodiment of the present disclosure further comprises a third initialization circuit; wherein the third initialization circuit is electrically connected to the initial control terminal, the second voltage terminal or the third first node and is used to control the connection between the third first node and the second voltage terminal under the control of the initial control signal provided by the initial control terminal.

[0225] In a specific implementation, the control circuit may further include a third initialization circuit. When the display device is switched on, the third initialization circuit, under the control of the initial control signal, controls the connection between the third first node and the second voltage terminal to control the potential of the third first node to a second voltage, and the third output control circuit, under the control of the potential of the third first node, controls the connection between the third first control node and the third second node.

[0226] In at least one embodiment of the present disclosure, the control circuit further comprises a third first node control circuit; wherein the third first node control circuit is electrically connected to the third fourth node, the second voltage terminal or the third first node and is used to control the connection between the third first node and the second voltage terminal by controlling the potential of the third fourth node.

[0227] In a specific implementation, the control circuit may further comprise a third first node control circuit, wherein the third first node control circuit, under control of the potential of the third fourth node, controls the connection between the third first node and the second voltage terminal; wherein, after the phase of providing the control signal of the Nth stage, the third first node control circuit controls the connection between the third first node and the second voltage terminal when the potential of the third fourth node is at an effective voltage such that the potential of the third first node is at the second voltage, wherein the third output control circuit, under control of the potential of the third first node, controls the connection between the third first control node and the third second node.

[0228] In at least one embodiment of the present disclosure, the effective voltage can be a low voltage if the transistor included in the third first node control circuit is a p-type transistor, and the effective voltage can be a high voltage if the transistor included in the third first node control circuit is an n-type transistor.

[0229] As in Fig. As shown in 46, the control circuit can be based on at least one embodiment of the Fig. The control circuit shown in Figure 45 further comprises a third initialization circuit 321 and a third first node control circuit 322; wherein the third initialization circuit 321 is electrically connected to the initial control terminal NCX, the third first node N3-1 or the second voltage terminal V2 and is used to control the connection between the third first node N3-1 and the second voltage terminal V2 under the control of the initial control signal provided by the initial control terminal NCX; wherein the third first node control circuit 322 is electrically connected to the third fourth node N3-4, the third first node N3-1 or the second voltage terminal V2 and is used to control the connection between the third first node N3-1 and the second voltage terminal V2 by controlling the potential of the third fourth node N3-4.

[0230] Optionally, the third initialization circuit includes a third seventh transistor; wherein the gate of the third seventh transistor is electrically connected to the initial control terminal, the first electrode of the third seventh transistor is electrically connected to the third first node, and the second electrode of the third seventh transistor is electrically connected to the second voltage terminal.

[0231] Optionally, the third first node control circuit includes a third eighth transistor; wherein the gate of the third eighth transistor is electrically connected to the third fourth node, the first electrode of the third eighth transistor is electrically connected to the third first node, and the second electrode of the third eighth transistor is electrically connected to the second voltage terminal.

[0232] The control circuit according to at least one embodiment of the present disclosure further comprises a third control node control circuit; wherein the third third control node control circuit is electrically connected to the third first node, the third fifth node, the third second control node, the third third control node and the third sixth node respectively, and is used to control the connection between the third fifth node and the third third control node under the control of the potential of the third first node, and to control the connection between the third second control node and the third sixth node under the control of the potential of the third sixth node, and to control the connection between the third sixth node and the third third control node.

[0233] In a specific implementation, the control circuit can include a third third control node control circuit, wherein the third third control node control circuit controls the potential of the third third control node under the control of the potential of the third first node and the potential of the third sixth node.

[0234] As in Fig. 47 shows the control circuit based on at least one embodiment of the in Fig. 46 control circuit shown furthermore a third control node control circuit 330;

[0235] wherein the third third control node control circuit 330 is electrically connected to the third first node N3-1, the third fifth node N3-5, the third second control node NC3-2, the third third control node NC3-3 and the third sixth node N3-6 respectively, and is used to control the connection between the third fifth node N3-5 and the third third control node NC3-3 under the control of the potential of the third first node N3-1, and to control the connection between the third second control node NC3-2 and the third sixth node N3-6 under the control of the potential of the third sixth node N3-6, and to control the connection between the third sixth node N3-6 and the third third control node NC3-3.

[0236] Optionally, the third third control node control circuit includes a third ninth transistor, a third tenth transistor, and a third eleventh transistor; wherein the gate of the third ninth transistor is electrically connected to the third first node, the first electrode of the third ninth transistor is electrically connected to the third fifth node, and the second electrode of the third ninth transistor is electrically connected to the third third control node; wherein the gate of the third tenth transistor and the second electrode of the third tenth transistor are each electrically connected to the third sixth node, and the first electrode of the third tenth transistor is electrically connected to the third second control node; wherein the gate of the third eleventh transistor and the first electrode of the third eleventh transistor are each electrically connected to the third sixth node, and the second electrode of the third eleventh transistor is electrically connected to the third third control node.

[0237] In at least one embodiment of the present disclosure, the third control signal generation circuit comprises a third first control output circuit, a third second control output circuit, a third first control node control circuit and a third second control node control circuit; wherein the third first control node control circuit is used to control the potential of the third first control node; wherein the third second control node control circuit is used to control the potential of the third second control node; wherein the third first control output circuit is electrically connected to the third first control node, the first voltage terminal or the control signal output terminal of the N-th stage and is used to control the connection between the control signal output terminal of the N-th stage and the first voltage terminal by controlling the potential of the third first control node; wherein the third second control output circuit is electrically connected to the third second control node, the second voltage terminal or the control signal output terminal of the N-th stage and is used to control the connection between the control signal output terminal of the N-th stage and the second voltage terminal by controlling the potential of the third second control node.

[0238] As in Fig. 48 shows the control circuit based on at least one embodiment of the in Fig. 47 shown control circuit further includes a third first control node control circuit 331, a third second control node control circuit 332, a third first control output circuit 333 and a third second control output circuit 334; wherein the third first control node control circuit 331 is electrically connected to the third first control node NC3-1 and is used to control the potential of the third first control node NC3-1; wherein the third second control node control circuit 332 is electrically connected to the third second control node NC3-2 and is used to control the potential of the third second control node NC3-2; wherein the third first control output circuit 333 is electrically connected to the third first control node NC3-1, the first voltage terminal V1 or the control signal output terminal NS (N) of the N-th stage and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the first voltage terminal V1 by controlling the potential of the third first control node NC3-1; wherein the third second control output circuit 334 is electrically connected to the third second control node NC3-2, the control signal output terminal NS (N) of the N-th stage or the second voltage terminal V2 and is used to control the connection between the control signal output terminal NS (N) of the N-th stage and the second voltage terminal V2 under control of the potential of the third second control node NC3-2.

[0239] In at least one embodiment of the present disclosure, the third first control node control circuit comprises a third seventh node control circuit, a third eighth node control circuit, a third third node control circuit and a third first control circuit; wherein the third seventh node control circuit is electrically connected to the third seventh node, the second voltage terminal, the first clock signal terminal, and the third fifth node, respectively, and is used to control the connection between the third seventh node and the second voltage terminal under the control of the first clock signal provided by the first clock signal terminal, and to control the connection between the third seventh node and the first clock signal terminal under the control of the potential of the third fifth node; wherein the third eighth node control circuit is electrically connected to the second voltage terminal, the third seventh node or the third eighth node, and is used to control the connection between the third seventh node and the third eighth node under the control of the second voltage signal provided by the second voltage terminal; wherein the third third node control circuit is electrically connected to the third eighth node, the second clock signal terminal, and the third third node, respectively, and is used to control the electrical connection between the third third node and the second clock signal terminal by controlling the potential of the third eighth node, and to control the potential of the third third node according to the potential of the third eighth node; wherein the third first control circuit is electrically connected to the second clock signal terminal, the third third node, the third first control node, the third fifth node and the first voltage terminal respectively, and is used to control the connection between the third third node and the third first control node under the control of the second clock signal provided by the second clock signal terminal, and to control the connection between the third first control node and the first voltage terminal under the control of the potential of the third fifth node.

[0240] In a specific implementation, the third first control node control circuit may comprise a third seventh node control circuit, a third eighth node control circuit, a third third node control circuit, and a third first control circuit; wherein the third seventh node control circuit, under the control of the first clock signal and the potential of the third fifth node, controls the potential of the third seventh node; the third eighth node control circuit, under the control of the second voltage signal, controls the connection between the third seventh node and the third eighth node; the third third node control circuit, under the control of the potential of the third eighth node, controls the electrical connection between the third third node and the second clock signal terminal, and, according to the potential of the third eighth node, controls the potential of the third third node;and the third first control circuit, under the control of the second clock signal, controls the connection between the third third node and the third first control node, and, under the control of the potential of the third fifth node, controls the connection between the third first control node and the first voltage terminal.

[0241] In at least one embodiment of the present disclosure, the third second control node control circuit comprises a third sixth node control circuit, a third fifth node control circuit, a third ninth node control circuit, a third fourth node control circuit and a third second control circuit; wherein the third sixth node control circuit is electrically connected to the second voltage terminal, the third ninth node, the third sixth node and the third fourth node respectively, and is used to control the connection between the third ninth node and the third sixth node under the control of the second voltage signal provided by the second voltage terminal, and to control the potential of the third sixth node according to the potential of the third fourth node; wherein the third fifth node control circuit is electrically connected to the control signal output terminal of the N-1th stage, the first clock signal terminal, the third fifth node, the initial control terminal, and the first voltage terminal, respectively, and is used to control the connection between the third fifth node and the control signal output terminal of the N-1th stage under control of the first clock signal provided by the first clock signal terminal, and to control the connection between the third fifth node and the first voltage terminal under control of the initial control signal provided by the initial control terminal; wherein the third ninth node control circuit is electrically connected to the first clock signal terminal, the control signal output terminal of the N-1th stage or the third ninth node, and is used to control the connection between the third ninth node and the control signal output terminal of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal; wherein the third fourth node control circuit is electrically connected to the third seventh node, the first voltage terminal, the third fourth node, the second clock signal terminal, and the third sixth node, respectively, and is used to control the connection between the third fourth node and the first voltage terminal by controlling the potential of the third seventh node, and to control the connection between the third fourth node and the second clock signal terminal by controlling the potential of the third sixth node; wherein the third second control circuit is electrically connected to the second voltage terminal, the third fifth node or the third second control node, and is used to control the connection between the third fifth node and the third second control node under the control of the second voltage signal provided by the second voltage terminal.

[0242] In a specific implementation, the third second control node control circuit may comprise a third sixth node control circuit, a third fifth node control circuit, a third ninth node control circuit, a third fourth node control circuit, and a third second control circuit; wherein the third fourth node control circuit, under the control of the potential of the third seventh node and the potential of the third sixth node, controls the potential of the third fourth node; the third sixth node control circuit, under the control of the second voltage signal, controls the connection between the third ninth node and the third sixth node, and, according to the potential of the third fourth node, controls the potential of the third sixth node;The third fifth node control circuit, under the control of the first clock signal, controls the connection between the third fifth node and the control signal output terminal of the N-1th stage, and under the control of the initial control signal, controls the connection between the third fifth node and the first voltage terminal; the third ninth node control circuit, under the control of the first clock signal, controls the connection between the third ninth node and the control signal output terminal of the N-1th stage; the third fourth node control circuit, under the control of the potential of the third seventh node, controls the connection between the third fourth node and the first voltage terminal, and under the control of the potential of the third sixth node, controls the connection between the third fourth node and the second clock signal terminal;and the third second control circuit, under the control of the second voltage signal, controls the connection between the third fifth node and the third second control node;

[0243] As in Fig. As shown in 49, the third first control node control circuit comprises at least one embodiment of the one shown in Fig. 48 control circuit shown a third seventh node control circuit 341, a third eighth node control circuit 342, a third third node control circuit 343 and a third first control circuit 344; wherein the third seventh node control circuit 341 is electrically connected to the third seventh node N3-7, the second voltage terminal V2, the first clock signal terminal GCK or the third fifth node N3-5 and is used to control the connection between the third seventh node N3-7 and the second voltage terminal V2 under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the third seventh node N3-7 and the first clock signal terminal GCK under the control of the potential of the third fifth node N3-5; wherein the third eighth node control circuit 342 is electrically connected to the second voltage terminal V2, the third seventh node N3-7 or the third eighth node N3-8 and is used to control the connection between the third seventh node N3-7 and the third eighth node N3-8 under the control of the second voltage signal provided by the second voltage terminal V2; wherein the third third node control circuit 343 is electrically connected to the third eighth node N3-8, the second clock signal terminal GCB or the third third node N3-3 and is used to control the electrical connection between the third third node N3-3 and the second clock signal terminal GCB by controlling the potential of the third eighth node N3-8, and to control the potential of the third third node N3-3 according to the potential of the third eighth node N3-8; wherein the third first control circuit 344 is electrically connected to the second clock signal terminal GCB, the third third node N3-3, the third first control node NC3-1, the third fifth node N3-5 and the first voltage terminal V1 respectively, and is used to control the connection between the third third node N3-3 and the third first control node NC3-1 under the control of the second clock signal provided by the second clock signal terminal GCB, and to control the connection between the third first control node NC3-1 and the first voltage terminal V1 under the control of the potential of the third fifth node N3-5; the third second control node control circuit comprises a third sixth node control circuit 351, a third fifth node control circuit 352, a third ninth node control circuit 353, a third fourth node control circuit 354 and a third second control circuit 355; wherein the third sixth node control circuit 351 is electrically connected to the second voltage terminal V2, the third ninth node N3-9, the third sixth node N3-6 and the third fourth node N3-4 respectively, and is used to control the connection between the third ninth node N3-9 and the third sixth node N3-6 under the control of the second voltage signal provided by the second voltage terminal V2, and to control the potential of the third sixth node N3-6 according to the potential of the third fourth node N3-4; wherein the third fifth node control circuit 352 is electrically connected to the control signal output terminal NS (N-1) of the N-1th stage, the first clock signal terminal GCK, the third fifth node N3-5, the initial control terminal NCX or the first voltage terminal V1 and is used to control the connection between the third fifth node N3-5 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK, and to control the connection between the third fifth node N3-5 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX; wherein the third ninth node control circuit 353 is electrically connected to the first clock signal terminal GCK, the control signal output terminal NS (N-1) of the N-1th stage or the third ninth node N3-9 and is used to control the connection between the third ninth node N3-9 and the control signal output terminal NS (N-1) of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal GCK; wherein the third fourth node control circuit 354 is electrically connected to the third seventh node N3-7, the first voltage terminal V1, the third sixth node N3-6, the third fourth node N3-4 and the second clock signal terminal GCB respectively, and is used to control the connection between the third fourth node N3-4 and the first voltage terminal V1 by controlling the potential of the third seventh node N3-7, and to control the connection between the third fourth node N3-4 and the second clock signal terminal GCB by controlling the potential of the third sixth node N3-6; wherein the third second control circuit 355 is electrically connected to the second voltage terminal V2, the third fifth node N3-5 or the third second control node NC3-2 and is used to control the connection between the third fifth node N3-5 and the third second control node NC3-2 under the control of the second voltage signal provided by the second voltage terminal V2.

[0244] Optionally, the third seventh node control circuit includes a third twelfth transistor and a third thirteenth transistor, the third eighth node control circuit includes a third fourteenth transistor, the third third node control circuit includes a third fifteenth transistor and a third third capacitor, and the third first control circuit includes a third sixteenth transistor and a third seventeenth transistor; wherein the gate of the third twelfth transistor is electrically connected to the first clock signal terminal, the first electrode of the third twelfth transistor is electrically connected to the second voltage terminal, and the second electrode of the third twelfth transistor is electrically connected to the third seventh node; wherein the gate of the third thirteenth transistor is electrically connected to the third fifth node, the first electrode of the third thirteenth transistor is electrically connected to the third seventh node, and the second electrode of the third thirteenth transistor is electrically connected to the first clock signal terminal; wherein the gate of the third fourteenth transistor is electrically connected to the second voltage terminal, the first electrode of the third fourteenth transistor is electrically connected to the third seventh node, and the second electrode of the third fourteenth transistor is electrically connected to the third eighth node; wherein the gate of the third fifteenth transistor is electrically connected to the third eighth node, the first electrode of the third fifteenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the third fifteenth transistor is electrically connected to the third third node; wherein the gate of the third sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the third sixteenth transistor is electrically connected to the third third node, and the second electrode of the third sixteenth transistor is electrically connected to the third first control node; wherein the gate of the third seventeenth transistor is electrically connected to the third fifth node, the first electrode of the third seventeenth transistor is electrically connected to the third first control node, and the second electrode of the third seventeenth transistor is electrically connected to the first voltage terminal.

[0245] Optionally, the third sixth node control circuit includes a third eighteenth transistor and a third fourth capacitor, the third fifth node control circuit includes a third nineteenth transistor and a twentieth transistor, the third ninth node control circuit includes a third twenty-first transistor, the third fourth node control circuit includes a third twenty-second transistor and a third twenty-third transistor, and the third second control circuit includes a third twenty-fourth transistor; wherein the gate of the third eighteenth transistor is electrically connected to the second voltage terminal, the first electrode of the third eighteenth transistor is electrically connected to the third ninth node, and the second electrode of the third eighteenth transistor is electrically connected to the third sixth node; wherein the first terminal of the third fourth capacitor is electrically connected to the third fourth node, and the second terminal of the third fourth capacitor is electrically connected to the third sixth node; wherein the gate of the third nineteenth transistor is electrically connected to the first clock signal terminal, the first electrode of the third nineteenth transistor is electrically connected to the drive signal output terminal of the N-1th stage, and the second electrode of the third nineteenth transistor is electrically connected to the third fifth node; wherein the gate of the twentieth transistor is electrically connected to the initial control terminal, the first electrode of the twentieth transistor is electrically connected to the first voltage terminal, and the second electrode of the twentieth transistor is electrically connected to the third fifth node; wherein the gate of the third twenty-first transistor is electrically connected to the first clock signal terminal, the first electrode of the third twenty-first transistor is electrically connected to the drive signal output terminal of the N-1 stage, and the second electrode of the third twenty-first transistor is electrically connected to the third ninth node; wherein the gate of the third twenty-second transistor is electrically connected to the third seventh node, the first electrode of the third twenty-second transistor is electrically connected to the first voltage terminal, and the second electrode of the third twenty-second transistor is electrically connected to the third fourth node; wherein the gate of the third twenty-third transistor is electrically connected to the third sixth node, the first electrode of the third twenty-third transistor is electrically connected to the third fourth node, and the second electrode of the third twenty-third transistor is electrically connected to the second clock signal terminal; wherein the gate of the third twenty-fourth transistor is electrically connected to the second voltage terminal, the first electrode of the third twenty-fourth transistor is electrically connected to the third ninth node, and the second electrode of the third twenty-fourth transistor is electrically connected to the third second control node.

[0246] Optionally, the third first drive output circuit includes a twenty-fifth transistor and a third fifth capacitor, and the third second drive output circuit includes a third twenty-sixth transistor and a third sixth capacitor; wherein the gate of the twenty-fifth transistor is electrically connected to the third first control node, the first electrode of the twenty-fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the twenty-fifth transistor is electrically connected to the drive signal output terminal of the Nth stage; wherein the first terminal of the third fifth capacitor is electrically connected to the third first control node, and the second terminal of the third fifth capacitor is electrically connected to the first voltage terminal; wherein the gate of the third twenty-sixth transistor is electrically connected to the third second control node, the first electrode of the third twenty-sixth transistor is electrically connected to the drive signal output terminal of the Nth stage, and the second electrode of the third twenty-sixth transistor is electrically connected to the second voltage terminal; wherein the first terminal of the third sixth capacitor is electrically connected to the control signal output terminal of the Nth stage, and the second terminal of the third sixth capacitor is electrically connected to the second voltage terminal.

[0247] As in Fig. As shown in 50, the third gating circuit comprises at least one embodiment of the one shown in Fig. The control circuit shown in 49 includes a third first transistor T3-1 and a third second transistor T3-2; wherein the gate of the third first transistor T3-1 is electrically connected to the drive signal output terminal NS (N) of the N-th stage, the drain of the third first transistor T3-1 is electrically connected to the third first node N3-1, and the source of the third first transistor T3-1 is electrically connected to the drain of the third second transistor T3-2; wherein the gate of the third second transistor T3-2 is electrically connected to the third third node N3 (N-1) of the N-1th stage, and the source of the third second transistor T3-2 is electrically connected to the gating input terminal VCT; The third output control circuit includes a third transistor T3-3; wherein the gate of the third third transistor T3-3 is electrically connected to the third first node N3-1, the source of the third third transistor T3-3 is electrically connected to the third first control node NC3-1, and the drain of the third third transistor T3-3 is electrically connected to the third second node N3-2; The third voltage control circuit includes a third first capacitor C3-1; wherein the first terminal of the third first capacitor C3-1 is electrically connected to the third first node N3-1, and the second terminal of the third first capacitor C3-1 is electrically connected to the third second node N3-2; The third second node control circuit includes a third fourth transistor T3-4; wherein the gate of the third fourth transistor T3-4 is electrically connected to the third third control node NC3-3, the source of the third fourth transistor T3-4 is electrically connected to the third second node N3-2, and the drain of the third fourth transistor T3-4 is electrically connected to the high voltage terminal VGH; The third output circuit includes a third fifth transistor T3-5, a third sixth transistor and a third second capacitor C3-2; wherein the gate of the third fifth transistor T3-5 is electrically connected to the third second node N2, the source of the third fifth transistor T3-5 is electrically connected to the high voltage terminal VGH, and the drain of the third fifth transistor T3-5 is electrically connected to the output control terminal NO (N); wherein the gate of the third sixth transistor T3-6 is electrically connected to the third third control node NC3-3, the source of the third sixth transistor T3-6 is electrically connected to the output control terminal NO (N), and the drain of the third sixth transistor T3-6 is electrically connected to the low voltage terminal VGL; wherein the first terminal of the third second capacitor C3-2 is electrically connected to the third second node N3-2, and the second terminal of the third second capacitor C3-2 is electrically connected to the high voltage terminal VGH; The third initialization circuit includes a third seventh transistor T3-7; wherein the gate of the third seventh transistor T3-7 is electrically connected to the initial control termina...

Claims

[1] Control circuit comprising a first control signal generation circuit, a first output control circuit, a first gating circuit, a first first energy storage circuit, a first second energy storage circuit and a first output circuit; and N is a positive integer; wherein the first control signal generation circuit is electrically connected to a first first control node, a first second control node or a control signal output terminal of the N-th stage and is used to generate a control signal of the N-th stage under the control of a potential of the first first control node and a potential of the first second control node and to output it via the control signal output terminal of the N-th stage; wherein the first output control circuit is electrically connected to a first first node, the first first control node or a first second node and is used to control the connection between the first first control node and the first second node under the control of a potential of the first first node; wherein the first gating circuit is electrically connected to the first node, a gating input terminal or a gating control terminal, and is used to control the writing of a gating input signal provided by the gating input terminal to the first node under the control of a gating control signal provided by the gating control terminal; wherein the first energy storage circuit is electrically connected to the first node or the first second node and is used to control the potential of the first second node according to the potential of the first node; wherein the first second energy storage circuit is electrically connected to a first third control node or an output control terminal of the N-th stage and is used to control the potential of the first third control node according to a control output signal of the N-th stage provided by the output control terminal of the N-th stage; wherein the first output circuit is electrically connected to the first second node, the first third control node, a first voltage terminal, a second voltage terminal or the output control terminal of the Nth stage and is used to control the connection between the output control terminal of the Nth stage and the first voltage terminal under control of the potential of the first second node and to control the connection between the output control terminal of the Nth stage and the second voltage terminal under control of the potential of the first third control node; where the first third control node and the first second control node are different nodes. [2] Control circuit according to claim 1, wherein the first gating circuit is used to control the writing of a gating input signal provided by the gating input terminal to the first first node when the potential of a first third node of the N-1th stage is at a second voltage and the potential of the control signal of the N-th stage is at a second voltage. [3] Control circuit according to claim 1, wherein the first gating circuit comprises a first first transistor; wherein a gate of the first first transistor is electrically connected to the gating control terminal, a first electrode of the first first transistor is electrically connected to the first first node, and a second electrode of the first first transistor is electrically connected to the gating input terminal. [4] Control circuit according to claim 1, wherein the gating control terminal comprises a first gating control terminal and a second gating control terminal; and the first gating circuit comprises a first first transistor and a first second transistor; wherein a gate of the first first transistor is electrically connected to the first gating control terminal, a first electrode of the first first transistor is electrically connected to the first first node, and a second electrode of the first first transistor is electrically connected to a first electrode of the first second transistor; wherein a gate of the first second transistor is electrically connected to the second gating control terminal, and a second electrode of the first second transistor is electrically connected to the gating input terminal; wherein the first gating control terminal is a drive signal output terminal of the N-th stage, the second gating control terminal is a first third node of the N-1-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a first third node of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, and the first first transistor and the first second transistor are each a p-type transistor; or wherein the first gating control terminal is a drive signal output terminal of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, the first transistor is an n-type transistor, and the first transistor is a p-type transistor; or wherein the first gating control terminal is a drive signal output terminal of the N-th stage, the second gating control terminal is a drive signal output terminal of the N-1th stage, the first transistor is a p-type transistor, and the first transistor is an n-type transistor; or wherein the first gating control terminal accepts an inverted signal of the drive signal of the N-1th stage, the second gating control terminal is a drive signal output terminal of the N-th stage, and the first first transistor and the first second transistor are each p-type transistors; or wherein the first gating control terminal is a drive signal output terminal of the N-th stage, the second gating control terminal accepts an inverted signal of the drive signal of the N-1th stage, and the first first transistor and the first second transistor are each p-type transistors; or wherein the first gating control terminal is a drive signal terminal of the N-1th stage, the second gating control terminal accepts an inverted signal of the drive signal of the N-th stage, and the first first transistor and the first second transistor are each n-type transistors; or wherein the first gating control terminal receives an inverted signal of the drive signal of the N-th stage, the second gating control terminal is a drive signal terminal of the N-1-th stage, and the first first transistor and the first second transistor are each an n-type transistor. [5] Control circuit according to one of claims 1 to 4, wherein the first first energy storage circuit comprises a first first capacitor and the first second energy storage circuit comprises a first second capacitor; wherein a first terminal of the first first capacitor is electrically connected to the first first node, and a second terminal of the first first capacitor is electrically connected to the first second node; wherein a first terminal of the first second capacitor is electrically connected to the first third control node, and a second terminal of the first second capacitor is electrically connected to the output control terminal of the Nth stage. [6] Control circuit according to one of claims 1 to 4, wherein the first output control circuit comprises a first third transistor; wherein a gate of the first third transistor is electrically connected to the first first node, a first electrode of the first third transistor is electrically connected to the first first control node and a second electrode of the first third transistor is electrically connected to the first second node. [7] Control circuit according to one of claims 1 to 4, further comprising a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the first second node or the first voltage connection and is used to control the connection between the first second node and the first voltage connection by controlling the potential of the first third control node. [8] Control circuit according to one of claims 1 to 4, further comprising a first second node control circuit; wherein the first second node control circuit is electrically connected to the first third control node, the output control terminal of the N-th stage, the first second node or the first voltage terminal and is used to control the connection between the first second node and the first voltage terminal by controlling the potential of the first third control node and the control output signal of the N-th stage provided by the output control terminal of the N-th stage. [9] Control circuit according to claim 7, wherein the first second node control circuit comprises a first fourth transistor; wherein a gate of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to the first second node, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal. [10] Control circuit according to claim 8, wherein the first second node control circuit comprises a first fourth transistor and a first control transistor; wherein a gate of the first fourth transistor is electrically connected to the first third control node, a first electrode of the first fourth transistor is electrically connected to a second electrode of the first control transistor, and a second electrode of the first fourth transistor is electrically connected to the first voltage terminal; wherein a gate of the first control transistor is electrically connected to the output control terminal of the Nth stage, and a first electrode of the first control transistor is electrically connected to the first second node. [11] Control circuit according to any one of claims 1 to 4, wherein the first output circuit comprises a first fifth transistor, a first sixth transistor and a first third capacitor; wherein a gate of the first fifth transistor is electrically connected to the first second node, a first electrode of the first fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the first fifth transistor is electrically connected to the output control terminal of the Nth stage; wherein a gate of the first sixth transistor is electrically connected to the first third control node, a first electrode of the first sixth transistor is electrically connected to the output control terminal of the Nth stage, and a second electrode of the first sixth transistor is electrically connected to the second voltage terminal; wherein a first terminal of the first third capacitor is electrically connected to the first second node, and a second terminal of the first third capacitor is electrically connected to the first voltage terminal. [12] Control circuit according to one of claims 1 to 4, further comprising a first initialization circuit; wherein the first initialization circuit is electrically connected to an initial control terminal, the second voltage terminal or the first first node and is used to control the connection between the first first node and the second voltage terminal under the control of an initial control signal provided by the initial control terminal. [13] Control circuit according to one of claims 1 to 4, further comprising a first first node control circuit; wherein the first first node control circuit is electrically connected to a first fourth node, the second voltage terminal or the first first node and is used to control the connection between the first first node and the second voltage terminal by controlling the potential of the first fourth node. [14] Control circuit according to claim 12, wherein the first initialization circuit comprises a first seventh transistor; wherein a gate of the first seventh transistor is electrically connected to the initial control terminal, a first electrode of the first seventh transistor is electrically connected to the first first node, and a second electrode of the first seventh transistor is electrically connected to the second voltage terminal. [15] Control circuit according to claim 13, wherein the first first node control circuit comprises a first eighth transistor; wherein a gate of the first eighth transistor is electrically connected to the first fourth node, a first electrode of the first eighth transistor is electrically connected to the first first node, and a second electrode of the first eighth transistor is electrically connected to the second voltage terminal. [16] Control circuit according to one of claims 1 to 4, further comprising a first third control node control circuit; wherein the first third control node control circuit is electrically connected to the first first node, a first fifth node, the first second control node, the first third control node or a first sixth node and is used to control the connection between the first fifth node and the first third control node by controlling the potential of the first first node, and to control the connection between the first second control node and the first sixth node and the connection between the first sixth node and the first third control node by controlling the potential of the first sixth node. [17] Control circuit according to claim 16, wherein the first third control node control circuit comprises a first ninth transistor, a first tenth transistor and a first eleventh transistor; wherein a gate of the first ninth transistor is electrically connected to the first first node, a first electrode of the first ninth transistor is electrically connected to the first fifth node, and a second electrode of the first ninth transistor is electrically connected to the first third control node; wherein a gate of the first tenth transistor and a second electrode of the first tenth transistor are each electrically connected to the first sixth node, and a first electrode of the first tenth transistor is electrically connected to the first second control node; wherein a gate of the first eleventh transistor and a first electrode of the first eleventh transistor are each electrically connected to the first sixth node, and a second electrode of the first eleventh transistor is electrically connected to the first third control node. [18] Control circuit according to one of claims 1 to 4, further comprising a first output pull-down circuit; wherein the first output pull-down circuit is electrically connected to the first control node, the control signal output terminal of the Nth stage or the second voltage terminal and is used to control the connection between the control signal output terminal of the Nth stage and the second voltage terminal by controlling the potential of the first control node. [19] Control circuit according to any one of claims 1 to 4, wherein the first control signal generation circuit comprises a first first control output circuit, a first second control output circuit, a first first control node control circuit and a first second control node control circuit; wherein the first control node control circuit is used to control the potential of the first control node; wherein the first second control node control circuit is used to control the potential of the first second control node; wherein the first first control output circuit is electrically connected to the first first control node, the first voltage terminal or the control signal output terminal of the Nth stage and is used to control the connection between the control signal output terminal of the Nth stage and the first voltage terminal by controlling the potential of the first first control node; wherein the first second control output circuit is electrically connected to the first second control node, the second voltage terminal or the control signal output terminal of the N-th stage and is used to control the connection between the control signal output terminal of the N-th stage and the second voltage terminal by controlling the potential of the first second control node. [20] Control circuit according to claim 19, wherein the first first control node control circuit comprises a first seventh node control circuit, a first eighth node control circuit, a first third node control circuit and a first first control circuit; wherein the first seventh node control circuit is electrically connected to a first seventh node, the second voltage terminal, a first clock signal terminal, or the first fifth node, and is used to control the connection between the first seventh node and the second voltage terminal under the control of a first clock signal provided by the first clock signal terminal, and to control the connection between the first seventh node and the first clock signal terminal under the control of the potential of the first fifth node; wherein the first eighth node control circuit is electrically connected to the second voltage terminal, the first seventh node, or a first eighth node, and is used to control the connection between the first seventh node and the first eighth node under the control of a second voltage signal provided by the second voltage terminal; wherein the first third node control circuit is electrically connected to the first eighth node, a second clock signal terminal or the first third node and is used to control the electrical connection between the first third node and the second clock signal terminal by controlling the potential of the first eighth node, and to control the potential of the first third node according to the potential of the first eighth node; wherein the first first control circuit is electrically connected to the second clock signal terminal, the first third node, the first first control node, the first fifth node or the first voltage terminal and is used to control the connection between the first third node and the first first control node under the control of a second clock signal provided by the second clock signal terminal, and to control the connection between the first first control node and the first voltage terminal under the control of the potential of the first fifth node. [21] Control circuit according to claim 19, wherein the first second control node control circuit comprises a first sixth node control circuit, a first fifth node control circuit, a first ninth node control circuit, a first fourth node control circuit and a first second control circuit; wherein the first sixth node control circuit is electrically connected to the second voltage terminal, a first ninth node, the first sixth node or the first fourth node and is used to control the connection between the first ninth node and the first sixth node under the control of the second voltage signal provided by the second voltage terminal, and to control the potential of the first sixth node according to the potential of the first fourth node; wherein the first fifth node control circuit is electrically connected to the control signal output terminal of the N-1th stage, the first clock signal terminal, the first fifth node, the initial control terminal, and the first voltage terminal, and is used to control the connection between the first fifth node and the control signal output terminal of the N-1th stage under control of the first clock signal provided by the first clock signal terminal, and to control the connection between the first fifth node and the first voltage terminal under control of the initial control signal provided by the initial control terminal; wherein the first ninth node control circuit is electrically connected to the first clock signal terminal, the control signal output terminal of the N-1th stage or the first ninth node, and is used to control the connection between the first ninth node and the control signal output terminal of the N-1th stage under the control of the first clock signal provided by the first clock signal terminal; wherein the first fourth node control circuit is electrically connected to the first seventh node, the first voltage terminal, the first fourth node, the second clock signal terminal, and the first sixth node, respectively, and is used to control the connection between the first fourth node and the first voltage terminal by controlling the potential of the first seventh node, and to control the connection between the first fourth node and the second clock signal terminal by controlling the potential of the first sixth node; wherein the first second control circuit is electrically connected to the second voltage terminal, the first fifth node or the first second control node, and is used to control the connection between the first fifth node and the first second control node under the control of the second voltage signal provided by the second voltage terminal. [22] Control circuit according to claim 20, wherein the first seventh node control circuit comprises a first twelfth transistor and a first thirteenth transistor, the first eighth node control circuit comprises a first fourteenth transistor, the first third node control circuit comprises a first fifteenth transistor and a first fourth capacitor, and the first first control circuit comprises a first sixteenth transistor and a first seventeenth transistor; wherein a gate of the first twelfth transistor is electrically connected to the first clock signal terminal, a first electrode of the first twelfth transistor is electrically connected to the second voltage terminal, and a second electrode of the first twelfth transistor is electrically connected to the first seventh node; wherein a gate of the first thirteenth transistor is electrically connected to the first fifth node, a first electrode of the first thirteenth transistor is electrically connected to the first seventh node, and a second electrode of the first thirteenth transistor is electrically connected to the first clock signal terminal; wherein a gate of the first fourteenth transistor is electrically connected to the second voltage terminal, a first electrode of the first fourteenth transistor is electrically connected to the first seventh node, and a second electrode of the first fourteenth transistor is electrically connected to the first eighth node; wherein a gate of the first fifteenth transistor is electrically connected to the first eighth node, a first electrode of the first fifteenth transistor is electrically connected to the second clock signal terminal, and a second electrode of the first fifteenth transistor is electrically connected to the first third node; wherein a first terminal of the first fourth capacitor is electrically connected to the first eighth node, and a second terminal of the first fourth capacitor is electrically connected to the first third node; wherein a gate of the first sixteenth transistor is electrically connected to the second clock signal terminal, a first electrode of the first sixteenth transistor is electrically connected to the first third node, and a second electrode of the first sixteenth transistor is electrically connected to the first first control node; wherein a gate of the first seventeenth transistor is electrically connected to the first fifth node, a first electrode of the first seventeenth transistor is electrically connected to the first first control node, and a second electrode of the first seventeenth transistor is electrically connected to the first voltage terminal. [23] Control circuit according to claim 21, wherein the first sixth node control circuit comprises a first eighteenth transistor and a first fifth capacitor, the first fifth node control circuit comprises a first nineteenth transistor and a first twentieth transistor, the first ninth node control circuit comprises a first twenty-first transistor, the first fourth node control circuit comprises a first twenty-second transistor and a first twenty-third transistor, and the first second control circuit comprises a first twenty-fourth transistor; wherein a gate of the first eighteenth transistor is electrically connected to the second voltage terminal, a first electrode of the first eighteenth transistor is electrically connected to the first ninth node, and a second electrode of the first eighteenth transistor is electrically connected to the first sixth node; wherein a first terminal of the first fifth capacitor is electrically connected to the first fourth node, and a second terminal of the first fifth capacitor is electrically connected to the first sixth node; wherein a gate of the first nineteenth transistor is electrically connected to the first clock signal terminal, a first electrode of the first nineteenth transistor is electrically connected to the drive signal output terminal of the N-1th stage, and a second electrode of the first nineteenth transistor is electrically connected to the first fifth node; wherein a gate of the first twentieth transistor is electrically connected to the initial control terminal, a first electrode of the first twentieth transistor is electrically connected to the first voltage terminal, and a second electrode of the first twentieth transistor is electrically connected to the first fifth node; wherein a gate of the first twenty-first transistor is electrically connected to the first clock signal terminal, a first electrode of the first twenty-first transistor is electrically connected to the drive signal output terminal of the N-1th stage, and a second electrode of the first twenty-first transistor is electrically connected to the first ninth node; wherein a gate of the first twenty-second transistor is electrically connected to the first seventh node, a first electrode of the first twenty-second transistor is electrically connected to the first voltage terminal, and a second electrode of the first twenty-second transistor is electrically connected to the first fourth node; wherein a gate of the first twenty-third transistor is electrically connected to the first sixth node, a first electrode of the first twenty-third transistor is electrically connected to the first fourth node, and a second electrode of the first twenty-third transistor is electrically connected to the second clock signal terminal; wherein a gate of the first twenty-fourth transistor is electrically connected to the second voltage terminal, a first electrode of the first twenty-fourth transistor is electrically connected to the first ninth node, and a second electrode of the first twenty-fourth transistor is electrically connected to the first second control node. [24] Control circuit according to claim 19, wherein the first first control output circuit comprises a first twenty-fifth transistor and a first sixth capacitor, and the first second control output circuit comprises a first twenty-sixth transistor and a first seventh capacitor; wherein a gate of the first twenty-fifth transistor is electrically connected to the first control node, a first electrode of the first twenty-fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the first twenty-fifth transistor is electrically connected to the drive signal output terminal of the Nth stage; wherein a first terminal of the first sixth capacitor is electrically connected to the first first control node, and a second terminal of the first sixth capacitor is electrically connected to the first voltage terminal; wherein a gate of the first twenty-sixth transistor is electrically connected to the first second control node, a first electrode of the first twenty-sixth transistor is electrically connected to the drive signal output terminal of the Nth stage, and a second electrode of the first twenty-sixth transistor is electrically connected to the second voltage terminal; wherein a first terminal of the first seventh capacitor is electrically connected to the drive signal output terminal of the Nth stage, and a second terminal of the first seventh capacitor is electrically connected to the second voltage terminal. [25] Control circuit according to claim 18, wherein the first output pulldown circuit comprises a first twenty-seventh transistor; wherein a gate of the first twenty-seventh transistor is electrically connected to the first control node, a first electrode of the first twenty-seventh transistor is electrically connected to the drive signal output terminal of the Nth stage, and a second electrode of the first twenty-seventh transistor is electrically connected to the second voltage terminal. [26] Control method applied to a control circuit according to any one of claims 1 to 25, the control method comprising: Generating and outputting a control signal of an Nth stage via a control signal output terminal of the Nth stage under the control of a potential of a first first control node and a potential of a first second control node by a first control signal generation circuit; Controlling the connection between the first control node and a first second node by controlling a potential of a first first node through the first output control circuit; Controlling the writing of a gating input signal to the first node under the control of a gating control signal by a first gating circuit; Controlling the potential of the first second node according to the potential of the first first node by a first first energy storage circuit; Control of the potential of a first third control node according to a control output signal of the Nth stage provided by an output control terminal of the Nth stage by a first second energy storage circuit; Controlling the connection between the output control terminal of the Nth stage and a first voltage terminal by controlling the potential of the first second node by a first output circuit, and controlling the connection between the output control terminal of the Nth stage and a second voltage terminal by controlling the potential of the first third control node by the first output circuit; where the first third control node and the first second control node are distinct nodes, and N is a positive integer. [27] Control module comprising several stages of control circuits according to any one of claims 1 to 25; wherein the control circuit of the N-th stage and the control circuit of the N-1-th stage comprise control signal output terminals which are electrically connected to each other, and N is a positive integer. [28] Display device comprising a control module according to claim 27.

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