3-D Integrated Circuit Antenna Arrays

Abstract

Antenna structures that can be arranged in close proximity with respect to an associated RFFE IC, regardless of the antenna element size. An antenna structure, including a grid or planar antenna or an array of antenna elements, is co-manufactured as part of or with one or more associated RFFE ICs using 3D stacks of IC die, either directly or as part of an embedded die packaging technology. Some embodiments include a combinable co-manufactured antenna element that includes at least one internally co-manufactured RF antenna element configured to be electrically connected to a corresponding RF antenna element in a second combinable co-manufactured antenna element using 3D stacks of integrated circuits.Some embodiments include a plurality of combinable, co-manufactured antenna elements coupled together by 3D stacking of integrated circuits such that the antenna elements form a grid antenna or comprise an array of antenna patches.

Description

CROSS-REFERENCE TO SIMILAR APPLICATIONS

[0001] This application claims priority to U.S. Patent Application No. 18 / 088,444, filed December 23, 2022, the contents of which are incorporated herein by reference in their entirety. BACKGROUND(1) Technical field

[0002] This invention relates to electronic circuits and, more particularly, to high frequency integrated circuits and related methods. (2) Background

[0003] Many modern electronic systems include radio frequency (RF) transceivers; examples include cellular phones, personal computers, tablet computers, wireless network components, televisions, cable system set-top boxes, automotive communication systems, wireless sensing devices, and radar systems. Many RF transceivers are capable of transmitting and receiving in full-duplex or half-duplex modes over multiple frequencies in multiple bands; for example, in the United States, the 2.4 GHz band is divided into 14 channels spaced approximately 5 MHz apart, and each channel operates in a half-duplex time-division division mode. As another example, a modern smart phone may include RF transceiver circuits capable of operating simultaneously on different cellular communication systems (e.g.,GSM, CDMA, LTE and 5G in multiple bands within the 400-7000 MHz range), on various wireless network frequencies and protocols (e.g., various IEEE 802.11 “WiFi” protocols at 2.4 GHz, 5 GHz and 6 GHz), and on “personal” networks (e.g., Bluetooth-based systems).

[0004] A frequency-division duplex radio system operates in one RF band for uplink RF signals (e.g., handset to base station) and a separate RF band for downlink RF signals (e.g., base station to handset). A time-division duplex radio system operates in a single RF band, frequently alternating between uplink and downlink RF signals within the single band. An RF band typically spans a range of frequencies (e.g., 10 to 1000 MHz per band), and the actual signal transmission and reception may be in subbands or channels of such bands, which may overlap. Alternatively, two widely spaced RF bands may be used for signal transmission and reception, respectively.

[0005] More advanced radio systems, such as some mobile phone systems, can operate across multiple RF bands to transmit and receive signals. Such multi-band operation enables a single radio system to be interoperable with different international frequency allocations and signal coding systems (e.g., 5G, LTE, CDMA, GSM).

[0006] Some advanced radio systems use MIMO (multiple-input, multiple-output) technology to multiply the capacity of a radio link by using multiple transmit and receive antennas to exploit multipath propagation. The same MIMO architecture can be used to improve the signal-to-noise ratio (SNR) of a radio link rather than its capacity. For example, some advanced radio systems use a phased array antenna architecture with multiple antenna elements that enable beam steering to improve transmission range through increased antenna directivity.

[0007] To accommodate multiple frequencies and multiple protocols (especially MIMO), as well as beam steering, a system component (e.g., a user's mobile phone, sometimes referred to as "user equipment" or UE) may include multiple antennas. For example, Fig. 1 is a block diagram of a prior art RF front end (RFFE) 100 in a single transmitter and four receiver configuration. In the example shown, a multi-path switch 102 is coupled to multiple antennas (four in this example) ANT1-ANT4, to a power amplifier PA, and to multiple low-noise amplifiers (four in this example) LNA1-LNA4. The multi-path switch 102 is configured to allow the connection of any amplifier (PA or LNA) to any antenna ANT1-ANT4, thereby enabling both the transmission and reception of RF signals. In some embodiments, the multi-path switch 102 may include circuitry designed to separate transmitted and received signals, such as duplexers.

[0008] State of the Art RF systems operating in the low GHz range manufacture one or more antenna elements in a planar array off-die with respect to integrated circuit (IC) chips embodying an RFFE. It is common practice to co-locate each RFFE IC near one or more antenna elements by stacking the RFFE ICs in parallel planes with respect to the planar array of antenna elements to minimize link lengths and associated losses. Thus, for example, each planar array of antenna elements and each RFFE IC can be considered to be essentially "2.5" dimensional objects with appreciable X and Y dimensions, but relatively small Z dimensions. An RF transceiver, receiver, or transmitter may comprise a substrate (e.g.,a printed circuit board (PCB) having one or more antenna elements mounted in a first planar array on a surface, with one or more RFFE ICs, each with parallel XY dimensions (i.e., coaxial Z dimensions), mounted adjacent to one or more antenna elements. Each RFFE IC may be coupled to other ICs mounted on the substrate for modulation / demodulation of RF signals and general signal processing and control circuitry (noting that some of these pre-RFFE and / or post-RFFE functions may instead be embodied in an RFFE IC).

[0009] One problem encountered with such coplanar configurations of antenna elements and RFFE ICs is that, as RF frequencies increase, the XY size of the antenna elements decreases faster than the XY size of the associated RFFE IC dies or IC chips, to the point that at sufficiently high frequencies (e.g., above about 100 GHz), it may no longer be possible to place an RFFE IC sufficiently close to associated antenna elements on a PCB—essentially, the RFFE IC areas do not scale much with frequency, while the antenna element size and spacing do, so the total XY area of ​​the RFFE ICs exceeds the XY area of ​​the array of antenna elements.

[0010] Accordingly, there is a need for an antenna structure that can be arranged in close proximity with respect to an associated RFFE IC, regardless of the antenna element size. Summary

[0011] The present invention encompasses antenna structures that can be arranged in close proximity with an associated RFFE IC, regardless of the antenna element size. An antenna structure, including a grid or planar antenna or an array of antenna elements, is fabricated as part of or together with one or more associated RFFE ICs using three-dimensional (3D) stacks of IC dies, either directly or as part of an embedded die packaging technology.

[0012] Some embodiments include an IC including a substructure, a superstructure including multiple layers of dielectric, metallization layers, and conductive vias interconnecting the metallization layers, and at least one RF antenna element fabricated with the IC. In some embodiments, at least one of the RF antenna elements is configured to be electrically connectable to a corresponding RF antenna element in a second IC, wherein the IC and the second IC are coupled together using 3D IC stacking.

[0013] Some embodiments utilize embedded die packaging technology. For example, some embodiments include an embedded die package including at least one IC die and at least one RF antenna element fabricated together with the embedded die package and electrically connected to at least one of the at least one IC die.

[0014] Some embodiments include a combinable co-fabricated antenna element (CCAE) including at least one internally co-fabricated RF antenna element configured to be electrically connected to a corresponding RF antenna element in a second combinable co-fabricated antenna element, wherein the combinable co-fabricated antenna element and the second combinable co-fabricated antenna element are coupleable to each other via 3D IC stacking.

[0015] Some embodiments include a plurality of combinable co-manufactured antenna elements coupled together by 3D IC stacks such that the antenna elements form a grid antenna or comprise an array of antenna patches.

[0016] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Further features, objects, and advantages of the invention will become apparent from the description and drawings, as well as from the claims. DESCRIPTION OF THE DRAWINGS It shows / It shows: Fig. Figure 1 is a block diagram of a prior art RF front end (RFFE) in a single transmitter and four receiver configuration. Fig. 2A is a cross-sectional side view of an embodiment of an IC die according to the present invention along a YZ dimensional plane. Fig. Figure 2B is a cross-sectional side view of an embodiment of an embedded IC die package according to the present invention along a YZ dimensional plane. Fig. 3A is a front perspective view of a first embodiment of a 3D IC incorporating CCAEs according to the present invention. Fig. Figure 3B is a bottom-to-back perspective view of the stack of CCAEs in Fig. 3A. Fig. Figure 3C is a front view of the stack of CCAEs in Fig. 3A. Fig. 3D a side elevation view of the stack of CCAEs in Fig. 3A. Fig. 3E a top view of the stack of CCAEs in Fig. 3A. Fig. 4 is a top perspective view of a second embodiment of the present invention incorporating a dual stack of CCAEs. Fig. 5 is a plan view of a third embodiment of a stack of CCAEs. Fig. 6 is a plan view of a fourth embodiment of a stack of CCAEs. Fig. Figure 7 is a front elevation view of an alternative grid antenna configuration that may be manufactured as part of a CCAE. Fig. 8 is a front view of a fifth embodiment of a stack of CCAEs. Fig. 9 a plan view of a substrate, which may be, for example, a printed circuit board or a die module substrate (e.g., a thin-film tile). Fig. 10 illustrates a prior art wireless communication environment that includes various wireless communication systems and that may include one or more mobile wireless devices. Fig. 11 is a block diagram of a transceiver that could be used in a wireless device, such as a mobile phone, and that may advantageously incorporate an embodiment of the present invention to improve performance. Fig. 12 is a process flow diagram showing a method for manufacturing an integrated circuit. Fig. 13 is a process flow diagram showing a method of manufacturing an integrated circuit die package. Fig. 14 is a process flow diagram showing a first method for manufacturing a combinable co-manufactured antenna element. Fig. 15 is a process flow diagram showing a second method for manufacturing a combinable co-manufactured antenna element. Fig. 16 is a process flow diagram showing a third method for manufacturing a combinable co-manufactured antenna element. Fig. 17 is a process flow diagram showing a first method for manufacturing an antenna structure. Fig. 18 is a process flow diagram showing a second method for manufacturing an antenna structure.

[0017] The same reference symbols and designations in the various drawings indicate the same elements. DETAILED DESCRIPTION

[0018] The present invention encompasses antenna structures that can be arranged in close proximity with an associated RFFE IC, regardless of the antenna element size. An antenna structure, including a grid or planar antenna or an array of antenna elements, is fabricated as part of or together with one or more associated RFFE ICs using three-dimensional (3D) stacking technology, either directly or as part of an embedded chip packaging technology. MOSFET IC manufacturing

[0019] It may be useful to review how a two-dimensional (2-D) metal-oxide-semiconductor field-effect transistor (MOSFET) circuit is fabricated using a conventional silicon-on-insulator (SOI) process. Starting from a wafer substrate, such as silicon, an insulating buried oxide (BOX) layer is formed, upon which an active layer, typically of doped silicon, is formed. On and / or within the active layer, one or more MOSFET structures are formed within the confines of a single IC die (unsingulated at this point). Each wafer substrate typically contains hundreds to thousands of unsingulated dies.

[0020] A MOSFET structure generally includes a mask-shaped channel, a gate, a source, a drain, and isolation regions. The current IC manufacturing process is generally considered front-end-of-line (FEOL), where individual components (transistors, capacitors, resistors, inductors, etc.) are patterned in or on the active layer. FEOL generally covers everything up to the deposition of metal interconnect layers and can be considered the fabrication of tool substructures.

[0021] After the final FEOL step, a wafer contains multiple die regions, each containing isolated transistors without interconnect conductors. The back-end-of-line (BEOL) is the second stage of IC manufacturing, where the individual devices (transistors, capacitors, resistors, inductors, etc.) within a die region are connected with conductors formed as part of or spanning one or more metal interconnect layers. BEOL involves the formation of electrical contacts (pads), vias, insulating layers (dielectrics), metallization layers, and die-to-package interconnect locations. In some applications, through-substrate vias (TSVs) can be formed, with each TSV passing through the wafer substrate between the active layer and a connection point, such as a bond pad.

[0022] Some BEOL manufacturing processes or post-BEOL manufacturing processes (e.g., as part of an outsourced semiconductor assembly and outsourced test) allow for the deposition of a redistribution layer (RDL), which is generally an additional patterned conductive layer (usually aluminum) on an IC die that provides the input / output (I / O) pads of an IC die for coupling to other locations on the chip and / or to another IC die and / or to special packaging structures. The RDL can be formed on the "top" BEOL buildup of an IC die. In some cases (e.g., for single-layer transfer or SLT die structures), the RDL can be formed adjacent to a primary circuit layer containing MOSFET active regions after removing the wafer substrate and reattaching the primary circuit layer and top structure to a handle wafer.

[0023] Thus, a MOSFET IC die is essentially formed in two parts: a "lower" FEOL substructure and an "upper" BEOL superstructure, formed in a die area of ​​a substrate. After FEOL and BEOL processing, the wafer can undergo a series of additional process steps, including dicing, testing, and packaging, to form multiple IC dies. 3D stacking technology

[0024] The electronics industry continues to strive for ever-increasing electronic functionality and performance in a wide variety of products, including (by way of example only) personal electronics (e.g., "smart" watches and fitness wearables), PCs, tablet computers, wireless networking components, televisions, "set-top" boxes for cable systems, radar systems, and mobile phones. Increased functionality and / or performance typically results in more transistors and other electronic components on an IC die. While the number of transistors per unit area of ​​an IC die has increased over time as IC manufacturing process nodes have reduced device dimensions, the 2D "footprint" of some IC dies has not decreased at the same rate, primarily due to the use of more (albeit smaller) transistors to implement increased functionality and / or performance.The 2D footprint of an IC die is a constraint on reducing the size of modules and circuit boards within products.

[0025] To reduce the 2D footprint of an IC die, a number of 3D technologies have been developed, focusing on stacking and bonding aligned IC dies originally fabricated on different wafers (also known as wafer-to-wafer bonding), stacking and bonding individual IC dies onto non-isolated IC dies on a wafer (also known as die-to-wafer bonding), and stacking and bonding a single IC die onto another IC die (also known as die-to-die bonding).Such a technology can be referred to as "hybrid bonding" (HB), in which the circuitry of a 2D IC is divided and fabricated on different wafers or dies and then stacked vertically in a 3D structure, with, for example, approximately half of the circuitry formed on a first, or "bottom," wafer / die and approximately half of the circuitry formed on a second, or "top," wafer or die, which is then bonded to the bottom wafer / die. When bonding the two wafers / dies, both dielectric materials (e.g., silicon dioxide, SiCN, SiCOH, and / or similar dielectrics) and conductive interconnect materials (e.g., copper, aluminum, and / or their alloys) are generally used. Generally, a high density of interconnects between the top and bottom wafers / dies is desirable to achieve good communication between them.The interconnect pitch can be between approximately 0.2 and 10 µm, and preferably in the range of approximately 2-5 µm. HB technology has a proven high trace density, is a planar technology that requires no underfill or carrier wafer integration, and enables the formation of traces between two IC wafers / dies during the bonding phase of processing at relatively low temperatures (e.g., < 400 °C).

[0026] Another technology for reducing the 2D footprint of an IC die uses 3D embedded chip packaging. For example, one or more individual IC dies can be embedded on one or more substrate layers (typically an organic material), with conductive pillars (e.g., copper) connecting to other IC dies on stacked substrate layers or to connection points (e.g., bond pads, bumps, or pins) for external connections. The substrate layer on which an IC is embedded essentially functions as a printed circuit board, with the advantage that it can be further processed to connect embedded ICs to other ICs on the same substrate layer or on different substrate layers, as well as to other types of components (e.g., capacitors, inductors, sensors, MEMS devices, etc.). Connections can be made using conventional BEOL processes (e.g.,Sequential formation of one or more dielectric or conductive layers around an embedded IC die, including formation of interlayer connections such as vias, or by laminating multiple layers configured to receive an embedded IC die and containing horizontal and vertical conductors. After initial lamination, additional laminated layers may be added and / or conventional BEOL processes may be applied post-lamination to form additional structures, layers, and / or connection points. Co-fabricated antenna arrays

[0027] Embodiments of the present invention utilize 3D IC stacking or 3D embedded die packaging together with BEOL or post-embedded processes to collectively fabricate an antenna structure, which may include a grid or planar antenna or an array of antenna elements.

[0028] For example, Fig. 2A is a cross-sectional side view of an embodiment of an IC die 200 according to the present invention, taken along a YZ dimension plane. The X dimension is on the side. A conventional MOSFET substructure 202 includes a wafer substrate 204 (e.g., Si, high-resistivity Si, etc.), an insulating buried oxide (BOX) layer 206, and an active layer 208, typically of doped silicon, generally containing multiple MOSFETs. As described above, the substructure 202 is fabricated as part of an FEOL process.

[0029] Formed on the substructure 202 is a superstructure 210 comprising a plurality of successive layers of dielectric layers 212, metallization layers 214-222, and conductive vias 226 interconnecting the metallization layers 214-222. The dielectric layers 212 are shown as substantially continuous regions surrounding the metallization layers 214-222 and conductive vias 226. As described above, the superstructure 210 is fabricated as part of a BEOL process.

[0030] In some embodiments, the substructure 202 may be as thick as about 200 μm (hence the dashed line to indicate a much larger possible relative thickness) and as thin as about 2 μm (e.g., when the wafer substrate 204 is thinned). In some embodiments, the top structure 210 may be as thick as about 9 μm.

[0031] In the illustrated example, RF antenna elements 230-234 are also formed from conductive material as part of the BEOL process. The antenna elements 230-234 are generally formed using the same materials (e.g., Cu, Al) and sequential processes as the metallization layers 214-222 and conductive vias 226. In Fig. 2A, the antenna elements 230-234 are shaded differently than the metallization layers 214-222 only for contrast purposes, but in some applications, the antenna elements 230-234 may actually be fabricated with different materials at the expense of additional masking steps and time.

[0032] Electrically connected to the antenna elements 230-234 are optional TSVs 236, which are coupled to substrate bond pads 238, enabling connections to at least the antenna elements 230-234 from the "bottom" of the IC die 200. Optional vias 240 also couple the antenna elements 230-234 to superstructure bond pads 242, enabling connections to at least the antenna elements 230-234 from the "top" of the IC die 200.

[0033] Fig. 2A does not show the X dimension of the IC die 200, but as will become apparent from the following figures, the antenna elements 230-234 may extend along the X dimension of the IC die 200.

[0034] In the depicted example, metallization layer 216 is electrically coupled to antenna element 232, and metallization layer 218 is electrically coupled to antenna element 234. Antenna element 230 may be coupled to a metallization layer elsewhere along the X-dimension of IC die 200. Active layer 208 may include RFFE components, such as a multi-path switch, one or more low-noise amplifiers (LNA), and / or one or more power amplifiers (PA). Thus, IC die 200, as shown in Fig. 2A illustrates three complete antenna elements 230-234 and may include the necessary RFFE components to replace an RFFE die and an external antenna element. Note that the designed size of the antenna elements 230-234 may be adjusted for a particular frequency range, if needed, generally being designed to be smaller as the frequency increases. In some embodiments, an IC die 200 may be fabricated without active circuitry but with one or more antenna elements (see below for details on using such a structure).

[0035] As another example, Fig. 2B is a cross-sectional side view of one embodiment of an embedded IC die package 250 according to the present invention, taken along a YZ dimensional plane. An IC die 252 is embedded, in a known manner, within a stack of planar lamination layers 254 (each layer indicated by a dashed line) that include horizontal (in-plane) conductors 256 and vertical (perpendicular to the plane) conductors or vias 258. In the illustrated example, some of the horizontal conductors 256 contact chip pads 260 that form part of the IC die 252.

[0036] An antenna element 262 is fabricated (i.e., formed simultaneously) by portions of the horizontal and vertical conductors (however, the antenna element 262 is shaded differently than the horizontal and vertical conductors 256, 258 for contrast purposes). Bond pads 264 are shown formed on the top and bottom surfaces of the lamination layers 254, enabling connections to at least the antenna element 262. The antenna element 262 may be coupled to the IC die 252 by one or more horizontal and / or vertical conductors 256, 258. The finished embedded IC die package 250 may then be used like an integrated circuit and attached to other structures, such as spacers, die modules, or printed circuit boards.

[0037] Fig. 2B does not show the X dimension of the embedded IC die package 250, but as will become apparent from the following figures, the antenna element 262 may extend along the X dimension of the embedded IC die package 250.

[0038] The antenna element 262 is thus formed outside the embedded IC die 252, but encompassed and integrally formed within the embedded IC die package 250. In some applications, more than one antenna element 262 may be formed within an embedded IC die package 250. In some applications, more than one IC die 252 may be embedded within the same embedded IC die package 250. In some embodiments, the embedded IC die package 250 may be as thick as about 400-500 µm. In some embodiments, a die package such as the embedded IC die package 250 may be fabricated without an embedded IC die 252, but with one or more antenna elements 262 (see below for details on using such a structure).

[0039] In the illustrated example, the antenna element 262 is coupled to the IC die 252 by a horizontal conductor 256a. The antenna element 262 may also be coupled to the IC die 252 at a different location along the X-dimension of the embedded IC die package 250. The IC die 252 may include RFFE components, such as a multi-way switch, one or more LNAs, and / or one or more PAs. Thus, the embedded IC die package 250, as shown in Fig. 2B illustrates a complete antenna element 262 and may include the necessary RFFE components to replace an RFFE die and an external antenna element. As will be appreciated, the designed size of the antenna element 262 may be adjusted for a particular frequency range, if needed, and is generally designed to be smaller as the frequency increases.

[0040] It should be noted that one of the Fig. 2A and Fig. 2B can provide close proximity of an antenna element to an active circuit region (e.g., co-manufactured IC MOSFETs or an embedded IC die). Close proximity is particularly useful at high frequencies, especially above approximately 100 GHz, to reduce parasitic resistances, inductances, and capacitances. Furthermore, the Fig. 2A and Fig. 2B visually indicates that the antenna element sizing is limited only by the X (sideways) and Z axes, while the co-fabricated RFFE IC circuit can extend along either or both of the X and Y axes without regard to the size of the antenna element(s), which is particularly useful for antenna arrays designed for frequencies at or above approximately 100 GHz. Essentially, the co-fabricated RFFE IC circuit is perpendicular (and not coplanar) with respect to the antenna elements. Combinable, co-manufactured antenna elements

[0041] For the purposes of this disclosure, the terms “CCAE” and “combinable co-manufactured antenna element” are collective terms for (1) an IC die 200 that incorporates all or a portion of at least one internally co-manufactured antenna element (e.g., antenna elements 230-234 in Fig. 2A) and may include MOSFET circuits, and / or (2) an embedded IC die package 250 that includes all or a portion of at least one co-manufactured antenna element (e.g., antenna element 262 in Fig. 2B) and may include an embedded IC package 252.

[0042] An important aspect of the present invention is that combinable co-manufactured antenna elements (CCAEs) can be combined using 3D stacking technology to form a larger antenna structure, such as a grid antenna or an array of antenna elements. In some embodiments, the CCAEs do not all need to be the same type. For example, a grid antenna or an array of antenna elements can be constructed using a combination of IC dies 200 that include at least one internally co-manufactured antenna element and embedded IC packages 250 that include at least one co-manufactured antenna element. Stacking can be achieved using any of the technologies described above or equivalents, including (but not limited to) wafer-to-wafer bonding, die-to-wafer bonding, die-to-die bonding, and 3D embedded die packaging.One advantage of such stacking is that the 2D footprint of the stacked CCAEs is significantly reduced by a factor of the number of CCAEs within a stack. For example, six CCAEs stacked vertically (along the Z direction) would have the same 2D footprint (XY footprint) as a single CCAE.

[0043] Fig. 3A is a front perspective view of a first embodiment of a 3D IC including CCAEs 302a-302f according to the present invention. In the illustrated example, the upper and lower CCAEs 302a, 302f include only a co-manufactured antenna element (i.e., no active circuitry), while the inner CCAEs 302b-302e of the stack each include respective active circuit regions 304b-304e (which would be in the form of a portion of active circuitry, such as MOSFETs for an IC die 200, and in the form of an entire IC in the case of an embedded IC die package 250). The CCAEs are stacked such that internal antenna elements (e.g., antenna element 230 in Fig. 2A, the antenna element 262 in Fig. 2B) are aligned and electrically coupled (e.g., by bonding aligned bond pads 264 in the case of embedded IC die packages 250 or aligned pairs of substrate bond pads 238 and overlay bond pads 242 in the case of IC dies 200). To avoid clutter, vias between the CCAEs 302a-302f are not shown.

[0044] In the depicted example, the interconnected antenna elements of CCAEs 302a-302f form a grid antenna 306. If the manufacturing process allows for sufficiently dense conductive patterns for the co-manufactured antenna elements within each CCAE, the interconnected antenna elements of CCAEs 302a-302f may form an antenna that comprises—or closely approximates—a solid planar antenna. One advantage of locating the grid antenna 306 laterally (e.g., in the XZ plane) is that when the stack of CCAEs 302a-302f is mounted in a module or on a PCB, the generally orthogonal grid antenna 306 can be positioned to receive and transmit RF signals to the side of a product, such as the edge of a mobile phone, where RF signal passage may be less obstructed by other product structures and circuitry.

[0045] Fig. Figure 3B is a bottom-to-back perspective view of the stack 300 of CCAEs 302a-302f in Fig. 3A. In the illustrated example, vias 308 are shown between the CCAEs 302a-302f, but connections between the grid antenna 306 and the active circuit regions 304b-304e are omitted.

[0046] Fig. 3C is a front view of the stack 300 of CCAEs 302a-302f in Fig. 3A. This view shows the X-dimensional span of the antenna elements comprising grid antenna 306. Note that while grid antenna 306 is shown as a single grid, in some embodiments, the single illustrated grid antenna 306 may be divided into two or more grid antennas. For example, the illustrated grid antenna 306 may be divided into two coplanar, spaced-apart grid antennas by simply reconfiguring which CCAEs 302a-302f are connected together.

[0047] Fig. 3D a side elevation view of the stack 300 of CCAEs 302a-302f in Fig. 3A. This view shows electrical connections 310 between the grid antenna 306 and the active circuit regions 304b-304e, but the vias between the CCAE's 302a-302f are not labeled to avoid clutter. Also shown is an optional second grid antenna 306', which is fabricated in the same manner as the grid antenna 306.

[0048] Fig. 3E is a plan view of the stack 300 of CCAEs 302a-302f in Fig. 3A. The uppermost active circuit region 304b is shown in a dashed phantom outline. Also shown are optional grid antennas 306a-306c, which can be manufactured together or co-manufactured in the same manner as grid antenna 306; the number of additional grid antennas 306a-306c, if any, depends on a particular design objective. Electrical connections 310 between grid antenna 306 and active circuit regions 304b-304e (see Fig. 3A-3D) are shown in two different shades, indicating that the connections can be made at different layers of the stack 300 of CCAEs 302a-302f.

[0049] Fig. 4 is a top perspective view of a second embodiment of the present invention including a dual stack 400a, 400b of CCAEs 402a-402f. Each stack 400a, 400b includes respective side-by-side grid antennas 406a1, 406a2 and 406b1, 406b2 formed from respective portions of the co-manufactured antenna elements within the CCAEs 402a-402f. In alternative embodiments, one or more of the stacks 400a, 400b may include only one grid antenna or more than two grid antennas. The stacks 400a, 400b may be directly connected using a 3D stacking technology described above or an equivalent technology, or via a conventional electrical interface (e.g., an interposer) for routing electrical connections between one IC-like structure to another IC-like structure. For example, in Fig. 4 an intermediate piece may be positioned at the interface 408 between the stack 400a and the stack 400b.

[0050] In the illustrated example, each CCAE stack 400a, 400b includes four active circuit regions, each of which would be in the form of a portion of active circuitry, such as MOSFETs for an IC die 200, and in the form of an entire IC in the case of an embedded IC die package 250. In the depicted example, two adjacent pairs of active circuit regions 404c1, 404c2 and 404d1, 404d2 are located within the respective CCAEs 402c, 404d.

[0051] In an alternative embodiment, the Fig. 4 may be constructed using four "unit cells," each comprising a stack of CCAEs 402a-402f and associated active circuit regions (e.g., 404c1 and 404d1), but without adjacent pairs of active circuit regions or dual antenna elements (effectively splitting the illustrated CCAE stacks 400a, 400b along dashed line 410). Connections may be made between the unit cells in the horizontal and vertical directions, for example, by an interposer positioned at the interface 408 between the upper unit cells and the lower unit cells.

[0052] The Fig. The configuration illustrated in Figure 4 also shows that an IC die or IC die package (e.g. IC die 200 from Fig. 2A or IC die package 250 from Fig. 2B) may include more than one antenna element and that an embedded IC die package 250 may include more than one embedded IC die 252, each with all or a portion of at least one associated antenna element.

[0053] Fig. 5 is a top view of a third embodiment of a stack 500 of CCAEs. In the illustrated example, there are three active circuit regions 504a-504c (shown in dashed phantom outline) and four grid antennas 506a-506d. The illustrated configuration shows that grid antennas can be formed between active circuit regions (which, for this example, would be in the form of three spaced-apart regions of active circuitry for an IC die 200 and in the form of three different ICs in the case of an embedded IC die package 250). The illustrated configuration also shows that multiple grid antennas (e.g., grid antennas 506b, 506c) may be coupled to an active circuit region 504b through connectors 510 and that an antenna element (e.g., grid antenna 506c) may be coupled to more than one active circuit region (e.g., active circuit regions 504b, 504c).As noted above, in some embodiments, an antenna element may not connect to an active circuit region within a particular CCAE.

[0054] Fig. 6 is a top view of a fourth embodiment of a stack 600 of CCAEs. In the depicted example, there is one active circuit region 604 (shown in dashed phantom outline) and four grid antennas 506a-506d (connectors from the active circuit region 604 to the grid antennas 506a-506d have been omitted for clarity). The illustrated configuration shows that the grid antennas 506a-506d may be formed with a non-uniform pitch (in this example, non-uniform in the Y dimension). As noted above, in some embodiments, an antenna element may not connect to an active circuit area within a particular CCAE.

[0055] The single grid antenna, which is Fig. 3A can support the reception and / or transmission of dual-polarized signals. However, it may be desirable to use separate grid antennas, for example, to increase isolation between polarizations. Fig. 7 is a front elevation view of an alternative grid antenna configuration that may be fabricated as part of a CCAE. In the illustrated example, a first grid antenna 702 is fabricated with primarily vertical elements, and a second antenna 704 is fabricated with primarily horizontal elements and spaced from the first grid antenna 702 (for simplicity, the associated structure including any active circuitry is omitted). The two separate antenna grids 702, 704 can thus support dual polarization, with the first grid antenna 702 being most sensitive to vertically polarized RF signals 706 and the second grid antenna 704 being most sensitive to horizontally polarized RF signals.

[0056] Fig. 8 is a front view of a fifth embodiment of a stack 800 of CCAEs 802a-802f. In the depicted example, each CCAE 802a-802f includes an active circuit region 804a-804f. Further, rather than forming connected antenna elements within each CCAE 802a-802f, a plurality of spaced-apart antenna elements or "patches" 806 within each CCAE 802a-802f are fabricated together and electrically connected to an associated active circuit region 804a-804f. When the CCAEs 802a-802f are stacked, the antenna patches 806 form an array of antenna elements that can be used as a phased array antenna. In general, it is useful to space the antenna patches by less than or equal to half the wavelength of a target frequency (e.g., for 150 GHz RF signals, the target frequency wavelength is about 2 mm, so the spacing Sbetween the antenna patches should be about S= 1 mm).As is known in the art, an array of antenna elements can be used with a phased array RF circuit to enable beam steering.

[0057] While the Fig. 3A-3E and 4-8 illustrate combinations of CCAEs, in some applications a single CCAE may be used, for example, as an integrated antenna and RFFE IC, where the co-manufactured antenna element is sufficiently large to function adequately in a selected frequency range without having to increase the size of the antenna structure by combining CCAEs. Circuit designs

[0058] Circuits and devices according to the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be enclosed in IC packages and / or modules for ease of handling, manufacturing, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into a package.The ICs and / or modules are then typically combined with other components, often on a printed circuit board (PCB), to form part of a final product, such as a mobile phone, laptop, or electronic tablet, or to form a higher-level module that can be used in a variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless.

[0059] As an example of further integration of embodiments of the present invention with other components, Fig. 9 is a top view of a substrate 900, which may be, for example, a printed circuit board or a die module substrate (e.g., a thin-film tile). In the depicted example, the substrate 900 includes a plurality of ICs 902a-902d having pads 904 that would be interconnected by conductive vias and / or traces on and / or within the substrate 900 or on the opposite (back) surface of the substrate 900 (to avoid clutter, the conductive surface traces are not shown and not all pads are labeled). The ICs 902a-902d may embody, for example, signal switches, active filters, amplifiers (including one or more LNAs), and other circuits. For example, IC 902b may be a stack of CCAEs, as shown in FIGS. Fig. 3A-3E and 4-8.

[0060] The substrate 900 may also include one or more passive devices 906 embedded in, formed on, and / or attached to the substrate 900. Although shown as generic rectangles, the passive devices 906 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (including, for example, MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., connected by conductive traces on or in the substrate 900 to other passive devices 906 and / or the individual ICs 902a-902d. The front or back of the substrate 900 may be used as a site for forming other structures. System aspects

[0061] Embodiments of the present invention are useful in a variety of larger radio RF circuits and systems for performing a variety of functions, including (but not limited to) impedance matching circuits, RF PAs, RF LNAs, phase shifters, attenuators, antenna beam steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0062] Radio system use includes wireless RF systems (including base stations, relay stations, and handheld transceivers) that use various technologies and protocols, including various types of Orthogonal Frequency Division Multiple Access (“OFDM”), Quadrature Amplitude Modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G New Radio, 6G, and WiFi (e.g., 802.11 a, b, g, ac, ax, be) protocols, as well as other radio communications standards and protocols.

[0063] As an example of the use of a wireless RF system, Fig. 10 illustrates a prior art wireless communications environment 1000 including various wireless communications systems 1002 and 1004, and which may include one or more mobile wireless devices 1006. A wireless device 1006 may be a mobile phone, a wirelessly capable computer or tablet, or other wireless communications unit or device. A wireless device 1006 may also be referred to as a mobile station, a user equipment, an access terminal, or other terminology known in the telecommunications industry.

[0064] A wireless device 1006 may be capable of communicating with multiple wireless communication systems 1002, 1004 using one or more telecommunications protocols, such as those listed above. A wireless device 1006 may also be capable of communicating with one or more satellites 1008, such as navigation satellites (e.g., GPS) and / or telecommunications satellites. The wireless device 1006 may be equipped with multiple antennas, external and / or internal, for operating at different frequencies and / or for providing diversity against harmful path effects, such as fading and multipath interference.

[0065] The wireless communication system 1002 may, for example, be a CDMA-based system that includes one or more base station transceivers (BSTs) 1010 and at least one central switching center (SC) 1012. Each BST 1010 provides wireless radio communication for wireless devices 1006 within its coverage area. The SC 1012 couples to one or more BSTs 1010 in the wireless system 1002 and provides coordination and control for these BSTs 1010.

[0066] The wireless communication system 1004 may, for example, be a TDMA-based system that includes one or more transceiver nodes 1014 and a network center (NC) 1016. Each transceiver node 1014 provides wireless radio communication for wireless devices 1006 within its coverage area. The NC 1016 couples to one or more transceiver nodes 1014 in the wireless system 1004 and provides coordination and control for these transceiver nodes 1014.

[0067] In general, each BST 1010 and each transceiver node 1014 is a fixed station that provides communication coverage for wireless devices 1006 and may also be referred to as base stations or other terminology known in the telecommunications industry. The SC 1012 and the NC 1016 are network entities that provide coordination and control for the base stations and may also be referred to by other terminology known in the telecommunications industry.

[0068] An important aspect of any wireless system, including those in Fig. 10 systems, lies in the details of how the component elements of the system behave. Fig. 11 is a block diagram of a transceiver 1100 that could be used in a wireless device, such as a cellular phone, and that may advantageously incorporate an embodiment of the present invention to improve performance. As illustrated, the transceiver 1100 includes a mix of analog RF circuitry for directly transmitting and / or converting signals on an RF signal path, analog non-RF circuitry for operational requirements outside the RF signal path (e.g., for bias voltages and switching signals), and digital circuitry for control and user interface requirements. In this example, a receiver path Rx includes RF front-end (RFFE), intermediate frequency (IF) block, back-end, and baseband sections (note that in some implementations, the distinction between the sections may vary).The various illustrated sections and circuit elements may be implemented in one chip or multiple IC dies. For example, in the illustrated example, the RF front-end may include an RFFE module and a mixing block, which may be embodied in (or as part of) different IC dies or modules. The various chips and / or modules may be interconnected by transmission lines T. IN and T OUT (e.g. microstrip, coplanar waveguide or an equivalent structure or circuit), one or both of which may have, for example, a 50Ω impedance.

[0069] The receiver path Rx receives wireless RF signals through at least one antenna 1102 and a switching unit 1104, which may be implemented with active switching devices (e.g., field-effect transistors or FETs) and / or with passive devices implementing frequency-domain multiplexing, such as a diplexer or duplexer. The antenna 1102 may be a grid antenna or an array of antenna elements in accordance with the teachings of this disclosure. An RF filter 1106 directs desired received RF signals to at least one LNA 1108a, whose output from the RFFE module is coupled to at least one LNA 1108b in the mixer block (in this example, through the transmission line T IN). The LNA(s) 1108b may provide buffering, input matching, and reverse isolation. The switching unit 1104, the RF filter 1106, and the at least one LNA 1108a, as well as other circuitry within the mixer block and / or the IF block, may be fabricated as part of an active circuit region of a CCAE.

[0070] The output of the LNA(s) 1108b is combined in a corresponding mixer 1110 with the output of a first local oscillator 1112 to generate an IF signal. The IF signal may be amplified by an IF amplifier 1114 and subjected to an IF filter 1116 before being applied to a demodulator 1118, which may be coupled to a second local oscillator 1120. The demodulated output of the demodulator 1118 is converted to a digital signal by an analog-to-digital converter 1122 and provided to one or more system components 1124 (e.g., video graphics circuitry, sound circuitry, storage devices, etc.). The converted digital signal may represent, for example, video or still images, sounds, or symbols, such as text or other characters.

[0071] In the illustrated example, a transmitter path Tx includes baseband, back-end, IF block, and RF front-end sections (again, in some implementations, the distinction between sections may vary). Digital data from one or more system components 1124 is converted to an analog signal by a digital-to-analog converter 1126, the output of which is applied to a modulator 1128, which may also be coupled to the second local oscillator 1120. The modulated output of the modulator 1128 may be subjected to an IF filter 1130 before being amplified by an IF amplifier 1132. The output of the IF amplifier 1132 is then combined with the output of the first local oscillator 1112 in a mixer 1134 to generate an RF signal.The RF signal may be amplified by a driver 1136, whose output is coupled to a power amplifier (PA) 1138 (in this example via the transmission line T. OUT ). The amplified RF signal may be coupled to an RF filter 1140, the output of which is coupled to at least one antenna 1102 via switching unit 1104. Switching unit 1104, RF filter 1140, and PA 1138, as well as other circuitry, may be fabricated as part of an active circuit region of a CCAE.

[0072] The operation of the transceiver 1100 is controlled in a known manner by a microprocessor 1142, which interacts with system control components 1144 (e.g., user interfaces, memory / storage devices, application programs, operating system software, power control, etc.). In addition, the transceiver 1100 generally includes other circuitry, such as a bias circuit 1146 (which may be distributed throughout the transceiver 1100 near transistor devices), electrostatic discharge (ESD) protection circuitry, test circuitry (not shown), factory programming interfaces (not shown), etc.

[0073] For example, in modern transceivers, there are often more than one receiver path (Rx) and one transmitter path (Tx) to accommodate multiple frequencies and / or signaling modalities. Furthermore, as should be apparent to one of ordinary skill in the art, some components of the transceiver 1100 may be positioned in a different order (e.g., filters) or omitted. Other components may (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.

[0074] Embodiments of the present invention reduce the sizing and spacing between antenna elements and associated active circuit regions, independent of the IC die area, by substantially co-fabricating RFFE IC circuitry perpendicular to (rather than coplanar with) the antenna elements, thereby improving performance. Embodiments of the present invention further enable grid antennas or an array of antenna elements to be sized as may be required for operation in high frequency ranges (e.g., at or above about 100 GHz) and enable a small 2D footprint. As one of ordinary skill in the art will understand, a system architecture is advantageously impacted by the present invention in critical ways, including reduced parasitics, better range, better reception, lower power, longer battery life, and wider bandwidth. Methods

[0075] Another aspect of the invention includes methods for manufacturing integrated circuits that include a co-manufactured RF antenna element. For example, Fig. 12 illustrates a process flow diagram 1200 illustrating a method of fabricating an integrated circuit, including: fabricating a substructure (block 1202); fabricating a superstructure including multiple layers of dielectric, metallization layers, and conductive vias interconnecting the metallization layers (block 1204); and fabricating at least one radio frequency antenna element together with the integrated circuit (block 1206).

[0076] Fig. 13 is a process flow diagram 1300 illustrating a method of manufacturing an integrated circuit die package, including: embedding at least one integrated circuit chip within an embedded die package (block 1302); and co-fabricating at least one radio frequency antenna element within the die package and electrically connected to at least one of the at least one integrated circuit chip (block 1304).

[0077] Additional aspects of the above methods may include one or more of the following: wherein the substructure includes an active layer including a plurality of MOSFETs; further including at least one of the at least one radio-frequency antenna element being electrically connectable to a corresponding radio-frequency antenna element in a second integrated circuit via 3D stacking of integrated circuits; wherein at least one of the at least one integrated circuit die includes a plurality of MOSFETs; and / or further including at least one of the at least one radio-frequency antenna element being electrically connectable to a corresponding radio-frequency antenna element in a second embedded die package via 3D stacking of integrated circuits.

[0078] Fig. 14 is a process flow diagram 1400 illustrating a first method for manufacturing a combinable co-manufactured antenna element, including manufacturing at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in a second combinable co-manufactured antenna element via 3D stacking of integrated circuits (block 1402).

[0079] Fig. 15 is a process flow diagram 1500 illustrating a second method for manufacturing a combinable co-manufactured antenna element, including manufacturing an integrated circuit package including at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in a second combinable co-manufactured antenna element via 3D stacking of integrated circuits (block 1502).

[0080] Fig. 16 is a process flow diagram 1600 illustrating a third method for manufacturing a combinable co-manufactured antenna element, including manufacturing a die package including at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in a second combinable co-manufactured antenna element via 3D stacking of integrated circuits (block 1602).

[0081] Additional aspects of the above methods may include one or more of the following: wherein the combinable co-manufactured antenna element further includes an active circuit region; wherein the integrated circuit chip further includes an active layer including a plurality of MOSFETs; and / or wherein the embedded die package includes at least one integrated circuit chip and at least one of the at least one integrated circuit chip includes a plurality of MOSFETs.

[0082] Fig. 17 is a process flow diagram 1700 illustrating a first method of manufacturing an antenna structure including coupling a plurality of combinable co-manufactured antenna elements via 3D stacking of integrated circuits, wherein each combinable co-manufactured antenna element includes at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in another combinable co-manufactured antenna element (block 1702).

[0083] Fig.18 is a process flow diagram 1800 illustrating a second method of manufacturing an antenna structure including coupling a plurality of combinable co-manufactured antenna elements coupled together via 3-D stacking of integrated circuits, wherein each combinable co-manufactured antenna element includes at least one internally co-manufactured radio frequency antenna patch (block 1802).

[0084] Additional aspects of the above methods may include one or more of the following: wherein the electrically connected radio-frequency antenna elements from the plurality of combinable, co-manufactured antenna elements form a grid antenna; wherein each combinable, co-manufactured antenna element includes a plurality of radio-frequency antenna patches; wherein a combination of the radio-frequency antenna patches from the plurality of combinable, co-manufactured antenna elements forms an antenna array; wherein at least one of the plurality of combinable, co-manufactured antenna elements includes an active circuit region; wherein at least one of the plurality of combinable, co-manufactured antenna elements comprises an integrated radio-frequency circuit with the at least one internally co-manufactured radio-frequency antenna element;wherein at least one of the plurality of combinable, co-manufactured antenna elements comprises an embedded die package with the at least one internally co-manufactured radio-frequency antenna element; and / or wherein the internally co-manufactured radio-frequency antenna elements define a first plane, and wherein at least one of the plurality of combinable, co-manufactured antenna elements comprises: an active circuit region defining a second plane extending substantially perpendicular to the first plane; Manufacturing technologies & options

[0085] The term "MOSFET" as used in this disclosure includes any FET with an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates with a metal or metal-like, insulator, and / or semiconductor structure. The terms "metal" or "metal-like" include at least one electrically conductive material (such as aluminum, copper, or another metal, or highly doped polysilicon, graphene, or another electrical conductor), "insulator" includes at least one insulating material (such as silicon oxide or another dielectric material), and "semiconductor" includes at least one semiconductor material.

[0086] As used in this disclosure, the term "radio frequency" (RF) refers to an oscillation rate in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency can be the frequency of an electromagnetic wave or an alternating voltage or current in a circuit.

[0087] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. Furthermore, references to orientations and directions (e.g., "top," "bottom," "above," "below," "side," "vertical," "horizontal," etc.) refer to the example drawings and do not necessarily represent absolute orientations or directions.

[0088] Various embodiments of the invention may be implemented to meet a variety of specifications. Unless otherwise noted above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including, but not limited to, standard bulk silicon, high-resistance bulk silicon CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS).Unless otherwise stated above, embodiments of the invention may be implemented in other transistor technologies, such as bipolar junction transistors (BJTs), BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, MESFET, InP HBT, InP HEMT, FinFET, GAAFET, and SiC-based power device technologies, using 2D, 2.5D, and 3D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI- or SOS-based process, or when fabricated using processes that have similar characteristics. Fabrication in CMOS using SOI or SOS processes enables low-power circuits, the ability to withstand high-power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequencies up to and above 300 GHz).Monolithic IC implementation is particularly useful because parasitic capacitances can generally be kept low through careful design (or at least kept uniform across all units so that they can be compensated).

[0089] Voltage levels may be adjusted and / or voltage and / or logic signal polarities reversed depending on a particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS and enhancement-mode or depletion-mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, for example, by adjusting device sizes, serially "stacking" components (particularly FETs) to withstand larger voltages, and / or using multiple components in parallel to handle larger currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without substantially altering the functionality of the disclosed circuits. Conclusion

[0090] A number of embodiments of the invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order-independent and thus may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. Various activities described with respect to the methods identified above may be performed repetitively, serially, and / or in parallel.

[0091] It should be understood that the foregoing description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufacturers, or compositions of matter set forth in the following claims. (It should be noted that parenthesized designations of claim elements are provided for convenience in referring to such elements and do not, in and of themselves, indicate any particular required order or enumeration of elements; further, such designations may be reused in dependent claims as references to additional elements without being considered to initiate a conflicting characterization sequence.) QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 088,444

[0001]

Claims

[1] Integrated circuit that includes: (a) a substructure; (b) a superstructure including multiple layers of dielectric, metallization layers, and conductive vias interconnecting the metallization layers; and (c) at least one radio frequency antenna element manufactured together with the integrated circuit. [2] The device of claim 1, wherein the substructure includes an active layer including a plurality of transistors. [3] The device of claim 1, wherein at least one of the at least one radio frequency antenna element is configured to be electrically connectable to a corresponding radio frequency antenna element in a second integrated circuit, wherein the integrated circuit and the second integrated circuit are coupled to each other by means of 3-D stacking of integrated circuits. [4] The apparatus of claim 1, wherein the at least one radio frequency antenna element defines a first plane and the substructure includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [5] Embedded die package that includes (a) at least one integrated circuit; and (b) at least one radio frequency antenna element fabricated together with the embedded die package and electrically connected to at least one of the at least one integrated circuit chips. [6] The device of claim 5, wherein at least one of the at least one integrated circuit device includes a plurality of transistors. [7] The device of claim 5, wherein at least one of the at least one radio frequency antenna element is configured to be electrically connectable to a corresponding radio frequency antenna element in a second embedded die package, wherein the embedded die package and the second embedded die package are coupled to each other by means of 3D stacking of integrated circuits. [8] The apparatus of claim 5, wherein the at least one radio frequency antenna element defines a first plane and the integrated circuit package includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [9] A first combinable co-manufactured antenna element comprising at least one internally co-manufactured radio frequency antenna element configured to be electrically connectable to a corresponding internally co-manufactured radio frequency antenna element in a second combinable co-manufactured antenna element, wherein the first combinable co-manufactured antenna element and the second combinable co-manufactured antenna element are coupled to one another by means of 3D stacking of integrated circuits. [10] The apparatus of claim 9, wherein the first combinable co-manufactured antenna element further includes an active circuit region. [11] The apparatus of claim 9, wherein the first combinable co-manufactured antenna element further includes an active circuit region including a plurality of transistors. [12] The apparatus of claim 9, wherein the at least one internally co-manufactured radio frequency antenna element defines a first plane, and wherein at least one of the first and second combinable co-manufactured antenna elements includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [13] A plurality of combinable co-manufactured antenna elements coupled together by 3-D stacking of integrated circuits, each combinable co-manufactured antenna element including at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in another combinable co-manufactured antenna element. [14] The apparatus of claim 13, wherein the electrically connected radio frequency antenna elements of the plurality of combinable co-manufactured antenna elements form a grid antenna. [15] The apparatus of claim 13, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region. [16] The device of claim 15, wherein the active circuit region includes an active layer containing a plurality of transistors. [17] The apparatus of claim 13, wherein the at least one internally co-manufactured radio frequency antenna element defines a first plane, and wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [18] The apparatus of claim 13, wherein at least one of the plurality of combinable co-manufactured antenna elements includes a radio frequency integrated circuit including the at least one internally co-manufactured radio frequency antenna element. [19] The apparatus of claim 13, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an embedded die package including the at least one internally co-manufactured radio frequency antenna element. [20] A plurality of combinable, co-manufactured antenna elements coupled together by means of 3-D stacks of integrated circuits, each combinable, co-manufactured antenna element including at least one internally co-manufactured radio frequency antenna patch. [21] The apparatus of claim 20, wherein each combinable co-manufactured antenna element includes a plurality of radio frequency antenna patches. [22] The apparatus of claim 20, wherein a combination of the radio frequency antenna patches of the plurality of combinable co-manufactured antenna elements forms an antenna array. [23] The apparatus of claim 20, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region. [24] The device of claim 23, wherein the active circuit region includes an active layer containing a plurality of transistors. [25] The apparatus of claim 20, wherein the at least one internally co-manufactured radio frequency antenna patch defines a first plane, and wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [26] The apparatus of claim 20, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an integrated radio frequency circuit including the at least one internally co-manufactured radio frequency antenna patch. [27] The apparatus of claim 20, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an embedded die package including the at least one internally co-manufactured radio frequency antenna patch. [28] A method of manufacturing an integrated circuit, comprising: (a) producing a substructure; (b) forming a superstructure comprising multiple layers of dielectric, metallization layers, and conductive vias interconnecting the metallization layers; and (c) co-manufacturing at least one radio frequency antenna element with the integrated circuit. [29] The method of claim 28, wherein the substructure includes an active layer containing a plurality of transistors. [30] The method of claim 28, further comprising configuring at least one of the at least one radio frequency antenna element to be electrically connectable to a corresponding radio frequency antenna element in a second integrated circuit by 3-D stacking of integrated circuits. [31] The method of claim 28, wherein the at least one radio frequency antenna element defines a first plane and wherein the substructure includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [32] A method of manufacturing an integrated circuit die package, comprising: (a) embedding at least one integrated circuit component in an embedded die package; and (b) co-manufacturing at least one radio frequency antenna element within the embedded die package and electrically connecting it to at least one of the at least one integrated circuit die. [33] The method of claim 32, wherein at least one of the at least one integrated circuit device includes a plurality of transistors. [34] The method of claim 32, further comprising configuring at least one of the at least one radio frequency antenna element to be electrically connectable to a corresponding radio frequency antenna element in a second embedded die package by 3-D stacking of integrated circuits. [35] The method of claim 32, wherein the at least one radio frequency antenna element defines a first plane and wherein at least one integrated circuit device includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [36] A method for manufacturing a combinable co-manufactured antenna element, comprising manufacturing at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in a second combinable co-manufactured antenna element by means of 3D stacking of integrated circuits. [37] The method of claim 36, wherein the combinable co-manufactured antenna element further includes an active circuit region. [38] The method of claim 36, wherein the combinable co-manufactured antenna element further includes an active circuit region containing a plurality of transistors. [39] The method of claim 36, wherein the at least one internally co-manufactured radio frequency antenna element defines a first plane, and wherein at least one of the first and second combinable co-manufactured antenna elements includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [40] A method for manufacturing a combinable co-manufactured antenna element, comprising manufacturing an integrated circuit package including at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in a second combinable co-manufactured antenna element by means of 3D stacking of integrated circuits. [41] The method of claim 40, wherein the integrated circuit chip further includes an active layer containing a plurality of transistors. [42] The method of claim 40, wherein the at least one internally co-manufactured radio frequency antenna element defines a first plane, and wherein at least one of the first and second combinable co-manufactured antenna elements includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [43] A method for manufacturing a combinable co-manufactured antenna element, comprising manufacturing a die package including at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in a second combinable co-manufactured antenna element by means of 3D stacking of integrated circuits. [44] The method of claim 43, wherein the embedded die package includes at least one integrated circuit chip and at least one of the at least one integrated circuit chip includes a plurality of transistors. [45] The method of claim 43, wherein the at least one internally co-manufactured radio frequency antenna element defines a first plane, and wherein at least one of the first and second combinable co-manufactured antenna elements includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [46] A method for manufacturing an antenna structure comprising coupling a plurality of combinable co-manufactured antenna elements by means of 3D stacking of integrated circuits, wherein each combinable co-manufactured antenna element includes at least one internally co-manufactured radio frequency antenna element configured to be electrically connected to a corresponding radio frequency antenna element in another combinable co-manufactured antenna element. [47] The method of claim 46, wherein the electrically connected radio frequency antenna elements of the plurality of combinable co-manufactured antenna elements form a grid antenna. [48] ​​The method of claim 46, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region. [49] The method of claim 46, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region containing a plurality of transistors. [50] The method of claim 46, wherein the at least one internally co-manufactured radio frequency antenna element of the plurality of combinable co-manufactured antenna elements defines a first plane, and wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [51] The method of claim 46, wherein at least one of the plurality of combinable co-manufactured antenna elements includes a radio frequency integrated circuit including the at least one internally co-manufactured radio frequency antenna element. [52] The method of claim 46, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an embedded die package including the at least one internally co-manufactured radio frequency antenna element. [53] A method for manufacturing an antenna structure, comprising coupling a plurality of combinable, co-manufactured antenna elements coupled to one another by means of 3D stacking of integrated circuits, wherein each combinable, co-manufactured antenna element includes at least one internally co-manufactured radio frequency antenna patch. [54] The method of claim 53, wherein each combinable co-manufactured antenna element includes a plurality of radio frequency antenna patches. [55] The method of claim 53, wherein a combination of the radio frequency antenna patches of the plurality of combinable co-manufactured antenna elements forms an antenna array. [56] The method of claim 53, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region. [57] The method of claim 53, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region containing a plurality of transistors. [58] The method of claim 53, wherein the at least one internally co-manufactured radio frequency antenna patch of the plurality of combinable co-manufactured antenna elements defines a first plane, and wherein at least one of the plurality of combinable co-manufactured antenna elements includes an active circuit region defining a second plane extending substantially perpendicular to the first plane. [59] The method of claim 53, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an integrated radio frequency circuit including the at least one internally co-manufactured radio frequency antenna patch. [60] The method of claim 53, wherein at least one of the plurality of combinable co-manufactured antenna elements includes an embedded die package including the at least one internally co-manufactured radio frequency antenna patch.

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