SEMICONDUCTOR DEVICE

Abstract

The present invention provides a semiconductor device comprising a transistor section and a diode section, wherein the transistor section comprises a first gate-trough section arranged to be closest to the diode section, and a first mesa section touching the first gate-trough section and arranged between the first gate-trough section and the diode section below the first gate-trough section, a first floating region is provided, and the first mesa section has an uncovered region that does not overlap with the first floating region.

Description

BACKGROUND 1. TECHNICAL AREA

[0001] The present invention relates to a semiconductor device. 2. STATE OF THE ART

[0002] In the prior art, a semiconductor device is known which has a transistor such as an insulated gate bipolar transistor (IGBT) (see, for example, patent documents 1 to 4). State-of-the-art documents, patent documents Patent document 1: Japanese patent no. 6472714 Patent document 2: Japanese patent no. 4456013 Patent document 3: Japanese patent application publication no. 2020-21941 Patent document 4: Japanese patent application publication no. 2010-232627 GENERAL DISCLOSURE (Technical Task)

[0003] In a semiconductor device, it is preferable to suppress a snapback phenomenon. (Solution to the problem)

[0004] To solve the problems described above, one aspect of the present invention provides a semiconductor device. The semiconductor device can have a semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type. Each of the semiconductor devices described above can have one or more transistor sections having a collector region of a second conductivity type on the lower surface of the semiconductor substrate.

[0005] Each of the semiconductor devices described above can have one or more diode sections having a first-type conductivity cathode region on the lower surface of the semiconductor substrate, arranged alternately with the transistor sections in a first direction. In each of the semiconductor devices described above, each of the transistor sections can have:A plurality of trench sections arranged side-by-side in the first direction, each having one or more gate trench sections. In each of the semiconductor devices described above, each transistor section may have a plurality of mesa sections, which are regions arranged between the trench sections in the first direction. In any of the semiconductor devices described above, each transistor section may have a floating region of the second conductivity type, arranged for at least one of the gate trench sections and located below a lower end of the gate trench section. In each of the semiconductor devices described above, the one or more gate trench sections may have a first gate trench section arranged to be closest to the diode section.In each of the semiconductor devices described above, the plurality of mesa sections can include a first mesa section that touches the first gate-trench section and is located between the first gate-trench section and the diode section. In each of the semiconductor devices described above, a first floating region can be located below the first gate-trench section. In each of the semiconductor devices described above, the first mesa section can have an uncovered region that does not overlap with the first floating region.

[0006] In each of the semiconductor devices described above, the plurality of trench sections can include one or more blind trench sections. In each of the semiconductor devices described above, the first mesa section can be located between the first gate trench section and a first blind trench section. In each of the semiconductor devices described above, the first floating region located below the lower end of the first gate trench section may not extend to a region below the lower end of the first blind trench section.

[0007] In each of the semiconductor devices described above, the first floating area cannot touch the first blind trench section in plan view.

[0008] In each of the semiconductor devices described above, the plurality of trench sections can include a second blind trench section located on a side of the first gate trench section opposite the first blind trench section, and in each of the semiconductor devices described above, in the first direction, the distance between the first floating region and the second blind trench section can be smaller than the distance between the first floating region and the first blind trench section.

[0009] In each of the semiconductor devices described above, the first floating area can touch the second blind trench section in plan view.

[0010] In each of the semiconductor devices described above, the first mesa section can have a first-type conductivity-type emitter region that touches the upper surface of the semiconductor substrate, and In each of the semiconductor devices described above, the first mesa section can have a base region of the second conductivity type, which is located between the emitter region and the drift region. In each of the semiconductor devices described above, the first mesa section can have a longitudinal dimension in a second direction, and In each of the semiconductor devices described above, the first mesa section can have the uncovered area in an intermediate region between both ends of the emitter region in the second direction.

[0011] In each of the semiconductor devices described above, a plurality of uncovered regions, each of which is the uncovered region, can be arranged individually in the second direction in the intermediate region.

[0012] In each of the semiconductor devices described above, in the intermediate region, the total length of the plurality of uncovered regions in the second direction can be smaller than the total length of regions in the second direction that overlap with the first floating region.

[0013] In each of the semiconductor devices described above, the first mesa section can have a contact area of ​​the second conductivity type that touches the upper surface of the semiconductor substrate and is arranged alternately with the emitter area in the second direction. In each of the semiconductor devices described above, the first levitation area can be located below at least one of the emitter areas, each of which is the emitter area, and at least a portion of the contact area can be the uncovered area.

[0014] In each of the semiconductor devices described above, the first levitation region can overlap the entirety of at least one of the emitter regions. In each of the semiconductor devices described above, each of the contact regions, which is the contact region, can have an uncovered region.

[0015] Each of the semiconductor devices described above can have a well region of the second conductivity type, located outside the first mesa region in the second direction, and exhibiting a higher concentration than that of the base region. Each of the semiconductor devices described above can have a first extension region of the second conductivity type, extending in the second direction from the well region to a position that overlaps with the emitter region.

[0016] In each of the semiconductor devices described above, the well region can be located outside the emitter region in the first direction. Each of the semiconductor devices described above can have a second extension region of the second conductivity type, extending in the first direction from the well region to a position that overlaps with the emitter region.

[0017] In each of the semiconductor devices described above, the diode section can have a plurality of blind-trough sections arranged side by side in the first direction and a mesa section arranged between the blind-trough sections in the first direction. In each of the semiconductor devices described above, the floating region can also be arranged below a lower end of at least one of the blind-trough sections of the diode section.

[0018] In each of the semiconductor devices described above, an interval in which the floating region is arranged in the first direction in the diode section can be the same as an interval in which the floating region is arranged in the first direction in the transistor section.

[0019] In each of the semiconductor devices described above, the transistor section can have a boundary region comprising one or more of the trench sections and one or more of the mesa sections between the first gate trench section and the diode section. In each of the semiconductor devices described above, the floating region can also be located below the lower end of at least one of the trench sections of the boundary region.

[0020] In each of the semiconductor devices described above, an interval in which the floating region in the first direction is located in the boundary region can be the same as an interval in which the floating region in the first direction is located in the transistor section except for the boundary region.

[0021] In each of the semiconductor devices described above, an area of ​​the uncovered region in the first mesa section can be larger than an area of ​​a region that does not overlap with the floating region in the mesa section in contact with the gate trench section, except for the first gate trench section.

[0022] The summary section does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a subcombination of the features described above. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. Figure 2 shows an enlarged view of area D in Fig. 1. Fig. 3 is a view that shows an example of a cross-section ee in Fig. 2 shows. Fig. Figure 4 is a diagram showing an example arrangement of a floating area 202 in top view. Fig. Figure 5 is a diagram showing another arrangement example of the floating area 202 in top view. Fig. Figure 6 is a view showing another example of the cross-section ee. Fig. Figure 7 is a view showing another example of the cross-section ee. Fig. Figure 8 is a top view showing an example of a transition area 92. Fig. 9 is a view that shows an example of a cross-section ff in Fig. 8 shows. Fig. Figure 10 is an XZ cross-section showing another structural example of a boundary region 90 and a diode section 80. Fig. Figure 11 is a diagram showing a collector voltage-collector current characteristic curve in an example and a reference example. Fig. Figure 12 is a diagram showing a trade-off property between a turn-on loss and a reverse recovery dV / dt in a reference example and an example. DESCRIPTION OF EXAMPLE FORMS OF EXECUTION

[0023] The present invention is described below by means of embodiments of the invention, but these embodiments do not limit the invention according to the claims. Furthermore, not all combinations of features described in the embodiments are essential for a solution of the invention.

[0024] As used herein, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as a "top" side, and another side is referred to as a "bottom" side. A surface of two principal surfaces of a substrate, layer, or other element is referred to as an upper surface, and another surface is referred to as a lower surface. "Top" and "bottom" directions are not limited to a direction of gravity or a direction in which a semiconductor device is mounted.

[0025] In this description, technical situations can be described using orthogonal coordinate axes: an X-axis, a Y-axis, and a Z-axis. These orthogonal coordinate axes only indicate the relative positions of components and do not restrict any specific direction. For example, the Z-axis is not limited to indicating an elevation direction relative to the ground. It should be noted that a +Z-axis direction and a -Z-axis direction are opposite directions to each other. When a Z-axis direction is described without specifying the symbols, it means that the direction is parallel to both the +Z-axis and the -Z-axis.

[0026] In this description, orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and the Y-axis, respectively. Additionally, an axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this description, the direction of the Z-axis can be described as a depth direction. Furthermore, in this description, a direction parallel to the upper and lower surfaces of the semiconductor substrate can be described as a horizontal direction, encompassing both an X-axis and a Y-axis direction.

[0027] A region extending from the center of the semiconductor substrate in the depth direction to the upper surface of the semiconductor substrate can be referred to as an upper surface face. Similarly, a region extending from the center of the semiconductor substrate in the depth direction to the lower surface of the semiconductor substrate can be referred to as a lower surface face.

[0028] In the present description, a case where a term such as "equal" or "same" is used may include a case where a defect is present due to a variation in manufacturing or the like. The defect is, for example, within 10%.

[0029] In this description, the conductivity type of a doped region containing impurities is described as P-like or N-like. In this description, the impurities can specifically be either N-like donors or P-like acceptors and can be described as dopants. In this description, doping means introducing the donor or acceptor into the semiconductor substrate and transforming it into a semiconductor exhibiting an N-like conductivity type or a semiconductor exhibiting a P-like conductivity type.

[0030] In this description, a doping concentration means a concentration of the donor or a concentration of the acceptor in a thermal equilibrium state. In this description, a net doping concentration means a net concentration obtained by adding the donor concentration, set as a positive ion concentration, to the acceptor concentration, set as a negative ion concentration, taking charge polarities into account. For example, if the donor concentration N D is and the acceptor concentration N A is the net doping concentration at any position as N D - N A As specified. In the present description, the net doping concentration can simply be described as the doping concentration.

[0031] In this description, P+-like or N+-like signifies a higher doping concentration than that of P-like or N-like, and P--like or N--like signifies a lower doping concentration than that of P-like or N-like. Furthermore, P++-like or N++-like signifies a higher doping concentration than that of P+-like or N+-like. In this description, a system of units is an SI system of units unless otherwise stated. Although a unit of length can be expressed in cm, various calculations can be performed after conversion to meters (m).

[0032] In this description, a chemical concentration refers to the atomic density of an impurity, measured independently of any electrical activation state. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by capacitance-voltage profiling (CV profiling). Alternatively, a carrier concentration measured by spreading resistance profiling (SRP profiling) can be set as the net doping concentration. The carrier concentration measured by either CV or SRP can be a value in a thermal equilibrium state. Furthermore, in an N-like region, the donor concentration is sufficiently higher than the acceptor concentration, and thus the carrier concentration of the region can be set as the donor concentration.Similarly, in a P-like region, the carrier concentration can be set as the acceptor concentration. In the present description, the doping concentration of the N-like region can be referred to as the donor concentration, and the doping concentration of the P-like region can be referred to as the acceptor concentration.

[0033] If a concentration distribution of donor, acceptor, or net doping exhibits a peak in a region, a value of the peak can be defined as the concentration of donor, acceptor, or net doping in that region. In a case where the concentration of donor, acceptor, or net doping in a region is substantially uniform, or the like, a mean donor, acceptor, or net doping concentration in that region can be defined as the donor, acceptor, or net doping concentration. In the present description, atoms / cm² are used.3 or / cm 3 Used to express concentration per unit volume. This unit is used for the donor or acceptor concentration, or the chemical concentration in the semiconductor substrate. The number of atoms can be omitted.

[0034] The carrier concentration measured by the SRP method may be lower than the concentration of the donor or the acceptor. In a region where current is flowing when spreading resistance is measured, the carrier mobility of the semiconductor substrate may be lower than its value in a crystalline state. This reduction in carrier mobility occurs when carriers are scattered due to a disturbance (perturbation) of the crystal structure caused by a lattice defect or similar factor.

[0035] The donor or acceptor concentration, calculated from the carrier concentration measured by the CV or SRP method, can be lower than the chemical concentration of the element representing the donor or acceptor. For example, in a silicon semiconductor, the donor concentration of phosphorus or arsenic, acting as the donor, or the acceptor concentration of boron, acting as the acceptor, is approximately 99% of their respective chemical concentrations. Conversely, in the same silicon semiconductor, the donor concentration of hydrogen, acting as the donor, is approximately 0.1% to 10% of its chemical concentration.

[0036] Fig. Figure 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. Figure 1 shows the position of each element projected onto a top surface of a semiconductor substrate 10. In Fig. Figure 1 shows only some elements of the semiconductor device 100, and illustrations of some elements have been omitted.

[0037] The semiconductor device 100 comprises the semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed from a semiconductor material. For example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an end face 162 in plan view. When referred to simply as the plan view in this description, this means that the semiconductor substrate 10 is viewed from a top surface. In this example, the semiconductor substrate 10 has two sets of end faces 162, which are opposite each other in plan view. Fig. 1 The X-axis and the Y-axis are parallel to each of the end faces 162. Additionally, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0038] The semiconductor substrate 10 is provided with an active section 160. The active section 160 is a region in which a main current flows in the depth direction between the upper surface and a lower surface of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is arranged above the active section 160, but an illustration of this is shown in Fig. 1 omitted. The active section 160 may refer to an area that overlaps with the emitter electrode in plan view. Furthermore, an area enclosed between active sections 160 in plan view may also be included in the active section 160.

[0039] The active section 160 has transistor sections 70 containing transistor elements such as an insulated-gate bipolar transistor (IGBT). The active section 160 may also have diode sections 80 containing diode elements such as a freewheeling diode (FWD). In the Fig. In the example shown, transistor sections 70 and diode sections 80 are arranged alternately along a predetermined orientation (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse conduction IGBT (RC-IGBT).

[0040] In Fig. 1 is a region in which each of the transistor sections 70 is arranged, indicated by a symbol “I”, and a region in which each of the diode sections 80 is arranged is indicated by a symbol “F”. In the present description, a direction perpendicular to the arrangement direction in the top view can be referred to as an extent direction (in Fig. 1 the Y-axis direction). Each of the transistor sections 70 and the diode sections 80 can have a longitudinal dimension in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension directions of the transistor section 70 and the diode section 80, and a longitudinal direction of each trench section described below, can be the same.

[0041] Each of the diode sections 80 has an N+-type cathode region in an area that contacts the lower surface of the semiconductor substrate 10. In this description, an area in which the cathode region is located is referred to as a diode section 80. In other words, the diode section 80 is an area that overlaps the cathode region in a top view. A P+-type collector region may be located on the lower surface of the semiconductor substrate 10 in a region other than the cathode region. In this description, the diode section 80 may also have an extension region 81 in which the diode section 80 extends in the Y-axis direction to a gate rotor as described below. The collector region is located on a lower surface of the extension region 81.

[0042] The transistor section 70 has a P+-like collector region in an area that contacts the lower surface of the semiconductor substrate 10. Furthermore, in the transistor section 70, an N-like emitter region, a P-like base region, and a gate structure with a gate conduction section and a dielectric gate film are regularly arranged on the upper surface of the semiconductor substrate 10.

[0043] The semiconductor device 100 can have one or more contact fields above the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate field 164. The semiconductor device 100 can have a contact field, such as an anode field, a cathode field, and a current-sensing field. Each contact field is located in a region around the end face 162. The region around the end face 162 refers to an area between the end face 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each contact field can be connected to an external circuit via a wiring connection, such as a wire.

[0044] A gate potential is applied to the gate array 164. The gate array 164 is electrically connected to a conductive section of a gate trench section of the active section 160. The semiconductor device 100 includes the gate runner, which connects the gate array 164 to the gate trench section. Fig. 1 is the gate runner hatched with diagonal lines.

[0045] The gate rotor in this example comprises an outer gate rotor 130 and an active-side gate rotor 131. The outer gate rotor 130 is located, in plan view, between the active section 160 and the end face 162 of the semiconductor substrate 10. In this example, the outer gate rotor 130 encloses the active section 160 in plan view. An area enclosed by the outer gate rotor 130 in plan view can be defined as the active section 160. Furthermore, a trough region is formed below the gate rotor. The trough region is a P-shaped region with a higher concentration than the base region described below and extends from the upper surface of the semiconductor substrate 10 to a position lower than that of the base region. An area enclosed by the trough region in plan view can be defined as the active section 160.

[0046] The outer gate rotor 130 is connected to the gate array 164. The outer gate rotor 130 is arranged above the semiconductor substrate 10. The outer gate rotor 130 can be a metal wiring conductor containing aluminum or the like.

[0047] The active-side gate rotor 131 is located in the active section 160. Locating the active-side gate rotor 131 in the active section 160 can reduce variations in the wiring length from the gate array 164 for each region of the semiconductor substrate 10.

[0048] The outer gate rotor 130 and the active-side gate rotor 131 are connected to the gate trench section of the active section 160. The outer gate rotor 130 and the active-side gate rotor 131 are arranged above the semiconductor substrate 10. The outer gate rotor 130 and the active-side gate rotor 131 can form a wiring conductor made of a semiconductor, such as polysilicon doped with an impurity.

[0049] The active-side gate rotor 131 can be connected to the outer-encircling gate rotor 130. In this example, the active-side gate rotor 131 is arranged to extend in the X-axis direction to intersect the active section 160 substantially at the midpoint of the Y-axis direction, from one outer-encircling gate rotor 130 to another outer-encircling gate rotor 130 that have enclosed the active section 160. When the active section 160 is divided by the active-side gate rotor 131, the transistor sections 70 and the diode sections 80 can be arranged alternately in the X-axis direction in each divided region.

[0050] The semiconductor device 100 can include a temperature sensing section (not shown) which is a PN junction diode formed from polysilicon or the like, and a current sensing section (not shown) which simulates an operation of the transistor section which is arranged in the active section 160.

[0051] In this example, the semiconductor device 100 has an edge termination section 190 between the active section 160 and the end face 162 in a top view. The edge termination section 190 is arranged between the outer gate rotor 130 and the end face 162. The edge termination section 190 reduces the electric field strength at the upper surface of the semiconductor substrate 10. The edge termination section 190 can include a guard ring, a field plate, and / or a RESURF, arranged in a ring shape to enclose the active section 160.

[0052] Fig. Figure 2 shows an enlarged view of area D in Fig. 1. Region D is a region comprising a transistor section 70, a diode section 80, and the active-side gate rotor 131. The semiconductor device 100 in this example comprises a gate trench section 40, a blind trench section 30, a well section 11, an emitter section 12, a base section 14, and a contact section 15, which are arranged within the upper surface of the semiconductor substrate 10. Both the gate trench section 40 and the blind trench sections 30 are examples of the trench section. Furthermore, the semiconductor device 100 in this example comprises an emitter electrode 52 and the active-side gate rotor 131, which are arranged above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate rotor 131 are arranged to be separated from each other.

[0053] A dielectric interlayer film is arranged between the emitter electrode 52 and the active-side gate rotor 131 and the upper surface of the semiconductor substrate 10; however, the dielectric interlayer film is in Fig. 2 omitted. In the dielectric interlayer film in the present example, a contact section 54 is arranged such that it extends through the dielectric interlayer film. The contact section 54 can have a contact hole arranged in the dielectric interlayer film and a conductive element with which the contact hole is filled. In Fig. 2 each contact section 54 is hatched with the diagonal lines.

[0054] The emitter electrode 52 is positioned above the gate trench section 40, the blind trench section 30, the trough section 11, the emitter section 12, the base section 14, and the contact section 15. The emitter electrode 52 is connected to the emitter section 12, the contact section 15, and the base section 14 at the upper surface of the semiconductor substrate 10 via the contact section 54. Furthermore, the emitter electrode 52 is connected to a blind conductor section in the blind trench section 30 via the contact hole located in the dielectric interlayer film. The emitter electrode 52 can also be connected to the blind conductor section of the blind trench section 30 at an edge of the blind trench section 30 in the Y-axis direction.

[0055] The active-side gate runner 131 is connected to the gate trench section 40 via the contact hole located in the dielectric interlayer film. The active-side gate runner 131 can be connected to a gate conductor section of the gate trench section 40 at an edge section 41 of the gate trench section 40 in the Y-axis direction. The active-side gate runner 131 is not connected to the blind conductor section in the blind trench section 30.

[0056] The emitter electrode 52 is made of a material that contains metal. Fig. Figure 2 shows a region in which the emitter electrode 52 is arranged. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like, beneath a region formed of aluminum or the like. Furthermore, a plug formed by embedding tungsten or the like, to be in contact with the barrier metal and aluminum or the like, may be contained in the contact hole.

[0057] The trough region 11 is arranged such that it overlaps the active-side gate rotor 131. The trough region 11 is arranged such that it extends with a predetermined width into a region that does not overlap with the active-side gate rotor 131. In this example, the trough region 11 is arranged such that it is spaced from one end of the contact section 54 in the Y-axis direction relative to the active-side gate rotor 131. The trough region 11 is a region of a second conductivity type with a higher doping concentration than that of the base region 14. In this example, the base region 14 is P-type, and the trough region 11 is P+-type.

[0058] Each transistor section 70 and diode section 80 has a plurality of trench sections arranged in a specific orientation. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more blind trench sections 30 are arranged alternately along the orientation. In the diode section 80 of this example, a plurality of blind trench sections 30 are arranged along the orientation. The diode section 80 of this example does not have a gate trench section 40.

[0059] The ditch section 40 in the present example can have two straight pieces 39 extending along the direction of extension perpendicular to the arrangement direction (pieces of a ditch that are straight along the direction of extension), and the edge section 41 connecting the two straight pieces 39. The direction of extension in Fig. 2 is the Y-axis direction.

[0060] At least part of the edge section 41 is preferably arranged in a curved shape in the top view. The edge section 41, which connects the end sections of the two straight pieces 39 in the Y-axis direction, makes it possible to reduce the electric field strength at the end sections of the straight pieces 39.

[0061] In the transistor section 70, the blind trench sections 30 are arranged between the respective straight sections 39 of the gate trench sections 40. A single blind trench section 30 can be arranged between each straight section 39, or multiple blind trench sections 30 can be arranged. The blind trench section 30 can have a straight shape extending in the direction of travel, or it can have straight sections 29 and an edge section 31 similar to the gate trench section 40.

[0062] The diffusion depth of the trough area 11 can be greater than the depths of the gate trench section 40 and the blind trench section 30. The end sections in the Y-axis direction of the gate trench section 40 and the blind trench section 30 are arranged in the trough area 11 in plan view. In other words, at the end section of each trench section in the Y-axis direction, a bottom section of each trench section is covered by the trough area 11 in the depth direction. This configuration allows the electric field strength at the bottom section of each trench section to be reduced.

[0063] A mesa section is arranged between the respective trench sections in the arrangement direction. The mesa section refers to a region located between the trench sections within the semiconductor substrate 10. For example, the upper end of the mesa section is the upper surface of the semiconductor substrate 10. The depth position of a lower end of the mesa section is the same as the depth position of a lower end of the trench section. In this example, the mesa section is arranged such that it extends in the extent direction (the Y-axis direction) along the trench at the upper surface of the semiconductor substrate 10.

[0064] In the present example, a mesa section 60 is arranged within the transistor section 70, and a mesa section 61 is arranged within the diode section 80. The transistor section 70 in the present example has a boundary region 90. The boundary region 90 is an end section of the transistor section 70 in the X-axis direction and is in contact with the diode section 80. The boundary region 90 is provided with a collector region 22 on a lower surface 23 of the semiconductor substrate 10. The boundary region 90 can have one or more trench sections. The gate trench section 40, the blind trench section 30, or both trench sections can be arranged within the boundary region 90. A mesa section 62 is arranged within the boundary region 90. As referred to in this description simply as the mesa section, it designates the mesa section 60, the mesa section 61, and the mesa section 62.Mesa section 62 can have the same structure as mesa section 61. The boundary region 90 can be a region where a structure on one side of the upper surface 21 is similar to that of diode section 80, and a structure on one side of the lower surface 23 is similar to that of transistor section 70. Transistor section 70 can be without boundary region 90. In this case, mesa section 60 of transistor section 70 and mesa section 61 of diode section 80 are arranged such that they are adjacent to each other at the boundary between transistor section 70 and diode section 80.

[0065] Each mesa section is provided with the base region 14. In the mesa section, a region that is positioned such that it is closest to the active-side gate rotor 131 is defined as base region 14-e in the base region 14 that is exposed to the upper surface of the semiconductor substrate 10. Fig. Figure 2 shows the base region 14-e, which is located at one end of each mesa section in the extension direction. The base region 14-e is also located at another end of each mesa section. Each mesa section can be located with the emitter region 12 of a first conductivity type and / or the contact region 15 of the second conductivity type in a region enclosed in the top view between the base regions 14-e. In the present example, the emitter region 12 is N+-like and the contact region 15 is P+-like with a higher concentration than that of the base region 14. The emitter region 12 and the contact region 15 can be located in the depth direction between the base region 14 and the top surface of the semiconductor substrate 10.

[0066] The mesa section 60 of the transistor section 70 has the emitter region 12, which is exposed to the upper surface of the semiconductor substrate 10. The emitter region 12 contacts the gate trench section 40. The mesa section 60, which contacts the gate trench section 40, may have the contact region 15, which is exposed to the upper surface of the semiconductor substrate 10.

[0067] The emitter area 12 in mesa section 60 touches the gate ditch section 40. The emitter area 12 either touches the blind ditch section 30 or does not touch it. The emitter area 12 is also located in an area that overlaps with the contact section 54.

[0068] Contact area 15 in mesa section 60 is located in the area that overlaps with contact section 54. Contact area 15 either touches or does not touch gate ditch section 40. Contact area 15 either touches or does not touch blind ditch section 30.

[0069] In the example of Fig. 2. The emitter area 12 is located in the mesa section 60, extending from one trench section to another in the X-axis direction. The contact area 15 in the mesa section 60 can also be located from one trench section to another in the X-axis direction. The contact area 15 does not touch either of the two trench sections that enclose the mesa section 60. In this case, the base area 14 can be located between the contact area 15 and the trench section.

[0070] In the example of Fig. In one example, the contact area 15 and the emitter area 12 in the mesa section 60 are arranged alternately along the extension direction of the trench section (Y-axis direction). In another example, the contact area 15 and the emitter area 12 in the mesa section 60 can be arranged in a strip shape along the extension direction of the trench section (Y-axis direction). For example, the emitter area 12 is located in an area touching the trench section, and the contact area 15 is located in an area situated between the emitter areas 12. Furthermore, the mesa section 60 can be provided with the emitter area 12 instead of the contact area 15. For example, the emitter area 12 can be located in an entire area situated between the base areas 14-e in the Y-axis direction.

[0071] The mesa section 61 of the diode section 80 is not provided with the emitter section 12. The base regions 14 and the contact regions 15 can be arranged on an upper surface of the mesa section 61. In the region enclosed between the base regions 14-e on the upper surface of the mesa section 61, the contact region 15 can be in contact with each of the base regions 14-e. The base region 14 can be arranged in a region enclosed between the contact regions 15 on the upper surface of the mesa section 61. The base region 14 can be arranged in the entire region enclosed between the contact regions 15. In the present example, the mesa section 62 has a structure in the boundary region 90 that is similar to that of the mesa section 61.

[0072] The contact section 54 is arranged above each mesa section. The contact section 54 is arranged in the area enclosed between the base areas 14-e. In this example, the contact section 54 is arranged above each area of ​​the contact area 15, the base area 14, and the emitter area 12. The contact section 54 is not arranged in areas corresponding to the base area 14-e and the basin area 11. The contact section 54 can be arranged in the center of the mesa section 60 in the arrangement direction (X-axis direction).

[0073] In the diode section 80, an N+-type cathode region 82 is arranged in a region adjacent to the lower surface of the semiconductor substrate 10. The P+-type collector region 22 can be arranged on the lower surface of the semiconductor substrate 10 in a region where the cathode region 82 is not located. The cathode region 82 and the collector region 22 are arranged between the lower surface 23 of the semiconductor substrate 10 and a buffer region 20. Fig. 2 is a boundary between the cathode area 82 and the collector area 22, represented by a dotted line.

[0074] The cathode region 82 is arranged such that it is spaced away from the well region 11 in the Y-axis direction. This configuration ensures sufficient distance between a P-shaped region (the well region 11), which has a comparatively high doping concentration and extends to the deep position, and the cathode region 82, thus improving the breakdown voltage. In the present example, an end section of the cathode region 82 in the Y-axis direction is arranged such that it is spaced further away from the well region 11 than an end section of the contact section 54 in the Y-axis direction. In another example, the end section of the cathode region 82 in the Y-axis direction can be arranged between the well region 11 and the contact section 54.

[0075] Fig. 3 is a view that shows an example of a cross-section ee in Fig. Figure 2 shows the cross-section ee, which is an XZ plane passing through an emitter region 12 and a cathode region 82. The semiconductor device 100 in this example includes the semiconductor substrate 10, a dielectric interlayer film 38, the emitter electrode 52, and a collector electrode 24 in cross-section.

[0076] The dielectric interlayer film 38 is arranged on the upper surface of the semiconductor substrate 10. The dielectric interlayer film 38 is a film comprising at least one layer of a dielectric film, such as silicate glass, to which an impurity, such as boron or phosphorus, is added, a thermal oxide film, or other dielectric films. The dielectric interlayer film 38 is provided with the contact section 54, which is described with reference to Fig. 2 is described.

[0077] The contact section 54 is arranged such that it extends through the dielectric interlayer film 38. The contact section 54 can be formed from a metal that differs from that of the emitter electrode 52. The contact section 54 can contain tungsten. A lower section of the contact section 54 can be provided with a barrier metal layer containing at least one titanium film or a titanium nitride film. The contact section 54 can extend to an upper surface 21 of the semiconductor substrate 10 or to an inner surface of the semiconductor substrate 10. In the example of Fig. In section 3, the contact section 54 is a contact groove that extends from the upper surface 21 of the semiconductor substrate 10 to an inner side of each mesa section. This allows for an increased contact area between the contact section 54 and the semiconductor substrate 10. In cross-section, a lower end of the contact section 54 of the transistor section 70 is in contact with the emitter region 12. In cross-section, a lower end of the contact section 54 of the diode section 80 is in contact with the base region 14.

[0078] The emitter electrode 52 is arranged above the dielectric interlayer film 38. The emitter electrode 52 is connected to the semiconductor substrate 10 via the contact section 54. The collector electrode 24 is arranged on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this description, the direction (the Z-axis direction) in which the emitter electrode 52 is connected to the collector electrode 24 is referred to as the depth direction.

[0079] The semiconductor substrate 10 has an N-shaped drift region 18. The drift region 18 is located in the transistor section 70 and in the diode section 80, respectively.

[0080] In the mesa section 60 of the transistor section 70, the N+-type emitter region 12 and the P-type base region 14 are arranged sequentially, starting from the side of the upper surface 21 of the semiconductor substrate 10. The drift region 18 is located below the base region 14. The mesa section 60 may include an N+-type collector region 16. The collector region 16 is located between the base region 14 and the drift region 18.

[0081] The emitter region 12 is exposed to the upper surface 21 of the semiconductor substrate 10 and touches the gate trench section 40. The emitter region 12 touches the trench sections on both sides of the mesa section 60. The emitter region 12 has a higher doping concentration than that of the drift region 18.

[0082] Base area 14 is located below emitter area 12. In this example, base area 14 touches emitter area 12. Base area 14 touches the trench sections on both sides of mesa section 60.

[0083] The collection area 16 is located below the base area 14. The collection area 16 is an N+-like region with a higher doping concentration than that of the drift area 18. That is, the collection area 16 has a higher donor concentration than that of the drift area 18. Positioning the collection area 16 with its high concentration between the drift area 18 and the base area 14 can enhance the charge carrier injection (IE) effect and reduce the turn-on voltage. The collection area 16 can be positioned to cover the entire lower surface of the base area 14 in each mesa section 60.

[0084] In the mesa section 61 of the diode section 80, the P--like base region 14 is in contact with the upper surface 21 of the semiconductor substrate 10. The drift region 18 is located below the base region 14. The collector region 16 can also be located below the base region 14 in the mesa section 61.

[0085] In the mesa section 62 of the boundary region 90, the P-like base region 14 is in contact with the upper surface 21 of the semiconductor substrate 10. The drift region 18 is located below the base region 14. In the mesa section 62, the collection region 16 can be located below the base region 14. The mesa section 62 in the present example has a structure similar to that of the mesa section 61. In each example in the present description, the center of the trench section in the X-axis direction can be defined as an end section of the boundary region 90 in the X-axis direction.

[0086] In transistor section 70 and diode section 80, the N+-like buffer region 20 can each be located below the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 can exhibit a concentration peak with a higher doping concentration than that of the drift region 18. A doping concentration at a concentration peak refers to a doping concentration at a local maximum of the concentration peak. Additionally, the doping concentration of the drift region 18 can be defined as the average of doping concentrations in a region where the doping concentration distribution is essentially flat.

[0087] The buffer region 20 can have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peak of the buffer region 20 can, for example, be located at the same depth position as a chemical concentration peak of hydrogen (a proton) or phosphorus. The buffer region 20 can act as a field-stopping layer, preventing a depletion layer extending from a lower end of the base region 14 from reaching the P+-like collector region 22 and the N+-like cathode region 82.

[0088] In transistor section 70, the P+-like collector region 22 is located below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 can have an acceptor that is the same as or different from an acceptor of the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0089] The N+-like cathode region 82 is located below the buffer region 20 in the diode section 80. The donor concentration in the cathode region 82 is higher than the donor concentration in the drift region 18. A donor in the cathode region 82 could be, for example, hydrogen or phosphorus. It should be noted that an element acting as both a donor and an acceptor in each region is not limited to the example described above. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24.

[0090] The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum.

[0091] One or more gate trench sections 40 and one or more blind trench sections 30 are arranged on the side of the upper surface 21 of the semiconductor substrate 10. Each trench section extends through the base region 14 and is arranged from the upper surface 21 of the semiconductor substrate 10 to a region below the base region 14. In a region where the emitter region 12 and / or the contact region 15 and / or the collector region 16 are located, each trench section also extends through the doping regions of these regions. A structure in which the trench section extends through the doping region is not limited to a structure formed by forming the doping region and subsequently forming the trench section in that sequence.A structure in which the trench section is formed and subsequently the doping area between the trench sections is formed is also included in the structure in which the trench section runs through the doping area.

[0092] As described above, transistor section 70 is equipped with gate-trough section 40 and blind-trough section 30. Diode section 80 is equipped with blind-trough section 30 but not with gate-trough section 40. In this example, the boundary between diode section 80 and transistor section 70 in the X-axis direction is the boundary between cathode region 82 and collector region 22.

[0093] In this example, boundary area 90 is equipped with blind ditch section 30 and is not equipped with gate ditch section 40. The ditch section at the end of boundary area 90 on one side of transistor section 70 can be gate ditch section 40.

[0094] The gate trench section 40 comprises a gate trench located in the upper surface 21 of the semiconductor substrate 10, a dielectric gate film 42, and a gate conductor section 44. The dielectric gate film 42 is arranged to cover an inner wall of the gate trench. The dielectric gate film 42 can be formed by oxidizing or nitriding a semiconductor on the inner wall of the gate trench. The gate conductor section 44 is located further inside the gate trench than the dielectric gate film 42. In other words, the dielectric gate film 42 insulates the gate conductor section 44 from the semiconductor substrate 10. The gate conductor section 44 is formed from a conductive material such as polysilicon.

[0095] The gate conduction section 44 can be arranged to be longer in the depth direction than the base region 14. The gate trench section 40 is covered in cross-section by the dielectric interlayer film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conduction section 44 is electrically connected to the gate rotor. When a predetermined gate voltage is applied to the gate conduction section 44, a channel is formed through an electron inversion layer in a surface layer of the base region 14 at a boundary in contact with the gate trench section 40.

[0096] The blind trench sections 30 can have the same cross-sectional structure as the gate trench sections 40. The blind trench section 30 comprises a blind trench located in the upper surface 21 of the semiconductor substrate 10, a dielectric dummy film 32, and a dummy conductor section 34. The dummy conductor section 34 is electrically connected to the emitter electrode 52. The dielectric dummy film 32 is arranged to cover an inner wall of the blind trench. The dummy conductor section 34 is located within the blind trench and further inward than the dielectric dummy film 32. The dielectric dummy film 32 insulates the dummy conductor section 34 from the semiconductor substrate 10. The dummy conductor section 34 can be made of the same material as the gate conductor section 44. For example, the dummy conductor section 34 is made of a conductive material such as polysilicon.The dummy line section 34 can have the same length in the depth direction as the gate line section 44.

[0097] In this example, the gate trench section 40 and the blind trench section 30 are covered with the dielectric interlayer film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that bottom sections of the blind trench section 30 and the gate trench section 40 may have curved surfaces that are convex downwards (curved shapes in the cross-sections). In this description, a depth position of a lower end 43 of the gate trench section 40 is defined as Zt.

[0098] The semiconductor device 100 in the present example has a P-shaped floating region 202 located below the lower end 43 of the gate trench section 40. The lower end 43 of the gate trench section 40 refers to a portion of the gate trench section 40 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of Fig. 3 is the lower end 43 of the gate trench section 40, located in the X-axis direction at the center of the gate trench section 40. Furthermore, a lower end 33 of the blind trench section 30 refers to a portion within the blind trench section 30 that is closest to the lower surface 23 of the semiconductor substrate 10. In the example of Fig. 3 is the lower end 33 of the blind trench section 30 in the X-axis direction in the middle of the blind trench section 30.

[0099] At least a portion of the floating area 202 is positioned in a location that overlaps the lower end 43 in plan view and is located below the lower end 43 in the Z-axis direction. The floating area 202 may have a portion that does not overlap the lower end 43 in plan view. The floating area 202 may have a portion that is located above the lower end 43. The floating area 202 may touch the lower end 43 or be spaced apart from the lower end 43. In the example of Fig. 3 The floating area 202 touches the entire curved surface part including the lower end 43 in the gate trench section 40. The floating area 202 can be formed after the formation of a trench structure of the gate trench section 40 and before the formation of the gate conduit section 44 by implanting the P-like dopant in the vicinity of a lower end of the trench structure.

[0100] The levitation region 202 is electrically levitated with respect to an electrode made of metal, polysilicon, or the like. An N-type region and / or a dielectric film is arranged between the levitation region 202 and the electrode. In other words, the levitation region 202 and the electrode are not connected to each other by a P-type region or a conductive material. The doping concentration of the levitation region 202 can be lower than or equal to the doping concentration of the base region 14, or it can be higher than the doping concentration of the base region 14. In the present example, the doping concentration of the levitation region 202 is higher than the doping concentration of the base region 14. The doping concentration can be higher than or equal to 1 × 10⁻⁶ 15 cm -3 and less than or equal to 1 × 10 17 cm -3 be.

[0101] The floating area 202 is arranged such that it is spaced apart from the base area 14. An N-shaped area (in this example the collection area 16 and / or the drift area 18) is arranged between the floating area 202 and the base area 14.

[0102] Each transistor section 70 has one or more floating regions 202. Each transistor section 70 can have a plurality of floating regions 202. In each transistor section 70, the floating region 202 can be arranged in at least one gate trench section 40, the floating region 202 can be arranged in 50% or more of the gate trench sections 40, the floating region 202 can be arranged in 80% or more of the gate trench sections 40, or the floating region 202 can be arranged in all gate trench sections 40.

[0103] In at least one transistor section 70, the floating region 202 is arranged in the gate-trough section 40 that is closest to the diode section 80. In a plurality of transistor sections 70, the floating region 202 can be arranged in the gate-trough section 40 that is closest to the diode section 80. In all transistor sections 70, the floating region 202 can be arranged in the gate-trough section 40 that is closest to the diode section 80.

[0104] In the present description, among one or more gate trench sections 40 in the transistor section 70, the one that is arranged such that it is closest to the diode section 80 in a first direction is defined as a first gate trench section 40-1. Among one or more blind trench sections 30 in the transistor section 70, those that are arranged such that they are adjacent to the first gate trench section 40-1 are defined as a first blind trench section 30-1 and a second blind trench section 30-2. The first blind trench section 30-1 is arranged outside the first gate trench section 40-1. In other words, the first blind trench section 30-1 is arranged between the first gate trench section 40-1 and the diode section 80. In the present example, the first blind trench section 30-1 is arranged at the end section of the boundary region 90.The second blind ditch section 30-2 is located within the first gate ditch section 40-1. In other words, the second blind ditch section 30-2 is located on the side of the first gate ditch section 40-1 opposite the first blind ditch section 30-1.

[0105] Among a multitude of mesa sections 60, the one that touches the first gate ditch section 40-1 and is located between the first gate ditch section 40-1 and the diode section 80 is designated as the first mesa section 60-1. The first mesa section 60-1 is the mesa section 60 located between the first gate ditch section 40-1 and the first blind ditch section 30-1.

[0106] The mesa section 60, which touches the first gate ditch section 40-1 and is located on a side opposite the first mesa section 60-1, is defined as the second mesa section 60-2. The second mesa section 60-2 is the mesa section 60 located between the first gate ditch section 40-1 and the second blind ditch section 30-2.

[0107] Among one or more floating areas 202, the one located below the first gated trench section 40-1 is designated as the first floating area 202. Each floating area 202 may extend to a region below the lower end 33 of the trench section (in this example, the blind trench section 30) that is adjacent to the corresponding gated trench section 40. Each floating area 202 may or may not touch the trench section adjacent to the gated trench section 40. In this example, each floating area 202 does not extend in the X-axis direction to a position beyond the trench section adjacent to the gated trench section 40. Each floating area 202 does not extend below the mesa section 60 that does not touch the gated trench section 40.

[0108] Fig. Figure 3 shows the first gate trench section 40-1, the first float section 202-1, the first mesa section 60-1, and the second mesa section 60-2, which are arranged at an end section of the transistor section 70 in the X-axis direction. When the transistor section 70 is arranged between two diode sections 80, the transistor section 70 has the first gate trench section 40-1, the first float section 202-1, the first mesa section 60-1, and the second mesa section 60-2 at each end section on both sides in the X-axis direction.

[0109] The lower end 33 of each blind trench section 30 can touch an N-type region (in this example, the drift region 18). In this example, on the side of the upper surface 21 of the semiconductor substrate 10 below the lower end 33, there is no P-type region and an N-type region (in this example, the drift region 18) is arranged.

[0110] By arranging the floating region 202, it is possible to prevent electrons from flowing to the lower end 43 of the first gate trench section 40-1 when the transistor section 70 is turned on, thus causing a depletion layer to remain near the lower end 43. This makes it possible to reduce the reverse recovery dV / dt. The reverse recovery dV / dt is the slope of a time waveform of an anode-cathode voltage at a given point in time during the reverse recovery of the diode section 80. Furthermore, when the semiconductor device 100 is used in a circuit such as a three-phase inverter, it is possible to reduce one end of a voltage waveform of the IGBT, which is arranged in opposite branches. Therefore, it is possible to improve a trade-off between turn-on loss and reverse recovery dV / dt.

[0111] On the other hand, in the semiconductor device 100, in which the transistor section 70 and the diode section 80 are arranged side by side, some of the electrons injected from the emitter region 12 of the transistor section 70 flow into the cathode region 82 of the diode section 80. Therefore, it becomes difficult to raise the potential of a PN junction at the end of the collector region 22 of the transistor section 70, and a snapshot may occur when the transistor section 70 is turned on. If the floating region 202 is present, an electron flow from the emitter region 12 is hindered, and thus it becomes even more difficult to raise the potential of the PN junction at the end of the collector region 22, making the snapshot likely to occur.

[0112] In the present example, the first mesa section 60-1, located in the vicinity of the diode section 80, has an uncovered area that does not overlap with the first levitation region. This allows electrons to flow more easily from the first mesa section 60-1, thereby suppressing the snapshot. In other words, it is possible to suppress the snapshot while also improving the compromise property described above.

[0113] Fig. Figure 4 is a diagram showing an example of the arrangement of the floating area 202 in a top view. Fig. Figure 4 shows an enlarged view of transistor section 70 in the vicinity of the boundary region 90. Furthermore, it shows Fig. 4 the basin area 11, which is arranged outside the emitter area 12 in the Y-axis direction. Above the basin area 11 extends the area with respect to Fig. 1 described outer-circumferential gate rotor 130 in X-axis direction.

[0114] In at least one transistor section 70, the first mesa section 60-1 has an uncovered area 212 that does not overlap with the first floating area 202-1. The uncovered area 212 can be located in the plurality of transistor sections 70 within the first mesa section 60-1, or the uncovered area 212 can be located in all transistor sections 70 within the first mesa section 60-1. In the present example, the uncovered area 212 is located over the entire first mesa section 60-1 in the X-axis direction.

[0115] Each mesa section 60 has a longitudinal dimension in the Y-axis direction. The direction of extension of the longest straight line between the end faces of the mesa section 60 in plan view can be defined as a longitudinal direction of the mesa section 60. In each mesa section 60, a region between both ends of the emitter region 12 in the Y-axis direction is defined as an intermediate region 210. In the mesa section 60 in the present example, the emitter regions 12 are arranged individually in the Y-axis direction. In this case, outer end sections of the two emitter regions 12, which are arranged at both ends in the Y-axis direction, are defined as both ends of the intermediate region 210. In the mesa section 60, the emitter regions 12 and the contact regions 15 can be arranged alternately in the Y-axis direction.

[0116] The uncovered region 212 can be located in the intermediate region 210 of the first mesa section 60-1. In the present example, a plurality of first levitation regions 202-1 are individually arranged along the Y-axis in the intermediate region 210 of the first mesa section 60-1. Furthermore, a plurality of uncovered regions 212 are also individually arranged along the Y-axis in the intermediate region 210 of the first mesa section 60-1. This allows electrons to flow easily from the first mesa section 60-1, thereby suppressing the snapshot.

[0117] The first floating area 202-1 can overlap the first blind trench section 30-1 in plan view or be spaced apart from it. If the first floating area 202-1 is spaced apart from the first blind trench section 30-1, it is possible to further suppress the snapshot.

[0118] In the intermediate region 210 of the first mesa section 60-1, the total length L2 of the plurality of uncovered regions 212 in the Y-axis direction may be less than the total length L1 of regions in the Y-axis direction that overlap with the first floating region 202-1. The total length L2 may be 70% or less of the total length L1, or it may be 50% or less. The total length L2 may be 10% or more of the total length L1, 30% or more, or 50% or more.

[0119] The total length of L2 can be greater than the total length of L1. This makes it easy to suppress the snapback. The total length of L2 can be 1.3 times or more of the total length of L1, 1.5 times or more, or twice or more. The total length of L2 can be 10 times or less of the total length of L1, three times or less, or twice or less.

[0120] The uncovered area 212 can also be located in the intermediate area 210 of the second mesa section 60-2. The arrangement of the first suspended area 202-1 of the second mesa section 60-2 and the uncovered area 212 in the Y-axis direction can be similar to that of the first mesa section 60-1. The first suspended area 202-1 in the second mesa section 60-2 can overlap the second blind trench section 30-2 in plan view or be spaced apart from it. For example, the first suspended area 202-1 can overlap the second blind trench section 30-2 and can be spaced apart from the first blind trench section 30-1.

[0121] In the present example, the first floating region 202-1 is arranged below at least one emitter region 12 of the first mesa section 60-1. The first floating region 202-1 can overlap the entirety of the corresponding emitter region 12. The first floating region 202-1 can be arranged below a plurality of emitter regions 12. The first floating regions 202-1 can be arranged for all emitter regions 12, with the exception of those emitter regions 12 that are located at both ends in the Y-axis direction. Furthermore, the first floating regions 202-1 can be arranged for all emitter regions 12, including those emitter regions 12 that are located at both ends in the Y-axis direction. By arranging the first floating region 202-1 to overlap the emitter region 12, it becomes easy to improve the compromise property between the turn-on loss and the reverse recovery dV / dt.

[0122] In the present example, at least part of the contact region 15 is the uncovered region 212. Every contact region 15 can contain the uncovered region 212. In every contact region 15, a part that is in contact with the emitter region 12 can overlap the first levitation region 202-1. Every contact region 15 can also not overlap the first levitation region 202-1.

[0123] In another example, the first floating area 202-1 can be arranged below at least one contact area 15 of the first mesa section 60-1. The first floating areas 202-1 can be arranged below a plurality of contact areas 15. The first floating areas 202-1 can be arranged for all contact areas 15, except for those contact areas 15 located at both ends in the Y-axis direction. Furthermore, the first floating areas 202-1 can be arranged for all contact areas 15, including those contact areas 15 located at both ends in the Y-axis direction.

[0124] In this case, at least part of the emitter region 12 is the uncovered region 212. Each emitter region 12 can have the uncovered region 212. In each emitter region 12, a portion that is in contact with the contact region 15 can overlap the first levitation region 202-1. Each emitter region 12 can also fail to overlap the first levitation region 202-1. By positioning the first levitation region 202-1 to overlap the contact region 15, the electrons continue to flow easily, making it easy to suppress the snapshot.

[0125] In the mesa sections 60, except for the first mesa section 60-1 and the second mesa section 60-2, a floating area 202 can be arranged for each mesa section 60. The length of the floating area 202 of the mesa section 60 in the Y-axis direction is greater than the length L1 of one of the first floating areas 202-1 in the Y-axis direction. The length of the floating area 202 in this example is equal to the sum of the lengths L1 and L2. In this example, the positions of both ends of the floating area 202 in the Y-axis direction are the same as the positions of the outer end sections of the first floating area 202-1, which are arranged at both ends in the Y-axis direction. The length of the suspended area 202 in the Y-axis direction can be 50% or more of the length of the straight section 39 of the gate ditch section 40 in the Y-axis direction, can be 70% or more, or can be 90% or more.

[0126] An area (referred to as the first area) of the uncovered region 212 in the first mesa section 60-1 in plan view may be larger than an area (referred to as the second area) of a region that does not overlap with the suspended region 202 in mesa section 60 in contact with gated ditch section 40, except for the first gated ditch section 40-1. The first area is a value obtained by multiplying a width of the first mesa section 60-1 in the X-axis direction by the sum of the lengths L2. The second area is a value obtained by multiplying a width of the mesa section 60 in the X-axis direction by the sum of the lengths of regions in the Y-axis direction that do not overlap with the suspended region 202. The second area may be zero.

[0127] As in Fig. As shown in Figure 4, a first expansion region 204 can be arranged such that it extends from the trough region 11 to a position that overlaps with the emitter region 12. The first expansion region 204 is a P-shaped region. The first expansion region 204 is connected to the trough region 11. The trough region 11 is connected to the emitter electrode 52. The first expansion region 204 can be located at the same depth as the float region 202. The first expansion region 204 can have the same doping concentration as the float region 202. The first expansion region 204 is separated from the float region 202.

[0128] In this example, the first expansion region 204 overlaps the entire emitter region 12 that is closest to the well region 11. The first expansion region 204 may not overlap the emitter region 12 that is second closest to the well region 11. By arranging the first expansion region 204, it is possible to adjust a region from the well region 11 to a region below the outermost emitter region 12 to an emitter potential. This makes it possible to adjust the electric field distribution so that it is uniform in a region where the first expansion region 204 is arranged, thereby suppressing a decrease in the breakdown voltage. The first expansion region 204 can be arranged over the entire transistor section 70 in the X-axis direction. The first expansion region 204 can be arranged over the entire diode section 80 in the X-axis direction.

[0129] Fig. Figure 5 is a diagram showing another arrangement example of the floating area 202 in a top view. The arrangement of the first floating area 202-1 is similar to that in the example of Fig. 4. In the present example, the other floating areas 202, like the first floating area 202-1, are also arranged individually in the Y-axis direction, similar to the first floating area 202-1. In the present example, the length of the other floating area 202, like that of the first floating area 202-1, in the Y-axis direction can be equal to the length L1 of the first floating area 202-1. A distance in the Y-axis direction between the other floating areas 202, like that of the first floating area 202-1, can be equal to a distance L2 between the first floating areas 202-1.

[0130] At least one of the floating areas 202 other than the first floating area 202-1 can be arranged individually in the Y-axis direction. For example, the floating areas 202 adjacent to the first floating area 202-1 can be arranged individually in the Y-axis direction. The other floating areas 202 can be arranged continuously in the Y-axis direction, similar to the example of Fig. 4. As in Fig. As shown in Figure 5, all floating areas 202 can be arranged individually in the Y-axis direction.

[0131] Fig. Figure 6 is a view showing another example of the cross-section ee. The present example differs from the one referred to in Fig. 3 described example in the arrangement of the first floating area 202-1. The other structures can be one of those described with reference to Fig. 3 to Fig. The 5 described examples are similar.

[0132] In this example, the first suspended area 202-1 does not extend in the X-axis direction to an area below the lower end 33 of the first blind trench section 30-1. In plan view, the first suspended area 202-1 is not in contact with the first blind trench section 30-1. The uncovered area 212 is located between the first suspended area 202-1 and the first blind trench section 30-1. The first suspended area 202-1 may or may not extend to an area below the contact section 54 of the first mesa section 60-1. The first suspended area 202-1 may or may not extend to the midpoint of the first mesa section 60-1 in the X-axis direction.

[0133] The first floating area 202-1 can be arranged individually in the Y-axis direction, similar to the examples from Fig. 4 and Fig. 5. In another example, the first floating area 202-1 can be arranged continuously as a single area in the Y-axis direction, similar to the floating area 202 in Fig. 4 and Fig. 5. In this case too, the uncovered area 212 is located between the first blind trench section 30-1 and the first suspended area 202, and thus it is possible to suppress the snapback.

[0134] The width of the first mesa section 60-1 in the X-axis direction is defined as X1. The width of the uncovered area 212 in the X-axis direction can be 10% or more of the width X1, 20% or more, or 30% or more. The width of the uncovered area 212 in the X-axis direction can be 90% or less of the width X1, 80% or less, or 70% or less. As in Fig. As shown in Figure 6, the width of the uncovered area 212 in the X-axis direction can be 50% or less of the width X1.

[0135] The first suspended area 202-1 can touch the second blind trench section 30-2 in plan view. In the present example, the first suspended area 202-1 touches the second blind trench section 30-2 in the XZ cross-section.

[0136] The width of the second mesa section 60-2 in the X-axis direction is defined as X2. The width X2 can be smaller than the width X1. In other words, the first gate trench section 40-1 is arranged such that it is prestressed in one direction of the second blind trench section 30-2 between the first blind trench section 30-1 and the second blind trench section 30-2. With such a configuration, when the P-type dopant is implanted and diffused through the trench structure of the first gate trench section 40-1 to form the first suspended area 202-1, it is easily achieved that the first suspended area 202-1 is spaced apart from the first blind trench section 30-1 and brought into contact with the second blind trench section 30-2.

[0137] Fig. Figure 7 is a view showing another example of the cross-section ee. The present example differs from the one referred to in Fig. The example described in section 6 is the arrangement of the first floating area 202-1. The other structures can be one of those described with reference to Fig. The 6 described examples are similar.

[0138] The first suspended section 202-1 in this example is arranged such that it is also spaced apart from the second blind trench section 30-2 in plan view. In the X-axis direction, a distance between the first suspended section 202-1 and the first blind trench section 30-1 is defined as X3, and a distance between the first suspended section 202-1 and the second blind trench section 30-2 is defined as X4. The distance X4 can be smaller than the distance X3. The distance X4 can be 50% or less of the distance X3, or it can be 30% or less. The distance X4 can be as in the example of Fig. The value is zero at 6. In the present example, it is also possible to suppress the snapback.

[0139] The other floating areas 202, as well as the first floating area 202-1, can be similar to the example of Fig. 6. In another example, all floating regions 202 can have a structure similar to the first floating region 202-1 of Fig. 7 is.

[0140] Fig. Figure 8 is a top view showing an example of a transition area 92. A structure of the transition area 92, which refers to Fig. The structure of transition area 92, described in section 8, can be combined with one of the examples described in this description. Fig. The structure described in section 8 can be combined with the structure of the levitation region 202 in one of the examples described in this description. In another example, the levitation region 202 can be used in the semiconductor device 100, which is described with reference to Fig. As described in section 8, exhibit a structure that differs from those in the examples of Fig. 1 to Fig. 7 distinguishes. Alternatively, the semiconductor device 100, which refers to Fig. The semiconductor device 100, which is described in section 8, does not have a floating region 202. Fig. The diode section 80, as described in section 8, cannot be present.

[0141] In the present example, the trough area 11 is also arranged outside the emitter area 12 in the X-axis direction. In the present example, the outer gate rotor 130, which extends in the Y-axis direction, is arranged above the trough area 11.

[0142] The transition region 92 is arranged between the emitter region 12 (or the transistor section 70) and the trough region 11 in the X-axis direction. The transition region 92 has one or more trench sections arranged side by side in the X-axis direction. The transition region 92 can have one or more blind trench sections 30, can have one or more gate trench sections 40, or can have both blind trench sections 30 and gate trench sections 40. The transition region 92 in this example has trench sections arranged in a pattern similar to that of the transistor section 70. In the transistor section 70 in this example, one gate trench section 40 and two blind trench sections 30 are arranged alternately. Similarly, in the transition region 92, one gate trench section 40 and two blind trench sections 30 can be arranged alternately.

[0143] One or more trench sections can also be arranged within the basin area 11. In the present example, two blind trench sections 30 are arranged within the basin area 11.

[0144] The transition region 92 can have the collector region 22 in a position in contact with the lower surface 23. The transition region 92 can have the cathode region 82 in a position in contact with the lower surface 23. The transition region 92 has one or more mesa sections 63. The drift region 18 can be exposed to the upper surface 21 of the mesa section 63. In another example, the base region 14 can be located on the upper surface 21 of the mesa section 63.

[0145] The semiconductor device 100 in the present example has a second expansion region 220 located in the transition region 92. The second expansion region 220 is a P-shaped region extending in the X-axis direction from the well region 11 to a position that overlaps with the emitter region 12. The second expansion region 220 is connected to the well region 11. The second expansion region 220 can be located at the same depth as the floating region 202. The second expansion region 220 can have the same doping concentration as the floating region 202.

[0146] In this example, the second extension area 204 overlaps the entire emitter area 12 of the mesa section 60 that is closest to the basin area 11 in the X-axis direction. The second extension area 204 can overlap the entire emitter areas 12 of two or more mesa sections 60 that are closest to the basin area 11. If the contact area 15 is located in the mesa section 60, the second extension area 204 also overlaps with the contact area 15. The second extension area 204 is not connected to the floating area 202.

[0147] By arranging the second extension area 220, it is possible to adjust the transition area 92 to the emitter potential. This makes it possible to adjust the electric field distribution so that it is uniform in the transition area 92, thereby suppressing a decrease in the breakdown voltage. The second extension area 220 can be arranged in a larger area in the Y-axis direction than the floating area 202. The second extension area 220 can be connected to the area with reference to Fig. The first extension area 204 or the like described in section 4 must be connected to an end section in the Y-axis direction.

[0148] Fig. 9 is a view that shows an example of a cross-section ff in Fig. Figure 8 shows the cross-section ff, which is the XZ plane, comprising the well region 11, the transition region 92, and the transistor section 70. As described above, the outer gate rotor 130 is arranged above the well region 11. The outer gate rotor 130 and the well region 11 are insulated from each other by a dielectric film 221, such as an oxide film. Fig. 9 The structures of the upper surface side, such as the emitter electrode 52 and the dielectric interlayer film 38, and the structure of the lower surface side, such as the collector electrode 24, have been omitted.

[0149] The second extension area 220 is arranged below the lower ends of one or more trench sections located in the transition area 92. The second extension area 220 can be in contact with the lower end of each trench section. The second extension area 220 extends in the X-axis direction towards the transistor section 70 beyond the transition area 92.

[0150] The second extension area 220 extends to a region below the emitter region 12. The second extension area 220 can extend to a region below the lower end of at least one gate-trough section 40 of the transistor section 70. The floating region 202 is not located below the gate-trough section 40. By arranging the second extension area 220, it is possible to adjust the electric field distribution so that it is uniform in the transition region 92, thereby suppressing a decrease in the breakdown voltage.

[0151] Fig. Figure 10 is an XZ cross-section showing another structural example of the boundary region 90 and the diode section 80. In Fig. 10 The structures of the upper surface side, such as the emitter electrode 52 and the dielectric interlayer film 38, and the structure of the lower surface side, such as the collector electrode 24, have been omitted.

[0152] In the reference to Fig. 1 to Fig. In the example described in section 9, the boundary region 90 and the diode section 80 are not provided with the floating region 202. In the present example, at least one of the boundary region 90 or the diode section 80 is provided with the floating region 202. With reference to Fig. The structure described in point 10 can be attributed to one of those mentioned with reference to Fig. 1 to Fig. The 9 described examples can be applied. By arranging the floating region 202 in the boundary region 90, it is possible to adjust the electric field distributions so that they are uniform in transistor section 70, with the exception of boundary region 90. By arranging the floating region 202 in diode section 80, it is possible to adjust the electric field distributions so that they are uniform in transistor section 70 and diode section 80.

[0153] In the example of Fig. 10. The arrangement pattern of the trench sections in transistor section 70 differs from that in the example of Fig. 3 or the like. In the example of Fig. In section 10, a gate trench section 40 and a blind trench section 30 are arranged alternately in the X-axis direction. The arrangement pattern of the trench sections in transistor section 70 can either be the pattern in Fig. 3 or Fig. It could be 10 or another pattern. In the transistor section 70 in the present example, each gate trench section 40 is provided with the floating area 202.

[0154] The floating area 202 in the example of Fig. 10 does not extend to a position that overlaps with the trench section (the blind trench section 30 in the present example) which is arranged to be adjacent to the corresponding gate trench section 40. As with reference to Fig. 3 to Fig. As described in section 9, the suspended area 202 can extend to a position that overlaps with at least one trench section arranged so that it is adjacent to the gate trench section 40.

[0155] In the example of Fig. The boundary region 90 comprises a plurality of blind trench sections 30, a plurality of mesa sections 62, and one or more floating zones 202. The floating zone 202 is located below the lower end of at least one trench section of the boundary region 90. An interval F2 in which the floating zone 202 is located in the X-axis direction within the boundary region 90 can be the same as an interval F1 in which the floating zone 202 is located in the X-axis direction within the transistor section 70, excluding the boundary region 90. By adjusting the intervals in which the floating zones 202 are located so that they are equal to each other, it is also possible to adjust the electric field distribution to be uniform. The interval in which the floating zone 202 is located is a distance between the center positions of the respective floating zones 202 in the X-axis direction.

[0156] In the example of Fig. In 10, the floating region 202 is also arranged below the lower end of at least one trench section of the diode section 80. An interval F3, in which the floating region 202 is arranged in the X-axis direction in the diode section 80, can be the same as the interval F1 in the transistor section 70. By adjusting the intervals in which the floating regions 202 are arranged so that they are equal to each other, it is also possible to adjust the electric field distribution so that it is uniform.

[0157] In the boundary region 90, the plurality of floating areas 202 can be arranged individually in the Y-axis direction, or the floating area 202 can be arranged continuously as a single area. In the diode section 80, the plurality of floating areas 202 can be arranged individually in the Y-axis direction, or the floating area 202 can be arranged continuously as a single area.

[0158] The intervals F1, F2, and F3 of the floating ranges 202 cannot be equal. Interval F1 can be larger than or smaller than interval F2. Interval F1 can be larger than or smaller than interval F3. Interval F3 can be larger than or smaller than interval F2. By adjusting intervals F1 through F3, it is possible to adjust the breakdown voltage distributions of transistor section 70, limiting region 90, and diode section 80. For example, if interval F1 is set large, it is possible to lower the breakdown voltage of transistor section 70 and relatively increase the breakdown voltage of diode section 80. Conversely, by setting interval F3 large, it is possible to lower the breakdown voltage of diode section 80 and relatively increase the breakdown voltage of transistor section 70.Furthermore, the intervals F1 to F3 can be set so that the breakdown voltages of the transistor section 70, the limiting region 90 and the diode section 80 are equal.

[0159] The distances between all trench sections in the semiconductor device 100 in the X-axis direction can be equal. In another example, the distances between the trench sections in the X-axis direction can not be uniform.

[0160] Fig. Figure 11 is a diagram showing a collector voltage-collector current characteristic in an example and a reference example. The reference example is one in which the uncovered region 212 is not located in the first mesa section 60-1. The example is one in which the uncovered region 212 is located in the first mesa section 60-1.

[0161] In the reference example, the suspension region 202 makes it difficult for the electron current from the first mesa section 60-1 to flow to the collector region 22. Therefore, in the reference example, as in Fig. Figure 11 shows the snapshot, in which almost no collector current flows until the collector voltage exceeds a predetermined voltage. In contrast, in the semiconductor device 100 according to the example, the electron current from the first mesa section 60-1 flows easily to the collector region 22. Therefore, the snapshot does not occur.

[0162] Fig. Figure 12 is a diagram showing a trade-off property between a turn-on loss and a reverse recovery dV / dt in a reference example and an example. Fig. Figure 12 shows the trade-off relationship in which the turn-on loss is increased when the reverse recovery dV / dt is reduced.

[0163] The reference example in Fig. 12 is a semiconductor device that does not have a levitation region 202. The semiconductor device of the example is the semiconductor device 100, which is described with reference to Fig. 1 to Fig. As described in section 10, the semiconductor device 100 of the example has the floating range 202, which improves the compromise property. For example, if the reverse recovery dV / dt is set to the same value, the turn-on loss in the example is smaller than in the reference example.

[0164] As with reference to Fig. As described in section 12, it is possible with the semiconductor device 100 to improve the compromise property between the turn-on loss and the reverse recovery dV / dt. As described in section 12, Fig. As described in section 11, it is possible to suppress the snapback with the semiconductor device 100.

[0165] Although the present invention has been described with reference to the embodiments described above, its technical scope is not limited to these embodiments. It is obvious to those skilled in the art that various modifications or improvements can be made to the embodiments described above. It is also evident from the scope of the claims that embodiments added by such modifications or improvements can be included in the technical scope of the present invention.

[0166] The operations, procedures, steps, stages, or the like of any process performed by a device, system, program, or method shown in the claims, embodiments, or diagrams may be performed in any order, provided that the order is not specified by "before," "before," or the like, and provided that the output of a preceding process is not used in a subsequent process. Even if, for the sake of simplicity, the process flow is described in the claims, embodiments, or diagrams using expressions such as "first" or "next," this does not necessarily mean that the process must be performed in that order. REFERENCE MARK LIST 10 Semiconductor substrate 11 Bathtub area 12 emitter area 14 Basic area 15 Contact area 16 Collection area 18 Drift range 20 Buffer area 21 upper surface 22 Collector area 23 lower surface 24 Collector electrode 29 even pieces 30 Blind trench section 30-1 first blind trench section 30-2 second blind trench section 31 Marginal section 32 dielectric blind film 33 lower end 34 Blind line section 38 dielectric interlayer film 39 even pieces 40 Gattergraben section 40-1 first gate ditch section 41 marginal section 42 dielectric gate film 43 lower end 44 Gate line section 45 trench 52 Emitter electrode 54 Contact section 60, 61, 62, 63 Mesa section 60-1 first mesa section 60-2 second mesa section 70 Transistor section 80 diode section 81 Extension area 82 Cathode area 90 Border area 92 Transition area 100 semiconductor devices 130 outer-circumference gate runner 131 active-side gate runner 160 active section 162 Front 164 Gatterfeld 190 edge finish structure section 202 Floating area 202-1 first suspension area 204 first expansion area 212 uncovered area 220 second expansion area 221 dielectric film. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2020-21941

[0002] JP 2010-232627

[0002]

Claims

[1] Semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; one or more transistor sections having a collector region of a second conductivity type on the lower surface of the semiconductor substrate; and one or more diode sections having a cathode region of the first conductivity type on the lower surface of the semiconductor substrate and arranged alternately with the transistor sections in a first direction, wherein each of the transistor sections has a multitude of trench sections arranged side by side in the first direction, each containing one or more gate trench sections, a multitude of mesa sections, which are areas arranged between the trench sections in the first direction, and a floating area of ​​the second conductivity type, which is arranged for at least one of the gate trench sections and which is located below a lower end of the gate trench section, one or more gate trench sections have a first gate trench section that is arranged so that it is closest to the diode section, the multitude of mesa sections have a first mesa section that touches the first gate ditch section and is located between the first gate ditch section and the diode section, A first suspended area is arranged under the first section of the gate ditch, and the first mesa section has an uncovered area that does not overlap with the first floating area. [2] Semiconductor device according to claim 1, wherein the multitude of trench sections includes one or more blind trench sections, the first mesa section is located between the first gate ditch section and a first blind ditch section, and the first suspended area, which is located below the lower end of the first gate ditch section, does not extend to an area below a lower end of the first blind ditch section. [3] Semiconductor device according to claim 2, wherein the first suspended area in top view does not touch the first blind trench section. [4] Semiconductor device according to claim 3, wherein the multitude of ditch sections includes a second blind ditch section, which is located on a side of the first gate ditch section opposite the first blind ditch section, and In the first direction, the distance between the first suspended area and the second blind trench section is smaller than the distance between the first suspended area and the first blind trench section. [5] Semiconductor device according to claim 4, wherein the first floating area touches the second blind trench section in plan view. [6] Semiconductor device according to claim 1, wherein the first mesa section comprises an emitter region of the first conductivity type that touches the upper surface of the semiconductor substrate, and a base region of the second conductivity type, which is located between the emitter region and the drift region, the first mesa section has a longitudinal dimension in a second direction, and The first mesa section has the uncovered area in an intermediate region between both ends of the emitter region in the second direction. [7] Semiconductor device according to claim 6, wherein in the intermediate region a plurality of uncovered regions, each of which is the uncovered region, are individually arranged in the second direction. [8] Semiconductor device according to claim 7, wherein in the intermediate region the total length of the plurality of uncovered regions in the second direction is less than the total length of regions in the second direction that overlap with the first levitation region. [9] Semiconductor device according to claim 7, wherein the first mesa section has a contact area of ​​the second conductivity type that touches the upper surface of the semiconductor substrate and is arranged alternately with the emitter area in the second direction, and the first floating area is arranged under at least one of the emitter areas, each of which is the emitter area, and at least part of the contact area is the uncovered area. [10] Semiconductor device according to claim 9, wherein the first floating region overlaps the entirety of at least one of the emitter regions, and Each of the contact areas, which is the contact area, has the uncovered area. [11] Semiconductor device according to claim 6, further comprising: a trough area of ​​the second conductivity type, located outside the first mesa section in the second direction and exhibiting a higher concentration than that of the base area; and a first extension area of ​​the second conductivity type, which extends in the second direction from the trough area to a position that overlaps with the emitter area. [12] Semiconductor device according to claim 6, further comprising: a trough region of the second conductivity type, located outside the emitter region in the first direction and exhibiting a higher concentration than that of the base region; and a second extension area of ​​the second conductivity type, extending in the first direction from the trough area to a position that overlaps with the emitter area. [13] Semiconductor device according to claim 1, wherein the diode section a large number of blind trench sections arranged side by side in the first direction, and a mesa section arranged between the blind trench sections in the first direction, and the floating area is also located below a lower end of at least one of the blind trench sections of the diode section. [14] Semiconductor device according to claim 13, wherein an interval in which the floating region is arranged in the first direction in the diode section is the same as an interval in which the floating region is arranged in the first direction in the transistor section. [15] Semiconductor device according to claim 1, wherein the transistor section has a boundary region that includes one or more of the trench sections and one or more of the mesa sections between the first gate trench section and the diode section, and the suspended area is also located below a lower end of at least one of the trench sections of the boundary area. [16] Semiconductor device according to claim 15, wherein an interval in which the floating region in the first direction is arranged in the boundary region is the same as an interval in which the floating region in the first direction is arranged in the transistor section except for the boundary region. [17] Semiconductor device according to any one of claims 1 to 16, wherein an area of ​​the uncovered region in the first mesa section is larger than an area of ​​a region that does not overlap with the floating region in the mesa section in contact with the gate ditch section except for the first gate ditch section.

Images