Semiconductor device, semiconductor assembly and vehicle

Abstract

A semiconductor device comprises: a support conductor having a first front surface facing a first side in a thickness direction; a plurality of semiconductor elements, including four or more semiconductor elements, arranged on the first front surface; and a sealing resin covering the plurality of semiconductor elements and the support conductor. The plurality of semiconductor elements is arranged side by side in a first direction perpendicular to the thickness direction and includes a first semiconductor element and a second semiconductor element located near a center in the first direction.A first distance, which is a distance between a center of the first semiconductor element and a center of the second semiconductor element, is greater than a second distance, which is a distance between the center of one of the first semiconductor element and the second semiconductor element and a center of one of a third semiconductor element and a fourth semiconductor element, which is adjacent to one of the first semiconductor element and the second semiconductor element in the first direction.

Description

TECHNICAL AREA

[0001] The present disclosure relates to a semiconductor device, a semiconductor device assembly and a vehicle. STATE OF THE ART

[0002] Semiconductor devices incorporating a variety of power switching elements, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated-gate bipolar transistors (IGBTs), are conventionally known. These semiconductor devices are mounted in a wide variety of electronic devices, ranging from industrial equipment to household appliances and information terminals, or even devices mounted in vehicles. Patent document 1 discloses a conventional semiconductor device. In the semiconductor device disclosed in patent document 1, a plurality of semiconductor chips (semiconductor elements) are arranged on a line (a conductor). The semiconductor chips are linearly aligned at predetermined intervals in an x-direction perpendicular to a thickness direction of the line.

[0003] During operation, semiconductor chips generate heat. In recent years, the amount of heat generated by semiconductor chips has increased with the current-carrying capacity of semiconductor devices. In semiconductor chips aligned as described above, disturbances caused by heat generated by the semiconductor chips lead to a temperature increase. A semiconductor chip positioned near the center of the x-axis (the direction in which the semiconductor chips are aligned) is strongly affected by thermal disturbances from a neighboring semiconductor chip and can reach a high temperature due to heat concentration. The effect of such thermal disturbances leads to an increase in thermal resistance and prevents a large current from flowing through the semiconductor device. STATE OF THE ART Patent document

[0004] Patent document 1: WO 2019 / 244372 BRIEF DESCRIPTION OF THE INVENTION Problem to be solved by the invention

[0005] One objective of the present disclosure is to provide a semiconductor device that is improved compared to conventional semiconductor devices. In particular, in view of the circumstances described above, one objective of the present disclosure is to provide a semiconductor device that is suitable for suppressing the disturbances caused by heat generated by a plurality of semiconductor elements and for reducing thermal resistance. Means to solve the problem

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a conductor with a first front surface facing a first side in a thickness direction, and a first back surface facing a side opposite the first front surface; a plurality of semiconductor elements comprising four or more semiconductor elements arranged on the first front surface; and a sealing resin covering the plurality of semiconductor elements and at least one section of the conductor. The plurality of semiconductor elements is arranged side by side in a first direction perpendicular to the thickness direction. If the number of semiconductor elements is even, the plurality of semiconductor elements comprises a first semiconductor element and a second semiconductor element arranged near a center in the first direction.A first distance, which is the distance between the center of the first semiconductor element and the center of the second semiconductor element, is greater than a second distance, which is the distance between the center of one of the first and second semiconductor elements and the center of another semiconductor element adjacent to the first and second semiconductor elements in the first direction. If the number of semiconductor elements is odd, the plurality of semiconductor elements includes a third semiconductor element located near the center in the first direction, a fourth semiconductor element adjacent to the third semiconductor element on one side in the first direction, and a fifth semiconductor element adjacent to the third semiconductor element on a second side in the first direction.A third distance, which is a distance between the center of the third semiconductor element and the center of the fourth semiconductor element, and a fourth distance, which is a distance between the center of the third semiconductor element and the center of the fifth semiconductor element, are each greater than a fifth distance, which is a distance between the center of one of the fourth semiconductor element and the fifth semiconductor element and the center of another of the semiconductor elements, adjacent to one of the fourth semiconductor element and the fifth semiconductor element in the first direction.

[0007] A second aspect of the present disclosure provides a semiconductor device assembly comprising: the semiconductor device according to the first aspect of the present disclosure; a cooler; and a cooling unit that cools the cooler. The second rear surface of the support is exposed by the sealing resin, and the cooler includes a section that is in contact with the second rear surface.

[0008] A third aspect of the present disclosure provides a vehicle which includes: a power conversion device configured to include the semiconductor device according to the first aspect of the present disclosure. Advantages of the invention

[0009] This configuration can suppress thermal disturbances between the semiconductor elements and reduce thermal resistance.

[0010] Other features and advantages of the present disclosure will become clearer from the detailed description below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. Fig. Figure 2 is a top view showing the semiconductor device according to the first embodiment of the present disclosure. Fig. Figure 3 is a top view showing the semiconductor device according to the first embodiment of the present disclosure. Fig. Figure 4 is a view from below, showing the semiconductor device according to the first embodiment of the present disclosure. Fig. 5 is a cross-sectional view along the in Fig. Line VV shown in 3. Fig. 6 is a cross-sectional view along the in Fig. 3 shown line VI-VI. Fig. 7 is a cross-sectional view along the in Fig. 3 shown line VII-VII. Fig. 8 is a cross-sectional view along the in Fig. 3 lines shown VIII-VIII. Fig. Figure 9 is a schematic top view showing the arrangement of a plurality of semiconductor elements in the semiconductor device according to the first embodiment of the present disclosure. Fig. Figure 10 is a schematic view showing a vehicle having the semiconductor device according to the first embodiment of the present disclosure. Fig. Figure 11 is a cross-sectional view showing a first example of a semiconductor device assembly comprising the semiconductor device according to the first embodiment of the present disclosure. Fig. Figure 12 is a block diagram showing a configuration of the semiconductor device assembly in Fig. 11 shows. Fig. Figure 13 is a cross-sectional view showing a second example of a semiconductor device assembly comprising the semiconductor device according to the first embodiment of the present disclosure. Fig. Figure 14 is a schematic top view showing a variation in the arrangement of the semiconductor elements. Fig. Figure 15 is a schematic top view showing a variation in the arrangement of the semiconductor elements. Fig. Figure 16 is a schematic top view showing a variation in the arrangement of the semiconductor elements. Fig. Figure 17 is a schematic top view showing a variation in the arrangement of the semiconductor elements. Fig. Figure 18 is a top view showing a semiconductor device according to a second embodiment of the present disclosure. Fig. 19 is a cross-sectional view along the in Fig. 18 shown line XIX-XIX. Fig. 20 is a cross-sectional view along the in Fig. Line XX-XX shown in 18. Fig. 21 is a cross-sectional view along the in Fig. 18 shown line XXI-XXI. Fig. Figure 22 is a schematic top view showing the arrangement of a plurality of semiconductor elements in the semiconductor device according to the second embodiment of the present disclosure. Fig. Figure 23 is a top view showing a semiconductor device according to a third embodiment of the present disclosure. Fig. Figure 24 is a schematic top view showing the arrangement of a plurality of semiconductor elements in the semiconductor device according to the third embodiment of the present disclosure. Fig. Figure 25 is a schematic view showing a vehicle having the semiconductor device according to the third embodiment of the present disclosure. Fig. Figure 26 is a schematic top view showing the arrangement of a plurality of semiconductor elements in a semiconductor device according to a first variation of the third embodiment. Fig. Figure 27 is a schematic top view showing the arrangement of the plurality of semiconductor elements in the semiconductor device according to the first variation of the third embodiment. Fig. Figure 28 is a schematic top view showing the arrangement of the plurality of semiconductor elements in the semiconductor device according to the first variation of the third embodiment. Fig. Figure 29 is a schematic top view showing the arrangement of the plurality of semiconductor elements in the semiconductor device according to the first variation of the third embodiment. MODE FOR EXECUTING THE INVENTION

[0011] Preferred embodiments of the present disclosure are described in detail below with reference to the drawings.

[0012] The terms “first”, “second” and “third” in the present revelation are used only for identification purposes and are not intended to indicate any order for the elements that are accompanied by these terms.

[0013] In the present disclosure, unless otherwise specified, the expressions "an object A is formed in an object B" and "an object A is formed on an object B" include "an object A is formed directly in / on an object B" and "an object A is formed in / on an object B with another object inserted between object A and object B." Similarly, unless otherwise specified, the expressions "an object A is set up in an object B" and "an object A is set up on an object B" include "an object A is set up directly in / on an object B" and "an object A is set up in / on an object B with another object inserted between object A and object B."Similarly, unless otherwise specified, the expression "an object A is located on an object B" includes "an object A is located on an object B in contact with object B" and "an object A is located on an object B with another object inserted between object A and object B." Furthermore, unless otherwise specified, the expression "an object A overlaps with an object B in a certain direction" includes "an object A overlaps with the entirety of an object B" and "an object A overlaps with a part or section of an object B." Furthermore, the expression "a plane A faces (a first side or a second side) in a direction B" is not limited to the case where the angle of plane A with respect to direction B is 90°, but also includes the case where plane A is inclined with respect to direction B. First embodiment:

[0014] Fig. Figures 1 to 8 show a semiconductor device according to a first embodiment of the present disclosure. A semiconductor device A1 of the present embodiment comprises a plurality of conductors or terminals 1, a plurality of conductors or terminals 2, a support 3, a carrier conductor 32, a plurality of semiconductor elements 4, a wiring section 5, a thermistor 6, a plurality of wires 71, a plurality of wires 72, a plurality of wires 73, a plurality of wires 74 and a sealing resin 8.

[0015] Fig. Figure 1 is a perspective view showing the semiconductor device A1. Fig. Figure 2 is a top view showing the semiconductor device A1. Fig. Figure 3 is a top view showing the semiconductor device A1 as seen through the sealing resin 8. Fig. Figure 4 is a view from below, showing the semiconductor device A1. Fig. 5 is a cross-sectional view along the in Fig. Line VV shown in 3. Fig. 6 is a cross-sectional view along the in Fig. 3 shown line VI-VI. Fig. 7 is a cross-sectional view along the in Fig. 3 shown line VII-VII. Fig. 8 is a cross-sectional view along the in Fig. Line VIII-VIII shown in 3. The outline of the sealing resin 8 is in Fig. 3 is indicated by an imaginary line (two-dotted line). In Fig. Wires 71 are omitted in numbers 5 to 8.

[0016] In the description of semiconductor device A1, the thickness direction (top view direction) of the carrier 3 is an example of a “thickness direction” in the present disclosure and is referred to as a “thickness direction z”. A direction perpendicular to the thickness direction z is an example of a “first direction” in the present disclosure and is referred to as a “first direction x”. The direction perpendicular to the thickness direction z and to the first direction x is an example of a “second direction” in the present disclosure and is referred to as a “second direction y”. The left side in Fig. 2 and Fig. Figure 3 in the present revelation is an example of a “first side in the first direction” and is referred to as an “x1-side in the first direction x”. The right side in Fig. 2 and Fig. Figure 3 is an example of a "second side in the first direction" and is referred to as an "x2 side in the first direction x". The top side in Fig. 2 and Fig. Figure 3 in the present revelation is an example of a “first side in the second direction” and is referred to as a “y1-side in the second direction y”. The lower side in Fig. 2 and Fig. Figure 3 in the present revelation is an example of a “second side in the second direction” and is referred to as a “y2-side in the second direction y”. The top side in Fig. Figures 5 to 8 in the present disclosure are an example of a “first side in the thickness direction” and are referred to as a “z1 side in the thickness direction z”. The underside in Fig. 5 to 8 is an example of a “second side in the thickness direction” and is referred to as a “z2 side in the thickness direction z”.

[0017] As in Fig. 3 and Fig. As shown in Figures 5 to 8, the support 3 and the conductor 32 support the semiconductor elements 4. The support 3 is not particularly limited to a specific configuration and can be an active metal solder substrate (AMB substrate) or a direct-bonded copper substrate (DBC substrate). In the present embodiment, the support 3 is made of an insulating substrate 31 and a metal layer 33. The support 3 has a second front surface 3a and a second rear surface 3b. The second front surface 3a faces the z1 side in the thickness direction z. The second rear surface 3b faces the side opposite the second front surface 3a (the z2 side in the thickness direction z). The AMB substrate or the DBC substrate serving as the support 3 comprises the insulating substrate 31, the conductor 32, and the metal layer 33.The total thickness (the dimension in the thickness direction z) of the insulating substrate 31, the carrier conductor 32 and the metal layer 33 in the carrier 3 is not particularly limited and can be approximately 0.4 mm to 3.0 mm.

[0018] The insulating substrate 31 is, for example, made of a ceramic material with excellent thermal conductivity. Examples of such ceramic materials include silicon nitride (SiN) and aluminum oxide (Al₂O₃). The material of the insulating substrate 31 is not limited to ceramics and can, for example, be an insulating resin sheet. The shape of the insulating substrate 31 is not particularly restricted and can be a rectangle in plan view. In the present embodiment, the insulating substrate 31 has a rectangular shape, elongated in the first direction x, when viewed in the thickness direction z. The insulating substrate 31 has a second front surface 3a. The second front surface 3a is a plane facing the z1 side in the thickness direction z. The thickness of the insulating substrate 31 is not particularly restricted and can be approximately 0.05 mm to 1.0 mm.

[0019] The carrier conductor 32 is formed on the second front surface 3a of the insulating substrate 31. The component material of the carrier conductor 32 contains, for example, copper (Cu). The component material can contain aluminum (Al) instead of copper. For example, the use of the DBC substrate or the like and the structuring of a copper foil bonded to the second front surface 3a can facilitate the formation of the carrier conductor 32, which encloses a first conductor 321 up to an eighth conductor 328, as described below. The carrier conductor 32 has a first front surface 32a and a first back surface 32b. The first front surface 32a faces the z1 side in the thickness direction z. The first rear surface 32b faces the side opposite the first front surface 32a (the z2 side in the thickness direction z) and faces the second front surface 3a.The thickness of the carrier conductor 32 is not particularly limited and can be approximately 0.1 mm to 1.5 mm.

[0020] The support conductor 32 has a first conductor 321, a second conductor 322, a third conductor 323, a fourth conductor 324, a fifth conductor 325, a sixth conductor 326, a seventh conductor 327, and an eighth conductor 328. The surfaces of the first conductor 321 to the eighth conductor 328 may be coated with silver (Ag).

[0021] The first conductor 321 is located near the center in the first direction x on the second front surface 3a of the insulating substrate 31. The first conductor 321 carries one of the semiconductor elements 4. The second conductor 322 is located on the x2 side in the first direction x relative to the first conductor 321 and is adjacent to the first conductor 321. The second conductor 322 carries one of the semiconductor elements 4. The third conductor 323 is located on the x1 side in the first direction x relative to the first conductor 321 and is adjacent to the first conductor 321. The third conductor 323 carries one of the semiconductor elements 4. The fourth conductor 324 is located on the x1 side in the first direction x relative to the third conductor 323 and is adjacent to the third conductor 323. The fourth conductor 324 carries one of the semiconductor elements 4.

[0022] The fifth conductor 325 and the sixth conductor 326 are located near the corner of the insulating substrate 31 on the x2 side in the first direction x and on the y1 side in the second direction y. A wire 73 is connected to the fifth conductor 325. A wire 72 is connected to the sixth conductor 326. The seventh conductor 327 and the eighth conductor 328 are located near the corner of the insulating substrate 31 on the x1 side in the first direction x and on the y1 side in the second direction y. The seventh conductor 327 and the eighth conductor 328 are located on the x1 side in the first direction x relative to the third conductor 323 and on the y1 side in the second direction y relative to the fourth conductor 324. A wire 73 is connected to the seventh conductor 327. A wire 72 is connected to the eighth conductor 328. The support conductor 32, which carries the semiconductor elements 4, corresponds to an example of a “conductor” in the present disclosure.

[0023] The metal layer 33 is bonded to the lower surface (the surface facing the z2 side in the thickness direction z) of the insulating substrate 31. The metal layer 33 is made of the same material as the carrier conductor 32. The metal layer 33 has a second rear surface 3b. The second rear surface 3b is a plane facing the z2 side in the thickness direction z. In the present embodiment, the second rear surface 3b is exposed by the sealing resin 8. A heat dissipation component (e.g., a heat sink), not shown in the figures, can be attached to the second rear surface 3b. A structure (e.g., an AMB substrate or a DBC substrate) made from the carrier conductor 32 and the support 3 (i.e., the insulating substrate 31 and the metal layer 33) has, for example, a heat capacity of 0.01 to 15 J / K. The structure (e.g.,an AMB substrate or a DBC substrate), which is made from the carrier conductor 32 and the carrier 3, has, for example, a thermal resistance of 0.0003 to 1.5 K / W.

[0024] The wiring section 5 is formed on the second front surface 3a of the insulating substrate 31. The wiring section 5 is made of a conductive material. The conductive material of the wiring section 5 is not particularly restricted. The conductive material of the wiring section 5 can contain silver (Ag), copper (Cu), or gold (Au). The following description is based on an example where the wiring section 5 contains silver. It should be noted that the wiring section 5 can contain copper instead of silver, or gold instead of silver or copper. Alternatively, the wiring section 5 can contain Ag-Pt or Ag-Pd. The method for forming the wiring section 5 is not particularly restricted. For example, the wiring section 5 can be formed by sintering a paste containing these metals. The thickness of the wiring section 5 is not particularly restricted and can be approximately 5 µm to 30 µm.Wiring section 5 is thinner than the carrier conductor 32.

[0025] The shape, etc., of the wiring section 5 is not particularly restricted. In the present embodiment, the wiring section 5 has two wires 501, as shown in Fig. Figure 3 shows that the two wires 501 are located near the corner of the insulating substrate 31 on the x1 side in the first direction x and on the y1 side in the second direction y. The two wires 501 are spaced apart and aligned in the second direction y. Each of the wires 501 has a pad section 502. The pad section 502 is located at the end of the wire 501 on the x2 side in the first direction x. The two pad sections 502 are bonded to respective terminals of the thermistor 6.

[0026] For example, each of the conductors 1 contains a metal and has a higher thermal conductivity than the insulating substrate 31. The metal in each conductor 1 is not particularly restricted and can be copper, aluminum, iron (Fe), oxygen-free copper, or any alloy thereof (e.g., Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). The conductors 1 can be nickel (Ni) plated. The conductors 1 can be formed by pressing a die onto a metal plate or by etching a metal plate. The method for forming the conductors 1 is not particularly restricted. The thickness of each conductor 1 is not particularly restricted and can be approximately 0.4 mm to 0.8 mm. The conductors 1 are spaced apart from each other.

[0027] In the present embodiment, the conductors 1 include a conductor 11, a conductor 12, a conductor 13, a conductor 14, and a conductor 15. The conductors 11, 12, 13, 14, and 15 form the conductive paths to the semiconductor elements 4 and project from the side surface (a lateral resin surface 86 described below) of the sealing resin 8, which extends in the second direction y of the y2-side (the lower side in Fig. 2) is facing it.

[0028] Line 11 is installed on the support conductor 32. In the present embodiment, line 11 is installed on the second conductor 322. As in Fig. As shown in Figure 7, conductor 11 is bonded to the second conductor 322 via a conductive bonding material 19. The conductive bonding material 19 can be any material capable of bonding conductor 11 to the second conductor 322 and electrically connecting them. Examples of conductive bonding material 19 include silver paste, copper paste, and solder.

[0029] The configuration of the line 11 is not particularly restricted. In the present embodiment, the line 11 is subdivided for description into a connecting end section 111, a projecting section 112, an inclined section 113, and a parallel section 114, as shown in Fig. 3 and Fig. 7 shown.

[0030] The connecting end section 111 is rectangular in plan view and bonded to the second conductor 322. The connecting end section 111 is electrically bonded to the end of the second conductor 322 on the y2 side in the second direction y via the conductive bonding material 19. The inclined section 113 and the parallel section 114 are covered with the sealing resin 8. The inclined section 113 is connected to the connecting end section 111 and the parallel section 114 and is inclined relative to the connecting end section 111 and the parallel section 114. The parallel section 114 is connected to the inclined section 113 and the protruding section 112 and runs parallel to the connecting end section 111. The protruding section 112 is the section of the conductor 11 that protrudes from the sealing resin 8 and is connected to one end of the parallel section 114.In the illustrated example, two protruding sections 112 are provided with a gap between them in the first direction x. The protruding sections 112 project in the second direction y towards the side opposite the connecting end section 111. The protruding sections 112 can be used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding sections 112 are bent towards the side facing the second front surface 3a of the insulating substrate 31 in the thickness direction z.

[0031] The conductor 12 is arranged on the carrier conductor 32. In the present embodiment, the conductor 12 is arranged on the first conductor 321. The conductor 12 is bonded to the first conductor 321 via a conductive bonding material. The configuration of the conductor 12 is not particularly restricted. In the present embodiment, the conductor 12 is subdivided for description into a connecting end section 121, a projecting section 122, an inclined section 123, and a parallel section 124, as shown in Fig. 3 shown.

[0032] The connecting end section 121 is rectangular in plan view and bonded to the first conductor 321. The connecting end section 121 is electrically bonded to the end of the first conductor 321 on the y2 side in the second direction y via the conductive bonding material. The inclined section 123 and the parallel section 124 are covered with the sealing resin 8. The inclined section 123 is connected to the connecting end section 121 and the parallel section 124 and is inclined relative to the connecting end section 121 and the parallel section 124. The parallel section 124 is connected to the inclined section 123 and the projecting section 122 and runs parallel to the connecting end section 121. A wire 71 is connected to the parallel section 124. The protruding section 122 is the section of the conduit 12 that protrudes from the sealing resin 8 and is connected to one end of the parallel section 124.The projecting section 122 extends in the second direction y towards the side opposite the connecting end section 121. The projecting section 122 can be used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the projecting section 122 is bent towards the side facing the second front surface 3a of the insulating substrate 31 in the thickness direction z.

[0033] Line 13 is installed on the support conductor 32. In the present embodiment, line 13 is installed on the third conductor 323. As in Fig. As shown in Figure 6, the conductor 13 is bonded to the third conductor 323 via a conductive bonding material 19. The configuration of the conductor 13 is not particularly restricted. In the present embodiment, the conductor 13 is subdivided for description into a connection end section 131, a projecting section 132, an inclined section 133, and a parallel section 134, as shown in Figure 6. Fig. 3 and Fig. 6 shown.

[0034] The connecting end section 131 is rectangular in plan view and bonded to the third conductor 323. The connecting end section 131 is electrically bonded to the end of the third conductor 323 on the y2 side in the second direction y via the conductive bonding material 19. The inclined section 133 and the parallel section 134 are covered with the sealing resin 8. The inclined section 133 is connected to the connecting end section 131 and the parallel section 134 and is inclined relative to the connecting end section 131 and the parallel section 134. The parallel section 134 is connected to the inclined section 133 and the projecting section 132 and runs parallel to the connecting end section 131. A wire 71 is connected to the parallel section 134. The protruding section 132 is the section of the conduit 13 that protrudes from the sealing resin 8 and is connected to one end of the parallel section 134.The projecting section 132 extends in the second direction y towards the side opposite the connecting end section 131. The projecting section 132 can be used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the projecting section 132 is bent towards the side facing the second front surface 3a of the insulating substrate 31 in the thickness direction z.

[0035] The conductor 14 is arranged or configured on the carrier conductor 32. In the present embodiment, the conductor 14 is configured on the fourth conductor 324. The conductor 14 is bonded to the fourth conductor 324 via a conductive bonding material. The configuration of the conductor 14 is not particularly restricted. In the present embodiment, the conductor 14 is subdivided for description into a connecting end section 141, a projecting section 142, an inclined section 143, and a parallel section 144, as shown in Fig. 3 shown.

[0036] The connecting end section 141 is rectangular in plan view and bonded to the fourth conductor 324. The connecting end section 141 is electrically bonded to the end of the fourth conductor 324 on the y2 side in the second direction y via the conductive bonding material. The inclined section 143 and the parallel section 144 are covered with the sealing resin 8. The inclined section 143 is connected to the connecting end section 141 and the parallel section 144 and is inclined relative to the connecting end section 141 and the parallel section 144. The parallel section 144 is connected to the inclined section 143 and the projecting section 142 and runs parallel to the connecting end section 141. A wire 71 is connected to the parallel section 144. The protruding section 142 is the section of the conduit 14 that protrudes from the sealing resin 8 and is connected to one end of the parallel section 144.The projecting section 142 extends in the second direction y towards the side opposite the connecting end section 141. The projecting section 142 can be used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the projecting section 142 is bent towards the side facing the second front surface 3a of the insulating substrate 31 in the thickness direction z.

[0037] In the present embodiment, the conductor 15 is not mounted on the support conductor 32 and is supported by the sealing resin 8. The conductor 15 does not include sections corresponding to the connecting end section 131 and the inclined section 133 of the conductor 13. It should be noted that the conductor 15 is not limited to this configuration. In the present embodiment, the conductor 15 is divided, for the sake of description, into a projecting section 152 and a parallel section 154, as shown in Fig. 3 shown.

[0038] The parallel section 154 is covered with the sealing resin 8. The parallel section 154 is parallel to the carrier conductor 32. A wire 71 is bonded to the parallel section 154. The protruding section 152 is the portion of the conductor 15 that protrudes from the sealing resin 8 and is connected to one end of the parallel section 154. The protruding section 152 projects in the second direction y from the sealing resin 8 towards the y2 side. The protruding section 152 can be used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding section 152 is bent towards the side facing the second front surface 3a of the insulating substrate 31 in the thickness direction z.

[0039] For example, each of the conductors 2 contains a metal and has a higher thermal conductivity than the insulating substrate 31. The metal in each conductor 2 is not particularly restricted and can be copper, aluminum, iron (Fe), oxygen-free copper, or any alloy thereof (e.g., Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). The conductors 2 can be nickel (Ni) plated. The conductors 2 can be formed by pressing a die onto a metal plate or by structuring a metal plate by etching. The method for forming the conductors 2 is not particularly restricted. The thickness of each conductor 2 is not particularly restricted and can be approximately 0.4 mm to 0.8 mm. The conductors 2 are spaced apart from each other.

[0040] In the present embodiment, the conductors 2 enclose a plurality of conductors 21, a plurality of conductors 22, and two conductors 23. The conductors 21 and the conductors 22 form conductive paths to source electrodes 43 and gate electrodes 44 (which are described below) of the semiconductor elements 4 and project from the side surface of the sealing resin 8 (a lateral resin surface 85 described below), which extends in the second direction y of the y1-side (the upper side in Fig. 2) is facing. The two conductors 23 form a conductive path to the thermistor 6 and protrude from the side surface of the sealing resin 8, which faces the y1 side in the second direction y.

[0041] The conductors 21 are not mounted on the carrier conductor 32 and are supported by the sealing resin 8. The conductors 21 are arranged at intervals in the first direction x. The configuration of each conductor 21 is not particularly restricted. In the present embodiment, each of the conductors 21 is subdivided for description into a projecting section 212 and a parallel section 214, as shown in Fig. 3 and Fig. 6 shown.

[0042] The parallel section 214 is covered with the sealing resin 8. The parallel section 214 is parallel to the carrier conductor 32. A wire 73 is connected to the parallel section 214. The protruding section 212 is the portion of the conductor 21 that protrudes from the sealing resin 8 and is connected to one end of the parallel section 214. The protruding section 212 projects in the second direction y from the sealing resin 8 towards the y1 side. The protruding section 212 can be used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding section 212 is bent towards the side facing the second front surface 3a of the insulating substrate 31 in the thickness direction z.

[0043] The conductors 22 are not mounted on the carrier conductor 32 and are supported by the sealing resin 8. The conductors 22 are spaced at intervals in the first direction x. Each conductor 22 is positioned close to one of the conductors 21 to form a pair with it. The configuration of each conductor 22 is not particularly restricted. In the present embodiment, each conductor 22 is subdivided for description into a projecting section 222 and a parallel section 224, as shown in Fig. 3 and Fig. 7 shown.

[0044] The parallel section 224 is covered with the sealing resin 8. The parallel section 224 is parallel to the carrier conductor 32. A wire 72 is connected to the parallel section 224. The protruding section 222 is the portion of the conductor 22 that protrudes from the sealing resin 8 and is connected to one end of the parallel section 224. The protruding section 222 projects in the second direction y from the sealing resin 8 towards the y1 side. The protruding section 222 can be used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding section 222 is bent towards the side facing the second front surface 3a of the insulating substrate 31 in the thickness direction z.

[0045] The two conductors 23 are not mounted on the carrier conductor 32 and are supported by the sealing resin 8. The two conductors 23 are aligned in the first direction x. The configuration of each conductor 23 is not particularly restricted. In the present embodiment, each of the conductors 23 is subdivided for description into a projecting section 232 and a parallel section 234, as shown in Fig. 3 and Fig. 5 shown.

[0046] The parallel section 234 is covered with the sealing resin 8. The parallel section 234 is parallel to the carrier conductor 32. A wire 74 is connected to the parallel section 234. The protruding section 232 is the portion of the conductor 23 that protrudes from the sealing resin 8 and is connected to one end of the parallel section 234. The protruding section 232 projects in the second direction y from the sealing resin 8 towards the y1 side. The protruding section 232 can be used to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding section 232 is bent towards the side facing the second front surface 3a of the insulating substrate 31 in the thickness direction z.

[0047] The semiconductor elements 4 are electronic components that are integral to the function of the semiconductor device A1. In the present embodiment, the semiconductor elements 4 are switching elements. The semiconductor elements 4 are arranged on the first front surface 32a of the carrier conductor 32. In particular, four or more semiconductor elements 4 are arranged at intervals, and each of these semiconductor elements 4 is supported by a conductor 321 to the fourth conductor 324 of the carrier conductor 32. In the present embodiment, the semiconductor elements 4 include semiconductor elements 40A to 40F. Although six semiconductor elements, namely semiconductor elements 40A to 40F, are provided in the illustrated example, the number of semiconductor elements 4 is not limited as long as the number is four or more.

[0048] Each of the semiconductor elements 4 (semiconductor elements 40A to 40F) can include at least one wide-bandgap semiconductor and one ultra-wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include silicon carbide (SiC) and gallium nitride (GaN). Examples of ultra-wide-bandgap semiconductors include gallium oxide (Ga₂O₃) and diamond (C). In the present embodiment, each of the semiconductor elements 4 (semiconductor elements 40A to 40F) can be a SiC MOSFET (SiC metal-oxide-semiconductor field-effect transistor), i.e., a MOSFET with a silicon carbide substrate (SiC substrate). Each of the semiconductor elements 4 can be a MOSFET with a silicon substrate (Si substrate) instead of a SiC substrate and can include an IGBT element. Alternatively, each of the semiconductor elements 4 can be a MOSFET containing gallium nitride (GaN).Furthermore, the semiconductor elements can be 4 diodes instead of the switching elements described above.

[0049] As in Fig. 3 and Fig. As shown in Figures 5 to 8, each of the semiconductor elements 4 has a rectangular plate shape in plan view and includes a front element surface 41, a back element surface 42, a source electrode 43, a gate electrode 44, and a drain electrode 45. The front element surface 41 and the back element surface 42 face away from each other in the thickness direction z. The front element surface 41 faces the z1 side in the thickness direction z. The back element surface 42 faces the z2 side in the thickness direction z. As shown in Fig. As shown in Figure 3, the source electrode 43 and the gate electrode 44 are positioned on the front surface of the element 41. As shown in Fig. As shown in Figures 5 to 7, the drain electrode 45 is positioned on the back surface of the element 42. The shape and arrangement of each of the source electrode 43, the gate electrode 44, and the drain electrode 45 are not particularly restricted. In the illustrated example, the source electrode 43 is larger than the gate electrode 44 when viewed in the thickness direction z. The source electrode 43 is composed of two separate regions when viewed in the thickness direction z. For example, each of the semiconductor elements 4 has a heat capacity of 0.0001 to 0.5 J / K. For example, each of the semiconductor elements 4 has a thermal resistance of 0.0003 to 1.5 K / W.

[0050] As in Fig. 3, Fig. 7 and Fig. As shown in Figure 8, the semiconductor elements 40A, 40B, and 40C are set up or arranged on the second conductor 322. As shown in Fig. 7 and Fig. As shown in Figure 8, each of the semiconductor elements 40A, 40B, and 40C is bonded to the second conductor 322 via a conductive bonding material 47, with the rear surface 42 of the element facing the second conductor 322. This electrically connects the drain electrode 45 of each of the semiconductor elements 40A, 40B, and 40C to the second conductor 322 via the conductive bonding material 47. The conductive bonding material 47 can be, for example, silver paste, copper paste, or solder. As shown in Fig. As shown in Figure 3, the source electrode 43 of the semiconductor element 40A is electrically connected to line 12 via a wire 71. The source electrode 43 of the semiconductor element 40B is electrically connected to line 13 via a wire 71. The source electrode 43 of the semiconductor element 40C is electrically connected to line 14 via a wire 71. The wires 71 are made of materials such as aluminum (Al) or copper (Cu). The material, diameter, and number of wires 71 are not limited.

[0051] As in Fig. As shown in Figure 3, the semiconductor element 40D is positioned on the first conductor 321. The semiconductor element 40D is bonded to the second conductor 322 via a conductive bonding material (not illustrated), with the rear surface 42 of the element facing the first conductor 321. This electrically connects the drain electrode 45 of the semiconductor element 40D to the first conductor 321 via the conductive bonding material. The source electrode 43 of the semiconductor element 40D is electrically connected to the conductor 15 via a wire 71.

[0052] As in Fig. 3, Fig. 6 and Fig. As shown in Figure 8, the semiconductor element 40E is mounted on the third conductor 323. Fig. 6 and Fig. As shown in Figure 8, the semiconductor element 40E is bonded to the third conductor 323 via a conductive bonding material 47, with the rear surface 42 of the element facing the third conductor 323. This electrically connects the drain electrode 45 of the semiconductor element 40E to the third conductor 323 via the conductive bonding material 47. As shown in Fig. As shown in Figure 3, the source electrode 43 of the semiconductor element 40E is electrically connected to the conductor 15 via a wire 71.

[0053] As in Fig. 3 and Fig. As shown in Figure 5, the semiconductor element 40F is mounted on the fourth conductor 324. As shown in Figure 5, the semiconductor element 40F is mounted on the fourth conductor 324. Fig. As shown in Figure 5, the semiconductor element 40F is bonded to the fourth conductor 324 via a conductive bonding material 47, with the rear surface 42 of the element facing the fourth conductor 324. This electrically connects the drain electrode 45 of the semiconductor element 40F to the fourth conductor 324 via the conductive bonding material 47. As shown in Fig. As shown in Figure 3, the source electrode 43 of the semiconductor element 40F is electrically connected to the line 15 via a wire 71.

[0054] The gate electrode 44 of the semiconductor element 40A is connected to the sixth conductor 326 via a wire 72, and the sixth conductor 326 is connected to a line 22 via a wire 72. The gate electrode 44 of the semiconductor element 40A is electrically connected to line 22 via wires 72 and the sixth conductor 326. Line 22, which is electrically connected to the gate electrode 44 of the semiconductor element 40A, is a terminal (gate terminal) used to input a control signal for the semiconductor element 40A. The source electrode 43 of the semiconductor element 40A is connected to the fifth conductor 325 via a wire 73, and the fifth conductor 325 is connected to a line 21 via a wire 73. The source electrode 43 of the semiconductor element 40A is electrically connected to the line 21 via the wires 73 and the fifth conductor 325.The lead 22, which is electrically connected to the source electrode 43 of the semiconductor element 40A, is a terminal (source detection terminal) used to detect a source signal for the semiconductor element 40A. The wires 72 and 73 are made of materials such as gold (Au), silver (Ag), copper (Cu), or aluminum (Al). The material, diameter, and number of wires 72 and 73 are not limited.

[0055] The gate electrode 44 of the semiconductor element 40B is electrically connected to a line 22 via a wire 72. The line 22, which is electrically connected to the gate electrode 44 of the semiconductor element 40B, is the gate terminal of the semiconductor element 40B. The source electrode 43 of the semiconductor element 40B is electrically connected to the line 21 via a wire 73. The line 21, which is electrically connected to the source electrode 43 of the semiconductor element 40B, is the source sensing terminal of the semiconductor element 40B.

[0056] The gate electrode 44 of the semiconductor element 40C is electrically connected to a lead 22 via a wire 72. Lead 22, which is electrically connected to the gate electrode 44 of the semiconductor element 40C, is the gate terminal of the semiconductor element 40C. The source electrode 43 of the semiconductor element 40C is electrically connected to a lead 21 via a wire 73. Lead 21, which is electrically connected to the source electrode 43 of the semiconductor element 40C, is the source sensing terminal of the semiconductor element 40C.

[0057] The gate electrode 44 of the semiconductor element 40D is electrically connected to a line 22 via a wire 72. The line 22, which is electrically connected to the gate electrode 44 of the semiconductor element 40D, is the gate terminal of the semiconductor element 40D. The source electrode 43 of the semiconductor element 40D is electrically connected to a line 21 via a wire 73. The line 21, which is electrically connected to the source electrode 43 of the semiconductor element 40D, is the source sensing terminal of the semiconductor element 40D.

[0058] The gate electrode 44 of the semiconductor element 40E is electrically connected to a line 22 via a wire 72. The line 22, which is electrically connected to the gate electrode 44 of the semiconductor element 40E, is the gate terminal of the semiconductor element 40E. The source electrode 43 of the semiconductor element 40E is electrically connected to a line 21 via a wire 73. The line 21, which is electrically connected to the source electrode 43 of the semiconductor element 40E, is the source sensing terminal of the semiconductor element 40E.

[0059] The gate electrode 44 of the semiconductor element 40F is electrically connected to a conductor 22 via a wire 72. In the present embodiment, one end of the wire 72 is bonded to the gate electrode 44 of the semiconductor element 40F, a middle section is bonded to the eighth conductor 328, and the other end is bonded to the conductor 22. The conductor 22, which is electrically connected to the gate electrode 44 of the semiconductor element 40F, is the gate terminal of the semiconductor element 40F. The source electrode 43 of the semiconductor element 40F is electrically connected to a conductor 21 via a wire 73. In the present embodiment, one end of the wire 73 is bonded to the source electrode 43 of the semiconductor element 40F, a middle section is bonded to the seventh conductor 327, and the other end is bonded to the conductor 21.The line 21, which is electrically connected to the source electrode 43 of the semiconductor element 40F, is the source sensing terminal of the semiconductor element 40F.

[0060] Semiconductor device A1 is configured as a half-bridge circuit. In this case, lines 12, 13, and 14 are electrically connected via an external connection, such that semiconductor elements 40A, 40B, and 40C form an upper branch of semiconductor device A1, and semiconductor elements 40D, 40E, and 40F form a lower branch. In the upper branch, semiconductor elements 40A, 40B, and 40C are connected in parallel. In the lower branch, semiconductor elements 40D, 40E, and 40F are also connected in parallel. Semiconductor elements 40A, 40B, and 40C are each connected in series with semiconductor elements 40D, 40E, and 40F to form bridge layers. In semiconductor device A1, lines 11 and 15 are used to input a DC voltage to be converted.Line 11 is a positive electrode (P terminal), and line 15 is a negative electrode (N terminal). Lines 12, 13, and 14 are used to output an alternating voltage resulting from the power conversion by the 40A to 40F semiconductor elements.

[0061] As in Fig. 3 and Fig. As shown in Figure 9, the semiconductor elements 4 (semiconductor elements 40A to 40F) of the present embodiment are arranged side by side in the first direction x. Semiconductor element 40A is located at the end on the x2 side in the first direction x, semiconductor element 40F is located at the end on the x1 side in the first direction x, and semiconductor elements 40A to 40F are arranged in this order from the x2 side in the first direction x to the x1 side in the first direction x.

[0062] Semiconductor element 40C and semiconductor element 40D are arranged near the center in the first direction x. It should be noted that "center in the first direction x" refers to a center line CL in the first direction x for semiconductor elements 40A to 40F arranged side by side in the first direction x, and the same applies to variations, etc., described below. As can be seen in the present embodiment, when the number of semiconductor elements 4 (semiconductor elements 40A to 40F) is even, two semiconductor elements among the semiconductor elements 4, namely semiconductor elements 40C and 40D, are arranged near the center in the first direction x.

[0063] In the illustrated example, semiconductor elements 40A to 40F include those that are not aligned along the first direction x and are located in different positions in the second direction y. Semiconductor element 40B is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40A on the x2 side in the first direction x. Semiconductor element 40C is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40B on the x2 side in the first direction x. Additionally, semiconductor element 40C is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40D on the x1 side in the first direction x. Semiconductor element 40D is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40E on the x1 side in the first direction x.Semiconductor element 40E is offset, with respect to the adjacent semiconductor element 40F on the x1 side in the first x direction, in the second y direction towards the y1 side. Semiconductor element 40E is located in the second y direction in the same (or substantially the same) position as semiconductor element 40B. Semiconductor element 40F is located in the second y direction in the same (or substantially the same) position as semiconductor element 40A. Among the semiconductor elements 4 (semiconductor elements 40A to 40F) arranged as described above, semiconductor element 40D corresponds to an example of a “first semiconductor element” in the present disclosure, and semiconductor element 40C corresponds to an example of a “second semiconductor element” in the present disclosure.The first conductor 321, on which the semiconductor element 40D (the first semiconductor element) is arranged, corresponds to an example of a “first section” in the present disclosure, and the second conductor 322, on which the semiconductor element 40C (the second semiconductor element) is arranged, corresponds to an example of a “second section” in the present disclosure.

[0064] As in Fig. As shown in Figure 9, the semiconductor elements 4 (semiconductor elements 40A to 40F) exhibit the following relationships with respect to the distance between the centers of adjacent semiconductor elements 4 in the first direction x. A first distance D1, which is the distance between a center C1 of semiconductor element 40D and a center C2 of semiconductor element 40C, both located near the center in the first direction x, is greater than a second distance D21, which is the distance between the center C1 of semiconductor element 40D and a center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D, in the first direction x.The distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is also greater than a second distance D22, which is the distance between the center C2 of semiconductor element 40C and a center C4 of semiconductor element 40B adjacent to semiconductor element 40C in the first direction x. In the present embodiment, the distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0065] The distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than a sixth distance D61, which is the distance between the center C3 of semiconductor element 40E and a center C5 of semiconductor element 40F, adjacent to each other, in the first direction x of the plurality of semiconductor elements 4. The first distance D1 is also greater than a sixth distance D62, which is the distance between the center C4 of semiconductor element 40B and a center C6 of semiconductor element 40A, adjacent to each other, in the first direction x of the plurality of semiconductor elements 4.

[0066] The distance (the second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E is greater than the distance (the sixth distance D61) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which are adjacent in the first direction x. The distance (the second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B is greater than the distance (the sixth distance D62) between the center C4 of semiconductor element 40B and a center C6 of semiconductor element 40A, which are adjacent in the first direction x.

[0067] The thermistor 6 is a temperature sensing element mounted on the second front surface 3a of the insulating substrate 31. The thermistor 6 is a resistor that exhibits a large change in electrical resistance in response to temperature changes, and a change in resistance in response to the ambient temperature causes a change in the voltage across its terminals. The temperature around / in the thermistor 6 is detected based on the voltage across its terminals. The characteristics of the thermistor 6 are not particularly limited. The thermistor 6 can be an NTC thermistor (negative temperature coefficient), a PTC thermistor (positive temperature coefficient), or a thermistor with other characteristics.

[0068] Thermistor 6 is provided to detect the temperature of semiconductor device A1. As shown in Fig. 3 and Fig. As shown in Figure 5, the thermistor 6 is provided via the two pad sections 502 of the wiring section 5 (the wires 501). The thermistor 6 is bonded to the pad sections 502 via conductive bonding materials 63. Each conductive bonding material 63 can be any material capable of bonding the thermistor 6 to the pad sections 502 and electrically connecting the thermistor 6 and the pad sections 502. For example, the conductive bonding materials 63 can be silver paste, copper paste, or solder. One terminal of the thermistor 6 is electrically bonded to one pad section 502 via a conductive bonding material 63, and the other terminal of the thermistor 6 is electrically bonded to the other pad section 502 via a conductive bonding material 63.

[0069] Each of the two pad sections 502 (the wires 501) is electrically connected to a line 23 via a wire 74. The pad sections 502 (the wires 501) and the wires 74 form conductive paths that electrically connect the thermistor 6 and the lines 23. The two lines 23 are terminals used to detect the temperature of the semiconductor device A1 and to output the voltage at the terminals of the thermistor 6.

[0070] In the present embodiment, the semiconductor device A1 encloses an insulating component 62, as shown in Fig. Figure 5 shows that the insulating component 62 is provided between the second front surface 3a of the insulating substrate 31 and the thermistor 6 and is electrically insulating. The insulating component 62 is a backfill that is injected between the second front surface 3a and the thermistor 6 in the thickness direction z. The component material of the insulating component 62 is not particularly restricted and can be a synthetic resin, mainly consisting of black epoxy resin. As shown in Fig. As shown in Figure 3, the thermistor 6 is positioned near the corner of the insulating substrate 31 on the x1 side in the first direction x and on the y1 side in the second direction y.

[0071] The semiconductor device A1 can include a different temperature sensing element instead of the thermistor 6. An example of such a temperature sensing element could be a semiconductor temperature sensor. The semiconductor temperature sensor could be a silicon diode that exhibits a large change in forward voltage in response to temperature changes and detects the ambient temperature based on the voltage across its terminals when a predetermined current is applied. In contrast to the present embodiment, the semiconductor device A1 can be configured without the thermistor 6 or any other temperature sensing element.

[0072] The sealing resin 8 covers at least the semiconductor elements 40A to 40F, the wiring section 5, the thermistor 6, the wires 71 to 74, parts or sections of the conductors 1 and 2, and a part / section of the carrier 3. The component material of the sealing resin 8 is not particularly restricted and can be black epoxy resin. The sealing resin 8 is formed, for example, by molds.

[0073] The sealing resin 8 has a front resin surface 81, a rear resin surface 82, and a plurality of side resin surfaces 83 to 86. As in Fig. As shown in Figures 5 to 8, the front resin surface 81 and the rear resin surface 82 are flat surfaces that are perpendicular to the thickness direction z and face away from each other in the thickness direction z. The front resin surface 81 faces the z1 side in the thickness direction z, and the rear resin surface 82 faces the z2 side in the thickness direction z. As shown in Fig. As shown in Figure 4, the rear resin surface 82 has a frame shape in plan view, which surrounds the second rear surface 3b of the support 3 (the metal layer 33). The second rear surface 3b of the support 3 is, for example, exposed by the rear resin surface 82 of the sealing resin 8 and flush with the rear resin surface 82. It is noted that the second rear surface 3b of the support 3 can protrude from the rear resin surface 82 of the sealing resin 8 in the thickness direction z towards the z2 side.

[0074] The lateral resin surfaces 83 to 86 are connected to the front resin surface 81 and the rear resin surface 82 and are flanked by these surfaces in the thickness direction z. As in Fig. As shown in Figure 2, the lateral resin surface 83 and the lateral resin surface 84 are spaced apart from each other in the first direction x. The lateral resin surface 83 faces the x1 side in the first direction x, and the lateral resin surface 84 faces the x2 side in the first direction x. As shown in Fig. As shown in Figure 2, the lateral resin surfaces 85 and 86 are spaced apart in the second direction y. The lateral resin surface 85 faces the y1 side in the second direction y, and the lateral resin surface 86 faces the y2 side in the second direction y. A portion / section of each line 2 protrudes from the lateral resin surface 85. A portion / section of each line 1 protrudes from the lateral resin surface 86. As shown in Fig. As shown in Figures 2 to 4, the lateral resin surface 83 is formed with a recess 831 that extends in the first direction x. The lateral resin surface 84 is formed with a recess 841 that extends in the first direction x. The recesses 831 and 841 can be used for fastening during the assembly of the semiconductor device A1. Although detailed descriptions are omitted, each of the lateral resin surfaces 85 and 86 is formed with a plurality of recesses that extend in the second direction y.

[0075] Next, an application example of the semiconductor device A1 will be presented with reference to Fig. 10 described. Fig. Figure 10 is a schematic view showing a vehicle B1 that includes the semiconductor device A1. The vehicle B1 includes an AC-DC converter 871, a power receiving device 872, a storage battery 873, a drive system 874, and a DC-DC converter 875. The semiconductor device A1 forms part (PFC circuit) of the AC-DC converter 871. When the vehicle B1 receives alternating current from a charging device 870, which is, for example, an outdoor AC power source, the AC-DC converter 871 converts the alternating current into high-voltage direct current. The AC-DC converter 871 supplies the high-voltage direct current to the storage battery 873.The power receiving device 872 supplies power to the storage battery 873 via a contactless charging system and receives power from a contactless charging device (not illustrated) located in a parking lot or the like by an electromagnetic induction method. The energy stored in the storage battery 873 is supplied to the drive system 874, which includes an inverter, an AC motor, and a gearbox. The drive system 874 powers the vehicle B1. The DC-DC conversion device 875 can be a step-down DC-DC converter and supplies power to electrical components other than those used to power the vehicle B1. The AC-DC conversion device 871 is an example of a "power conversion device" of the present disclosure.

[0076] Next, the advantages of the semiconductor device A1 according to the present embodiment will be described.

[0077] The semiconductor device A1 includes the carrier conductor 32, four or more semiconductor elements 4 (the semiconductor elements 40A to 40F), and the sealing resin 8. The semiconductor elements 40A to 40F include the semiconductor element 40D (the first semiconductor element) and the semiconductor element 40C (the second semiconductor element), which are located near the center in the first direction x. The distance (the first distance D1) between the center C1 of the semiconductor element 40D and the center C2 of the semiconductor element 40C is greater than the distance (the second distance D21) between the center C1 of the semiconductor element 40D and the center C3 of the semiconductor element 40E, which is adjacent to the semiconductor element 40D, in the first direction x, and is also greater than the distance (the second distance D22) between the center C2 of the semiconductor element 40C and the center C4 of the semiconductor element 40B, which is adjacent to the semiconductor element 40C, in the first direction x.This configuration can suppress thermal disturbances between semiconductor element 40D and semiconductor element 40C, which are located near the center, beneath semiconductor elements 40A to 40F. This prevents the concentration of heat generated by semiconductor elements 40A to 40F and reduces thermal resistance. As a result, semiconductor device A1 can easily handle high currents and improves durability.

[0078] The center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C are located at different positions in the second direction y, perpendicular to the first direction x, in which semiconductor elements 40A to 40F are arranged side by side. According to this configuration, heat generated by semiconductor elements 40D and 40C, which are located near the center beneath semiconductor elements 40A to 40F, can be efficiently dissipated to the environment, further suppressing thermal disturbances. Additionally, the above configuration can increase the distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C while simultaneously preventing an increase in the dimensions of semiconductor device A1 in the first direction x.

[0079] As in Fig. As shown in Figure 9, the centers of the adjacent semiconductor elements 4 are located in the first direction x, and in the second direction y, the centers of the semiconductor elements 4 (semiconductor elements 40A to 40F) are at different positions. According to this configuration, the heat generated by semiconductor elements 40A to 40F can be efficiently dissipated to the environment.

[0080] The distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40D and semiconductor element 40C located near the center, among semiconductor elements 40A to 40F. The above configuration is more preferred for reducing the thermal resistance of semiconductor device A1.

[0081] The distance (the second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E is greater than the distance (the sixth distance D61) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F. The distance (the second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B is greater than the distance (the sixth distance D62) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A. According to this configuration, the semiconductor elements 4 (semiconductor elements 40A to 40F) are arranged such that the distance between adjacent semiconductor elements 4 in the first direction x decreases with increasing distance from the center in the first direction x.This makes it possible to suppress the thermal disturbances between the semiconductor elements 4 (the semiconductor elements 40A to 40F) and to reduce the dimensions of the semiconductor device A1 in the first direction x.

[0082] The carrier conductor 32 includes the first conductor 321 (the first section) and the second conductor 322 (the second section), which are spaced apart from each other. Of the semiconductor elements 40A to 40F, only semiconductor element 40D (the first semiconductor element) is located on the first conductor 321. Of the semiconductor elements 40A to 40F, semiconductor element 40C (the second semiconductor element) and semiconductor element 40B, which is adjacent to semiconductor element 40C, are located on the second conductor 322. The center C1 of semiconductor element 40D (the first semiconductor element) is offset in the second direction y from the center of any one of the semiconductor elements 40A, 40B, 40E, and 40F towards the y1 side. The center C2 of the semiconductor element 40C (of the second semiconductor element) is offset in the second direction y from the center C1 of the semiconductor element 40D towards the y1 side.Heat generated by semiconductor element 40C and semiconductor element 40B, which are arranged on the common second conductor 322, tends to be trapped on the second conductor 322, and disturbances from the heat generated by semiconductor element 40C and semiconductor element 40B tend to cause an increase in the temperature of the second conductor 322. As described above, semiconductor element 40C is arranged furthest towards the y2 side in the second direction y among all semiconductor elements 40A to 40F. According to this arrangement, the second conductor 322, on which semiconductor element 40C is mounted, can efficiently dissipate the heat generated by semiconductor element 40C to the surroundings of semiconductor element 40C. This makes it possible to suppress thermal disturbances between semiconductor elements 40D, 40C, and 40B, thereby reducing the thermal resistance of the semiconductor device A1.

[0083] The semiconductor device A1 encloses the support 3. The first rear surface 32b of the support 32, on which the semiconductor elements 4 (semiconductor elements 40A to 40F) are mounted, is bonded to the second front surface 3a of the support 3 (the insulating substrate 31). The second rear surface 3b of the support 3 (the metal layer 33) is exposed by the sealing resin 8. According to this configuration, heat transferred from the semiconductor elements 4 to the support 3 (the insulating substrate 31) can be efficiently dissipated to the outside from the second rear surface 3b, thereby improving the heat dissipation of the semiconductor device A1.

[0084] First example of a semiconductor device assembly that includes a semiconductor device of the first embodiment: Fig. 11 and Fig. Figure 12 shows a first example of a semiconductor device assembly configured to include the semiconductor device A1. Fig. Figure 11 is a partial cross-sectional view showing a semiconductor device assembly B2 of the present example. Fig. Figure 12 is a block diagram showing a configuration of the semiconductor device assembly B2. The semiconductor device assembly B2 includes the semiconductor device A1, a cooler 91, a mounting component 92, a fastener 93, a control unit 94, a cooling unit 95, and a heating unit 96.

[0085] The cooler 91 is a heat dissipation component for cooling the semiconductor device A1. The cooler 91 is made of a metal material with high thermal conductivity. The component material of the cooler 91 is not particularly restricted and can be aluminum (Al), copper (Cu), or any of its alloys. The cooler 91 has a mounting surface 911 and a flow channel 912. The mounting surface 911 is a flat surface facing the z1 side in the thickness direction z. The flow channel 912 is a hollow section formed inside the cooler 91. The flow channel 912 allows the flow of cooling water as a coolant. The semiconductor device A1 is mounted on the mounting surface 911 of the cooler 91.The mounting surface 911 faces the second rear surface 3b of the carrier 3 of the semiconductor device A1 and the rear resin surface 82 of the sealing resin 8 and is in surface contact with the second rear surface 3b and the rear resin surface 82.

[0086] The mounting component 92 is provided to hold the semiconductor device A1 on the cooler 91. The mounting component 92 is positioned above the semiconductor device A1 in the second direction y. The fastening element 92 is, for example, a leaf spring. The mounting component 92 is attached to the cooler 91 by inserting two fastening elements 93 into two mounting holes 913 located on the respective sides of the semiconductor device A1 in the second direction y. The two fastening elements 93 are, for example, bolts. In a pressure contact state, the semiconductor device A1 is pressed against the cooler 91 by the elastic spring force of the mounting component 92, and the mounting surface 911 of the cooler 91 and the second rear surface 3b of the support 3 of the semiconductor device A1 are in close contact with each other.Should the contact between the mounting surface 911 and the second rear surface 3b be insufficient, the cooler 91 can be provided with a thermal interface material (TIM) (not illustrated). The TIM is, for example, made of thermal paste or a thermally conductive film and is applied between the mounting surface 911 and the second rear surface 3b. The TIM bonds the mounting surface 911 and the second rear surface 3b, ensuring close contact between them.

[0087] Cooling unit 95 is provided for cooling cooler 91. Cooling unit 95 can be configured to include a cooling water supply source and a switchable on / off valve, which are not illustrated. For example, when cooler 91 is being cooled by cooling unit 95, the valve is open to allow the cooling water supplied by the cooling water supply source to flow through flow channel 912. When cooling of cooler 91 is stopped, the valve is closed to stop the flow of cooling water through flow channel 912. It is sufficient for cooling unit 95 to cool cooler 91, and the specific configuration of cooling unit 95 is not restricted in any way.

[0088] The heating unit 96 is provided for heating the cooler 91. The heating unit 96 can be configured to include a heater (not illustrated) attached to the cooler 91. The heater is activated when, for example, the cooler 91 is heated by the heating unit 96. It is sufficient for the heating unit 96 to heat the cooler 91; the specific configuration of the heating unit 96 is not restricted in any way.

[0089] The control unit 94 controls the cooling unit 95 and the heating unit 96 based on the temperature detected by the thermistor 6 of the semiconductor device A1. For example, if the temperature detected by the thermistor 6 exceeds a predetermined first temperature, the control unit 94 activates the cooling unit 95 to cool the cooler 91. If the temperature detected by the thermistor 6 falls below a predetermined second temperature (where the second temperature is lower than the first temperature), the control unit 94 activates the heating unit 96 to heat the cooler 91. The specific control method used by the control unit 94 to control the cooling unit 95 and the heating unit 96 is not particularly restricted.

[0090] Next, the advantages of the semiconductor device assembly B2 will be described according to the present example.

[0091] The semiconductor device assembly B2 of the present example includes the semiconductor device A1, the cooler 91, the cooling unit 95 for cooling the cooler 91, and the control unit 94. The second rear surface 3b of the support 3 in the semiconductor device A1 is exposed by the sealing resin 8, and the cooler 91 has a section (the mounting surface 911 or the TIM) that is in contact with the second rear surface 3b of the support 3. Such a configuration can suppress a temperature rise of the semiconductor device A1.

[0092] The semiconductor device assembly B2 includes the control unit 94. The control unit 94 controls the cooling unit 95 based on the temperature detected by the thermistor 6 of the semiconductor device A1. According to the configuration, it is possible to prevent an excessive temperature rise of the semiconductor device A1 while monitoring its temperature, thereby controlling the semiconductor device A1 appropriately.

[0093] The semiconductor device assembly B2 includes the heating unit 96, which heats the cooler 91, and the control unit 94 controls the heating unit 96 based on the temperature detected by the thermistor 6. For example, if the semiconductor device A1 is mounted in a vehicle assembly fixture and used in a cold environment or the like, the configuration makes it possible to prevent an excessive temperature drop of the semiconductor device A1 while monitoring its temperature and controlling it appropriately.

[0094] Second example of a semiconductor device assembly, which includes the semiconductor device of the first embodiment: Fig. Figure 13 shows a second example of a semiconductor device assembly configured to include the semiconductor device A1. Fig. Figure 13 is a partial cross-sectional view showing a semiconductor device assembly B21 of the present example. The semiconductor device assembly B21 has the same configuration as the semiconductor device assembly B2 of the first example in Fig. 12. As in Fig. 12 and Fig. As shown in Figure 13, the semiconductor device assembly B21 includes the semiconductor device A1, a cooler 91, a mounting element 93, a control unit 94, a cooling unit 95, and a heating unit 96. The cooler 91, the control unit 94, the cooling unit 95, and the heating unit 96 are the same as those of the semiconductor device assembly B2 described above, and therefore detailed descriptions of them are omitted.

[0095] In the semiconductor device assembly B21, the semiconductor device A1 is mounted on a mounting surface 911 of the cooler 91. The mounting surface 911 faces the second rear surface 3b of the carrier 3 of the semiconductor device A1 and the rear resin surface 82 of the sealing resin 8 and is in surface contact with at least the second rear surface 3b.

[0096] The cooler 91 in the semiconductor device assembly B21 has two mounting holes 913. The two mounting holes 913 are located at positions corresponding to the recesses 831 and 841 of the semiconductor device A1. The semiconductor device A1 is attached to the cooler 91 by inserting two fasteners 93 through the recesses 831 and 841 and into the two mounting holes 913. The two fasteners 93 are, for example, bolts. When the semiconductor device A1 is attached to the cooler 91, it is pressed against the cooler 91, and the mounting surface 911 of the cooler 91 and the second rear surface 3b of the carrier 3 of the semiconductor device A1 are in close contact.Should the contact between the mounting surface 911 and the second rear surface 3b be insufficient, the cooler 91 can be equipped with a TIM, which is not illustrated here. The TIM is the same as the one described above in connection with the semiconductor device assembly B2 of the first example. Therefore, a description of the TIM is omitted here.

[0097] The semiconductor device assembly B2 of the present example includes the semiconductor device A1, the cooler 91, the cooling unit 95 for cooling the cooler 91, and the control unit 94. The second rear surface 3b of the support 3 in the semiconductor device A1 is exposed by the sealing resin 8, and the cooler 91 has a section (the mounting surface 911 or the TIM) that is in contact with the second rear surface 3b of the support 3. Such a configuration can suppress a temperature rise of the semiconductor device A1.

[0098] Next, the advantages of the semiconductor device assembly B21 will be described according to the present example.

[0099] The semiconductor device assembly B2 of the present example includes the semiconductor device A1, the cooler 91, the cooling unit 95 for cooling the cooler 91, and the control unit 94. The second rear surface 3b of the support 3 in the semiconductor device A1 is exposed by the sealing resin 8, and the cooler 91 has a section (the mounting surface 911 or the TIM) that is in contact with the second rear surface 3b of the support 3. Such a configuration can suppress a temperature rise of the semiconductor device A1. The semiconductor device assembly B21 also has similar advantages to those of the semiconductor device assembly B2 described above.

[0100] Variations in the arrangement of semiconductor elements: Fig. Figures 14 to 17 show variations in the arrangement of the semiconductor elements. Each of Fig. Figures 14 to 17 are a schematic top view showing the arrangement of the semiconductor elements 4. The component elements (i.e., the leads 1, the leads 2, the support 3, the wiring section 5, the thermistor 6, the wires 71, 72, 73, 74, and the sealing resin 8), with the exception of the semiconductor elements 4 and the support conductor 32 carrying the semiconductor elements 4, are the same as those in the semiconductor device A1 of the above embodiment, and descriptions of these elements are omitted. Fig. In Figure 14 and the following figures, elements that are identical or similar to the elements in the semiconductor device A1 in the above embodiment are designated with the same reference numerals, and descriptions thereof are omitted. The configurations of the elements in each of the variations and each of the examples in Fig. Figures 14 and the following figures can be combined as appropriate, provided that no technical contradictions arise.

[0101] In the Fig. In the arrangement example of semiconductor elements 4 shown in Figure 14, the semiconductor elements 4 comprise five semiconductor elements 40G to 40K. The semiconductor elements 4 (the semiconductor elements 40G to 40K) are arranged side by side in the first direction x. The semiconductor element 40G is located at the end on the x2 side in the first direction x, the semiconductor element 40K is located at the end on the x1 side in the first direction x, and the semiconductor elements 40G to 40K are arranged in this order from the x2 side in the first direction x to the x1 side in the first direction x. As shown in Fig. As shown in Figure 14, the semiconductor element 40I is positioned near the center in the first direction x, below the semiconductor elements 4, when the number of semiconductor elements 4 (of semiconductor elements 40G to 40K) is odd.

[0102] In the illustrated example, semiconductor elements 40G to 40K include those that are not aligned along the first direction x and are located at different positions in the second direction y. Semiconductor element 40H is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40G on the x2 side in the first direction x. Semiconductor element 40I is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40H on the x2 side in the first direction x. Additionally, semiconductor element 40I is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40J on the x1 side in the first direction x. Semiconductor element 40J is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40K on the x1 side in the first direction x.Semiconductor element 40J is located in the second direction y at the same (or substantially the same) position as semiconductor element 40H. Semiconductor element 40K is located in the second direction y at the same (or substantially the same) position as semiconductor element 40G. Among the semiconductor elements 4 (semiconductor elements 40G to 40K) arranged as described above, semiconductor element 40I corresponds to an example of a “third semiconductor element” in the present disclosure, semiconductor element 40J corresponds to an example of a “fourth semiconductor element” in the present disclosure, and semiconductor element 40H corresponds to an example of a “fifth semiconductor element” in the present disclosure.

[0103] The in Fig. The 14 semiconductor elements 4 shown (the semiconductor elements 40G to 40K) exhibit the following relationships with respect to the distance between the centers of the adjacent semiconductor elements 4 in the first direction x. A third distance D3, which is the distance between a center C7 of the semiconductor element 40I, located near the center, in the first direction x, and a center C8 of the semiconductor element 40J, which is adjacent to the semiconductor element 40I on the x1 side in the first direction x, and a fourth distance D4, which is the distance between the center C7 of the semiconductor element 40I and a center C9 of the semiconductor element 40H, which is adjacent to the semiconductor element 40I on the x2 side in the first direction x, are each greater than a fifth distance D51, which is the distance between the center C8 of the semiconductor element 40J and a center C10 of the semiconductor element 40K, which is adjacent to the semiconductor element 40J in the first direction x.Each of the third distance D3 and the fourth distance D4 is greater than a fifth distance D52, which is the distance between the center C9 of semiconductor element 40H and a center C11 of semiconductor element 40G, which is adjacent to semiconductor element 40H in the first direction x. In the illustrated example, each of the distance (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0104] The in Fig. The 14 semiconductor elements shown, 40G to 40K, include the semiconductor element 40I (the third semiconductor element) near the center in the first direction x, the semiconductor element 40J (the fourth semiconductor element) adjacent to the semiconductor element 40I on the x1 side in the first direction x, and the semiconductor element 40H (the fifth semiconductor element) adjacent to the semiconductor element 40I on the x2 side in the first direction x.Each of the distances (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J, and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H, is greater than the distance (the fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K, which is adjacent to semiconductor element 40J in the first direction x, and is greater than the distance (the fifth distance D52) between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G. This configuration can suppress the thermal disturbances between semiconductor element 40I, which is located near the center, among semiconductor elements 40G to 40K, and each of the semiconductor elements 40J and 40H, which are adjacent to semiconductor element 40I.This makes it possible to prevent the concentration of heat generated by the 40G to 40K semiconductor elements and to reduce thermal resistance. As a result, the semiconductor device can easily handle high currents and improves its durability.

[0105] The center C7 of semiconductor element 40I, and each of the centers C8 of semiconductor element 40J and C9 of semiconductor element 40H, are located at different positions in the second direction y perpendicular to the first direction x, in which semiconductor elements 40G to 40K are arranged side by side. According to this configuration, heat generated by semiconductor element 40I, which is located near the center, beneath semiconductor elements 40G to 40K, and by semiconductor elements 40J and 40H, which are adjacent to semiconductor element 40I, can be efficiently dissipated to the environment, further suppressing thermal disturbances.Additionally, the above configuration can increase the distance (the third distance D3) between the center C7 of the semiconductor element 40I and the center C8 of the semiconductor element 40J and the distance (the fourth distance D4) between the center C7 of the semiconductor element 40I and the center C9 of the semiconductor element 40H, while at the same time preventing an increase in the dimension of the semiconductor device in the first direction x.

[0106] The centers of the adjacent semiconductor elements 4 in the first direction x, comprising semiconductor elements 40G to 40K, are located at different positions in the second direction y. According to this configuration, heat generated by semiconductor elements 40G to 40K can be efficiently dissipated to the environment.

[0107] Each of the distances (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J, and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H, is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40I, which is located near the center of semiconductor elements 40G to 40K, and each of the semiconductor elements 40J and 40H adjacent to semiconductor element 40I. The above configuration is more preferred for reducing the thermal resistance of the semiconductor device.

[0108] In the Fig. In the arrangement example of semiconductor elements 4 shown in Figure 15, the semiconductor elements 4 comprise eight semiconductor elements 40A to 40F, 40L, and 40M. The semiconductor elements 4 (semiconductor elements 40L, 40A to 40F, and 40M) are arranged side by side in the first direction x. Semiconductor element 40L is located at the end on the x2 side in the first direction x, semiconductor element 40M is located at the end on the x1 side in the first direction x, and semiconductor elements 40L, 40A to 40F, and 40M are arranged in this order from the x2 side in the first direction x to the x1 side in the first direction x. As shown in Figure 15, the semiconductor elements 4 are arranged in the following order: Fig. As shown in Figure 15, if the number of semiconductor elements is even (4 semiconductor elements 40L, 40A to 40F, and 40M), two semiconductor elements, namely semiconductor element 40D (the first semiconductor element) and semiconductor element 40C (the second semiconductor element), are positioned near the center in the first x-direction. In the illustrated example, semiconductor elements 40L, 40A to 40F, and 40M are aligned in the first x-direction and are located in the same (or substantially the same) position in the second y-direction.

[0109] The in Fig. The 15 semiconductor elements 4 shown (semiconductor elements 40L, 40A to 40F and 40M) exhibit the following relationships with respect to the distance between the centers of adjacent semiconductor elements 4 in the first direction x. The first distance D1 between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C, which are located near the center, in the first direction x is greater than the second distance D21 between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D, in the first direction x. The distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is also greater than the second distance D22 between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B, which is adjacent to semiconductor element 40C in the first direction x.In the illustrated example, the distance (the first distance D1) between the center C1 of the semiconductor element 40D and the center C2 of the semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0110] The distance (the second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E is greater than the distance (the sixth distance D61) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which are adjacent to each other in the first direction x. The distance (the second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B is greater than the distance (the sixth distance D62) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A, which are adjacent to each other in the first direction x.

[0111] As in Fig. As shown in Figure 15, the distance (the sixth distance D61) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which are adjacent to each other, is greater in the first direction x than the distance (a sixth distance D63) between the center C5 of semiconductor element 40F and a center C12 of semiconductor element 40M, which are adjacent to each other, in the first direction x. Semiconductor element 40M is located farther from the center in the first direction x than semiconductor element 40F. The distance (the sixth distance D62) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A, which are adjacent to each other, in the first direction x, is greater than the distance (a sixth distance D64) between the center C6 of semiconductor element 40A and a center C13 of semiconductor element 40L, which are adjacent to each other, in the first direction x.The semiconductor element 40L is located further from the center in the first direction x than the semiconductor element 40A.

[0112] The in Fig. The 15 semiconductor elements shown, 40L, 40A to 40F and 40M, include semiconductor element 40D (the first semiconductor element) and semiconductor element 40C (the second semiconductor element), which are located near the center in the first direction x. The distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is greater than the distance (the second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D, in the first direction x, and is also greater than the distance (the second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B, which is adjacent to semiconductor element 40C, in the first direction x.This configuration can suppress thermal disturbances between semiconductor element 40D and semiconductor element 40C, which are located near the center beneath semiconductor elements 40L, 40A to 40F, and 40M. This prevents the concentration of heat generated by semiconductor elements 40L, 40A to 40F, and 40M, thus reducing thermal resistance. As a result, the semiconductor device can easily handle high currents and improves durability.

[0113] The distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40D and semiconductor element 40C located near the center, among semiconductor elements 40L, 40A to 40F, and 40M. The above configuration is more preferred for reducing the thermal resistance of the semiconductor device.

[0114] The distance (the second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E is greater than the distance (the sixth distance D61) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F. The distance (the sixth distance D61) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F is greater than the distance (the sixth distance D63) between the center C5 of semiconductor element 40F and the center C12 of semiconductor element 40M. The distance (the second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B is greater than the distance (the sixth distance D62) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A.The distance (the sixth distance D62) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A is greater than the distance (the sixth distance D64) between the center C6 of semiconductor element 40A and the center C13 of semiconductor element 40L. According to this configuration, the semiconductor elements 4 (semiconductor elements 40L, 40A to 40F, and 40M) are arranged such that the distance between adjacent semiconductor elements 4 in the first direction x decreases with increasing distance from the center in the first direction x. This makes it possible to suppress thermal disturbances between the semiconductor elements 4 (semiconductor elements 40L, 40A to 40F, and 40M) and to reduce the dimensions of the semiconductor device in the first direction x.

[0115] In the Fig. In the arrangement example of semiconductor elements 4 shown in Figure 16, the semiconductor elements 4 comprise nine semiconductor elements 40G to 40K, 40N, 40P, 40Q, and 40R. The semiconductor elements 4 (semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R) are arranged side by side in the first direction x. Semiconductor element 40Q is located at the end on the x2 side in the first direction x, semiconductor element 40R is located at the end on the x1 side in the first direction x, and semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R are arranged in this order from the x2 side in the first direction x to the x1 side in the first direction x. As shown in Figure 16, the semiconductor elements 4 are arranged in the first direction x. Fig. As shown in Figure 16, the semiconductor element 40I is positioned near the center in the first direction x when the number of semiconductor elements (4, 40Q, 40N, 40G to 40K, 40P, and 40R) is odd. In the illustrated example, the semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R are aligned in the first direction x and are in the same (or substantially the same) position in the second direction y.

[0116] The in Fig. The 16 semiconductor elements 4 shown (the semiconductor elements 40Q, 40N, 40G to 40K, 40P and 40R) exhibit the following relationships with respect to the distance between the centers of the adjacent semiconductor elements 4 in the first direction x. The third distance D3 between the center C7 of the semiconductor element 40I, which is located near the center, in the first direction x, and the center C8 of the semiconductor element 40J, which is adjacent to the semiconductor element 40I on the x1 side, in the first direction x, and the fourth distance D4 between the center C7 of the semiconductor element 40I and the center C9 of the semiconductor element 40H, which is adjacent to the semiconductor element 40I on the x2 side, in the first direction x, are each larger than the fifth distance D51 between the center C8 of the semiconductor element 40J and the center C10 of the semiconductor element 40K, which is adjacent to the semiconductor element 40J, in the first direction x.Each of the third distance D3 and the fourth distance D4 is also greater than the fifth distance D52 between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G, which is adjacent to semiconductor element 40H, in the first direction x. In the illustrated example, each of the distances (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0117] The distance (the fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K is greater than the distance (a seventh distance D71) between the center C10 of semiconductor element 40K and a center C14 of semiconductor element 40P, which are adjacent in the first direction x. The distance (the fifth distance D52) between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G is greater than the distance (a seventh distance D72) between the center C11 of semiconductor element 40G and a center C15 of semiconductor element 40N, which are adjacent in the first direction x.

[0118] As in Fig. As shown in Figure 16, the distance (the seventh distance D71) between the center C10 of semiconductor element 40K and the center C14 of semiconductor element 40P, which are adjacent in the first direction x, is greater than the distance (a seventh distance D73) between the center C14 of semiconductor element 40P and the center C16 of semiconductor element 40R, which are adjacent in the first direction x. Semiconductor element 40R is located further from the center in the first direction x than semiconductor element 40P. The distance (the seventh distance D72) between the center C11 of the semiconductor element 40G and the center C15 of the semiconductor element 40N, which are adjacent in the first direction x, is greater than the distance (a seventh distance D74) between the center C15 of the semiconductor element 40N and a center C17 of the semiconductor element 40Q, which are adjacent in the first direction x.The semiconductor element 40Q is located further from the center in the first direction x than the semiconductor element 40N.

[0119] The semiconductor elements 40Q, 40N, 40G to 40K, 40P and 40R include the semiconductor element 40I (the third semiconductor element) near the center in the first direction x, the semiconductor element 40J (the fourth semiconductor element) adjacent to the semiconductor element 40I on the x1 side in the first direction x, and the semiconductor element 40H (the fifth semiconductor element) adjacent to the semiconductor element 40I on the x2 side in the first direction x.Each of the distances (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H is greater than the distance (the fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K, which is adjacent to semiconductor element 40J in the first direction x, and is also greater than the distance (the fifth distance D52) between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G. This configuration can suppress the thermal disturbances between the semiconductor element 40I near the center of the semiconductor elements 40Q, 40N, 40G to 40K, 40P and 40R and each of the semiconductor elements 40J and 40H adjacent to the semiconductor element 40I.This makes it possible to prevent the concentration of heat generated by the 40G to 40K semiconductor elements and to reduce thermal resistance. As a result, the semiconductor device can easily handle high currents and improves its durability.

[0120] Each of the distances (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J, and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H, is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40I, located near the center, among semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R, and each of the semiconductor elements 40J and 40H adjacent to semiconductor element 40I. The above configuration is more preferred for reducing the thermal resistance of the semiconductor device.

[0121] The distance (the fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K is greater than the distance (the seventh distance D71) between the center C10 of semiconductor element 40K and the center C14 of semiconductor element 40P. The distance (the seventh distance D71) between the center C10 of semiconductor element 40K and the center C14 of semiconductor element 40P is greater than the distance (the seventh distance D73) between the center C14 of semiconductor element 40P and the center C16 of semiconductor element 40R. The distance (the fifth distance D52) between the center C9 of the semiconductor element 40H and the center C11 of the semiconductor element 40G is greater than the distance (the seventh distance D72) between the center C11 of the semiconductor element 40G and the center C15 of the semiconductor element 40N.The distance (the seventh distance D72) between the center C11 of semiconductor element 40G and the center C15 of semiconductor element 40N is greater than the distance (the seventh distance D74) between the center C15 of semiconductor element 40N and the center C17 of semiconductor element 40Q. According to this configuration, the semiconductor elements 4 (semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R) are arranged such that the distance between adjacent semiconductor elements 4 in the first direction x decreases with increasing distance from the center in the first direction x. This makes it possible to suppress thermal disturbances between the semiconductor elements 4 (semiconductor elements 40Q, 40N, 40G to 40K, 40P, and 40R) and to reduce the dimensions of the semiconductor device in the first direction x.

[0122] In the Fig. In the arrangement example of semiconductor elements 4 shown in Figure 17, the semiconductor elements 4 comprise seven semiconductor elements 40G to 40K, 40N, and 40P. The semiconductor elements 4 (the semiconductor elements 40N, 40G to 40K, and 40P) are arranged side by side in the first direction x. Semiconductor element 40N is located at the end on the x2 side in the first direction x, semiconductor element 40P is located at the end on the x1 side in the first direction x, and semiconductor elements 40N, 40G to 40K, and 40P are arranged in this order from the x2 side in the first direction x to the x1 side in the first direction x. As shown in Figure 17, the semiconductor elements 4 are arranged in the first direction x. Fig. As shown in Figure 17, the semiconductor element 40I is positioned near the center in the first direction x when the number of semiconductor elements 4 (the semiconductor elements 40N, 40G to 40K and 40P) is odd.

[0123] In the illustrated example, semiconductor elements 40N, 40G through 40K, and 40P are those that are not aligned along the first direction x and are located in different positions in the second direction y. Semiconductor element 40G is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40N on the x2 side in the first direction x. Semiconductor element 40H is offset towards the y2 side in the second direction y with respect to the adjacent semiconductor element 40G on the x2 side in the first direction x. Semiconductor element 40I is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40H on the x2 side in the first direction x. The semiconductor element 40J is offset, with respect to the adjacent semiconductor element 40I on the x2 side in the first direction x, and in the second direction y towards the y2 side.Semiconductor element 40K is offset relative to the adjacent semiconductor element 40J on the x2 side in the first direction x and towards the y1 side in the second direction y. Semiconductor element 40P is offset relative to the adjacent semiconductor element 40K on the x2 side in the first direction x and towards the y2 side in the second direction y. As shown in . Fig. As shown in Figure 17, the semiconductor elements 40N, 40G to 40K and 40P are arranged in zigzag lines in the second direction y.

[0124] The in Fig. The 17 semiconductor elements 4 shown (semiconductor elements 40N, 40G to 40K and 40P) exhibit the following relationships with respect to the distance between the centers of adjacent semiconductor elements 4 in the first direction x. The third distance D3 between the center C7 of semiconductor element 40I, which is located near the center, in the first direction x and the center C8 of semiconductor element 40J, which is adjacent to semiconductor element 40I on the x1 side, in the first direction x, and the fourth distance D4 between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H, which is adjacent to semiconductor element 40I on the x2 side, in the first direction x, are each greater than the fifth distance D51 between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K, which is adjacent to semiconductor element 40J, in the first direction x.Each of the third distance D3 and the fourth distance D4 is also greater than the fifth distance D52 between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G, which is adjacent to semiconductor element 40H, in the first direction x. In the illustrated example, each of the distances (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0125] The distance (the fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K is greater than the distance (the seventh distance D71) between the center C10 of semiconductor element 40K and the center C14 of semiconductor element 40P, which are adjacent in the first direction x. The distance (the fifth distance D52) between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G is greater than the distance (the seventh distance D72) between the center C11 of semiconductor element 40G and the center C15 of semiconductor element 40N, which are adjacent in the first direction x.

[0126] The in Fig. The 17 semiconductor elements shown, 40N, 40G to 40K and 40P, include the semiconductor element 40I (the third semiconductor element) near the center in the first direction x, the semiconductor element 40J (the fourth semiconductor element) adjacent to the semiconductor element 40I on the x1 side in the first direction x, and the semiconductor element 40H (the fifth semiconductor element) adjacent to the semiconductor element 40I on the x2 side in the first direction x.Each of the distances (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H is greater than the distance (the fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K, which is adjacent to semiconductor element 40J in the first direction x, and is also greater than the distance (the fifth distance D52) between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G. This configuration can suppress the thermal disturbances between the semiconductor element 40I, which is located near the center, beneath the semiconductor elements 40N, 40G to 40K and 40P, and each of the semiconductor elements 40J and 40H that are adjacent to the semiconductor element 40I.This makes it possible to prevent the concentration of heat generated by the 40G to 40K semiconductor elements and to reduce thermal resistance. As a result, the semiconductor device can easily handle high currents and improves its durability.

[0127] Each of the distances (the third distance D3) between the center C7 of semiconductor element 40I and the center C8 of semiconductor element 40J, and the distance (the fourth distance D4) between the center C7 of semiconductor element 40I and the center C9 of semiconductor element 40H, is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40I, located near the center, among semiconductor elements 40N, 40G to 40K, and 40P, and each of the semiconductor elements 40J and 40H adjacent to semiconductor element 40I. The above configuration is more preferred for reducing the thermal resistance of the semiconductor device.

[0128] The center C7 of semiconductor element 40I, each of the centers C8 of semiconductor element 40J, and the center C9 of semiconductor element 40H are located at different positions in the second direction y perpendicular to the first direction x, in which semiconductor elements 40N, 40G to 40K, and 40P are arranged side by side. According to this configuration, heat generated by semiconductor element 40I, which is located near the center, beneath semiconductor elements 40N, 40G to 40K, and 40P, and by semiconductor elements 40J and 40H, which are adjacent to semiconductor element 40I, can be efficiently dissipated to the environment, further suppressing thermal disturbances.Additionally, the above configuration can increase the distance (the third distance D3) between the center C7 of the semiconductor element 40I and the center C8 of the semiconductor element 40J and the distance (the fourth distance D4) between the center C7 of the semiconductor element 40I and the center C9 of the semiconductor element 40H, while at the same time preventing an increase in the dimension of the semiconductor device in the first direction x.

[0129] The centers of the adjacent semiconductor elements 4 in the first direction x, comprising semiconductor elements 40N, 40G to 40K, and 40P, are located at different positions in the second direction y. According to this configuration, heat generated by semiconductor elements 40N, 40G to 40K, and 40P can be efficiently dissipated to the environment. As shown in Fig. As shown in Figure 17, the semiconductor elements 40N, 40G to 40K, and 40P are arranged in zigzag lines in the second direction y. The above configuration can prevent an increase in the dimensions of the semiconductor device in the first direction x and the second direction y, while maintaining a desired distance between the centers of the adjacent semiconductor elements 4 in the first direction x, comprising the semiconductor elements 40N, 40G to 40K, and 40P.

[0130] The distance (the fifth distance D51) between the center C8 of semiconductor element 40J and the center C10 of semiconductor element 40K is greater than the distance (the seventh distance D71) between the center C10 of semiconductor element 40K and the center C14 of semiconductor element 40P. The distance (the fifth distance D52) between the center C9 of semiconductor element 40H and the center C11 of semiconductor element 40G is greater than the distance (the seventh distance D72) between the center C11 of semiconductor element 40G and the center C15 of semiconductor element 40N. According to this configuration, the semiconductor elements 4 (semiconductor elements 40N, 40G to 40K, and 40P) are arranged such that the distance between adjacent semiconductor elements 4 in the first direction x decreases with increasing distance from the center in the first direction x.This makes it possible to suppress the thermal disturbances between the semiconductor elements 4 (the semiconductor elements 40N, 40G to 40K and 40P) and to reduce the dimensions of the semiconductor device in the first direction x. Second embodiment:

[0131] Fig. Figures 18 to 21 show a semiconductor device according to a second embodiment of the present disclosure. A semiconductor device A2 of the present embodiment includes a plurality of conductors 1 (conductors 11 to 15), a plurality of conductors 2 (a plurality of conductors 21, a plurality of conductors 22 and two conductors 23), an insulating substrate 30, a plurality of semiconductor elements 4 (semiconductor elements 40A to 40F), a wiring section 5, a plurality of bonding sections 511 to 515, a bonding section 521, a thermistor 6, a plurality of wires 71, a plurality of wires 72, a plurality of wires 73 and a sealing resin 8. Fig. Figure 18 is a top view showing the semiconductor device A2 as seen through the sealing resin 8. Fig. 19 is a cross-sectional view along the in Fig. 18 shown line XIX-XIX. Fig. 20 is a cross-sectional view along the in Fig. Line XX-XX shown in 18. Fig. 21 is a cross-sectional view along the in Fig. Line XXI-XXI shown in Figure 18. The outline of the sealing resin 8 is in Fig. 18 is indicated by an imaginary line (two-dotted line). In Fig. In diagrams 19 to 21, wires 71 are omitted. Fig. 19 and Fig. In diagram 21, wires 72 and 73 are omitted.

[0132] The semiconductor device A2 of the present embodiment differs from the semiconductor device of the above embodiment mainly in that the semiconductor device A2 includes the insulating substrate 30 instead of the support 3 in the above embodiment, and in the configurations of the lines 1 (the lines 11 to 15) and the lines 2 (the lines 21, the lines 22 and the two lines 23) and the configuration of the wiring section 5.

[0133] The insulating substrate 30 carries the semiconductor elements 40A to 40F. The material of the insulating substrate 30 is not particularly restricted. For example, it is preferred that the material of the insulating substrate 30 has a higher thermal conductivity than that of the sealing resin 8. Examples of materials for the insulating substrate 30 include ceramics such as aluminum oxide (Al₂O₃), silicon nitride (SiN), aluminum nitride (AlN), and zirconia-containing aluminum oxide. The thickness of the insulating substrate 30 is not particularly restricted and can be approximately 0.1 mm to 1.0 mm.

[0134] The shape of the insulating substrate 30 is not particularly restricted. As in Fig. As shown in Figures 18 to 21, the insulating substrate 30 of the present embodiment has a second front surface 3a and a second rear surface 3b. The second front surface 3a faces the z1 side in the thickness direction z. The second rear surface 3b faces the side opposite the second front surface 3a (the z2 side in the thickness direction z). In the present embodiment, the second rear surface 3b is exposed by the sealing resin 8. A heat dissipation component (e.g., a heat sink), not shown in the figures, can be attached to the second rear surface 3b. In the illustrated example, the insulating substrate 30 is rectangular in plan view. Viewed in the thickness direction z, the insulating substrate 30 has a rectangular shape that is extended in the first direction x.The insulating substrate 30 is an example of a “support” in the present disclosure, and the support is formed from the insulating substrate 30.

[0135] The wiring section 5 is formed on the insulating substrate 30. In the present embodiment, the wiring section 5 is formed on the second front surface 3a of the insulating substrate 30. The wiring section 5 is made of a conductive material. The conductive material of the wiring section 5 is not particularly limited. The conductive material of the wiring section 5 can contain silver (Ag), copper (Cu), or gold (Au). The following description is given by way of an example in which the wiring section 5 contains silver. It should be noted that the wiring section 5 can contain copper instead of silver, or gold instead of silver or copper. Alternatively, the wiring section 5 can contain Ag-Pt or Ag-Pd. The method for forming the wiring section 5 is not particularly limited. For example, the wiring section 5 can be formed by sintering a paste containing these metals.The thickness of the wiring section 5 is not particularly limited and can be approximately 5 µm to 30 µm.

[0136] The shape, etc., of the wiring section 5 is not particularly restricted. In the present embodiment, the wiring section 5 includes two wires 501, as shown in Fig. 18 and Fig. Figure 19 shows the two wires 501 being located near the corner of the insulating substrate 30 on the x1 side in the first direction x and on the y1 side in the second direction y. The two wires 501 are spaced apart and aligned in the second direction y. Each of the wires 501 has a pad section 502. The pad section 502 is located at the end of the wire 501 on the x2 side in the first direction x. The two pad sections 502 are bonded to respective terminals of the thermistor 6.

[0137] As in Fig. As shown in Figures 19 to 21, the bonding sections 511 to 515 and the bonding section 521 are formed on the insulating substrate 30. In the present embodiment, the bonding sections 511 to 515 and the bonding section 521 are formed on the second front surface 3a of the insulating substrate 30. The material of the bonding sections 511 to 515 and the bonding section 521 is not particularly limited. For example, the bonding sections 511 to 515 and the bonding section 521 can be made of a material capable of bonding the insulating substrate 30 and the conductors 1. The bonding sections 511 to 515 and the bonding section 521 can, for example, be made of a conductive material. The conductive material of bonding sections 511 to 515 and bonding section 521 is not particularly restricted. The conductive material of bonding sections 511 to 515 and bonding section 521 may contain silver (Ag), copper (Cu), or gold (Au).The following description is provided with an example in which bonding sections 511 to 515 and bonding section 521 contain silver. In this example, bonding sections 511 to 515 and bonding section 521 contain the same conductive material as that of wiring section 5. It is noted that bonding sections 511 to 515 and bonding section 521 may contain copper instead of silver, or gold instead of silver or copper. Alternatively, bonding sections 511 to 515 and bonding section 521 may contain Ag-Pt or Ag-Pd. The method for forming bonding sections 511 to 515 and bonding section 521 is not particularly restricted. For example, as with wiring section 5, bonding sections 511 to 515 and bonding section 521 may be formed by sintering a paste containing the aforementioned metals.The thickness of each of the bonding sections 511 to 515 and the bonding section 521 is not particularly limited and can be approximately 5 µm to 30 µm.

[0138] For example, each of the conductors 1 contains a metal and exhibits better heat dissipation properties than the insulating substrate 30. The metal in each conductor 1 is not particularly restricted and can be copper, aluminum, iron (Fe), oxygen-free copper, or any alloy thereof (e.g., Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). The conductors 1 can be nickel (Ni) plated. The conductors 1 can be formed by pressing a die onto a metal plate or by structuring a metal plate by etching. However, the method for forming the conductors 1 is not limited to these methods. The thickness of each conductor 1 is not particularly restricted and can be approximately 0.4 mm to 0.8 mm. The conductors 1 are spaced apart from one another.

[0139] In the present embodiment, the lines 1 include a line 11, a line 12, a line 13, a line 14, and a line 15. Lines 11, 12, 13, 14, and 15, for example, form the conductive paths to the semiconductor elements 4.

[0140] The conductor 11 is mounted on the insulating substrate 30. In the present embodiment, the conductor 11 is mounted on the second front surface 3a. The conductor 11 is bonded to the bonding section 511 via a bonding material 18. The bonding material 18 can be any material capable of bonding the conductor 11 to the bonding section 511. To efficiently transfer heat from the conductor 11 to the insulating substrate 30, the bonding material 18 preferably has a relatively high thermal conductivity, such as silver paste, copper paste, or solder. Alternatively, the bonding material 18 can be an insulating material, such as an epoxy resin or a silicone resin. If the bonding section 511 is not formed on the insulating substrate 30, the conductor 11 can be bonded to the insulating substrate 30.

[0141] The configuration of the conduit 11 is not particularly restricted. In the present embodiment, the conduit 11 is divided for description into a mounting section 110, a projecting section 112, and an inclined section 113, as shown in Fig. 18, Fig. 20 and Fig. 21 shown.

[0142] The mounting section 110 is offset on the second front surface 3a of the insulating substrate 30 in the first direction x towards the x2 side. The semiconductor elements 40A, 40B, and 40C are arranged on the upper surface (a first front surface facing the z1 side in the thickness direction z) of the mounting section 110. The mounting section 110 forms a part or section of the “conductor” of the present disclosure. In contrast to the illustrated example, the mounting section 110 can have a plurality of depressions extending from the upper surface of the mounting section 110 in the thickness direction z towards the z2 side. The lower surface (a first back surface facing the z2 side in the thickness direction z) of the mounting section 110 is bonded to the bonding section 511 via the bonding material 18.The inclined section 113 is connected to the mounting section 110 and inclined relative to the mounting section 110. The protruding section 112 is connected to the inclined section 113, and a large portion of the protruding section 112 protrudes from the sealing resin 8. In the illustrated example, two protruding sections 112 are provided with a gap between them in the first direction x. The protruding sections 112 project in the second direction y toward the side opposite the mounting section 110. The protruding sections 112 can be used to electrically connect the semiconductor device A2 to an external circuit. In the illustrated example, the protruding sections 112 are bent toward the side facing the second front surface 3a of the insulating substrate 30 in the thickness direction z.

[0143] The conductor 12 is mounted on the insulating substrate 30. In the present embodiment, the conductor 12 is mounted on the second front surface 3a. The conductor 12 is bonded to the bonding section 512 via a bonding material 18. The configuration of the conductor 12 is not particularly restricted. In the present embodiment, the conductor 12 is subdivided for description into a mounting section 120, a projecting section 122, and an inclined section 123, as shown in Fig. 18 and Fig. 21 shown.

[0144] The mounting section 120 is offset in the first direction x relative to the mounting section 110 towards the x1 side and is adjacent to the mounting section 110. The semiconductor element 40D is mounted on the upper surface (a first front surface facing the z1 side in the thickness direction z) of the mounting section 120. The mounting section 120 forms a part / section of the “conductor” of the present disclosure. In contrast to the illustrated example, the mounting section 120 can have a plurality of depressions extending from the upper surface of the mounting section 120 towards the z2 side in the thickness direction z. The lower surface (a first back surface facing the z2 side in the thickness direction z) of the mounting section 120 is bonded to the bonding section 512 via a bonding material 18.The inclined section 123 is connected to the mounting section 120 and inclined relative to the mounting section 120. The protruding section 122 is connected to the inclined section 123, and a large portion of the protruding section 122 extends beyond the sealing resin 8. The protruding section 122 extends in the second direction y toward the side opposite the mounting section 120. The protruding section 122 can be used to electrically connect the semiconductor device A2 to an external circuit. In the illustrated example, the protruding section 122 is bent toward the side facing the second front surface 3a of the insulating substrate 30 in the thickness direction z.

[0145] The conductor 13 is mounted on the insulating substrate 30. In the present embodiment, the conductor 13 is mounted on the second front surface 3a. The conductor 13 is bonded to the bonding section 513 via a bonding material 18. The configuration of the conductor 13 is not particularly restricted. In the present embodiment, the conductor 13 is subdivided for description into a mounting section 130, a projecting section 132, and an inclined section 133, as shown in Fig. 18 and Fig. 21 shown.

[0146] The mounting section 130 is offset in the first direction x relative to the mounting section 120 towards the x1 side and is adjacent to the mounting section 120. The semiconductor element 40E is mounted on the upper surface (a first front surface facing the z1 side in the thickness direction z) of the mounting section 130. The mounting section 130 forms a part or section of the “conductor” of the present disclosure. In contrast to the illustrated example, the mounting section 130 can have a plurality of depressions extending from the upper surface of the mounting section 130 towards the z2 side in the thickness direction z. The lower surface (a first back surface facing the z2 side in the thickness direction z) of the mounting section 130 is bonded to the bonding section 513 via the bonding material 18.The inclined section 133 is connected to and inclined relative to the mounting section 130. The protruding section 132 is connected to the inclined section 133, and a large portion of the protruding section 132 extends beyond the sealing resin 8. The protruding section 132 extends in the second direction y toward the side opposite the mounting section 130. The protruding section 132 can be used to electrically connect the semiconductor device A2 to an external circuit. In the illustrated example, the protruding section 132 is bent toward the side facing the second front surface 3a of the insulating substrate 30 in the thickness direction z.

[0147] The conductor 14 is mounted on the insulating substrate 30. In the present embodiment, the conductor 14 is mounted on the second front surface 3a. The conductor 14 is bonded to the bonding section 512 via a bonding material 18. The configuration of the conductor 14 is not particularly restricted. In the present embodiment, the conductor 14 is subdivided for description into a mounting section 140, a projecting section 142, and an inclined section 143, as shown in Fig. 18, Fig. 19 and Fig. 21 shown.

[0148] The mounting section 140 is offset in the first direction x relative to the mounting section 130 towards the x1 side and is adjacent to the mounting section 130. The semiconductor element 40F is mounted on the upper surface (a first front surface facing the z1 side in the thickness direction z) of the mounting section 140. The mounting section 140 forms a part or section of the “conductor” of the present disclosure. In contrast to the illustrated example, the mounting section 140 can have a plurality of depressions extending from the upper surface of the mounting section 140 towards the z2 side in the thickness direction z. The lower surface (a first back surface facing the z2 side in the thickness direction z) of the mounting section 140 is bonded to the bonding section 514 via the bonding material 18.The inclined section 143 is connected to the mounting section 140 and inclined relative to the mounting section 140. The protruding section 142 is connected to the inclined section 143, and a large portion of the protruding section 142 extends beyond the sealing resin 8. The protruding section 142 extends in the second direction y toward the side opposite the mounting section 140. The protruding section 142 can be used to electrically connect the semiconductor device A2 to an external circuit. In the illustrated example, the protruding section 142 is bent toward the side facing the second front surface 3a of the insulating substrate 30 in the thickness direction z.

[0149] The conductor 15 is mounted on the insulating substrate 30. In the present embodiment, the conductor 15 is mounted on the second front surface 3a. As shown in Fig. 18 and Fig. As shown in Figure 19, the conductor 15 is bonded to the bonding section 515 via a bonding material 18. The configuration of the conductor 15 is not particularly restricted. In the present embodiment, the conductor 15 is divided for description into a pad section 151, a protruding section 152, and an inclined section 153, as shown in Figure 19. Fig. 18 and Fig. 19 shown.

[0150] The pad section 151 is covered with the sealing resin 8. The pad section 151 is parallel to the insulating substrate 30. A wire 71 is bonded to the upper surface (the surface facing the z1 side in the thickness direction z) of the pad section 151. The lower surface (the surface facing the z2 side in the thickness direction z) of the pad section 151 is bonded to the bonding section 515 via the bonding material 18. The inclined section 153 is connected to the pad section 151 and inclined relative to the pad section 151. The protruding section 152 is connected to the inclined section 153, and a large part of the protruding section 152 protrudes from the sealing resin 8. The protruding section 152 can be used to electrically connect the semiconductor device A2 to an external circuit.In the illustrated example, the protruding section 152 is bent towards the side facing the second front surface 3a of the insulating substrate 30 in the thickness direction z.

[0151] For example, each of the conductors 2 contains a metal and has a higher thermal conductivity than the insulating substrate 31. The metal in each conductor 2 is not particularly restricted and can be copper, aluminum, iron (Fe), oxygen-free copper, or any alloy thereof (e.g., Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). The conductors 2 can be nickel (Ni) plated. The conductors 2 can be formed by pressing a die onto a metal plate or by structuring a metal plate by etching. The method for forming the conductors 2 is not particularly restricted. The thickness of each conductor 2 is not particularly restricted and can be approximately 0.4 mm to 0.8 mm. The conductors 2 are spaced apart from each other.

[0152] For example, each of the conductors 2 contains a metal and has a higher thermal conductivity than the insulating substrate 30. The metal in each conductor 2 is not particularly restricted and can be copper, aluminum, iron (Fe), oxygen-free copper, or any alloy thereof (e.g., Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy, etc.). The conductors 2 can be nickel (Ni) plated. The conductors 2 can be formed by pressing a die onto a metal plate or by structuring a metal plate by etching. The method for forming the conductors 2 is not particularly restricted. The thickness of each conductor 2 is not particularly restricted and can be approximately 0.4 mm to 0.8 mm. The conductors 2 are spaced apart from each other.

[0153] In the present embodiment, the lines 2 include a plurality of lines 21, a plurality of lines 22, and two lines 23. The lines 21 and the lines 22 form conductive paths to the source electrodes 43 and gate electrodes 44 of the semiconductor elements 4 (the semiconductor elements 40A to 40F). The two lines 23 form a conductive path to the thermistor 6.

[0154] The conductors 21 are arranged on the insulating substrate 30. In the present embodiment, the conductors 21 are arranged on the second front surface 3a. The conductors 21 are provided at intervals in the first direction x. The configuration of each conductor 21 is not particularly restricted. In the present embodiment, each of the conductors 21 is subdivided for description into a projecting section 212, an inclined section 213, and a parallel section 214, as shown in Fig. 18 and Fig. 20 shown.

[0155] The parallel section 214 is covered with the sealing resin 8. The parallel section 214 is parallel to the insulating substrate 30. The lower surface (the surface facing the z2 side in the thickness direction z) of the parallel section 214 is bonded to the bonding section 521 via a conductive bonding material 28. The inclined section 213 is connected to one end of the parallel section 214 and is inclined relative to the parallel section 214. The protruding section 212 is a section of the conductor 21 that protrudes from the sealing resin 8 and is connected to one end of the inclined section 213. The protruding section 212 protrudes in the second direction y from the sealing resin 8 towards the y1 side. The protruding section 212 can be used to electrically connect the semiconductor device A2 to an external circuit.In the illustrated example, the protruding section 212 is bent towards the side facing the second front surface 3a of the insulating substrate 30 in the thickness direction z.

[0156] The conductors 22 are arranged on the insulating substrate 30. In the present embodiment, the conductors 22 are arranged on the second front surface 3a. The conductors 22 are provided at intervals in the first direction x. Each of the conductors 22 is provided near one of the conductors 21 to form a pair with the conductor 21. The configuration of each conductor 22 is not particularly restricted. In the present embodiment, each of the conductors 22 is subdivided for description into a projecting section 222, an inclined section 223, and a parallel section 224, as shown in Fig. 18 shown.

[0157] The parallel section 224 is covered with the sealing resin 8. The parallel section 224 is parallel to the insulating substrate 30. The lower surface (the surface facing the z2 side in the thickness direction z) of the parallel section 224 is bonded to the bonding section 521 via a conductive bonding material 28. The inclined section 223 is connected to one end of the parallel section 224 and is inclined relative to the parallel section 224. The protruding section 222 is a section of the conductor 22 that protrudes from the sealing resin 8 and is connected to one end of the inclined section 223. The protruding section 222 protrudes in the second direction y from the sealing resin 8 towards the y1 side. The protruding section 222 can be used to electrically connect the semiconductor device A2 to an external circuit.In the illustrated example, the protruding section 222 is bent towards the side that faces the second front surface 3a of the insulating substrate 30 in the thickness direction z.

[0158] The conductors 23 are arranged on the insulating substrate 30. In the present embodiment, the conductors 23 are arranged on the second front surface 3a. The two conductors 23 are arranged side by side in the first direction x. The configuration of each conductor 23 is not particularly restricted. In the present embodiment, each of the conductors 23 is subdivided for description into a projecting section 232, an inclined section 233, and a parallel section 234, as shown in Fig. 18 and Fig. 19 shown.

[0159] The parallel section 234 is covered with the sealing resin 8. The parallel section 234 is parallel to the insulating substrate 30. The lower surface (the surface facing the z2 side in the thickness direction z) of the parallel section 234 is bonded to a wire 501 via a conductive bonding material 28. The inclined section 233 is connected to one end of the parallel section 234 and is inclined relative to the parallel section 234. The protruding section 232 is a section of the wire 23 that protrudes from the sealing resin 8 and is connected to one end of the inclined section 233. The protruding section 232 protrudes in the second direction y from the sealing resin 8 to the y1 side. The protruding section 232 can be used to electrically connect the semiconductor device A2 to an external circuit.In the illustrated example, the protruding section 232 is bent towards the side that faces the second front surface 3a of the insulating substrate 30 in the thickness direction z.

[0160] As in Fig. 20 and Fig. As shown in Figure 21, each of the semiconductor elements 40A, 40B, and 40C is bonded to the mounting section 110 via a conductive bonding material 47, with a rear element surface 42 facing the mounting section 110. This electrically connects a drain electrode 45 of each of the semiconductor elements 40A, 40B, and 40C to the mounting section 110 via a conductive bonding material 47. The mounting section 110 is an example of the “second section” of the present disclosure.

[0161] As in Fig. As shown in Figure 21, the semiconductor element 40D is bonded to the mounting section 120 via a conductive bonding material 47, with a rear element surface 42 facing the mounting section 120. This electrically connects a drain electrode 45 of the semiconductor element 40D to the mounting section 120 via the conductive bonding material 47. The mounting section 120 is an example of the “first section” of the present disclosure. As shown in Fig. As shown in Figure 21, the semiconductor element 40E is bonded to the mounting section 130 via a conductive bonding material 47, with a rear element surface 42 facing the mounting section 130. This electrically connects a drain electrode 45 of the semiconductor element 40E to the mounting section 130 via the conductive bonding material 47. As shown in Fig. As shown in Figure 19, the semiconductor element 40F is bonded to the mounting section 140 via a conductive bonding material 47, with a rear element surface 42 facing the mounting section 140. This electrically connects a drain electrode 45 of the semiconductor element 40F to the mounting section 140 via the conductive bonding material 47.

[0162] As in Fig. As shown in Figure 18, in the present embodiment the gate electrode 44 of each of the semiconductor elements 4 (semiconductor elements 40A to 40F) is electrically connected to one of the leads 21 via a wire 72. The leads 21 are gate terminals of the semiconductor elements 4. The source electrode 43 of each of the semiconductor elements 4 (semiconductor elements 40A to 40F) is electrically connected to one of the leads 22 via a wire 73. The leads 22 are source detection terminals of the semiconductor elements 4.

[0163] As in Fig. 18 and Fig. As shown in Figure 22, the semiconductor elements 4 (semiconductor elements 40A to 40F) of the present embodiment are arranged side by side in the first direction x. The arrangement of the semiconductor elements 4 (semiconductor elements 40A to 40F) is the same (or substantially the same) as that of the semiconductor device A1 of the above embodiment. The relationship between the center positions of the semiconductor elements 4 (semiconductor elements 40A to 40F) and the distance between the centers of adjacent semiconductor elements 4, etc., are the same (or substantially the same) as those shown in the above embodiment with reference to Fig. 9 were described. Therefore, in Fig. 22 the same reference symbols as in Fig. 9 are provided, which are associated with the above embodiment, and descriptions of them are omitted.

[0164] As in Fig. As shown in Figure 18, the thermistor 6 is positioned near the corner of the insulating substrate 30 on the x1 side in the first direction x and on the y1 side in the second direction y.

[0165] Next, the advantages of the semiconductor device A2 according to the present embodiment will be described.

[0166] The semiconductor device A2 includes the carrier conductor 32, four or more semiconductor elements 4 (the semiconductor elements 40A to 40F), and the sealing resin 8. The semiconductor elements 40A to 40F include the semiconductor element 40D (the first semiconductor element) and the semiconductor element 40C (the second semiconductor element), which are located near the center in the first direction x. The distance (the first distance D1) between the center C1 of the semiconductor element 40D and the center C2 of the semiconductor element 40C is greater than the distance (the second distance D21) between the center C1 of the semiconductor element 40D and the center C3 of the semiconductor element 40E, which is adjacent to the semiconductor element 40D, in the first direction x, and is also greater than the distance (the second distance D22) between the center C2 of the semiconductor element 40C and the center C4 of the semiconductor element 40B, which is adjacent to the semiconductor element 40C, in the first direction x.This configuration can suppress thermal disturbances between semiconductor element 40D and semiconductor element 40C, which are located near the center, beneath semiconductor elements 40A to 40F. This prevents the concentration of heat generated by semiconductor elements 40A to 40F and reduces thermal resistance. As a result, semiconductor device A2 can easily handle high currents and improves durability.

[0167] The center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C are located at different positions in the second direction y perpendicular to the first direction x, in which semiconductor elements 40A to 40F are arranged side by side. According to this configuration, heat generated by semiconductor element 40D and semiconductor element 40C, which are located near the center beneath semiconductor elements 40A to 40F, can be efficiently dissipated to the environment, further suppressing thermal disturbances. Additionally, the above configuration can increase the distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C while simultaneously preventing an increase in the dimensions of semiconductor device A1 in the first direction x. Semiconductor device A2 also exhibits similar advantages to semiconductor device A1 in the above embodiment.

[0168] As with the semiconductor device A1 in the semiconductor device assembly B2 described above, the semiconductor device A2 of the present embodiment can be provided for a semiconductor device assembly that includes a cooler 91, a mounting component 92, a control unit 94, a cooling unit 95, and a heating unit 96. This allows the same advantages to be achieved as described in connection with the semiconductor device assembly B2. Third embodiment:

[0169] Fig. 23 and Fig. Figure 24 shows a semiconductor device according to a third embodiment of the present disclosure. A semiconductor device A3 of the present embodiment includes a plurality of the conductors 1 (the conductors 11 to 15), a plurality of the conductors 2 (a plurality of the conductors 21, a plurality of the conductors 22 and two conductors 23), an insulating substrate 30, a plurality of the semiconductor elements 4 (the semiconductor elements 40B, 40C, 40D and 40E), a wiring section 5, a thermistor 6, a plurality of wires 71, a plurality of the wires 72, a plurality of the wires 73 and a plurality of the wires 74 and a sealing resin 8. Fig. Figure 23 is a top view showing the semiconductor device A3 as seen through the sealing resin 8. Fig. Figure 24 is a schematic top view showing the arrangement of the semiconductor elements 4 in the semiconductor device A3. The outline of the sealing resin 8 is shown in Fig. 23 is indicated by an imaginary line (two-dot dash line).

[0170] The semiconductor device A3 of the present embodiment differs from the semiconductor device A1 of the above embodiment mainly in the arrangement of the semiconductor elements 4. The semiconductor device A3 of the present embodiment includes four semiconductor elements 4 (the semiconductor elements 40B, 40C, 40D and 40E). The arrangement of the semiconductor elements 40B to 40E is the same (or substantially the same) as that of the semiconductor elements 40B to 40E in the semiconductor device A1. The semiconductor device A3 is, for example, configured as a full-bridge circuit.

[0171] In the semiconductor device A3, which includes four (even number) semiconductor elements 4, semiconductor element 40C and semiconductor element 40D are arranged near the center in the first direction x. As can be seen in the present embodiment, when the number of semiconductor elements 4 (semiconductor elements 40B to 40E) is even, two semiconductor elements, namely semiconductor elements 40C and 40D, are arranged near the center in the first direction x, below the semiconductor elements 4.

[0172] In the illustrated example, semiconductor elements 40B through 40E include those that are not aligned along the first direction x and are located in different positions in the second direction y. Semiconductor element 40C is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40B on the x2 side in the first direction x. Additionally, semiconductor element 40C is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40D on the x1 side in the first direction x. Semiconductor element 40D is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40E on the x1 side in the first direction x. Semiconductor element 40E is located in the same (or substantially the same) position as semiconductor element 40B in the second direction y.Among the semiconductor elements 4 (semiconductor elements 40B to 40E) arranged as described above, semiconductor element 40D corresponds to an example of the “first semiconductor element” in the present disclosure, and semiconductor element 40C corresponds to an example of the “second semiconductor element” in the present disclosure. A first conductor 321 on which semiconductor element 40D (the first semiconductor element) is arranged corresponds to an example of the “first section” in the present disclosure, and a second conductor 322 on which semiconductor element 40C (the second semiconductor element) is arranged corresponds to an example of the “second section” in the present disclosure.

[0173] The in Fig. The 24 semiconductor elements 4 shown (semiconductor elements 40B to 40E) exhibit the following relationships with respect to the distance between the centers of adjacent semiconductor elements 4 in the first direction x. The first distance D1 between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C, which are located near the center, in the first direction x is greater than the second distance D21 between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D, in the first direction x. The distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is also greater than the second distance D22 between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B, which is adjacent to semiconductor element 40C in the first direction x.In the present embodiment, the distance (the first distance D1) between the center C1 of the semiconductor element 40D and the center C2 of the semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0174] Next, an application example of the semiconductor device A3 will be presented with reference to Fig. 25 described. Fig. Figure 25 is a schematic view showing a vehicle B11 that includes the semiconductor device A3. The vehicle B11 includes an AC-DC converter 871, a power receiving device 872, a storage battery 873, a drive system 874, and a DC-DC converter 875. When the vehicle B11 receives alternating current from a charging device 870, which is, for example, an outdoor AC power source, the AC-DC converter 871 converts the alternating current into high-voltage direct current. The AC-DC conversion device 871 supplies the high-voltage direct current to the storage battery 873. The power receiving device 872 supplies power to the storage battery 873 via a contactless charging system and receives power from a contactless charging device (not illustrated) located in a parking lot or the like, by an electromagnetic induction method.The energy stored in the storage battery 873 is supplied to the drive system 874, which includes an inverter, an AC motor, and a gearbox. The drive system 874 powers the vehicle B11. The DC-DC conversion device 875 can be a step-down DC-DC converter and supplies power to electrical components other than those used to power the vehicle B11. The semiconductor device A3 forms part or section of the DC-DC conversion device 875. The DC-DC conversion device 875 is an example of the power conversion device of this disclosure.

[0175] Next, the advantages of the semiconductor device A3 according to the present disclosure will be described.

[0176] The semiconductor device A3 includes a carrier conductor 32, four or more semiconductor elements 4 (the semiconductor elements 40B to 40E), and the sealing resin 8. The semiconductor elements 40B to 40E include the semiconductor element 40D (the first semiconductor element) and the semiconductor element 40C (the second semiconductor element), which are located near the center in the first direction x. The distance (the first distance D1) between the center C1 of the semiconductor element 40D and the center C2 of the semiconductor element 40C is greater than the distance (the second distance D21) between the center C1 of the semiconductor element 40D and the center C3 of the semiconductor element 40E, which is adjacent to the semiconductor element 40D, in the first direction x, and is also greater than the distance (the second distance D22) between the center C2 of the semiconductor element 40C and the center C4 of the semiconductor element 40B, which is adjacent to the semiconductor element 40C, in the first direction x.This configuration can suppress thermal disturbances between semiconductor element 40D and semiconductor element 40C, which are located near the center, beneath semiconductor elements 40B to 40E. This prevents the concentration of heat generated by semiconductor elements 40B to 40E and reduces thermal resistance. As a result, the semiconductor device A3 can easily handle high currents and improves durability.

[0177] The center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C are located at different positions in the second direction y, perpendicular to the first direction x, in which semiconductor elements 40B to 40E are arranged side by side. According to this configuration, heat generated by semiconductor elements 40D and 40C, which are located near the center beneath semiconductor elements 40B to 40E, can be efficiently dissipated to the environment, further suppressing thermal disturbances. Additionally, the above configuration can increase the distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C while simultaneously preventing an increase in the dimensions of semiconductor device A3 in the first direction x.

[0178] As in Fig. As shown in Figure 24, the centers of the adjacent semiconductor elements 4 are located in the first direction x, and in the second direction y, the centers of the semiconductor elements 4 (semiconductor elements 40B to 40E) are at different positions. According to this configuration, heat generated by semiconductor elements 40B to 40E can be efficiently dissipated to the environment.

[0179] The distance (the first distance D1) between the center C1 of semiconductor element 40D and the center C2 of semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40D and semiconductor element 40C located near the center, beneath semiconductor elements 40B to 40E. The above configuration is more preferred for reducing the thermal resistance of semiconductor device A3.

[0180] The carrier conductor 32 has the first conductor 321 (the first section) and the second conductor 322 (the second section), which are spaced apart from each other. Of the semiconductor elements 40B to 40E, only the semiconductor element 40D (the first semiconductor element) is located on the first conductor 321. Of the semiconductor elements 40B to 40E, the semiconductor element 40C (the second semiconductor element) and the semiconductor element 40B adjacent to the semiconductor element 40C are located on the second conductor 322. The center C1 of the semiconductor element 40D (the first semiconductor element) is offset in the second direction y from the center of either the semiconductor element 40B or 40E towards the y1 side. The center C2 of the semiconductor element 40C (the second semiconductor element) is offset in the second direction y from the center C1 of the semiconductor element 40D towards the y1 side.Heat generated by semiconductor element 40C and semiconductor element 40B, which are arranged on the common second conductor 322, tends to be trapped on the second conductor 322, and disturbances from the heat generated by semiconductor element 40C and semiconductor element 40B tend to cause an increase in the temperature of the second conductor 322. As described above, semiconductor element 40C, of ​​all semiconductor elements 40B to 40E, is arranged furthest towards the y2 side in the second direction y. According to this arrangement, the second conductor 322, on which semiconductor element 40C is mounted, can efficiently dissipate the heat generated by semiconductor element 40C to the surroundings of semiconductor element 40C. This makes it possible to suppress thermal disturbances between semiconductor elements 40D, 40C, and 40B, thereby reducing the thermal resistance of the semiconductor device A3.

[0181] First variation of the third embodiment: Fig. Figure 26 shows a semiconductor device according to a first variation of the third embodiment. Fig. Figure 26 is a schematic top view showing the arrangement of the semiconductor elements 4 in a semiconductor device A31 of the present variation.

[0182] The semiconductor device A31 of the present variation differs from the semiconductor devices A1 and A3 of the above embodiments mainly in the arrangement of the semiconductor elements 4. The semiconductor device A31 includes four semiconductor elements 4 (the semiconductor elements 40A, 40B, 40D and 40E). The arrangement of the semiconductor elements 40A, 40B, 40D and 40E is the same (or substantially the same) as that of the semiconductor elements 40A, 40B, 40D and 40E in the semiconductor device A1.

[0183] In the semiconductor device A31, which includes four (even number) semiconductor elements 4, semiconductor element 40B and semiconductor element 40D are arranged near the center in the first direction x. As can be seen in the present variation, when the number of semiconductor elements 4 (semiconductor elements 40A, 40B, 40D and 40E) is even, two semiconductor elements, namely semiconductor elements 40B and 40D, are arranged among the semiconductor elements 4 in the first direction x near the center.

[0184] In the illustrated example, semiconductor elements 40A, 40B, 40D, and 40E are those that are not aligned along the first x-direction and are located in different positions in the second y-direction. Semiconductor element 40B is offset towards the y1-direction in the second y-direction with respect to the adjacent semiconductor element 40A on the x2-side in the first x-direction. Semiconductor element 40D is offset towards the y1-side in the second y-direction with respect to the adjacent semiconductor element 40C on the x2-side in the first x-direction. Additionally, semiconductor element 40D is offset towards the y1-side in the second y-direction with respect to the adjacent semiconductor element 40E on the x1-side in the first x-direction. Semiconductor element 40E is located in the same (or substantially the same) position as semiconductor element 40B in the second y-direction.Among the semiconductor elements 4 (the semiconductor elements 40A, 40B, 40D and 40E) arranged as described above, the semiconductor element 40D corresponds to an example of the “first semiconductor element” in the present disclosure, and the semiconductor element 40B corresponds to an example of the “second semiconductor element” in the present disclosure.

[0185] The in Fig. The semiconductor elements 4 shown in Figure 26 (semiconductor elements 40A, 40B, 40D, and 40E) exhibit the following relationships with respect to the distance between the centers of adjacent semiconductor elements 4 in the first direction x. A first distance D12, which is the distance between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B, which are located near the center in the first direction x, is greater than the second distance D21 between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D in the first direction x. The distance (the first distance D12) between the center C1 of the semiconductor element 40D and the center C4 of the semiconductor element 40B is also greater than a second distance D23, which is the distance between the center C4 of the semiconductor element 40B and the center C6 of the semiconductor element 40A, which is adjacent to the semiconductor element 40B in the first direction x.In the present variation, the distance (the first distance D12) between the center C1 of the semiconductor element 40D and the center C4 of the semiconductor element 40B is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0186] In semiconductor device A31, semiconductor elements 40A, 40B, 40D, and 40E enclose semiconductor element 40D (the first semiconductor element) and semiconductor element 40B (the second semiconductor element), which are located near the center in the first direction x. The distance (the first distance D12) between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B is greater than the distance (the second distance D21) between the center C1 of semiconductor element 40D and the center C3 of semiconductor element 40E, which is adjacent to semiconductor element 40D in the first direction x, and is also greater than the distance (the second distance D23) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A, which is adjacent to semiconductor element 40B in the first direction x.This configuration can suppress thermal disturbances between semiconductor element 40D and semiconductor element 40B, which are located near the center beneath semiconductor elements 40A, 40B, 40D, and 40E. This prevents the concentration of heat generated by semiconductor elements 40A, 40B, 40D, and 40E and reduces thermal resistance. As a result, the A31 semiconductor device can easily handle high currents and improves durability.

[0187] The center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B are located at different positions in the second direction y perpendicular to the first direction x, in which semiconductor elements 40A, 40B, 40D, and 40E are arranged side by side. According to this configuration, heat generated by semiconductor elements 40D and 40B, which are located near the center beneath semiconductor elements 40A, 40B, 40D, and 40E, can be efficiently dissipated to the environment, further suppressing thermal disturbances. Additionally, the above configuration can increase the distance (the first distance D12) between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B while simultaneously preventing an increase in the dimensions of semiconductor device A31 in the first direction x.

[0188] The centers of the adjacent semiconductor elements 4 in the first direction x, comprising semiconductor elements 40A, 40B, 40D, and 40E, are located at different positions in the second direction y. According to this configuration, the heat generated by semiconductor elements 40A, 40B, 40D, and 40E can be efficiently dissipated to the environment.

[0189] The distance (the first distance D12) between the center C1 of semiconductor element 40D and the center C4 of semiconductor element 40B is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40D and semiconductor element 40B located near the center among semiconductor elements 40A, 40B, 40D, and 40E. The above configuration is more preferred for reducing the thermal resistance of semiconductor device A31.

[0190] Second variation of the third embodiment: Fig. Figure 27 shows a semiconductor device according to a second variation of the third embodiment. Fig. Figure 27 is a schematic top view showing the arrangement of the semiconductor elements 4 in a semiconductor device A32 of the present variation.

[0191] The semiconductor device A32 of the present variation differs from the semiconductor devices A1 and A3 of the above embodiments mainly in the arrangement of the semiconductor elements 4. The semiconductor device A32 includes four semiconductor elements 4 (the semiconductor elements 40B, 40C, 40E and 40F). The arrangement of the semiconductor elements 40B, 40C, 40E and 40F is the same (or substantially the same) as that of the semiconductor elements 40B, 40C, 40E and 40F in the semiconductor device A1.

[0192] In the semiconductor device A32, which includes four (even number) semiconductor elements 4, semiconductor element 40C and semiconductor element 40E are arranged near the center in the first direction x. As can be seen in the present variation, when the number of semiconductor elements 4 (semiconductor elements 40B, 40C, 40E, and 40F) is even, two semiconductor elements, namely semiconductor elements 40C and 40E, are arranged among the semiconductor elements 4 in the first direction x near the center.

[0193] In the illustrated example, semiconductor elements 40B, 40C, 40E, and 40F are those that are not aligned along the first x-direction and are located in different positions in the second y-direction. Semiconductor element 40C is offset towards the y1-direction in the second y-direction with respect to the adjacent semiconductor element 40B on the x2-side in the first x-direction. Additionally, semiconductor element 40C is offset towards the y1-side in the second y-direction with respect to the adjacent semiconductor element 40E on the x1-side in the first x-direction. Semiconductor element 40E is offset towards the y1-side in the second y-direction with respect to the adjacent semiconductor element 40F on the x1-side in the first x-direction. Semiconductor element 40E is located in the same (or substantially the same) position as semiconductor element 40B in the second y-direction.Among the semiconductor elements 4 (the semiconductor elements 40B, 40C, 40E and 40F) arranged as described above, the semiconductor element 40E corresponds to an example of the “first semiconductor element” in the present disclosure, and the semiconductor element 40C corresponds to an example of the “second semiconductor element” in the present disclosure.

[0194] The in Fig. The semiconductor elements 4 shown in Figure 27 (semiconductor elements 40B, 40C, 40E, and 40F) exhibit the following relationships with respect to the distance between the centers of adjacent semiconductor elements 4 in the first direction x. A first distance D13, which is the distance between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C, which are located near the center in the first direction x, is greater than a second distance D24, which is the distance between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x. The distance (the first distance D13) between the center C3 of the semiconductor element 40E and the center C2 of the semiconductor element 40C is also greater than the second distance D22 between the center C2 of the semiconductor element 40C and the center C4 of the semiconductor element 40B, which is adjacent to the semiconductor element 40C in the first direction x.In the present variation, the distance (the first distance D13) between the center C3 of the semiconductor element 40E and the center C2 of the semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0195] In semiconductor device A32, semiconductor elements 40B, 40C, 40E, and 40F enclose semiconductor element 40E (the first semiconductor element) and semiconductor element 40C (the second semiconductor element), which are located near the center in the first direction x. The distance (the first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is greater than the distance (the second distance D24) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x, and is also greater than the distance (the second distance D22) between the center C2 of semiconductor element 40C and the center C4 of semiconductor element 40B, which is adjacent to semiconductor element 40C in the first direction x.This configuration can suppress thermal disturbances between semiconductor element 40E and semiconductor element 40C, which are located near the center beneath semiconductor elements 40B, 40C, 40E, and 40F. This prevents the concentration of heat generated by semiconductor elements 40B, 40C, 40E, and 40F and reduces thermal resistance. As a result, the A32 semiconductor device can easily handle high currents and improves durability.

[0196] The center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C are located at different positions in the second direction y perpendicular to the first direction x, in which semiconductor elements 40B, 40C, 40E, and 40F are arranged side by side. According to this configuration, heat generated by semiconductor elements 40E and 40C, which are located near the center beneath semiconductor elements 40B, 40C, 40E, and 40F, can be efficiently dissipated to the environment, further suppressing thermal disturbances. Additionally, the above configuration can increase the distance (the first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C while simultaneously preventing an increase in the dimensions of semiconductor device A32 in the first direction x.

[0197] The centers of the adjacent semiconductor elements 4 in the first direction x, comprising semiconductor elements 40B, 40C, 40E, and 40F, are located at different positions in the second direction y. According to this configuration, heat generated by semiconductor elements 40B, 40C, 40E, and 40F can be efficiently dissipated to the environment.

[0198] The distance (the first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40E and semiconductor element 40C, which are located near the center, among semiconductor elements 40B, 40C, 40E, and 40F. The above configuration is more preferred for reducing the thermal resistance of semiconductor device A32.

[0199] Third variation of the third embodiment: Fig. Figure 28 shows a semiconductor device according to a third variation of the third embodiment. Fig. Figure 28 is a schematic top view showing the arrangement of the semiconductor elements 4 in a semiconductor device A33 of the present variation.

[0200] The semiconductor device A33 of the present variation differs from the semiconductor devices A1 and A3 of the above embodiments mainly in the arrangement of the semiconductor elements 4. The semiconductor device A33 includes four semiconductor elements 4 (the semiconductor elements 40A, 40C, 40E and 40F). The arrangement of the semiconductor elements 40A, 40C, 40E and 40F is the same (or substantially the same) as that of the semiconductor elements 40A, 40C, 40E and 40F in the semiconductor device A1.

[0201] In the semiconductor device A32, which includes four (even number) semiconductor elements 4, semiconductor element 40C and semiconductor element 40E are arranged near the center in the first direction x. As can be seen in the present variation, when the number of semiconductor elements 4 (semiconductor elements 40B, 40C, 40E, and 40F) is even, two semiconductor elements, namely semiconductor elements 40C and 40E, are arranged among the semiconductor elements 4 in the first direction x near the center.

[0202] In the illustrated example, semiconductor elements 40A, 40C, 40E, and 40F are those that are not aligned along the first direction x and are located in different positions in the second direction y. Semiconductor element 40C is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40A on the x2 side in the first direction x. Additionally, semiconductor element 40C is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40E on the x1 side in the first direction x. Semiconductor element 40E is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40F on the x1 side in the first direction x. Semiconductor element 40F is located in the second direction y in the same (or substantially the same) position as semiconductor element 40A.Among the semiconductor elements 4 (semiconductor elements 40A, 40C, 40E and 40F) arranged as described above, semiconductor element 40E corresponds to an example of the “first semiconductor element” in the present disclosure, and semiconductor element 40C corresponds to an example of the “second semiconductor element” in the present disclosure. A third conductor 323, on which semiconductor element 40E (the first semiconductor element) is arranged, corresponds to an example of the “first section” in the present disclosure, and the second conductor 322, on which semiconductor element 40C (the second semiconductor element) is arranged, corresponds to an example of the “second section” in the present disclosure.

[0203] The in Fig. The semiconductor elements 4 shown in Figure 28 (semiconductor elements 40A, 40C, 40E, and 40F) exhibit the following relationships with respect to the distance between the centers of adjacent semiconductor elements 4 in the first direction x. The first distance D13 between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C, which are located near the center in the first direction x, is greater than the second distance D24 between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x. The distance (the first distance D13) between the center C3 of the semiconductor element 40E and the center C2 of the semiconductor element 40C is also greater than a second distance D25, which is the distance between the center C2 of the semiconductor element 40C and the center C6 of the semiconductor element 40A, which is adjacent to the semiconductor element 40C in the first direction x.In the present variation, the distance (the first distance D13) between the center C3 of the semiconductor element 40E and the center C2 of the semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0204] In semiconductor device A33, semiconductor elements 40A, 40C, 40E, and 40F enclose semiconductor element 40E (the first semiconductor element) and semiconductor element 40C (the second semiconductor element), which are located near the center in the first direction x. The distance (the first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is greater than the distance (the second distance D24) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x, and is also greater than the distance (the second distance D25) between the center C2 of semiconductor element 40C and the center C6 of semiconductor element 40A, which is adjacent to semiconductor element 40C in the first direction x.This configuration can suppress thermal disturbances between semiconductor element 40E and semiconductor element 40C, which are located near the center beneath semiconductor elements 40A, 40C, 40E, and 40F. This prevents the concentration of heat generated by semiconductor elements 40A, 40C, 40E, and 40F and reduces thermal resistance. As a result, the A33 semiconductor device can easily handle high currents and improves durability.

[0205] The center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C are located at different positions in the second direction y perpendicular to the first direction x, in which semiconductor elements 40A, 40C, 40E, and 40F are arranged side by side. According to this configuration, heat generated by semiconductor elements 40E and 40C, which are located near the center beneath semiconductor elements 40B, 40C, 40E, and 40F, can be efficiently dissipated to the environment, further suppressing thermal disturbances. Additionally, the above configuration can increase the distance (the first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C while simultaneously preventing an increase in the dimensions of semiconductor device A33 in the first direction x.

[0206] The centers of the adjacent semiconductor elements 4 in the first direction x, comprising semiconductor elements 40A, 40C, 40E, and 40F, are located at different positions in the second direction y. According to this configuration, heat generated by semiconductor elements 40A, 40C, 40E, and 40F can be efficiently dissipated to the environment.

[0207] The distance (the first distance D13) between the center C3 of semiconductor element 40E and the center C2 of semiconductor element 40C is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40E and semiconductor element 40C, which are located near the center, among semiconductor elements 40A, 40C, 40E, and 40F. The above configuration is more preferred for reducing the thermal resistance of semiconductor device A33.

[0208] The carrier conductor 32 includes the third conductor 323 (the first section) and the second conductor 322 (the second section), which are spaced apart from each other. Of the semiconductor elements 40A, 40C, 40E, and 40F, only semiconductor element 40E (the first semiconductor element) is located on the third conductor 323. Of the semiconductor elements 40A, 40C, 40E, and 40F, semiconductor element 40C (the second semiconductor element) and the semiconductor element 40A adjacent to semiconductor element 40C are located on the second conductor 322. The center C3 of semiconductor element 40E (the first semiconductor element) is offset in the second direction y from the center of each of the semiconductor elements 40A and 40F in the second direction y towards the y1 side. The center C2 of the semiconductor element 40C (of the second semiconductor element) is offset in the second direction y from the center C3 of the semiconductor element 40E towards the y1 side.Heat generated by semiconductor element 40C and semiconductor element 40A, which are arranged on the common second conductor 322, tends to be trapped on the second conductor 322, and disturbances from the heat generated by semiconductor element 40C and semiconductor element 40A tend to cause an increase in the temperature of the second conductor 322. As described above, semiconductor element 40C, of ​​all semiconductor elements 40A, 40C, 40E, and 40F, is arranged furthest towards the y2 side in the second direction y. According to this arrangement, the second conductor 322, on which semiconductor element 40C is mounted, can efficiently dissipate the heat generated by semiconductor element 40C to the surroundings of semiconductor element 40C. This makes it possible to suppress thermal disturbances between semiconductor elements 40E, 40C, and 40A and thereby reduce the thermal resistance of the semiconductor device A33.

[0209] Fourth variation of the third embodiment: Fig. Figure 29 shows a semiconductor device according to a fourth variation of the third embodiment. Fig. Figure 29 is a schematic top view showing the arrangement of the semiconductor elements 4 in a semiconductor device A34 of the present variation.

[0210] The semiconductor device A34 of the present variation differs from the semiconductor devices A1 and A3 of the above embodiments mainly in the arrangement of the semiconductor elements 4. The semiconductor device A33 includes four semiconductor elements 4 (the semiconductor elements 40A, 40B, 40E and 40F). The arrangement of the semiconductor elements 40A, 40B, 40E and 40F is the same (or substantially the same) as that of the semiconductor elements 40A, 40B, 40E and 40F in the semiconductor device A1.

[0211] In the semiconductor device A33, which includes four (even number) semiconductor elements 4, semiconductor element 40B and semiconductor element 40E are arranged near the center in the first direction x. As can be seen in the present variation, when the number of semiconductor elements 4 (semiconductor elements 40A, 40B, 40E, and 40F) is even, two semiconductor elements, namely semiconductor elements 40B and 40E, are arranged among the semiconductor elements 4 in the first direction x near the center.

[0212] In the illustrated example, semiconductor elements 40A, 40B, 40E, and 40F are those that are not aligned along the first direction x and are located in different positions in the second direction y. Semiconductor element 40B is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40A on the x2 side in the first direction x. Semiconductor element 40B is adjacent to semiconductor element 40E on the x1 side in the first direction x and is located in the same (or substantially the same) position as semiconductor element 40E in the second direction y. Semiconductor element 40E is offset towards the y1 side in the second direction y with respect to the adjacent semiconductor element 40F on the x1 side in the first direction x. Semiconductor element 40F is located in the same (or substantially the same) position as semiconductor element 40A in the second direction y.Among the semiconductor elements 4 (the semiconductor elements 40A, 40B, 40E and 40F) arranged as described above, the semiconductor element 40E corresponds to an example of the “first semiconductor element” in the present disclosure, and the semiconductor element 40B corresponds to an example of the “second semiconductor element” in the present disclosure.

[0213] The in Fig.The semiconductor elements 4 shown in Figure 29 (semiconductor elements 40A, 40B, 40E, and 40F) exhibit the following relationships with respect to the distance between the centers of adjacent semiconductor elements 4 in the first direction x. A first distance D14 between the center C3 of semiconductor element 40E and the center C4 of semiconductor element 40B, which are located near the center, in the first direction x is greater than the second distance D24 between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x. The distance (the first distance D14) between the center C3 of the semiconductor element 40E and the center C4 of the semiconductor element 40B is also greater than the second distance D23 between the center C4 of the semiconductor element 40B and the center C6 of the semiconductor element 40A, which is adjacent to the semiconductor element 40B in the first direction x.In the present variation, the distance (the first distance D14) between the center C3 of the semiconductor element 40E and the center C4 of the semiconductor element 40B is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x.

[0214] In semiconductor device A34, semiconductor elements 40A, 40B, 40E, and 40F enclose semiconductor element 40E (the first semiconductor element) and semiconductor element 40B (the second semiconductor element), which are located near the center in the first direction x. The distance (the first distance D14) between the center C3 of semiconductor element 40E and the center C4 of semiconductor element 40B is greater than the distance (the second distance D24) between the center C3 of semiconductor element 40E and the center C5 of semiconductor element 40F, which is adjacent to semiconductor element 40E in the first direction x, and is also greater than the distance (the second distance D23) between the center C4 of semiconductor element 40B and the center C6 of semiconductor element 40A, which is adjacent to semiconductor element 40B in the first direction x.This configuration can suppress thermal disturbances between semiconductor element 40E and semiconductor element 40B, which are located near the center beneath semiconductor elements 40A, 40B, 40E, and 40F. This prevents the concentration of heat generated by semiconductor elements 40A, 40B, 40E, and 40F and reduces thermal resistance. As a result, the A34 semiconductor device can easily handle high currents and improves durability.

[0215] The distance (the first distance D14) between the center C3 of semiconductor element 40E and the center C4 of semiconductor element 40B is at least twice the length (length L1) of one side of each semiconductor element 4 along the first direction x. This configuration can suitably suppress the thermal disturbances between semiconductor element 40E and semiconductor element 40B, which are located near the center, among semiconductor elements 40A, 40B, 40E, and 40F. The above configuration is more preferred for reducing the thermal resistance of semiconductor device A34.

[0216] The semiconductor device according to the present disclosure is not limited to the embodiments described above. Various design modifications can be made to the specific configurations of the elements of the semiconductor device according to the present disclosure.

[0217] Although the present embodiments have been described with an example in which the semiconductor devices, such as semiconductor device A1, are configured as molded modules in which the sealing resin 8 is formed by molding, the present disclosure is not limited thereto. For example, the semiconductor device of the present disclosure may be configured as a shell module. In this case, the interior of the housing may be filled with an insulating material such as silicone gel, which acts as a sealing resin.

[0218] The present disclosure includes the embodiments described in the following clauses. Clause 1.

[0219] A semiconductor device comprising: a conductor with a first front surface facing a first side in a thickness direction, and a first rear surface facing a side opposite the first front surface; a plurality of semiconductor elements comprising four or more semiconductor elements arranged or configured on the first front surface; and a sealing resin that covers the multitude of semiconductor elements and at least one section of the conductor, wherein the multitude of semiconductor elements are arranged side by side in a first direction perpendicular to the thickness direction, where, if the number of semiconductor elements is even, the multitude of semiconductor elements comprises a first semiconductor element and a second semiconductor element arranged near a center in the first direction, a first distance, which is a distance between a center of the first semiconductor element and a center of the second semiconductor element, is greater than a second distance, which is a distance between the center of one of the first semiconductor element and the second semiconductor element and a center of another of the semiconductor elements that is adjacent to the one of the first semiconductor element and the second semiconductor element in the first direction, where, if the number of semiconductor elements is odd, the multitude of semiconductor elements includes a third semiconductor element located near the center in the first direction, a fourth semiconductor element adjacent to the third semiconductor element on a first side in the first direction, and a fifth semiconductor element adjacent to the third semiconductor element on a second side in the first direction, and a third distance, which is a distance between a center of the third semiconductor element and a center of the fourth semiconductor element, and a fourth distance, which is a distance between the center of the third semiconductor element and a center of the fifth semiconductor element, are each greater than a fifth distance, which is a distance between the center of one of the fourth semiconductor element and the fifth semiconductor element and a center of another of the semiconductor elements that is adjacent to one of the fourth semiconductor element and the fifth semiconductor element in the first direction. Clause 2.

[0220] The semiconductor device according to clause 1, wherein, if the number of semiconductor elements is even, the center of the first semiconductor element and the center of the second semiconductor element are located at different positions in a second direction perpendicular to the thickness direction and to the first direction, and if the number of semiconductor elements is odd, the center of the third semiconductor element is located in the second direction at a position different from the center of the fourth semiconductor element and from the center of the fifth semiconductor element. Clause 3.

[0221] The semiconductor device according to clause 2, wherein the centers of adjacent semiconductor elements in the first direction, from the plurality of semiconductor elements, are located at different positions in the second direction. Clause 4.

[0222] The semiconductor device according to one of clauses 1 to 3, wherein, if the number of semiconductor elements is even, the first distance is greater than a sixth distance, which is a distance between the centers of other semiconductor elements adjacent to each other in the first direction, from the multitude of semiconductor elements, and if the number of semiconductor elements is odd, Each of the third distance and the fourth distance is greater than a seventh distance, which is a distance between the centers of other semiconductor elements adjacent to each other in the first direction, from the multitude of semiconductor elements. Clause 5.

[0223] The semiconductor device according to clause 4, wherein, if the number of semiconductor elements is even, the second distance is greater than the sixth distance, and if the number of semiconductor elements is odd, the fifth distance is larger than the seventh distance. Clause 6.

[0224] The semiconductor device according to clause 5, wherein, if the number of semiconductor elements is even, The sixth distance decreases when the other semiconductor elements adjacent to each other in the first direction are further away from the center in the first direction, and if the number of semiconductor elements is odd, The seventh distance decreases as the other semiconductor elements adjacent to each other in the first direction are located further away from the center in the first direction. Clause 7.

[0225] The semiconductor device according to any one of clauses 1 to 6, wherein, if the number of semiconductor elements is even, the first distance is at least twice the length of one side of each semiconductor element along the first direction, and if the number of semiconductor elements is odd, Each of the third and fourth distances is at least twice the length of one side of each semiconductor element along the first direction. Clause 8.

[0226] The semiconductor device according to clause 2, wherein the conductor includes a first section and a second section spaced apart from each other, Of the multitude of semiconductor elements, only the first semiconductor element is set up on the first section, of the multitude of semiconductor elements, the second semiconductor element and a semiconductor element adjacent to the second semiconductor element are set up on the second section, the center of the first semiconductor element is offset to a first side in the second direction relative to the center of any other semiconductor element among the multitude of semiconductor elements in the second direction, and the center of the second semiconductor element is offset to the first side in the second direction relative to the center of the first semiconductor element in the second direction. Clause 9.

[0227] The semiconductor device according to any one of clauses 1 to 8, further comprising a support with a second front surface facing the first side in the thickness direction, and with a second rear surface facing a side opposite the second front surface, wherein the first rear surface of the conductor is bonded to the second front surface. Clause 10.

[0228] The semiconductor device according to clause 9, wherein the support comprises an insulating substrate enclosing the second front surface and a metal layer bonded to a surface of the insulating substrate located on a side opposite the second front surface, the metal layer enclosing the second rear surface. Clause 11.

[0229] The semiconductor device according to clause 10, wherein the insulating substrate is made of a ceramic material. Clause 12.

[0230] The semiconductor device according to clause 9, wherein the conductor is formed from a conductor and the carrier is formed from the insulating substrate. Clause 13.

[0231] The semiconductor device according to any one of clauses 9 to 12, wherein each of the plurality of semiconductor elements is a switching element. Clause 14.

[0232] The semiconductor device according to clause 13, wherein each of the plurality of semiconductor elements has a front element surface facing the first side in the thickness direction, a rear element surface facing a second side in the thickness direction, a source electrode and a gate electrode arranged on the front element surface, and a drain electrode arranged on the rear element surface. Clause 15.

[0233] The semiconductor device according to clause 10 or 11, wherein a structure made from the conductor and the support has a heat capacity of 0.01 to 15 J / K and Each of the numerous semiconductor elements has a heat capacity of 0.0001 to 0.5 J / K. Clause 16.

[0234] The semiconductor device according to clause 10 or 11, wherein a structure made from the conductor and the support has a thermal resistance of 0.0003 to 1.5 K / W and Each of the numerous semiconductor elements has a thermal resistance of 0.0003 to 1.5 K / W. Clause 17.

[0235] The semiconductor device according to clause 13 or 14, wherein each of the plurality of semiconductor elements comprises at least one large bandgap semiconductor and one ultra-large bandgap semiconductor. Clause 18.

[0236] A semiconductor device assembly comprising: the semiconductor device according to any one of clauses 9 to 17; a cooler; and a cooling unit that cools the cooler, where the second rear surface of the carrier is exposed by the sealing resin and the cooler has a section that is in contact with the second rear surface. Clause 19.

[0237] The semiconductor device assembly according to clause 18, further comprising a control unit, wherein the semiconductor device includes a temperature sensing element located on the second front surface of the substrate, and The control unit controls the cooling unit based on a temperature detected by the temperature detection element. Clause 20.

[0238] The semiconductor device assembly according to clause 19, further comprising a heating unit that heats the cooler, the control unit controls the heating unit based on a temperature detected by the temperature detection element. Clause 21.

[0239] A vehicle comprising a power conversion device configured to include the semiconductor device according to clause 13 or 14. REFERENCE MARK

[0240] A1, A2, A3, A31, A32, A33 and A34: Semiconductor device B1, B11: Vehicle B2, B21: Semiconductor device assembly 1, 11 to 15: Conductor 110: Mounting section (conductor, second section) 120: Mounting section (conductor, first section) 130, 140: Mounting section (conductor) 18: Bonding material 19: Conductive bonding material 2, 21 to 23: Conductor 28: Conductive bonding material 3: Carrier 3a: Second front surface 3b: Second rear surface 30, 31: Insulating substrate 32: Carrier conductor (conductor) 32a: First front surface 32b: First rear surface 321: First conductor 322: Second conductor 323: Third conductor 324: Fourth conductor 325: Fifth conductor 326: Sixth conductor 327: Seventh conductor 328: Eighth conductor 33: Metal layer 4, 40A to 40N40P to 40R: Semiconductor element 41: Front element surface 42: Rear element surface 43: Source electrode 44: Gate electrode 45: Drain electrode 47: Conductive bonding material 5: Wiring section 501: Wiring 502: Pad section 511 to 515, 521: Bonding section 6: Thermistor 62: Insulating component 63: Conductive bonding material 71 to 74: Wire 8: Sealing resin 81: Front resin surface 82: Rear resin surface 83 to 86: Side resin surface 831, 841: Recess 870: Charging device 871: AC-DC converter (current converter) 872: Current receiving device 873: Storage battery 874: Drive system 875: DC-DC conversion device (power conversion device) 91: Cooler 911: Mounting surface 912: Flow channel 913: Mounting hole 92: Mounting component 93: Fastening element 94: Control unit 95: Cooling unit 96: Heating unit D1, D12, D13, D14: First spacing D21, D21, D23, D24,D25: Second gap D3: Third gap D4: Fourth gap D51, D52: Fifth gap D61 to D64: Sixth gap D71 to D74: Seventh gap QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] WO 2019 / 244372

[0004]

Claims

[1] Semiconductor device comprising: a conductor with a first front surface facing a first side in a thickness direction, and a first rear surface facing a side opposite the first front surface; a plurality of semiconductor elements comprising four or more semiconductor elements arranged on the first front surface; and a sealing resin that covers the multitude of semiconductor elements and at least one section of the conductor, wherein the multitude of semiconductor elements are arranged side by side in a first direction perpendicular to the thickness direction, where, if the number of semiconductor elements is even, the multitude of semiconductor elements comprises a first semiconductor element and a second semiconductor element arranged near a center in the first direction, a first distance, which is a distance between a center of the first semiconductor element and a center of the second semiconductor element, is greater than a second distance, which is a distance between the center of one of the first semiconductor element and the second semiconductor element and a center of another of the semiconductor elements that is adjacent to one of the first semiconductor element and the second semiconductor element in the first direction, where, if the number of semiconductor elements is odd, the multitude of semiconductor elements includes a third semiconductor element located near the center in the first direction, a fourth semiconductor element adjacent to the third semiconductor element on a first side in the first direction, and a fifth semiconductor element adjacent to the third semiconductor element on a second side in the first direction, and a third distance, which is a distance between a center of the third semiconductor element and a center of the fourth semiconductor element, and a fourth distance, which is a distance between the center of the third semiconductor element and a center of the fifth semiconductor element, are each greater than a fifth distance, which is a distance between the center of one of the fourth semiconductor element and the fifth semiconductor element and a center of another of the semiconductor elements that is adjacent to one of the fourth semiconductor element and the fifth semiconductor element in the first direction. [2] Semiconductor device according to claim 1, wherein, if the number of semiconductor elements is even, the center of the first semiconductor element and the center of the second semiconductor element are located at different positions in a second direction perpendicular to the thickness direction and to the first direction, and if the number of semiconductor elements is odd, the center of the third semiconductor element is located in the second direction at a position different from the center of the fourth semiconductor element and from the center of the fifth semiconductor element. [3] Semiconductor device according to claim 2, wherein the centers of adjacent semiconductor elements in the first direction are located at different positions in the second direction from the plurality of semiconductor elements. [4] Semiconductor device according to any one of claims 1 to 3, wherein, if the number of semiconductor elements is even, the first distance is greater than a sixth distance, which is a distance between the centers of other semiconductor elements adjacent to each other in the first direction, from the multitude of semiconductor elements, and if the number of semiconductor elements is odd, Each of the third distance and the fourth distance is greater than a seventh distance, which is a distance between the centers of other semiconductor elements adjacent to each other in the first direction, from the multitude of semiconductor elements. [5] Semiconductor device according to claim 4, wherein, if the number of semiconductor elements is even, the second distance is greater than the sixth distance, and if the number of semiconductor elements is odd, the fifth distance is larger than the seventh distance. [6] Semiconductor device according to claim 5, wherein, if the number of semiconductor elements is even, The sixth distance decreases when the other semiconductor elements adjacent to each other in the first direction are further away from the center in the first direction, and if the number of semiconductor elements is odd, The seventh distance decreases when the other semiconductor elements adjacent to each other in the first direction are located further away from the center in the first direction. [7] Semiconductor device according to any one of claims 1 to 6, wherein, if the number of semiconductor elements is even, the first distance is at least twice the length of one side of each semiconductor element along the first direction, and if the number of semiconductor elements is odd, Each of the third and fourth distances is at least twice the length of one side of each semiconductor element along the first direction. [8] Semiconductor device according to claim 2, wherein the conductor includes a first section and a second section which are spaced apart from each other, Of the multitude of semiconductor elements, only the first semiconductor element is set up on the first section, of the multitude of semiconductor elements, the second semiconductor element and a semiconductor element adjacent to the second semiconductor element are set up on the second section, the center of the first semiconductor element is offset to a first side in the second direction relative to the center of any other semiconductor element from the multitude of semiconductor elements in the second direction, and the center of the second semiconductor element is offset to the first side in the second direction relative to the center of the first semiconductor element in the second direction. [9] Semiconductor device according to any one of claims 1 to 8, further comprising a carrier with a second front surface facing the first side in the thickness direction and with a second rear surface facing a side opposite the second front surface, wherein the first rear surface of the conductor is bonded to the second front surface. [10] Semiconductor device according to claim 9, wherein the support comprises an insulating substrate enclosing the second front surface and a metal layer bonded to a surface of the insulating substrate located on a side opposite the second front surface, the metal layer enclosing the second rear surface. [11] Semiconductor device according to claim 10, wherein the insulating substrate is made of a ceramic material. [12] Semiconductor device according to claim 9, wherein the conductor is formed from a conductor and the support is formed from the insulating substrate. [13] Semiconductor device according to any one of claims 9 to 12, wherein each of the plurality of semiconductor elements is a switching element. [14] Semiconductor device according to claim 13, wherein each of the plurality of semiconductor elements has a front element surface facing the first side in the thickness direction, a rear element surface facing a second side in the thickness direction, a source electrode and a gate electrode arranged on the front element surface, and a drain electrode arranged on the rear element surface. [15] Semiconductor device according to claim 10 or 11, wherein a structure made from the conductor and the support has a heat capacity of 0.01 to 15 J / K and each of the plurality of semiconductor elements has a heat capacity of 0.0001 to 0.5 J / K. [16] Semiconductor device according to claim 10 or 11, wherein a structure made from the conductor and the support has a thermal resistance of 0.0003 to 1.5 K / W and each of the plurality of semiconductor elements has a thermal resistance of 0.0003 to 1.5 K / W. [17] Semiconductor device according to claim 13 or 14, wherein each of the plurality of semiconductor elements comprises at least one of a large band gap semiconductor and one of an ultra-large band gap semiconductor. [18] Semiconductor device assembly comprising: the semiconductor device according to any one of claims 9 to 17; a cooler; and a cooling unit that cools the cooler, where the second rear surface of the carrier is exposed to the sealing resin, and the cooler has a section that is in contact with the second rear surface. [19] Vehicle comprising a power conversion device configured to include the semiconductor device according to claim 13 or 14.

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