Semiconductor component and method for manufacturing a semiconductor component

Abstract

A semiconductor device comprises a chip formed by a wide-bandgap semiconductor and having a main surface on which a semiconductor region of a first conductivity type is formed, a base defect region of a second conductivity type formed in a surface layer section of the semiconductor region, a first defect region formed in a surface layer section of the base defect region, and a second defect region of a conductivity type opposite to that of the first defect region formed in the surface layer section of the base defect region, wherein the second defect region is adjacent to the first defect region in a first direction, wherein the second defect region is formed in a band shape extending orthogonally to the first direction in a second direction, and has a projection section.which selectively protrudes in the first direction towards the first defect area.

Description

Related registrations

[0001] The present application corresponds to Japanese patent application No. 2023-099595, which was filed with the Japanese Patent Office on June 16, 2023, and the entire disclosure of that application is incorporated herein by reference. Technical field

[0002] The present disclosure relates to a semiconductor device and a manufacturing process for it. State of the art

[0003] Patent literature 1 discloses a SiC semiconductor device comprising a plurality of p-type body regions formed on a front surface section of an n-type SiC semiconductor layer, each of the p-type body regions forming a unit cell, an n-type source region formed within the p-type body region, a gate electrode facing the p-type body region across a gate insulating film, and an n +-Type drain area and a p + -type collector region formed adjacent to each other on a rear surface section of the SiC semiconductor layer, and an n-type drift region between the p-type body region and the n + -type drain area, wherein the p + -Type collector area is designed to cover an area containing at least two unit cells in an X-axis along a front surface of the SiC semiconductor layer. List of publications Patent literature

[0004] Patent Literature 1: Japanese Patent Application Disclosure Document JP-2015 207 588 A Overview of the invention: Problems underlying the invention

[0005] A preferred embodiment of the present disclosure provides a semiconductor device capable of accurately forming a defect region even in a fine pattern, and a method for manufacturing the semiconductor device. Means to solve the problems

[0006] A preferred embodiment of the present disclosure provides a semiconductor device comprising a chip formed by a wide-bandgap semiconductor and having a main surface on which a semiconductor region of a first conductivity type is formed; a base-defect region of a second conductivity type formed in a surface layer section of the semiconductor region; and a first defect region formed in a surface layer section of the base-defect region.and has a second defect region of a conductivity type opposite to that of the first defect region and formed in the surface layer section of the base defect region, wherein the second defect region is adjacent to the first defect region in a first direction, wherein the second defect region is formed in a band shape extending orthogonally to the first direction in a second direction, and has a projection section selectively projecting towards the first defect region in the first direction.

[0007] A preferred embodiment of the present disclosure provides a method for manufacturing a semiconductor device comprising a step of preparing a wafer formed by a wide-bandgap semiconductor having a main surface on which a semiconductor region of a first conductivity type is formed, and selectively forming a plurality of body regions at distances or intervals in a first direction in a surface layer section of the semiconductor region by selectively implanting a defect of a second conductivity type into the semiconductor region;a step of forming a first mask selectively covering each of the body regions, the first mask having a first section extending in a second direction orthogonal to the first direction and having a first width in the first direction, and a pair of projection sections projecting from a center of the first section in the second direction to both sides in the first direction; a step of forming a first defect region in a surface layer section of the body region by implanting a defect of a first conductivity type into the body region through the first mask, and leaving behind a contact pattern region formed from a portion of the body region in an area covered by the first mask;a step of forming a second mask having an opening for selectively exposing the contact pattern region and covering the first defect region; a step of forming a body contact region in the surface layer portion of the body region by implanting a defect of a second conductivity type into the contact pattern region through the second mask; and a step of forming a gate electrode covering a channel formed in a region between the semiconductor region and the first defect region in the surface layer portion of the body region. Advantageous effects of the invention

[0008] According to the semiconductor device and the method for its manufacture according to a preferred embodiment of the present disclosure, a defect area can be precisely formed even in a fine pattern. Brief description of the drawings Fig. Figure 1 is a plan view illustrating a semiconductor device according to a preferred embodiment. Fig. 2 is a cross-sectional view along the in Fig. 1 shown line II-II. Fig. Figure 3 is a plan view illustrating a layout example of a first main surface. Fig. Figure 4 is an enlarged plan view illustrating a main section of the first main surface. Fig. Figure 5 is an enlarged plan view illustrating another main section of the first main surface. Fig. 6 is an enlarged plan view showing a main section of Fig. 5 illustrates. Fig. 7 is a cross-sectional view along the in Fig. 5 shown line VII-VII. Fig. 8 is a cross-sectional view along the in Fig. 5 shown line VIII-VIII. Fig. 9 is a cross-sectional view along the in Fig. 5 shown line IX-IX. Fig. 10 is a cross-sectional view along the in Fig. Line XX shown in section 5. Fig. Figure 11 is a schematic view illustrating a wafer. Fig. Figure 12A is a cross-sectional view illustrating a method for manufacturing the semiconductor device. Fig. 12B is a cross-sectional view showing a Fig. 12A illustrates the following step. Fig. 12C is a cross-sectional view that shows a Fig. 12B illustrates the following step. Fig. 12D is a cross-sectional view that shows a Fig. 12C illustrates the following step. Fig. 12E is a cross-sectional view that shows a Fig. 12D illustrates the following step. Fig. 12F is a cross-sectional view that shows a Fig. 12E illustrates the following step. Fig. 12G is a cross-sectional view that shows a Fig. 12F illustrates the following step. Fig. 12H is a cross-sectional view that shows a Fig. 12G illustrates the following step. Fig. 12I is a cross-sectional view that shows a Fig. 12H illustrates the following step. Fig. 12J is a cross-sectional view that shows a Fig. 12I illustrates the following step. Fig. 12K is a cross-sectional view that shows a Fig. The following step is illustrated in the 12J. Fig. 12L is a cross-sectional view that shows a Fig. 12K illustrates the following step. Fig. 12M is a cross-sectional view that shows a Fig. 12L illustrates the following step. Fig. 12N is a cross-sectional view that shows a Fig. The following step is illustrated in 12M. Fig. 12O is a cross-sectional view that shows a Fig. 12N illustrates the following step. Fig. 12P is a cross-sectional view that shows a Fig. 12O illustrates the following step. Fig. 13 is a view that shows a planar pattern of a Fig. The first mask shown in 12G illustrates this. Fig. Figure 14 is a cross-sectional view showing a modification example of a source area and a body contact area in Fig. 6 illustrates. Fig. Figure 15 is a view illustrating a first modification example of the body contact area. Fig. Figure 16 is a view illustrating a second modification example of the body contact area. Fig. Figure 17 is a view illustrating a third modification example of the body contact area. Fig. Figure 18 is a view illustrating a fourth modification example of the body contact area. Fig. Figure 19 is a view illustrating a fifth modification example of the body contact area. Description of embodiments

[0009] Preferred embodiments are described in detail below with reference to the attached drawings. The attached drawings are all schematic views and not drawn strictly to scale, and relative positions, scales, proportions, angles, etc., do not always correspond. Corresponding structures in the attached drawings are labeled with identical reference numerals, and repeated descriptions thereof are to be omitted or simplified. For structures whose description has been omitted or simplified, the description given before the omission or simplification shall apply.

[0010] When the term "essentially" is used in this description, it includes a numerical value (mode) that is equal to a numerical value (mode) of a comparison target, and also includes numerical errors (mode errors) in a range of ±10% based on the numerical value (mode) of the comparison target. Although the terms "first," "second," "third," etc., are used in the following description, these are symbols appended to the names of the respective structures to clarify the order of description and are not included with the intention of limiting the names of the respective structures.

[0011] In the following description, a semiconductor (defect) conductivity type is specified using "p-type" or "n-type," and the "p-type" can be referred to as a "first conductivity type" and the "n-type" as a "second conductivity type." Of course, the "n-type" can alternatively be referred to as the "first conductivity type" and the "p-type" as the "second conductivity type." The "p-type" is a conductivity type due to a trivalent element, and the "n-type" is a conductivity type due to a pentavalent element. The trivalent element is at least one type from boron, aluminum, gallium, and indium. The pentavalent element is at least one type from nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0012] Fig. Figure 1 is a plan view illustrating a semiconductor device 1 according to a preferred embodiment. Fig. 2 is a cross-sectional view along the in Fig. 1 shown line II-II. Fig. Figure 3 is a plan view illustrating a layout example of a first main surface 3. Fig. Figure 4 is an enlarged plan view illustrating a main section of the first main surface 3. Fig. Figure 5 is an enlarged plan view illustrating another main section of the first main surface 3.

[0013] Fig. 6 is an enlarged plan view showing a main section of Fig. 5 illustrates. Fig. 7 is a cross-sectional view along the in Fig. 5 shown line VII-VII. Fig. 8 is a cross-sectional view along the in Fig. 5 shown line VIII-VIII. Fig. 9 is a cross-sectional view along the in Fig. 5 shown line IX-IX. Fig. 10 is a cross-sectional view along the in Fig. Line XX shown in section 5.

[0014] With reference to the Fig. From 1 to 10, semiconductor device 1 is a semiconductor switching device with a transistor structure Tr with an insulated gate as an example of a device structure. The transistor structure Tr has a vertical structure. Semiconductor device 1 is a SiC semiconductor device with a chip 2 containing a SiC single crystal. The chip 2 can be referred to as a "SiC chip" or a "semiconductor chip".

[0015] In this embodiment, chip 2 is constructed from a single-crystal SiC crystal, which is a hexagonal crystal, and is formed in a rectangular cuboid shape. The hexagonal SiC single-crystal has several polytypes, including a 2H (hexagonal) SiC single-crystal, a 4H SiC single-crystal, a 6H SiC single-crystal, etc. This embodiment provides an example in which chip 2 is constructed from the 4H SiC single-crystal, but chip 2 could instead be constructed from a different polytype.

[0016] Chip 2 has a first main surface 3 on one side, a second main surface 4 on another side, and first to fourth side surfaces 5A to 5D that connect the first main surface 3 and the second main surface 4. In a plan view, viewed from a vertical direction Z (hereinafter referred to simply as the "plan view"), the first main surface 3 and the second main surface 4 are each rectangular. The vertical direction Z is also a thickness direction of Chip 2 and a normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 can be square or rectangular in plan view.

[0017] The first main surface 3 and the second main surface 4 are preferably formed by c-planes of the SiC single crystal. In this case, the first main surface 3 is preferably formed by a silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 is formed by a carbon plane ((000-1) plane) of the SiC single crystal.

[0018] The first face surface 5A and the second face surface 5B extend in a first direction X along the first principal surface 3 and face each other in a second direction Y, which intersects the first direction X along the first principal surface 3. In particular, the second direction Y is orthogonal to the first direction X. The third face surface 5C and the fourth face surface 5D extend in the second direction Y and face each other in the first direction X.

[0019] In the following description, one side in the first direction X refers to the side of the third face surface 5C, and the other side in the first direction X refers to the side of the fourth face surface 5D. Similarly, one side in the second direction Y refers to the side of the first face surface 5A, and the other side in the second direction Y refers to the side of the second face surface 5B. In this embodiment, the first direction X is an m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is an a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X can instead be the a-axis direction of the SiC single crystal, and the second direction Y can instead be the m-axis direction of the SiC single crystal.

[0020] Chip 2 (the first main surface 3 and the second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction with respect to the c-plane of the SiC single crystal. That is, a c-axis (the (0001) axis) of the SiC single crystal is inclined by exactly the off angle from the vertical axis in the off direction. The c-plane of the SiC single crystal is also inclined by exactly the off angle with respect to the horizontal plane.

[0021] The off-direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The off-angle can be greater than 0° and less than 10°. The off-angle can have a value that falls within at least one of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0022] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in a range of 4° ± 0.1°. This description does not preclude an embodiment in which the off-angle is 0° (that is, an embodiment in which the first principal surface 3 is exactly a just surface or an exact surface with respect to the c-plane).

[0023] The semiconductor device 1 comprises a first n-type semiconductor region 6, which is formed in a region (surface layer section) within the chip 2 on the side of the first main surface 3. The first semiconductor region 6 can be referred to as a "drift region," a "drain-drift region," a "drain region," etc. A drain potential, a high potential (first potential), is applied to the first semiconductor region 6. The first semiconductor region 6 is formed in a layer shape that extends along the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 consists of an epitaxial layer (in particular, a SiC epitaxial layer).

[0024] The semiconductor device 1 comprises a second n-type semiconductor region 7, which is formed in a region (surface layer section) within the chip 2 on the side of the second main surface 4. A drain potential is applied to the second semiconductor region 7. The second semiconductor region 7 can be referred to as a "drain region," etc. The second semiconductor region 7 has a higher n-type defect concentration than that of the first semiconductor region 6 and is electrically connected to the first semiconductor region 6 within the chip 2.

[0025] The second semiconductor region 7 is formed in a layered form extending along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 consists of a semiconductor substrate (in particular, a SiC substrate). That is, the chip 2 has a laminated structure comprising the semiconductor substrate and the epitaxial layer. The second semiconductor region 7 has a greater thickness than the thickness of the first semiconductor region 6.

[0026] The semiconductor device 1 comprises an active region 8, which is defined or set within the chip 2. The active region 8 is a region having a component structure (transistor structure Tr) in which an output current (drain current) is generated. The active region 8 is defined in an inner section of the chip 2 at intervals from the peripheral edges (the first to fourth face surfaces 5A to 5D) of the chip 2 in plan view. The active region 8 is defined in a polygonal shape (in this embodiment, a quadrilateral shape) having four sides parallel to the peripheral edges of the chip 2 in plan view. The area of ​​the active region 8 is preferably 50% or more and 90% or less than the area of ​​the first main surface 3.

[0027] The semiconductor device 1 comprises an outer edge region 9, which is defined in the chip 2 outside the active region 8. The outer edge region 9 is located in a region between the peripheral edges of the chip 2 and the active region 8 in plan view. The outer edge region 9 extends in a band shape along the active region 8 and is defined as a polygonal ring shape (in this embodiment, a quadrilateral ring shape) that surrounds the active region 8 in plan view.

[0028] The semiconductor device 1 comprises a plurality of p-type body regions 20, which are formed in a surface layer section of the first main surface 3 in the active region 8. A source potential is applied to the plurality of body regions 20 as a low potential (second potential), which differs from a high potential (first potential). The plurality of body regions 20 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. That is, the plurality of body regions 20 are arranged in a strip shape extending in the second direction Y.

[0029] The majority of body regions 20 are formed at intervals from a lower section of the first semiconductor region 6 in the direction of the first main surface 3 and face the second semiconductor region 7 across a portion of the first semiconductor region 6. The majority of body regions 20 are preferably formed at intervals from a middle section of the first semiconductor region 6 in the direction of the first main surface 3. The majority of body regions 20 are exposed from the first main surface 3.

[0030] The semiconductor device 1 comprises an outer p-type body region 21, which is formed in the surface layer section of the first main surface 3 in the outer edge region 9. The outer body region 21 preferably has a p-type defect concentration that is substantially equal to the p-type defect concentration of the body region 20. Of course, the p-type defect concentration of the outer body region 21 can be lower than the p-type defect concentration of the body region 20, or it can be higher than the p-type defect concentration of the body region 20.

[0031] The outer body region 21 is formed at intervals from the peripheral edges (the first to fourth side surfaces 5A to 5D) of the first main surface 3 in the direction of the active region 8 and extends in a band shape along the active region 8. The outer body region 21 has a section that extends in a band shape in the first direction X and a section that extends in a band shape in the second direction Y, and delimits the active region 8 from a plurality of directions.

[0032] In this embodiment, the outer body region 21 surrounds the active region 8 in plan view and is delimited in a polygonal ring-shaped form (in this embodiment, a quadrilateral ring-shaped form) that has four sides parallel to the peripheral edges of the first main surface 3. That is, the outer body region 21 forms a boundary section between the active region 8 and the outer edge region 9. The outer body region 21 can have an edge or boundary section that connects the section extending in the first direction X and the section extending in the second direction Y in plan view in an arc-shaped form (preferably a quarter-circle arc shape) (see Fig. 4).

[0033] The outer body region 21 has an inner edge segment on the side of the active region 8 and an outer edge segment on the side of the peripheral edge of the first principal surface 3. The inner edge segment of the outer body region 21 is connected to the majority of body regions 20 in the segment extending in the first direction X. Thus, the outer body region 21 is fixed at the same potential as the majority of body regions 20.

[0034] The outer body region 21 preferably has a greater width than the width of the body region 20. The width of the body region 20 is a width in a direction orthogonal to a direction of extension (that is, the first direction X). The width of the outer body region 21 is a width in a direction orthogonal to the direction of extension. Of course, the width of the outer body region 21 can be substantially equal to the width of the body region 20, or it can be less than the thickness or width of the body region 20.

[0035] The ratio of the width of the outer body region 21 to the width of the body region 20 can be 10 or more and 50 or less. The width ratio is preferably 20 or more and 40 or less.

[0036] The outer body region 21 is formed at a distance from the lower section of the first semiconductor region 6 in the direction of the first main surface 3 and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. The outer body region 21 is preferably formed at a distance from the middle section of the first semiconductor region 6 in the direction of the first main surface 3. The outer body region 21 is exposed from the first main surface 3.

[0037] The outer body region 21 preferably has a thickness (depth) that is essentially equal to the thickness (depth) of the body region 20. Of course, the thickness of the outer body region 21 can be less than the thickness of the body region 20, or it can be greater than the thickness of the body region 20.

[0038] With reference to the Fig. In the embodiment 6 to 9, the semiconductor device 1 comprises a plurality of n-type surface layer drift regions 22 formed in the surface layer portion of the first main surface 3. In this embodiment, each of the plurality of surface layer drift regions 22 is formed from a portion of the first semiconductor region 6. Naturally, the plurality of surface layer drift regions 22 can have a higher n-type defect concentration than the n-type defect concentration of the first semiconductor region 6, or they can have a lower n-type defect concentration than the n-type defect concentration of the first semiconductor region 6.

[0039] The majority of surface layer drift regions 22 are each delimited in a region between the majority of body regions 20 that are adjacent in the first direction X. In particular, the majority of surface layer drift regions 22 are each delimited by the majority of body regions 20 and the outer body region 21 in the surface layer section of the first main surface 3. The majority of surface layer drift regions 22 are arranged in intervals in the first direction X and are each formed in a band shape extending in the second direction Y. That is, the majority of surface layer drift regions 22 are formed in a strip shape extending in the second direction Y.

[0040] The semiconductor device 1 comprises an n-type source region 23, which is formed in surface layer sections of the majority of body regions 20. The source region 23 has a higher n-type defect concentration than the n-type defect concentration of the first semiconductor region 6. A source potential is applied to the source region 23.

[0041] The semiconductor device 1 comprises a plurality of p-type contact regions 25, each formed in the surface layer portion of the plurality of body regions 20 within the active region 8. The contact region 25 can be referred to as a "back-gate region". A source potential is applied to the plurality of contact regions 25. The contact region 25 has a higher p-type defect concentration than the p-type defect concentration of the body region 20.

[0042] With reference to the Fig. 5 and Fig. 6. Each body region 20 comprises a plurality of first sections 10 and a plurality of second sections 11 alternating in the second direction Y. A clear boundary need not be formed between the first section 10 and the second section 11. In the Fig. 5 and Fig. 6 The boundary between the first section 10 and the second section 11 is marked for clarity by an alternating long and short dashed line. As in the Fig. 5 and Fig. As illustrated in Figure 6, the first section 10 and the second section 11 can have the same length in the second direction Y, or they can have different lengths in the second direction Y. For example, in the second direction Y, the first section 10 can be longer than the second section 11, or the first section 10 can be shorter than the second section 11.

[0043] The majority of contact areas 25 are arranged at intervals for each of the first sections 10, skipping each of the second sections 11 in the second direction Y. In the body region 20, the contact area 25 and areas on either side of the contact area 25 in the first direction X can be the first section 10. The second section 11 can be an area between the majority of contact areas 25 that are adjacent to each other in the second direction Y.

[0044] Each contact area 25 extends in a band shape along the extension direction of the body area 20 (second direction Y). The contact area 25 is formed at a distance from the outer body area 21 in the second direction Y. That is, the contact area 25 is not formed within the outer body area 21. The contact area 25 is formed at a distance from a lower section of the body area 20 in the direction of the first main surface 3 and faces the first semiconductor area 6 across a portion of the body area 20. Each contact area 25 is formed at a distance from both peripheral edges on one side and the other side of the body area 20 in the first direction X. In this embodiment, the contact area 25 is formed in a central section of the body area 20 in the first direction X.

[0045] By forming the contact area 25, the source area 23 is divided into a plurality of source areas 24A and 24B in the first section 10. In other words, a contact area 25 is interposed in a region between the first source area 24A and the second source area 24B in the surface layer section of the corresponding body area 20. Each contact area 25 is sandwiched between the first source area 24A and the second source area 24B in the first direction X.

[0046] The plurality of source regions 24A and 24B in the surface layer section of each body region 20 comprises a first source region 24A, positioned on one side in the first direction X, and a second source region 24B, positioned on the other side in the first direction X. In this embodiment, a first source region 24A is formed on one end side of the body region 20 in the first direction X, and a second source region 24B is formed on the other end side of the body region 20.

[0047] The first source region 24A is formed at a distance from one end of the body region 20 to the other end and extends in a band shape along the extension direction of the body region 20. The first source region 24A is formed at a distance from the lower section of the body region 20 towards the first main surface 3 and faces the first semiconductor region 6 over a part of the body region 20.

[0048] The second source region 24B is located at a distance from the first source region 24A towards the opposite end of the body region 20. The second source region 24B is located at a distance from the opposite end of the body region 20 towards one end and extends in a band shape along the direction of extension of the body region 20. The second source region 24B is located at a distance from the lower section of the body region 20 towards the first main surface 3 and faces the first semiconductor region 6 across a portion of the body region 20.

[0049] With reference to Fig. 6 the contact area 25 comprises a first section 12, which extends in a band shape in the second direction Y, and a plurality of projection sections 13, which project outwards from the first section 12 in the first direction X.

[0050] The first section 12 intersects the first section 10 of body region 20 in the second direction Y and has a terminal section at a boundary position between the first section 10 and the second section 11. Depending on its planar shape, the first section 12 may also be referred to by a different name. For example, as in Fig. Figure 6 illustrates that if a shape assumed or formed by excluding the projecting section 13 (a shape in which sections vertically opposite each other across the projecting section 13 in the second direction Y are connected by a dashed line 17) is a band shape in plan view, the first section 12 can be described as a band-shaped section. The width (first width W1) of the first section 12 can be, for example, 0.2 µm or more and 0.6 µm or less. The first width W1 can be constant or substantially constant in or along the second direction Y.

[0051] In this embodiment, the plurality of projection sections 13 can comprise a pair of projection sections 14A and 14B, which project from a center of the first section 12 in the second direction Y to both sides in the first direction X. That is, a projection section 13 is formed on one side and on the other side of the first section 12 in the first direction X, respectively. In this embodiment, the projection section 13 that projects toward the first source region 24A is a first projection section 14A, and the projection section 13 that projects toward the second source region 24B is a second projection section 14B. The first projection section 14A and the second projection section 14B project from the same position of the first section 12 to opposite sides.

[0052] Each of the projecting sections 14A and 14B can have a polygonal shape in plan view, projecting with respect to the first section 12 and having one or more vertex sections 49. In this embodiment, each of the projecting sections 14A and 14B is formed in a triangular shape in plan view. In the contact area 25, the vertex section 49 has a rounded shape.

[0053] The pair of projecting sections 14A and 14B can have an overall shape of a rhombus or a circle, projecting symmetrically on both sides relative to the first section 12 in plan view. The overall shape of the pair of projecting sections 14A and 14B can be a shape defined by an outline 15 of the pair of projecting sections 14A and 14B and an inner extension line 16 (virtual line) of the outline 15 to the inside of the contact area 25 (first section 12). Fig. Figure 6 illustrates a pattern in which the overall shape of the pair of projecting sections 14A and 14B is a rhombus. In this embodiment, the total second width W2 of the pair of projecting sections 14A and 14B, from an end section in the first direction X of the first projecting section 14A to an end section in the first direction X of the second projecting section 14B, can be 1.2 µm or more and 1.6 µm or less.

[0054] Additionally, in this embodiment, the width WS of each of the first source region 24A and the second source region 24B on both sides of the first section 12 in the first direction X can be greater than the total second width W2 of the pair of protruding sections 14A and 14B. The width WS can be, for example, 2 µm or more and 4 µm or less.

[0055] The semiconductor device 1 comprises a plurality of p-type channel regions 26 and 27 formed in the surface layer section of the first main surface 3. The plurality of channel regions 26 and 27 are delimited in regions between end sections of the plurality of body regions 20 (the plurality of surface layer drift regions 22) and peripheral edges of the source region 23, respectively, in the surface layer sections of the plurality of body regions 20. In this embodiment, the plurality of channel regions 26 and 27 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. That is, the plurality of channel regions 26 and 27 are arranged in a strip shape extending in the second direction Y.

[0056] The plurality of channel regions 26 and 27 comprises a plurality of first channel regions 26 and a plurality of second channel regions 27. The plurality of first channel regions 26 is formed in a region on the side of the plurality of first source regions 24A and forms a current path extending in a horizontal direction. The plurality of second channel regions 27 is formed in a region on the side of the plurality of second source regions 24B and forms a current path extending in a horizontal direction.

[0057] The semiconductor device 1 comprises a plurality of gate structures 30 of a planar electrode type, arranged on the first main surface 3 in the active region 8. The plurality of gate structures 30 are spaced apart in the first direction X and are each formed in a band shape extending in the second direction Y. That is, the plurality of gate structures 30 are arranged in a strip shape extending in the second direction Y. The extension direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.

[0058] Each gate structure 30 is arranged on at least one channel region 26 or 27. In this embodiment, each gate structure 30 is arranged such that it extends over two adjacent body regions 20, specifically over a surface layer drift region 22, and covers the majority of channel regions 26 and 27. In particular, each gate structure 30 is arranged such that it extends over the source region 23 on the side of one body region 20 and the source region 23 on the side of the other body region 20, and covers the surface layer drift region 22, the source region 23 (the first source region 24A and the second source region 24B), the first channel region 26, and the second channel region 27.

[0059] The following describes a configuration of a gate structure 30. The gate structure 30 has a laminated structure comprising an insulating film 31 and a gate electrode 32. The gate structure 30 does not have an insulating sidewall structure (spacer) on one side of the gate electrode 32. The insulating film 31 can comprise at least one silicon oxide film, one silicon nitride film, and one silicon oxynitride film. In this embodiment, the insulating film 31 has a single-layer structure formed from the silicon oxide film. The insulating film 31 particularly preferably comprises a silicon oxide film formed from an oxide of the chip 2.

[0060] The insulating film 31 covers the first main surface 3 in a film form and is arranged on at least one channel region 26 or 27. In this embodiment, the insulating film 31 is arranged such that it extends over two body regions 20 that are adjacent to each other, specifically over a surface layer drift region 22, and covers the majority of channel regions 26 and 27.

[0061] In particular, the insulation film 31 is arranged such that it extends over the source area 23 on the side of one body area 20 and the source area 23 on the side of the other body area 20 and covers the surface layer drift area 22, the source area 23 (the first source area 24A and the second source area 24B), the first channel area 26 and the second channel area 27.

[0062] In the first section 10, the insulating film 31 partially covers the first source area 24A at a distance from the contact area 25, exposing part of the first source area 24A and the contact area 25 from the first main surface 3. In the first section 10, the insulating film 31 partially covers the second source area 24B at a distance from the contact area 25, exposing part of the second source area 24B and the contact area 25 from the first main surface 3. In the second section 11, the insulating film 31 partially covers the source area 23, exposing part of the source area 23 from the first main surface 3.

[0063] The thickness of the insulating film 31 can be 10 nm or more and 150 nm or less. The thickness of the insulating film 31 can be a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less. The thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.

[0064] The gate electrode 32 is arranged on the insulating film 31 and faces at least one channel region 26 or 27 across the insulating film 31. A gate potential is applied to the gate electrode 32 as a control potential. The gate electrode 32 controls the inversion and non-inversion of at least one channel region 26 or 27 in response to the gate potential.

[0065] The gate electrode 32 contains a conductive semiconductor polycrystal. The gate electrode 32 can contain either p-type polysilicon, n-type polysilicon, or both. The conductivity type of the gate electrode 32 is selected according to the required gate threshold voltage. The gate electrode 32 can be referred to as a "polysilicon gate," "poly gate," etc.

[0066] The gate electrode 32 is formed in a band shape extending in the second direction Y. That is, the direction of extension of the gate electrode 32 coincides with the off-direction of the SiC single crystal. In this embodiment, the gate electrode 32 is formed at intervals inwards from both end sections of the insulating film 31 in the first direction X and exposes both end sections of the insulating film 31.

[0067] In particular, the gate electrode 32 is arranged such that it extends over the source area 23 on the side of one body area 20 and the source area 23 on the side of the other body area 20, and is oriented towards the surface layer drift area 22, the source area 23 (the first source area 24A and the second source area 24B), the first channel area 26 and the second channel area 27 across the insulating film 31.

[0068] The gate electrode 32 comprises an electrode surface 33, a first side wall 34 on one side in the first direction X, and a second side wall 35 on the other side in the first direction X. The electrode surface 33 extends along the insulating film 31 (first main surface 3). The electrode surface 33 can extend substantially parallel to the insulating film 31 (first main surface 3).

[0069] The first side wall 34 is formed at a distance from one end section to the other end section of the insulating film 31 in the first direction X and extends in the vertical direction Z. The second side wall 35 is formed at a distance from the other end section to one end section of the insulating film 31 in the first direction X and extends in the vertical direction Z.

[0070] The first side wall 34 and the second side wall 35 can extend perpendicular to the insulating film 31. That is, the gate electrode 32 can be configured in a square shape (flat rectangular shape) in cross-sectional view. The first side wall 34 and the second side wall 35 can be inclined obliquely towards the electrode surface 33. That is, the gate electrode 32 can be configured in a tapered shape (preferably an isosceles trapezoidal shape) in cross-sectional view.

[0071] The width of the gate structure 30 can be 1 µm or more and 10 µm or less. The width of the gate structure 30 is a width in a direction orthogonal to the direction of extension (that is, the first direction X). The width of the gate structure 30 is preferably 1 µm or more and 5 µm or less.

[0072] The thickness of the gate structure 30 can be 0.1 µm or more and 2.0 µm or less. Preferably, the thickness of the gate structure 30 is 0.2 µm or more and 1.0 µm or less.

[0073] With reference to the Fig. 4, Fig. 5 and Fig. In the semiconductor device 1, a p-type termination region 45 is formed on the first main surface 3 in the outer edge region 9. The termination region 45, which can be referred to as a "well" or "trough" region, a "terminal well region", etc., can have a p-type defect concentration that is substantially equal to the p-type defect concentration of the outer body region 21. The p-type defect concentration of the termination region 45 can be higher than the p-type defect concentration of the outer body region 21, or it can be lower than the p-type defect concentration of the outer body region 21.

[0074] The connection area 45 is formed in a region between the peripheral edges of the first main surface 3 and the outer body region 21, at intervals inwards from the peripheral edges of the first main surface 3. The connection area 45 extends in a band shape along the outer body region 21 in plan view. The connection area 45 has a section that extends in a band shape in the first direction X and a section that extends in a band shape in the second direction Y in plan view, and delimits the active region 8 from a plurality of directions.

[0075] In this embodiment, the connection area 45 surrounds the outer body region 21 in plan view and is delimited in a polygonal ring-shaped form (a quadrilateral ring-shaped form in this embodiment) which has four sides parallel to the peripheral edges of the first main surface 3. The connection area 45 can have an edge section that connects the section extending in the first direction X and the section extending in the second direction Y in plan view in an arc-shaped form (preferably a quarter-circle arc shape) (see Fig. 4).

[0076] The connection area 45 is formed at a distance from the lower section of the first semiconductor area 6 towards the first main surface 3 and faces the second semiconductor area 7 across a portion of the first semiconductor area 6. The connection area 45 is preferably formed at a distance from the middle section of the first semiconductor area 6 towards the first main surface 3. The connection area 45 can have a thickness (depth) that is substantially equal to the thickness (depth) of the outer body area 21. The thickness of the connection area 45 can be greater than the thickness of the outer body area 21 or it can be less than the thickness of the outer body area 21.

[0077] The connection area 45 has an inner edge section on the side of the active area 8 and an outer edge section on the side of the peripheral edge of the first main surface 3. The inner edge section of the connection area 45 is connected to the outer edge section of the outer body area 21. As a result, the connection area 45 is fixed at the same potential as the outer body area 21 and is electrically connected to the plurality of body areas 20 through the outer body area 21. In this embodiment, the inner edge section of the connection area 45 is connected to the outer edge section of the outer body area 21 over its entire circumference.

[0078] The connection area 45 (inner edge section) has an overlap area 46 that overlaps the outer edge section of the outer body region 21. The overlap area 46 is a high-concentration area that encompasses both the outer edge section of the outer body region 21 and the inner edge section of the connection area 45. That is, the overlap area 46 encompasses both the p-type defect of the outer body region 21 and the p-type defect of the connection area 45 and has a p-type defect concentration that is higher than both the p-type defect concentration of the outer body region 21 and the p-type defect concentration of the connection area 45.

[0079] The overlap area 46 extends in a band shape along the outer body region 21 in plan view. The overlap area 46 has a section extending in a band shape in the first direction X and a section extending in a band shape in the second direction Y in plan view, and delimits the active region 8 from a plurality of directions. In this embodiment, the overlap area 46 is delimited in a polygonal ring shape (a quadrilateral ring shape in this embodiment) that has four sides parallel to the peripheral edges of the first main surface 3. The width of the overlap area 46 is preferably greater than the width of the body region 20. Of course, the width of the overlap area 46 cannot be greater than the width of the body region 20.

[0080] The semiconductor device 1 can have a p-type well region (46) with a relatively high concentration instead of the overlap region 46. In this case, the well region (46) has a p-type defect concentration that is higher than both the p-type defect concentration of the outer body region 21 and the p-type defect concentration of the terminal region 45. The well region (46) can be located either in a surface layer section of the outer body region 21, in a surface layer section of the terminal region 45, or in both.

[0081] The semiconductor device 1 comprises at least one (preferably two or more and twenty or fewer) p-type field region(s) 47, which is formed in the surface layer section of the first main surface 3 in the outer edge region 9. The number of field regions 47 is typically three or more and eight or fewer. In this embodiment, the semiconductor device 1 comprises three field regions 47. The plurality of field regions 47 is in an electrically suspended state and releases an electric field in the chip 2 at a peripheral edge section of the first main surface 3. The number, spacing, width, depth, p-type impurity concentration, etc., of the field regions 47 are arbitrary and can assume different values ​​according to the electric field to be released.

[0082] Field area 47 may have a p-type defect concentration that is essentially equal to the p-type defect concentration of body area 20 (connecting area 45). The p-type defect concentration of field area 47 may be higher than the p-type defect concentration of body area 20 (connecting area 45) or it may be lower than the p-type defect concentration of body area 20 (connecting area 45).

[0083] The majority of field areas 47 are formed in a region between the peripheral edges of the first main surface 3 and the active region 8, at intervals inwards from the peripheral edges of the first main surface 3. Specifically, the majority of field areas 47 are formed in a region between the peripheral edges of the first main surface 3 and the outer body region 21. More precisely, the majority of field areas 47 are arranged in a region between the peripheral edges of the first main surface 3 and the connection region 45, at intervals from the connection region 45 in the direction of the peripheral edges of the first main surface 3.

[0084] The majority of field areas 47 are formed in a band shape extending along the active area 8 (connection area 45) in plan view. Each of the majority of field areas 47 has a section extending in a band shape in the first direction X and a section extending in a band shape in the second direction Y. In this embodiment, the majority of field areas 47 are formed in a polygonal ring shape (in this embodiment, a quadrilateral ring shape) that surrounds the active area 8 (connection area 45) in plan view. The majority of field areas 47 may have an edge section that connects the section extending in the first direction X and the section extending in the second direction Y in an arc shape (preferably a quarter-circle arc shape) (see Fig. 4).

[0085] The majority of field regions 47 are formed at intervals from the lower section of the first semiconductor region 6 towards the first main surface 3 and are oriented towards the second semiconductor region 7 across a portion of the first semiconductor region 6. The majority of field regions 47 are preferably formed at intervals from the middle section of the first semiconductor region 6 towards the first main surface 3.

[0086] With reference to Fig. In embodiment 10, the semiconductor device 1 comprises an outer peripheral insulating film 51 that covers the first main surface 3 in the outer edge region 9. The outer peripheral insulating film 51 can comprise at least one silicon oxide film, one silicon nitride film, and one silicon oxynitride film. In this embodiment, the outer peripheral insulating film 51 has a single-layer structure formed from the silicon oxide film. The outer peripheral insulating film 51 particularly preferably comprises a silicon oxide film formed from an oxide of the chip 2. The outer peripheral insulating film 51 is preferably made of the same type of insulating material as the insulating material of the insulating film 31. The outer peripheral insulating film 51 preferably has a thickness that is substantially equal to the thickness of the insulating film 31.

[0087] The outer peripheral insulating film 51 covers the first main surface 3 in a film form in the outer edge region 9. The outer peripheral insulating film 51 jointly covers the outer body region 21, the connection region 45, and the plurality of field regions 47. The outer peripheral insulating film 51 is connected to the plurality of insulating films 31 on the side of the active region 8. In particular, the outer peripheral insulating film 51 is integrally formed with the plurality of insulating films 31 and forms an insulating film with the plurality of insulating films 31.

[0088] With reference to the Fig. 4, Fig. 5 and Fig. The semiconductor device 1 comprises a gate wiring 52, which is arranged on the first main surface 3 in the outer edge region 9. The semiconductor device 1 has no insulating sidewall structure (spacer) on one side of the gate wiring 52. The gate wiring 52 is selectively routed on the first main surface 3 and has a section that extends in a different direction than the majority of gate electrodes 32. The gate wiring 52 is connected to the majority of gate electrodes 32 and applies a gate signal to the majority of gate electrodes 32. The gate wiring 52 can be referred to as a "polysilicon gate wiring", a "poly gate wiring", a "second gate electrode", etc.

[0089] The gate wiring 52 contains a conductive semiconductor polycrystal. The gate wiring 52 can contain either p-type polysilicon or n-type polysilicon, or both. The gate wiring 52 preferably has the same conductivity type as the gate electrode 32. The conductivity type of the gate wiring 52 is matched to that of the gate electrode 32.

[0090] The gate wiring 52 is arranged on the outer peripheral insulating film 51 in the outer edge region 9. Specifically, the gate wiring 52 is arranged on a section of the outer peripheral insulating film 51 that covers the outer body region 21 and faces the outer body region 21 across the outer peripheral insulating film 51. The gate wiring 52 is formed at intervals from the peripheral edges of the first main surface 3 in the direction of the active region 8 and extends in a band shape along the active region 8. The gate wiring 52 has a section extending in a band shape in the first direction X and a section extending in a band shape in the second direction Y in plan view, and delimits the active region 8 from a plurality of directions.

[0091] In this embodiment, the gate wiring 52 surrounds the active area 8 in plan view and is bounded in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the peripheral edges of the first main surface 3. The gate wiring 52 can have an ended or continuous form. In this embodiment, the gate wiring 52 extends in a ribbon shape (a ring shape in this embodiment) along the outer body area 21 in plan view and faces the outer body area 21 across the outer peripheral insulation film 51 over its entire area in a lamination direction. The gate wiring 52 can have an edge orhave a boundary section that connects the section extending in the first direction X and the section extending in the second direction Y in plan view in an arc-shaped form (preferably a quarter-circle arc shape) (see . Fig. 4).

[0092] The gate wiring 52 is designed to be narrower than the outer body region 21 in plan view and is arranged above the outer body region 21 at intervals from the inner and outer edge sections of the outer body region 21. That is, in this embodiment, the majority of gate electrodes 32 extend above the outer body region 21, and the gate wiring 52 is connected to the majority of gate electrodes 32 above the outer body region 21.

[0093] The width of the gate wiring 52 is preferably greater than the width of the gate electrode 32. The width of the gate wiring 52 is a width in a direction orthogonal to its extension direction. Naturally, the width of the gate wiring 52 cannot be greater than the width of the gate electrode 32. The width of the gate wiring 52 can be greater than the width of the outer body region 21. The thickness of the gate wiring 52 is preferably substantially equal to the thickness of the gate electrode 32.

[0094] The gate wiring 52 comprises a wiring surface 53, a first wiring sidewall 54 on the inner edge side, and a second wiring sidewall 55 on the outer edge side. The wiring surface 53 extends along the outer peripheral insulating film 51 (first main surface 3). The wiring surface 53 can extend substantially parallel to the outer peripheral insulating film 51 (first main surface 3). The first wiring sidewall 54 extends in the vertical direction Z on the outer peripheral insulating film 51, and the second wiring sidewall 55 extends in the vertical direction Z on the outer peripheral insulating film 51.

[0095] The first wiring side wall 54 is connected to the plurality of gate electrodes 32 (the first side wall 34 and the second side wall 35) in a section extending in the first direction X. That is, the gate wiring 52 has a plurality of sections connected to the plurality of gate electrodes 32 in a T-shape. Thus, the gate wiring 52 is fixed at the same potential as the plurality of gate electrodes 32.

[0096] The first wiring sidewall 54 and the second wiring sidewall 55 can extend perpendicular to the outer peripheral insulation film 51. That is, the gate wiring 52 can be configured in a square shape (flat rectangular shape) in cross-sectional view. The first wiring sidewall 54 and the second wiring sidewall 55 can be inclined obliquely towards the wiring surface 53. That is, the gate wiring 52 can be configured in a tapered shape (preferably an isosceles trapezoidal shape) in cross-sectional view.

[0097] The semiconductor device 1 comprises an intermediate insulating film 70 that covers the first primary surface 3. The intermediate insulating film 70 can be referred to as an "intermediate insulating film", an "intermediate insulating film", etc. The intermediate insulating film 70 has an insulating surface 71 that extends along the first primary surface 3. The intermediate insulating film 70 jointly covers the active region 8 and the outer edge region 9 on the first primary surface 3.

[0098] The interlayer film 70 covers the majority of gate structures 30 in the active region 8. The interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32 with respect to each gate structure 30. That is, the interlayer film 70 has a section that directly covers the electrode surface 33, the first side wall 34, and the second side wall 35 of the gate electrode 32.

[0099] The interlayer film 70 covers the outer body region 21, the terminal region 45, and the majority of field regions 47 across the outer peripheral insulating film 51 in the outer edge region 9. The interlayer film 70 directly covers both the outer peripheral insulating film 51 and the gate wiring 52. That is, the interlayer film 70 has a section that directly covers the wiring surface 53, the first wiring side wall 54, and the second wiring side wall 55 of the gate wiring 52. In this embodiment, the interlayer film 70 extends continuously through the first to fourth side surfaces 5A to 5D. The interlayer film 70 can extend inward from the first to fourth side surfaces 5A to 5D at intervals, exposing the peripheral edge section (first semiconductor region 6) of the first main surface 3.

[0100] With reference to the Fig. In this embodiment, the intermediate film 70 has a laminated structure comprising a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film), which are laminated in that order starting from the side of the first main surface 3. That is, the intermediate film 70 has the insulating surface 71 formed by the second oxide film 73. The first oxide film 72 has a single-layer structure formed from the silicon oxide film, which is not doped with any impurity. The first oxide film 72 can be referred to as an NSG film (undoped silicate glass film).

[0101] The first oxide film 72 covers both the active region 8 and the outer edge region 9. The first oxide film 72 covers the majority of gate structures 30 in the active region 8. The first oxide film 72 covers both the insulating film 31 and the gate electrode 32 in a film form with respect to each gate structure 30.

[0102] The first oxide film 72 comprises a first covering section 74, a second covering section 75, and a third covering section 76. The first covering section 74 extends in a film-like form in the horizontal direction along the insulating film 31 (first main surface 3) and has a section that is in contact with the first side wall 34 (second side wall 35) of the gate electrode 32. In this embodiment, the first covering section 74 (first oxide film 72) has a lesser thickness than the thickness of the gate electrode 32 and covers the insulating film 31 at a distance from a height position of the electrode surface 33 of the gate electrode 32 in the direction of the insulating film 31.

[0103] The second covering section 75 extends from the first covering section 74 towards the electrode surface 33 in the lamination direction and directly covers the first side wall 34 (second side wall 35) in a film form.

[0104] The third covering section 76 extends from the second covering section 75 towards the electrode surface 33 and forms a film in the horizontal direction along the electrode surface 33. The third covering section 76 directly covers an entire area of ​​the electrode surface 33 between the first side wall 34 and the second side wall 35. The third covering section 76 preferably forms an arc-shaped corner section, which is curved in an arc shape, together with the second covering section 75 in a section that covers a corner section of the gate electrode 32. The arc-shaped corner section may have a center of curvature on the side of the gate electrode 32.

[0105] The first oxide film 72 covers the outer body region 21, the connection region 45 and the majority of field regions 47 across the outer peripheral insulation film 51 in the outer edge region 9. The first oxide film 72 covers the gate wiring 52 in the outer edge region 9.

[0106] The second oxide film 73 can have a single-layer structure formed from a phosphorus-containing silicon oxide film, or a laminated structure comprising a phosphorus-containing silicon oxide film. The phosphorus-containing silicon oxide film may contain boron. The phosphorus-containing silicon oxide film can be referred to as a PSG film (phosphosilicate glass film). The silicon oxide film containing both phosphorus and boron can be referred to as a BPSG film (boron-phosphosilicate glass film).

[0107] The second oxide film 73 can have a single-layer structure formed from a PSG film or a BPSG film laminated onto the first oxide film 72. The second oxide film 73 can have a laminated structure comprising a PSG film laminated onto the first oxide film 72 and a BPSG film laminated onto the PSG film. The second oxide film 73 can have a laminated structure comprising a BPSG film laminated onto the first oxide film 72 and a PSG film laminated onto the BPSG film. In this embodiment, the second oxide film 73 has a single-layer structure formed, for example, from a PSG film.

[0108] The second oxide film 73 covers the first oxide film 72 in a film form and together cover the active region 8 and the outer edge region 9 over the first oxide film 72. The second oxide film 73 together covers the majority of gate structures 30 over the first oxide film 72 in the active region 8. In particular, the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film form over the first oxide film 72.

[0109] The second oxide film 73 comprises a first upper cover section 80 and a second upper cover section 81. The first upper cover section 80 covers the first cover section 74 of the first oxide film 72. The first upper cover section 80 covers the insulating film 31 over the first cover section 74 in a section that is positioned on the first cover section 74.

[0110] The first upper cover section 80 extends in a film form in the lamination direction along the second cover section 75 from above the first cover section 74 and covers the first side wall 34 (second side wall 35) of the gate structure 30 over the second cover section 75.

[0111] The second upper cover section 81 covers the third cover section 76 of the first oxide film 72. The second upper cover section 81 extends in a film-like form in the horizontal direction from the first upper cover section 80 along the third cover section 76 and covers the electrode surface 33 of the gate structure 30 over the third cover section 76. The second upper cover section 81 covers the entire area of ​​the electrode surface 33 over the third cover section 76 between the first side wall 34 and the second side wall 35. The second upper cover section 81 preferably forms an arc-shaped corner section, which is curved in an arc shape, together with the first upper cover section 80 in a section that covers the corner section of the gate wiring 52. The arc-shaped corner section may have a center of curvature on the side of the gate wiring 52.

[0112] The second oxide film 73 jointly covers the outer body region 21, the connection region 45, and the majority of field regions 47 over the outer peripheral insulation film 51 and the first oxide film 72 in the outer edge region 9. The second oxide film 73 covers the gate wiring 52 over the first oxide film 72 in the outer edge region 9.

[0113] The semiconductor device 1 comprises a plurality of source openings 90 formed in the interlayer film 70 in the active region 8. The plurality of source openings 90 are formed in regions on the sides of the plurality of gate electrodes 32, at intervals from the plurality of gate electrodes 32, and expose the first main surface 3 (chip 2). In particular, the plurality of source openings 90 are formed in regions between the plurality of gate electrodes 32 and penetrate the insulating film 31 and the interlayer film 70.

[0114] The majority of source openings 90 have wall surfaces that penetrate both the first oxide film 72 and the second oxide film 73 and are delimited by both the first oxide film 72 and the second oxide film 73. The majority of source openings 90 have opening ends that are delimited by arcuate corner sections of the intermediate film 70. The majority of source openings 90 each expose the corresponding majority of source regions 23 (the first source region 24A and the second source region 24B) and the contact region 25.

[0115] In this embodiment, the plurality of source openings 90 are formed at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. That is, the plurality of source openings 90 are formed in a strip shape extending in the second direction Y. The plurality of source openings 90 are formed at intervals in the second direction Y from the gate wiring 52. That is, the plurality of source openings 90 are formed in a region surrounded by the plurality of gate electrodes 32 and the gate wiring 52.

[0116] The majority of source openings 90 can be formed in an area between two gate structures 30 that are adjacent to each other in the first direction X. In this case, the majority of source openings 90 can be formed at intervals in a line in the second direction Y. Furthermore, in this case, each source opening 90 can be formed in a square shape, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, etc., in plan view.

[0117] The source opening 90 can have a width W of 0.2 µm or more and 3 µm or less. The width W of the source opening 90 is preferably 0.3 µm or more and 1 µm or less. The source opening 90 can have a depth D of 0.2 µm or more and 2 µm or less. The depth D of the source opening 90 is preferably 0.5 µm or more and 1 µm or less.

[0118] The source opening 90 preferably has an aspect ratio (D / W) of 0.3 or more and 3 or less. The aspect ratio D / W is defined by the ratio of the depth D of the source opening 90 to the width W of the source opening 90. The aspect ratio D / W is preferably 0.5 or more and 2 or less. The aspect ratio D / W is particularly preferably greater than 1. According to this configuration, the majority of gate structures 30 are arranged at close intervals or pitches.

[0119] The semiconductor device 1 comprises a plurality of source recesses 91 formed in sections of the first main surface 3, each exposed by the plurality of source openings 90. The semiconductor device 1 need not necessarily include the source recess 91. Therefore, a configuration without the source recess 91 can be used.

[0120] Each of the plurality of source recesses 91 has a planar shape that corresponds to the planar shape of the corresponding source opening 90 and is recessed from the first main surface 3 towards the second main surface 4. Each of the plurality of source recesses 91 is formed at a distance from the lower portion of the corresponding body region 20 towards the first main surface 3 and exposes the corresponding plurality of source regions 23 and the contact region 25. In particular, the plurality of source recesses 91 is formed at a distance from the lower portions of the corresponding plurality of source regions 23 (contact region 25) towards the first main surface 3.

[0121] The semiconductor device 1 comprises at least one (in this embodiment, a plurality of) outer opening(s) 92 formed in the interlayer film 70 in the outer edge region 9. The plurality of outer openings 92 are formed in a section of the interlayer film 70 that covers the terminal area 45. The plurality of outer openings 92 penetrate the interlayer film 70 and expose the terminal area 45. In this embodiment, the plurality of outer openings 92 are formed in a section of the interlayer film 70 that covers the overlap region 46 of the terminal area 45 and exposes the overlap region 46.

[0122] The majority of outer openings 92 can expose the outer body region 21 instead of or in addition to the connection region 45 (overlap region 46). The majority of outer openings 92 have wall surfaces that penetrate both the first oxide film 72 and the second oxide film 73 and are delimited by both the first oxide film 72 and the second oxide film 73. The majority of outer openings 92 have opening ends that are delimited by the arcuate corner sections of the intermediate layer film 70.

[0123] The majority of the outer openings 92 are formed at intervals along the connection area 45 (overlap area 46) (see Fig. 4 and Fig. 5) The majority of external openings 92 can be configured in a square, rectangular, hexagonal, circular, etc., shape in plan view. The majority of external openings 92 can be configured in a band shape extending along the connection area 45 (overlap area 46) in plan view. Similar to the source opening 90, the external opening 92 can have a length-to-width ratio (D / W) (preferably greater than 1).

[0124] The semiconductor device 1 can have a single external opening 92. The single external opening 92 can be formed in a band shape extending along the terminal area 45 (overlap area 46). The single external opening 92 can have a section extending in a band shape in the first direction X and a section extending in a band shape in the second direction Y in plan view.

[0125] The single outer opening 92 can be configured in a polygonal ring shape (a quadrilateral ring shape in this embodiment) with or without ends, having four sides parallel to the peripheral edges of the first main surface 3. The single outer opening 92 can have an edge section that connects the section extending in the first direction X and the section extending in the second direction Y in a plan view in accordance with the connection area 45 (overlap area 46) in an arc-shaped form (preferably a quarter-circle arc shape) (see Fig. 4).

[0126] The semiconductor device 1 comprises a plurality of outer recesses 93 formed in sections of the first main surface 3, each exposed by the plurality of outer openings 92. The semiconductor device 1 need not necessarily include the outer recess 93. Therefore, a configuration without the outer recess 93 can be used.

[0127] Each of the plurality of outer recesses 93 has a planar shape that matches the planar shape of the corresponding outer opening 92 and is recessed from the first main surface 3 towards the second main surface 4. The plurality of outer recesses 93 are formed at intervals from a lower section of the connection area 45 (overlap area 46) to the first main surface 3, each exposing the connection area 45 (overlap area 46). When the single outer opening 92 is formed, a single outer recess 93 is created that matches the planar shape of the single outer opening 92.

[0128] The semiconductor device 1 comprises at least one (in this embodiment, a plurality of) gate opening(s) 94, which is / are formed in the interlayer film 70 in the outer edge region 9. The plurality of gate openings 94 is formed in a section of the interlayer film 70 that covers the gate wiring 52. The plurality of gate openings 94 penetrates the interlayer film 70 and exposes the wiring surface 53 of the gate wiring 52.

[0129] The majority of gate openings 94 have wall surfaces that penetrate both the first oxide film 72 and the second oxide film 73 and are delimited by both the first oxide film 72 and the second oxide film 73. The majority of gate openings 94 have opening ends that are delimited by the arc-shaped corner sections of the intermediate layer film 70.

[0130] The majority of gate openings 94 are formed at intervals along the gate wiring 52 (see Fig. 4 and Fig. 5) The majority of gate openings 94 can be configured in a square, rectangular, hexagonal, circular, etc., shape in plan view. The majority of gate openings 94 can be configured in a band shape extending along the gate wiring 52 in plan view. Similar to the source opening 90, the gate opening 94 can have a length-to-width ratio (preferably greater than 1).

[0131] The semiconductor device 1 can have a single gate opening 94. The single gate opening 94 can be formed in a band shape extending along the gate wiring 52. The single gate opening 94 can have a section extending in a band shape in the first direction X and a section extending in a band shape in the second direction Y in plan view.

[0132] The single gate opening 94 can be configured in a polygonal ring shape (a quadrilateral ring shape in this embodiment) with or without ends, having four sides parallel to the peripheral edges of the first main surface 3. The single gate opening 94 can have an edge section that connects the section extending in the first direction X and the section extending in the second direction Y in an arc-shaped form (preferably a quarter-circle arc shape) in accordance with the gate wiring 52 in plan view (see Fig. 4).

[0133] With reference to Fig. The semiconductor device 1 comprises a source pad electrode 95 arranged on the interlayer film 70. The source pad electrode 95 is a terminal electrode to which a source potential is externally applied. The source pad electrode 95 can be referred to as a "first pad electrode", a "first main surface electrode", a "first terminal electrode", etc.

[0134] The source pad electrode 95 is arranged on a section of the interlayer film 70 that covers the active area 8. The source pad electrode 95 covers the majority of gate electrodes 32 across the interlayer film 70 and is electrically separated from the majority of gate electrodes 32 by the interlayer film 70. The source pad electrode 95 is electrically connected to the majority of body areas 20, the outer body area 21, the majority of source areas 23 (the first source area 24A and the second source area 24B), the contact area 25, etc., through the majority of source openings 90.

[0135] In this embodiment, the source pad electrode 95 comprises a first pad section 96, a second pad section 97, and a third pad section 98. The first pad section 96 has a relatively large flat surface area and forms a main body of the source pad electrode 95. In this embodiment, the first pad section 96 is polygonal (a quadrilateral shape in this embodiment) with four sides parallel to the peripheral edges of the chip 2 in plan view and is further offset towards the side of the fourth surface 5D with respect to a central section of the active area 8. The first pad section 96 covers the plurality of gate electrodes 32 across the interlayer film 70 and is electrically connected to the plurality of body regions 20, etc., through the plurality of source openings 90.

[0136] The second pad section 97 has a smaller flat area than the flat area of ​​the first pad section 96 and extends in a ribbon shape (quadrilateral shape) from an end section (end section on the side of the first side surface 5A) of the first pad section 96 in the second direction Y and the first direction X, respectively, towards the third side surface 5C. The second pad section 97 covers the majority of gate electrodes 32 across the interlayer film 70 and is electrically connected to the majority of body regions 20, etc., through the majority of source openings 90.

[0137] The third pad section 98 has a smaller flat area than the flat area of ​​the first pad section 96. It extends in a band shape (quadrilateral shape) from the other end section (end section on the side of the second surface 5B) of the first pad section 96 in the second direction Y and the first direction X, respectively, towards the third surface 5C, and faces the second pad section 97 in the second direction Y. The third pad section 98 covers the majority of gate electrodes 32 across the interlayer film 70 and is electrically connected to the majority of body regions 20, etc., through the majority of source openings 90.

[0138] The flat surface of the third pad section 98 can be essentially equal to the flat surface of the second pad section 97. Of course, the flat surface of the third pad section 98 can be larger than the flat surface of the second pad section 97, or it can be smaller than the flat surface of the second pad section 97. Either the second pad section 97, or the third pad section 98, or both can be used as a connection section for current monitoring.

[0139] The source pad electrode 95 does not necessarily have to encompass both the second pad section 97 and the third pad section 98 simultaneously. The source pad electrode 95 can encompass only one of the second pad section 97 and the third pad section 98. Naturally, the source pad electrode 95 can be formed solely from the first pad section 96 and need not encompass the second pad section 97 and the third pad section 98.

[0140] With reference to the Fig. 7 to 9 the source pad electrode 95 comprises a first base electrode film 100 and a first main electrode film 102. The first base electrode film 100 can be referred to as a “source base electrode film”, and the first main electrode film 102 can be referred to as a “source main electrode film”.

[0141] The first base electrode film 100 forms a lower layer section of the source pad electrode 95 (of the first pad section 96, the second pad section 97, and the third pad section 98) and covers the intermediate layer film 70 in the active region 8. The first base electrode film 100 collectively covers a region of the intermediate layer film 70 in which the majority of source openings 90 are formed in a film-like structure. That is, the first base electrode film 100 extends from above the insulating surface 71 into the majority of source openings 90.

[0142] The first base electrode film 100 has a section that covers the insulating surface 71 of the intermediate film 70 in a film form, and a section that covers the wall surfaces of the plurality of source openings 90 in a film form. The first base electrode film 100 defines recesses in the plurality of source openings 90. The first base electrode film 100 may have a section that partially covers the gate wiring 52 across the intermediate film 70. The first base electrode film 100 may be formed at a distance inwards from the gate wiring 52 in plan view.

[0143] In this embodiment, the first base electrode film 100 has a laminated structure comprising a first electrode film 103 laminated onto the intermediate film 70, and a second electrode film 104 laminated onto the first electrode film 103. In this embodiment, the first electrode film 103 comprises a Ti film, and the second electrode film 104 comprises a TiN film.

[0144] The first base electrode film 100 need not necessarily have a laminated structure and can have a single-layer structure formed from one of the first electrode film 103 (Ti film) and the second electrode film 104 (TiN film). The thickness of the first electrode film 103 can be 10 nm or more and 100 nm or less. The thickness of the second electrode film 104 can be 50 nm or more and 200 nm or less.

[0145] The first electrode film 103 covers the area of ​​the intermediate film 70 in which the plurality of source openings 90 are formed in a film form, and extends from above the insulating surface 71 into the plurality of source openings 90. The first electrode film 103 has a section that covers the insulating surface 71 of the intermediate film 70 in a film form, and a section that covers the wall surfaces of the plurality of source openings 90 in a film form. The first electrode film 103 directly covers the insulating surface 71.

[0146] That is, the first electrode film 103 directly covers the second oxide film 73 on the insulation surface 71. The first oxide film 72 faces the majority of gate electrodes 32 across the interlayer film 70 in a section that covers the insulation surface 71.

[0147] The first electrode film 103 covers the arcuate corner section of the intermediate film 70 (second oxide film 73) in a film shape corresponding to this arcuate corner section and enters the source opening 90. That is, the first electrode film 103 has a section that extends in an arcuate shape along the arcuate corner section. Thus, the film formability of the first electrode film 103 with respect to the intermediate film 70 (the wall surface of the source opening 90) is improved.

[0148] The first electrode film 103 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73. The first electrode film 103 faces the first side wall 34 (second side wall 35) of the gate electrode 32 across the intermediate film 70.

[0149] The first electrode film 103 covers the first main surface 3 in a film form at a lower section of each source opening 90 and is electrically connected to the first main surface 3. In particular, the first electrode film 103 has a section that covers the lower section of each source opening 90 in a film form and is electrically connected to the plurality of source areas 23 (the first source area 24A and the second source area 24B) and the contact area 25.

[0150] The second electrode film 104 jointly covers the area of ​​the intermediate film 70 in which the majority of source openings 90 are formed, in a film form on the first electrode film 103. The second electrode film 104 has a section that covers the insulating surface 71 of the intermediate film 70 in a film form over the first electrode film 103, and a section that covers the wall surfaces of the majority of source openings 90 in a film form over the first electrode film 103.

[0151] The second electrode film 104 faces the majority of gate electrodes 32 across the first electrode film 103 and the intermediate layer film 70 in a section that covers the insulation surface 71.

[0152] The second electrode film 104 covers the arcuate corner section of the intermediate film 70 (second oxide film 73) in a film shape consistent with the first electrode film 103 and extends into the source opening 90. That is, the second electrode film 104 has a section that extends in an arcuate shape along the arcuate corner section of the intermediate film 70. Thus, the film formability of the second electrode film 104 is improved with respect to the intermediate film 70 (the wall surface of the source opening 90).

[0153] The second electrode film 104 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 over the first electrode film 103. The second electrode film 104 faces the first side wall 34 (second side wall 35) of the gate electrode 32 over the first electrode film 103 and the intermediate layer film 70.

[0154] The second electrode film 104 has a section that covers the lower section of each source opening 90 in a film form over the first electrode film 103 and is electrically connected to the majority of source areas 23 (the first source area 24A and the second source area 24B) and the contact area 25.

[0155] The first main electrode film 102 forms an upper layer section of the source pad electrode 95 (of the first pad section 96, the second pad section 97, and the third pad section 98) and covers the first base electrode film 100 in a film form. The first main electrode film 102 contains a conductive material that differs from the conductive material of the first base electrode film 100.

[0156] The first main electrode film 102 can comprise at least one Al film, one Al alloy film, one Cu film, and one Cu alloy film. The Al alloy film can comprise at least one AlSi alloy film, one AlCu alloy film, and one AlSiCu alloy film. The first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first base electrode film 100.

[0157] The thickness of the first main electrode film 102 can be 0.5 µm or more and 5 µm or less. The thickness of the first main electrode film 102 can have a value that falls within at least one of the following ranges: 0.5 µm or more and 1 µm or less, 1 µm or more and 1.5 µm or less, 1.5 µm or more and 2 µm or less, 2 µm or more and 2.5 µm or less, 2.5 µm or more and 3 µm or less, 3 µm or more and 3.5 µm or less, 3.5 µm or more and 4 µm or less, 4 µm or more and 4.5 µm or less, and 4.5 µm or more and 5 µm or less.

[0158] The first main electrode film 102 is mechanically and electrically connected to the first base electrode film 100 in a section that covers the insulating surface 71. As a result, the first main electrode film 102 faces the majority of gate electrodes 32 across the first base electrode film 100 and the intermediate layer film 70.

[0159] The semiconductor device 1 comprises a source finger electrode 110, which extends from the source pad electrode 95 to the outer edge region 9. The source finger electrode 110 transfers the source potential applied to the source pad electrode 95 to the outer edge region 9. In this embodiment, the source finger electrode 110 extends from a section of the source pad electrode 95 (first pad section 96) on the side of the fourth surface 5D to a section of the interlayer film 70 that covers the outer edge region 9.

[0160] The source finger electrode 110 extends above the connection area 45 and is electrically connected to the connection area 45 through the plurality of external openings 92. In particular, the source finger electrode 110 is electrically connected to the overlap area 46 of the connection area 45 through the plurality of external openings 92.

[0161] The source finger electrode 110 extends in a band shape along the connection area 45 (overlap area 46). In plan view, the source finger electrode 110 has a section extending in a band shape in the first direction X and a section extending in a band shape in the second direction Y. In this embodiment, the source finger electrode 110 is formed in a polygonal ring shape (in this embodiment, a quadrilateral ring shape) with four sides parallel to the peripheral edges of the first main surface 3 and surrounds the source pad electrode 95. The source finger electrode 110 can have an edge section that connects the section extending in the first direction X and the section extending in the second direction Y in a plan view in an arc shape (preferably a quarter-circle arc shape) (see Fig. 4).

[0162] Similar to the source pad electrode 95, the source finger electrode 110 comprises the first base electrode film 100 and the first main electrode film 102. The first base electrode film 100 forms a lower layer section of the source finger electrode 110 and covers the intermediate layer film 70 in the outer edge region 9.

[0163] The first base electrode film 100 covers a region of the intermediate film 70 in which the plurality of outer openings 92 are formed in a film form. That is, the first base electrode film 100 extends from above the insulating surface 71 into the plurality of outer openings 92. The first base electrode film 100 has a section that covers the insulating surface 71 of the intermediate film 70 in a film form and a section that covers the wall surfaces of the plurality of outer openings 92 in a film form. The first base electrode film 100 defines recesses in the plurality of outer openings 92. Similar to the source pad electrode 95, the first base electrode film 100 has a laminated structure comprising the first electrode film 103 and the second electrode film 104.

[0164] The first main electrode film 102 forms an upper layer section of the source finger electrode 110 and covers the first base electrode film 100 in a film-like form. The first main electrode film 102 is mechanically and electrically connected to the first base electrode film 100 in a section that covers the insulating surface 71. That is, the first main electrode film 102 is electrically connected to the terminal area 45 (overlap area 46) through the first base electrode film 100.

[0165] The semiconductor device 1 comprises a gate finger electrode 115, which is selectively guided on the interlayer film 70. The gate finger electrode 115 transmits a gate potential to the gate wiring 52. The gate finger electrode 115 is guided on a section of the interlayer film 70 that covers the gate wiring 52 (i.e., on the outer edge region 9) and is electrically connected to the gate wiring 52 through the plurality of gate openings 94.

[0166] The gate finger electrode 115 is located in a region between the source pad electrode 95 and the source finger electrode 110, at a distance from both. The gate finger electrode 115 is positioned on the gate wiring 52 and extends along the gate wiring 52 in a band shape. In plan view, the gate finger electrode 115 has a section extending in a band shape in the first direction X and a section extending in a band shape in the second direction Y.

[0167] In this embodiment, the gate-finger electrode 115 is formed in a ribbon shape with ends having four sides parallel to the peripheral edges of the first main surface 3 and surrounds the source-pad electrode 95. The gate-finger electrode 115 can have an edge section that connects the section extending in the first direction X and the section extending in the second direction Y in a plan view in an arc-shaped form (preferably a quarter-circle arc shape) (see Fig. 4) The gate finger electrode 115 has a pair of open ends that allow the source finger electrode 110 to pass through on the side of the fourth side surface 5D.

[0168] With reference to Fig. 10 The gate finger electrode 115 comprises a second base electrode film 120 and a second main electrode film 122. The second base electrode film 120 can be referred to as a ‘gate base electrode film’, and the second main electrode film 122 can be referred to as a ‘gate main electrode film’.

[0169] The second base electrode film 120 forms a lower layer section of the gate finger electrode 115 and covers the intermediate layer film 70 in the outer edge region 9. The second base electrode film 120 covers, in a film-like form, a region of the intermediate layer film 70 in which the plurality of gate openings 94 are formed. That is, the second base electrode film 120 extends from above the insulating surface 71 into the plurality of gate openings 94. The second base electrode film 120 has a section that covers the insulating surface 71 of the intermediate layer film 70 in a film-like form, and a section that covers the wall surfaces of the plurality of gate openings 94 in a film-like form. The second base electrode film 120 defines a plurality of recesses in each of the plurality of gate openings 94.

[0170] The second base electrode film 120 has a similar laminated structure to the first electrode film 103 and the second electrode film 104 of the first base electrode film 100. Since the laminated structure of the second base electrode film 120 is similar to the laminated structure of the first electrode film 103 and the second electrode film 104 of the first base electrode film 100, its description is omitted.

[0171] The second main electrode film 122 forms an upper layer section of the gate-finger electrode 115 and covers the second base electrode film 120 in a film-like form. The second main electrode film 122 contains a conductive material that differs from the conductive material of the second base electrode film 120.

[0172] The second main electrode film 122 can comprise at least one Al film, one Al alloy film, one Cu film, and one Cu alloy film. The Al alloy film can comprise at least one AlSi alloy film, one AlCu alloy film, and one AlSiCu alloy film. The second main electrode film 122 preferably contains the same type of conductive material as the conductive material of the first main electrode film 102. The second main electrode film 122 can have a thickness that is substantially equal to the thickness of the first main electrode film 102.

[0173] The second main electrode film 122 is mechanically and electrically connected to the second base electrode film 120 in a section that covers the insulating surface 71.

[0174] The semiconductor device 1 comprises a gate pad electrode 130, which is arranged on the interlayer film 70. The gate pad electrode 130 is a terminal electrode to which a gate potential is externally applied. The gate pad electrode 130 can be referred to as a "second pad electrode," a "second primary surface electrode," a "second terminal electrode," etc. The gate pad electrode 130 is located in a region between the source pad electrode 95 and the source finger electrode 110, at a distance from both the source pad electrode 95 and the source finger electrode 110.

[0175] In this embodiment, the gate pad electrode 130 is arranged in a region on the side of the third surface 5C with respect to the first pad section 96 and is sandwiched between the second pad section 97 and the third pad section 98. That is, the gate pad electrode 130 faces the first pad section 96 in the first direction X and faces the second pad section 97 and the third pad section 98 in the second direction Y.

[0176] The gate pad electrode 130 is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the peripheral edges of the chip 2 in plan view. The gate pad electrode 130 has a flat surface area that is smaller than the flat surface area of ​​the source pad electrode 95 (first pad section 96). The gate pad electrode 130 may have a flat surface area that is smaller than the flat surface area of ​​the second pad section 97 (third pad section 98).

[0177] The gate pad electrode 130 is arranged on a section covering the active area 8 and the outer edge area 9 and is connected to the gate finger electrode 115. The gate pad electrode 130 can cover the majority of gate electrodes 32 across the interlayer film 70 or can cover the gate wiring 52 across the interlayer film 70.

[0178] Similar to the gate finger electrode 115, the gate pad electrode 130 comprises the second base electrode film 120 and the second main electrode film 122. The second base electrode film 120 forms a lower layer section of the gate pad electrode 130 and covers the intermediate layer film 70 in a film-like form. The second main electrode film 122 forms an upper layer section of the gate pad electrode 130 and covers the second base electrode film 120 in a film-like form.

[0179] The gate potential applied to the gate pad electrode 130 is applied to the gate wiring 52 through the gate finger electrode 115. The gate potential is transferred to the majority of gate electrodes 32 via a wiring path (current path) along the gate wiring 52. As a result, the majority of gate electrodes 32 are switched on, and the on / off of the majority of channel areas 26 and 27 is controlled.

[0180] The semiconductor device 1 includes a drain pad electrode 140 that covers the second main surface 4. The drain pad electrode 140 is a terminal electrode to which a drain potential is externally applied. The drain pad electrode 140 can be referred to as a "third pad electrode," a "third main surface electrode," a "third terminal electrode," etc. The drain pad electrode 140 is electrically connected to the second semiconductor area 7. The drain pad electrode 140 can cover an entire area of ​​the second main surface 4, so that it is continuous with the peripheral edges (the first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain pad electrode 140 can partially cover the second main surface 4, so that a peripheral edge segment of the second main surface 4 is exposed.

[0181] A breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) can be 500 V or more and 3000 V or less. The breakdown voltage can have a value that falls within at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0182] Fig. Figure 11 is a schematic view illustrating a wafer 150 used to fabricate the semiconductor device 1. With reference to Fig. In section 11, wafer 150 is a base material of chip 2 and comprises a SiC single crystal. Wafer 150 is formed in a flat disk shape. Of course, wafer 150 can also be formed in a flat rectangular parallelepiped shape. Wafer 150 has a first main wafer surface 151 on one side, a second main wafer surface 152 on the other side, and a wafer side surface 153 that connects the first main wafer surface 151 and the second main wafer surface 152.

[0183] The first wafer main surface 151 corresponds to the first main surface 3 of chip 2, and the second wafer main surface 152 corresponds to the second main surface 4 of chip 2. The first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of the SiC single crystal. The first wafer main surface 151 is formed by a silicon plane of the SiC single crystal, and the second wafer main surface 152 is formed by a carbon plane of the SiC single crystal. Wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has the off-direction and off-angle described above.

[0184] Wafer 150 has a mark 154 indicating the crystal orientation of the SiC single crystal on the wafer side surface 153. The mark 154 can comprise either an orientation flat or an orientation notch, or both. The orientation flat is formed by a notched section that appears straight in plan view. The orientation notch is formed by a notched section that is notched in a recessed shape (for example, a tapered shape) towards a central section of the first main wafer surface 151 in plan view.

[0185] Marker 154 can include either a first orientation flat extending in the m-axis direction, or a second orientation flat extending in the a-axis direction, or both. Marker 154 can also include either an orientation notch recessed in the m-axis direction, or an orientation notch recessed in the a-axis direction, or both.

[0186] The wafer 150 comprises the first semiconductor region 6 in a region (surface layer section) on the side of the first wafer main surface 151. The first semiconductor region 6 is formed in a layer shape that extends along the first wafer main surface 151. In this embodiment, the first semiconductor region 6 consists of an epitaxial layer (in particular a SiC epitaxial layer).

[0187] The wafer 150 comprises the second semiconductor region 7 in a region (surface layer section) on the side of the second wafer main surface 152. The second semiconductor region 7 is formed in a layer shape that extends along the second main surface 4 and is electrically connected to the first semiconductor region 6. In this embodiment, the second semiconductor region 7 is formed from a wafer main body (in particular, a SiC wafer). That is, in this embodiment, the wafer 150 is formed from an epitaxial wafer (so-called epi-wafer) that has a laminated structure comprising the wafer main body and the epitaxial layer.

[0188] For example, a plurality of component areas 155 and a plurality of designated separation lines 156 are defined in the wafer 150 by an alignment mark, etc. Each component area 155 is an area corresponding to the semiconductor component 1. The plurality of component areas 155 are each defined in a rectangular shape in plan view.

[0189] In this embodiment, the plurality of component regions 155 are defined in a matrix along the first direction X and the second direction Y in plan view. The plurality of component regions 155 are each defined at an inward distance from the peripheral edge of the first wafer main surface 151 in plan view. The plurality of provided separation lines 156 are defined in a grid extending along the first direction X and the second direction Y to delimit the plurality of component regions 155.

[0190] The Fig. Figures 12A to 12P are cross-sectional views illustrating a method for manufacturing the semiconductor device 1. In the Fig. Figures 12A to 12P show a cross-section of a section of the active area 8 of a component area 155. Fig. 12A to 12P, the left view corresponds to a part of the cross-section of Fig. 7, and the right-hand view corresponds to part of the cross-section of Fig. 8. Fig. Figure 13 is a view illustrating a planar pattern of a first mask 37, which is in Fig. 12G is shown.

[0191] With reference to Fig. In step 12A, the wafer 150 described above is prepared first. Next, with reference to Fig. Figure 12B shows a base mask 18 formed on the first wafer main surface 151. The base mask 18 is preferably an inorganic mask (i.e., a hard mask). The base mask 18 can comprise at least one silicon oxide film, one silicon nitride film, and one silicon oxynitride film. In this embodiment, the base mask 18 is formed from a silicon oxide film (insulating film). The base mask 18 can be formed by a CVD process. Next, the base mask 18 is structured to form a base opening 19. The base opening 19 selectively exposes a region of the first wafer main surface 151 in which the body region 20 and the outer body region 21 (not shown) are formed.

[0192] Next, with reference to Fig. 12C selectively introduces a p-type defect into a surface layer section of the first wafer main surface 151 by an ion implantation process through the base mask 18, and the majority of body regions 20 are formed. Additionally, a p-type defect is selectively introduced into the surface layer section of the first wafer main surface 151 by an ion implantation process through the base mask 18, and the outer body region 21 is formed.

[0193] Next, with reference to Fig. In this embodiment, a sidewall insulating film 28 is formed on the first wafer main surface 151 to cover the base mask 18 and the body region 20. The sidewall insulating film 28 is preferably an inorganic mask (i.e., a hard mask). The sidewall insulating film 28 can comprise at least one silicon oxide film, one silicon nitride film, and one silicon oxynitride film. In this embodiment, the sidewall insulating film 28 is formed from a silicon oxide film (insulating film). The sidewall insulating film 28 can be formed by the CVD process.

[0194] Next, with reference to Fig. 12E of the sidewall insulation film 28 is back-etched. The back-etching continues until the front surfaces of the base mask 18 and the body region 20 are exposed. As a result, a selective portion of the sidewall insulation film 28 remains in contact with a side portion of the base mask 18 to form a sidewall 29. The sidewall 29 covers a peripheral edge portion of each body region 20. Portions of the body region 20 covered by the sidewall 29 are a plurality of channel regions 26 and 27. A width WB of an exposed portion of the body region 20 sandwiched between the adjacent sidewalls 29 can be, for example, 4 µm or more and 10 µm or less.

[0195] Next, with reference to Fig. 12F a mask material 36 that covers the side wall 29 and the base mask 18, configured to fill the base opening 19 of the base mask 18. The mask material 36 can be an organic material. The mask material 36 can comprise a positive- or negative-working photosensitive resin film (i.e., a resist film) as an organic material. Of course, the mask material 36 can also be an inorganic material (for example, a silicon oxide film, a silicon nitride film, a polysilicon film, etc.).

[0196] Next, with reference to Fig. 12G structures the mask material 36 to form the first mask 37. The first mask 37 has a first opening 38 that exposes an area in which the source area 23 (the first source area 24A and the second source area 24B) is to be formed.

[0197] Here, with reference to Fig. 13, the first mask 37 corresponds to the planar shape of the contact area 25. The first mask 37 comprises a first section 39 extending in a band shape in the second direction Y, and a plurality of projecting sections 40 extending outwards from the first section 39 in the first direction X.

[0198] The first section 39 intersects the first section 10 of body region 20 in the second direction Y and has a terminal section at the boundary position between the first section 10 and the second section 11. Depending on its planar shape, the first section 39 may also be referred to by another name. For example, as in Fig. Figure 13 illustrates that if a shape formed by excluding the projecting section 40 (a shape in which sections that are vertically opposite each other across the projecting section 40 in the second direction Y are connected by a dashed line 44) is a ribbon shape in plan view, the first section 39 can be described as a ribbon-shaped section. For example, the width (third width W3) of the first section 39 can be 0.2 µm or more and 0.6 µm or less.

[0199] In this embodiment, the plurality of projecting sections 40 can comprise a pair of projecting sections 41A and 41B, which project from the center of the first section 39 in the second direction Y to both sides in the first direction X. That is, a projecting section 40 is formed on each side of the first section 39 in the first direction X.

[0200] In this embodiment, each of the projecting sections 41A and 41B is formed in a triangular shape in plan view. In the first mask 37, the vertex section 48 has a sharp, pointed shape.

[0201] The pair of projecting sections 41A and 41B can have an overall shape of a rhombus or a circle, projecting symmetrically on both sides relative to the first section 39 in plan view. The overall shape of the pair of projecting sections 41A and 41B can be a shape defined by an outline 42 of the pair of projecting sections 41A and 41B and an inner extension line 43 (virtual line) of the outline 42 to the inside of the contact area 25 (first section 39). Fig. Figure 13 illustrates a pattern in which the overall shape of the pair of protruding sections 41A and 41B is a rhombus. In this embodiment, the total width (fourth width W4) of the pair of protruding sections 41A and 41B, from an end section of the first protruding section 41A in the first direction X to an end section of the second protruding section 41B in the first direction X, can be 1.2 µm or more and 1.6 µm or less.

[0202] Additionally, the length ratio (height H of the first mask 37 / third width W3) in the first section 39 of the first mask 37 can be 5 or more and 25 or less. The length ratio (height H of the first mask 37 / fourth width W4) of a section of the first mask 37 where the pair of projecting sections 41A and 41B is formed can be 0.8 or more and 4.8 or less.

[0203] Next, with reference to Fig. In step 12H, an n-type defect is selectively introduced into the surface layer of body region 20 through the first mask 37 using the ion implantation method to form the source region 23. Additionally, a contact pattern region 50 is formed, which is created from a portion of the body region 20 covered by the first mask 37. After the source region 23 is formed, the first mask 37 is removed.

[0204] Next, with reference to Fig. 12I A mask material is formed that covers the side wall 29 and the base mask 18. The mask material can be an organic material. The mask material can comprise a positive- or negative-working photosensitive resin film (that is, a resist film) as an organic material. Of course, the mask material can also be an inorganic material (for example, a silicon oxide film, a silicon nitride film, a polysilicon film, etc.). Next, the mask material is structured to form a second mask 56. The second mask 56 has a second opening 57 that exposes an area in which the contact area 25 is to be formed.

[0205] Next, with reference to Fig. 12J selectively introduces a p-type defect into the surface layer portion of body region 20 through the second mask 56 using the ion implantation method to form contact region 25. Contact region 25 is formed in the same planar pattern as the first mask 37. However, a slight pattern shift due to an error, etc., in the ion incidence angle may occur when the p-type defect is introduced. Therefore, the vertex portion 49 of the pair of protrusion portions 14A and 14B of contact region 25 may have a rounded shape, unlike the vertex portion 48 of the pair of protrusion portions 41A and 41B of the first mask 37 (see Fig. 6).

[0206] Next, with reference to Fig. 12K a base insulating film 58 is formed, covering the first main wafer surface 151. The base insulating film 58 forms a base for the insulating film 31 and the outer peripheral insulating film 51. The base insulating film 58 can be formed by the CVD (chemical vapor deposition) process or an oxidation treatment process (for example, a thermal oxidation treatment process).

[0207] Next, with reference to Fig. A base electrode is formed on the base insulating film 58. The base electrode is the basis for the gate electrode 32 and the gate wiring 52. The base electrode contains conductive polysilicon. The base electrode can be formed by the CVD process. Next, the base electrode is structured to form the gate electrode 32 and the gate wiring 52.

[0208] Next, with reference to Fig. In step 12M, the interlayer film 70 is formed on the first wafer main surface 151. In this step, the interlayer film 70 is formed with a section that directly covers the electrode surface 33, the first side wall 34, and the second side wall 35 of the gate electrode 32. In this embodiment, the interlayer film 70 has a laminated structure comprising the first oxide film 72 and the second oxide film 73. The first oxide film 72 comprises a silicon oxide film that is not doped with any impurities. The second oxide film 73 comprises a phosphorus-containing silicon oxide film. The first oxide film 72 can be formed by the CVD process. The second oxide film 73 can be formed by the CVD process. After the formation of the second oxide film 73, a reflow step (heat treatment step) is performed on the interlayer film 70.As a result, corner sections and the front surface roughness of the intermediate layer film 70 are smoothed.

[0209] Next, with reference to Fig. 12N places a mask with a predetermined layout on the intermediate film 70. The mask exposes areas where the majority of source openings 90, the majority of outer openings 92, and the majority of gate openings 94 are to be formed, and covers other areas. Next, an unnecessary section of the intermediate film 70 and an unnecessary section of the base insulating film 58 are removed by an etching process through the mask.

[0210] In this step, an unnecessary section of the second oxide film 73, an unnecessary section of the first oxide film 72, and an unnecessary section of the base insulating film 58 are removed in that order. The etching process can be a wet etching process and / or a dry etching process. The etching process is preferably an anisotropic dry etching process (for example, a RIE (reactive ion etching) process). As a result, the majority of source openings 90, the majority of outer openings 92, and the majority of gate openings 94 are formed in the intermediate film 70. Additionally, the insulating film 31 and the outer peripheral insulating film 51 are formed. This step can include a step of forming the majority of source openings 91 and a step of forming the majority of outer openings 93.In this case, a further excavation step is carried out of sections of the first wafer main surface 151, which are exposed by the majority of source openings 90 and the majority of outer openings 92, in the direction of the second wafer main surface 152. The mask is then removed.

[0211] Next, with reference to Fig. 12O a surface curved towards the obliquely upper part of the gate electrode 32 is formed at an upper corner section of the interlayer film 70 by a reflow process. A reflow condition is not particularly restricted as long as the reflow condition is such that the upper corner section of the interlayer film 70, which after etching in Fig. 12N is pointed, becomes arc-shaped. For example, it can be appropriately determined according to the film thickness and film quality of the interlayer film 70, the aperture width of the source aperture 90, etc.

[0212] Next, with reference to Fig. In step 12P, the first base electrode film 100 and the second base electrode film 120 are formed on the intermediate film 70. The first base electrode film 100 and the second base electrode film 120 can be formed by a sputtering process or a vapor deposition process. Next, the first main electrode film 102 and the second main electrode film 122 are formed on the first base electrode film 100 and the second base electrode film 120, respectively. The first main electrode film 102 and the second main electrode film 122 can each comprise at least one Al film, one Al alloy film, one Cu film, and one Cu alloy film. The Al alloy film can comprise at least one AlSi alloy film, one AlCu alloy film, and one AlSiCu alloy film. The first main electrode film 102 and the second main electrode film 122 can be formed by the sputtering process or the vapor deposition process.

[0213] Next, the drain pad electrode 140 is formed on the second main wafer surface 152. The drain pad electrode 140 can be formed by sputtering or vapor deposition. Then, the wafer 150 is cut along the designated parting line 156, and the majority of semiconductor devices 1 are cut out. The semiconductor device 1 is fabricated by the steps described above.

[0214] For example, the majority of gate structures 30 can be arranged at a close distance (“pitch”) to meet a requirement for reducing the size of a component. Since the distance between the adjacent gate structures 30 is reduced, the formation areas of the source area 23 and the contact area 25 are also reduced. Therefore, the installation areas of the first mask 37 and the second mask 56 are reduced when the source area 23 and the contact area 25 are formed.

[0215] In particular, with reference to Fig. 12G, since the first mask 37 is formed at a distance from the base mask 18, the side wall 29, etc., there is no support in a lateral direction. Therefore, its resistance to an external force is reduced, and it easily falls or tilts due to its own weight or an external force. On the other hand, according to the procedure described above, as in Fig. Figure 13 shows the first mask 37, which comprises the pair of projecting sections 41A and 41B and is partially wide. Since the durability (strength) against an external force can be improved by the pair of projecting sections 41A and 41B, it is possible to prevent the first mask 37 from falling or tipping over. As a result, the source area 23 and the contact area 25 themselves can be precisely formed in a fine pattern.

[0216] Additionally, chip 2 is a wide-bandgap semiconductor (SiC in this embodiment). The wide-bandgap semiconductor has a low diffusion coefficient for implanted impurity ions. Therefore, when an impurity region is formed in the lower direction of wafer 150, a method using high-acceleration implantation is employed instead of thermal diffusion, which is used for Si, etc. To prevent high-energy accelerated impurity ions from penetrating and being implanted through the mask (resist), it is necessary to make the mask thicker. For example, in this embodiment, the first mask 37 is thickened to prevent the n-type impurity from penetrating the first mask 37 and being implanted into the contact pattern region 50 when the source region 23 is formed.In particular, in the first section 39 of the first mask 37, the length ratio (the height H of the first mask 37 / the third width W3) is set to 5 or more and 25 or less. With such a high length ratio, there is considerable concern about the first mask 37 falling down or tipping over. However, such concern can be eliminated by the presence of the pair of projecting sections 41A and 41B.

[0217] On the other hand, it can be considered that the source area 23 is formed by implanting an n-type defect into an entire area sandwiched between the side walls 29, while the steps of the Fig. 12G and Fig. 12H can be omitted. A p-type defect can then be implanted into the source region 23 through the second mask 56, which is supported laterally by the side wall 29, to form the contact region 25. However, it is necessary to form the contact region 25 by implanting a p-type defect with an excessive concentration capable of disrupting the n-type defect of the previously formed source region 23. This can lead to a deterioration of the front surface condition of the first wafer main surface 151 due to excessive implantation of defect ions (for example, roughening of the front surface), and a deterioration of the function of the semiconductor device 1. For example, the contact resistance between the source pad electrode 95 and the contact region 25 can increase due to front surface roughness.On the other hand, in the procedure described above, since the ion implantation only needs to be performed once for each defect area, the front surface condition of the first main wafer surface 151 can be kept in a favorable condition.

[0218] Although preferred embodiments of the present disclosure have been described above, the present disclosure can also be implemented in other preferred embodiments.

[0219] For example, in the preferred embodiment described above, the contact area 25 is partially wide and the pair of projecting sections 14A and 14B is formed, but, as in Fig. As illustrated in Figure 14, the first source region 24A and the second source region 24B can be partially wide. In this case, a pair of protruding sections 59A and 59B can be formed, each projecting from the first source region 24A and the second source region 24B, respectively, towards the inside of the contact region 25. Furthermore, a structure similar to the pair of protruding sections 14A and 14B can be applied to a fine defect region formed in the chip 2, regardless of its function. For example, it can be applied to the plurality of field regions 47 formed in the outer edge region 9.

[0220] Additionally, patterns that are in the Fig. Figures 15 to 19 illustrate the modification pattern of contact area 25. Fig. 15 The first width W1 of the first section 12 of the contact area 25 gradually narrows from the pair of projecting sections 14A and 14B to an end section in the second direction Y. Thus, the first section 12 can be formed in a substantially tapered shape in plan view.

[0221] In Fig. In 16, a plurality of projecting sections 14A and 14B are formed on one side and on the other side of the first section 12 of the contact area 25 in the first direction X, respectively. Fig. 17 The pair of leading sections 14A and 14B are positioned from different positions of the first section 12 in the second direction Y to the opposite sides.

[0222] In Fig. In section 18, each of the projecting sections 14A and 14B is formed in a semicircular shape in plan view. Fig.In section 19, each of the projection sections 14A and 14B is formed in a quadrilateral shape in plan view. In this case, the corner sections (vertex sections 49) of the quadrilateral can have a rounded circular shape.

[0223] For example, in each of the preferred embodiments described above, a configuration can be used in which the relationship between the a-axis direction and the m-axis direction is reversed. A specific configuration in this case can be obtained by interchanging the “a-axis direction (off direction)” and the “m-axis direction (direction orthogonal to the off direction)” in the above description and the accompanying drawings.

[0224] In each of the preferred embodiments described above, a structure can be used in which the conductivity type of the "n-type" semiconductor region is inverted to the "p-type" and vice versa. A specific configuration in this case can be obtained by replacing "n-type" with "p-type" in the descriptions above and the accompanying drawings, while simultaneously replacing "p-type" with "n-type".

[0225] In each of the preferred embodiments described above, the chip 2 (the first semiconductor region 6 and the second semiconductor region 7), which contains a SiC single crystal, is used. However, the chip 2 (the first semiconductor region 6 and the second semiconductor region 7) can also include a single crystal of a wide-bandgap semiconductor other than the SiC single crystal. The wide-bandgap semiconductor is a semiconductor with a bandgap larger than that of silicon. Examples of single crystals of wide-bandgap semiconductors include gallium nitride, diamond, gallium oxide, etc. Of course, the chip 2 (the first semiconductor region 6 and the second semiconductor region 7) can also contain a silicon single crystal.

[0226] In each of the preferred embodiments described above, the second semiconductor region 7 is of the n-type. However, the second semiconductor region 7 can be of the p-type instead of the second semiconductor region 7 of the n-type. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, the "source" of the MISFET structure in the descriptions above is replaced by an "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by a "collector" of the IGBT structure. The second semiconductor region 7 of the p-type can be an impurity region containing a p-type impurity introduced into a surface layer section of the second main surface 4 of the chip 2 by the ion implantation method.

[0227] Examples of features extracted from this description and the attached drawings are given below. The alphanumeric characters etc. in parentheses represent the corresponding components etc. in the preferred embodiments described above, but are not intended to limit the scope of any clause or appendix to the preferred embodiments. The "semiconductor device" in the following clauses may, if necessary, be replaced by a "SiC semiconductor device," a "wide bandgap semiconductor device," a "semiconductor switching device," a "MISFET device," an "IGBT device," etc. [Annex 1-1]

[0228] Semiconductor device (1), comprising: a chip (2) formed by a wide bandgap semiconductor and having a main surface on which a semiconductor region (6) of a first conductivity type is formed; a base defect region (20) of a second conductivity type formed in a surface layer section of the semiconductor region (6); a first defect area (13, 25) which is formed in a surface layer section of the base defect area (20); and a second defect region (25, 13) of a conductivity type opposite to that of the first defect region (13, 25) formed in the surface layer section of the base defect region (20), wherein the second defect region (25, 13) is adjacent to the first defect region (13, 25) in a first direction (X), wherein the second defect region (25, 13) is formed in a band shape which extends in a second direction (Y) orthogonal to the first direction (X) and has a projection section (13) which selectively projects in the direction of the first defect region (13, 25) in the first direction (X). [Appendix 1-2]

[0229] Semiconductor device (1) according to Annex 1-1, wherein the second defect region (25, 13) is sandwiched between the first defect regions (13, 25) from both sides in the first direction (X), and a pair of the leading sections (14A, 14B) protrudes in the first direction (X) to opposite sides. [Appendix 1-3]

[0230] Semiconductor device (1) according to Annex 1-2, wherein the second defect region (25, 13) has a first section (12) extending in the second direction (Y) and having a first width (W1) in the first direction (X), and the pair of projection sections (14A, 14B) projecting from a center of the first section (12) in the second direction (Y) to the two sides in the first direction (X). [Appendix 1-4]

[0231] Semiconductor device (1) according to Annex 1-3, wherein the pair of projection sections (14A, 14B) has an overall shape of a rhombus or a circle which projects uniformly to both sides in plan view with respect to the first section (12). [Appendix 1-5]

[0232] Semiconductor device (1) according to Annex 1-3 or Annex 1-4, wherein the first width (W1) of the first section (12) is 0.2 µm or more and 0.6 µm or less, and a total second width (W2) of the pair of protrusion sections (14A, 14B) from a terminal section of one protrusion section (13) to a terminal section of the other protrusion section (13) is 1.2 µm or more and 1.6 µm or less. [Appendix 1-6]

[0233] Semiconductor device (1) according to Annex 1-5, wherein a width (WS) of the first defect region (13, 25) in the first direction (X) is greater than the second width (W2) of the pair of protrusion sections (14A, 14B). [Appendix 1-7]

[0234] Semiconductor device (1) according to Annex 1-1, comprising: a body region (20) as the base defect region (20) which is formed in the surface layer section of the semiconductor region (6); the first defect area (13) which is formed in a surface layer section of the body area (20); a body contact area (25) as the second defect area (25) which is formed in the surface layer section of the body area (20) which penetrates the first defect area (13) and is connected to the body area (20); a channel (26, 27) which is formed in a region between the semiconductor region (6) and the first defect region (13) in the surface layer section of the body region (20); and a gate electrode (32) which is formed on the channel (26, 27) across an insulating film (31). [Appendix 1-8]

[0235] Semiconductor device (1) according to Annex 1-7, wherein the majority of body areas (20) are arranged in a strip shape extending in the second direction (Y), each of the body regions (20) has a plurality of first sections (10) and a plurality of second sections (11) alternating in the second direction (Y), and the majority of body contact areas (25) are arranged at intervals for each of the first sections (10) in order to skip each of the second sections (11) in the second direction (Y). [Appendix 1-9]

[0236] Semiconductor device (1) according to Annex 1-8, wherein the body contact area (25) has a first section (12) which crosses the first section (10) in the second direction (Y) and has a first width (W1) in the first direction (X), and the pair of projection sections (14A, 14B) project from a center of the first section (12) in the second direction (Y) to the two sides in the first direction (X). [Appendix 1-10]

[0237] Semiconductor device (1) according to Annex 1-9, wherein the pair of projection sections (14A, 14B) has an overall shape of a rhombus or a circle which projects uniformly to both sides in plan view with respect to the first section (12). [Appendix 1-11]

[0238] Semiconductor device (1) according to Annex 1-10, wherein the first width (W1) of the first section (12) is 0.2 µm or more and 0.6 µm or less, and a total second width (W2) of the pair of protrusion sections (14A, 14B) from a terminal section of one protrusion section (14A) to a terminal section of the other protrusion section (14B) is 1.2 µm or more and 1.6 µm or less. [Appendix 1-12]

[0239] Semiconductor device (1) according to Annex 1-11, wherein a width (WS) of the first defect region (13) in the first direction (X) is greater than the second width (W2) of the pair of protrusion sections (14A, 14B). [Appendix 1-13]

[0240] Semiconductor device (1) according to Annex 1-1, comprising: a body region (20) as the base defect region (20) which is formed in the surface layer section of the semiconductor region (6); the second defect area (13), which is formed in a surface layer section of the body area (20); a body contact area (25) as the first defect area (25) which is formed in the surface layer section of the body area (20) which penetrates the second defect area (13) and is connected to the body area (20); a channel (26, 27) which is formed in a region between the semiconductor region (6) and the second defect region (13) in the surface layer section of the body region (20); and a gate electrode (32) which is formed on the channel (26, 27) across an insulating film (31). [Appendix 1-14]

[0241] Semiconductor device (1) according to Annex 1-13, wherein the majority of body areas (20) are arranged in a strip shape extending in the second direction (Y), each of the body regions (20) has a plurality of first sections (10) and a plurality of second sections (11) alternating in the second direction (Y), and the majority of body contact areas (25) are arranged at intervals for each of the first sections (10) in order to skip each of the second sections (11) in the second direction (Y). [Appendix 1-15]

[0242] Semiconductor device (1) according to any one of Annexes 1-1 to 1-14, wherein the chip (2) is a SiC chip. [Appendix 1-16]

[0243] Method for manufacturing a semiconductor device (1), comprising: a step of preparing a wafer (150) formed by a wide bandgap semiconductor having a main surface (151) on which a semiconductor region (6) of a first conductivity type is formed, and of selectively forming a plurality of body regions (20) at intervals in a first direction (X) in a surface layer section of the semiconductor region (6) by selectively implanting a defect of a second conductivity type into the semiconductor region (6); a step of forming a first mask (37) that selectively covers each of the body regions (20), wherein the first mask (37) has a first section (39) extending in a second direction (Y) orthogonal to the first direction (X) and having a first width (W3) in the first direction (X), and the pair of projecting sections (41A, 41B) projecting from a center of the first section (39) in the second direction (Y) to both sides in the first direction (X); a step of forming a first defect area (13) in a surface layer section of the body area (20) by implanting a defect of a first conductivity type into the body area (20) through the first mask (37), and leaving a contact pattern area (50) formed from a part of the body area (20) in an area covered by the first mask (37); a step of forming a second mask (56) which has an opening (57) for selectively exposing the contact pattern area (50) and covers the first defect area (13); a step of forming a body contact area (25) in the surface layer section of the body area (20) by implanting a disturbance of a second conductivity type into the contact pattern area (50) through the second mask (56); and a step of forming a gate electrode (32) covering a channel (26, 27) formed in a region between the semiconductor region (6) and the first defect region (13) in the surface layer section of the body region (20). [Appendix 1-17]

[0244] Method for manufacturing a semiconductor device (1) according to Annex 1-16, further comprising: a step of forming, on the main surface (151), a hard mask (18) which selectively has an opening (19) in an area in which the body area (20) is to be formed; a step of forming a side wall (29) on a side section of the hard mask (18) to cover an area in which the channel (26, 27) is to be formed after the body area (20) has been formed by implanting the second conductivity type defect through the hard mask (18); a step of forming a mask material (36) that covers the side wall (29) and the hard mask (18) to fill the opening in the hard mask (18); and a step of forming the first mask (37) by structuring the mask material (36). [Appendix 1-18]

[0245] Method for manufacturing a semiconductor device (1) according to Annex 1-16 or Annex 1-17, wherein a length ratio (a height (H) of the first section (39) / the width (W3) of the first section (39)) in the first section (12) of the first mask (37) is 5 or more and 25 or less. Reference symbol list 1 Semiconductor device 2 Chip 3 First main surface 4 Second main surface 5A First page surface 5B Second side surface 5C Third page surface 5D Fourth Side Surface 6 First semiconductor area 7 Second Semiconductor Area 8 Active Area 9 Outer edge area 10 First Section 11 Second Section 12 First Section 13th lead section 14A First lead section 14B Second Lead Section 15 Outline 16 Inner extension line 17 Dashed line 18 Basic mask 19 Base opening 20 Body Area 21 External body area 22 Surface layer drift range 23 Source area 24A First Source Area 24B Second Source Area 25 Contact area 26 First canal section 27 Second canal section 28 Sidewall insulation film 29 Side wall 30-gate structure 31 Insulation film 32 Gate electrode 33 Electrode surface 34 First side wall 35 Second side wall 36 mask materials 37 First mask 38 First Opening 39 First Section 40-minute lead section 41A First lead section 41B Second Lead Section 42 Outline 43 Inner extension line 44 Dashed line 45 Connection area 46 Overlap area 47 Field area 48 Vertex segment 49 Vertex segment 50 contact pattern area 51 Outer peripheral insulating film 52 Gate wiring 53 Wiring surface 54 First wiring side panel 55 Second wiring side panel 56 Second mask 57 Second Opening 58 Basic insulation film 59A Lead Section 59B Lead Section 70 Interlayer film 71 Insulation surface 72 First oxide film 73 Second oxide film 74 First cover section 75 Second cover section 76 Third cover section 80 First upper cover section 81 Second upper cover section 90 Source Opening 91 Source recess 92 Outer opening 93 Outer recess 94 Gate Opening 95 Source pad electrode 96 First Pad Section 97 Second Pad Section 98 Third Pad Section 100 First basic electrode film 102 First main electrode film 103 First electrode film 104 Second electrode film 110 Source finger electrode 115 Gate finger electrode 120 Second base electrode film 122 Second main electrode film 130 Gate pad electrode 140 Drain pad electrode 150 wafers 151 First wafer main surface 152 Second wafer main surface 153 Wafer side surface 154 Marking 155 Component area 156 Proposed dividing line W1 First Broad W2 Second Width W3 Third Latitude W4 Fourth Broad X First direction Y Second direction Z Vertical direction QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2023

[0001] JP 099595

[0001] JP-2015 207 588 A

[0004]

Claims

[1] Semiconductor device, comprising: a chip formed by a wide bandgap semiconductor and having a main surface on which a semiconductor region of a first conductivity type is formed; a base defect region of a second conductivity type, which is formed in a surface layer section of the semiconductor region; a first defect area that is formed in a surface layer section of the base defect area; and a second defect region of a conductivity type opposite to that of the first defect region formed in the surface layer section of the base defect region, wherein the second defect region is adjacent to the first defect region in a first direction, wherein the second defect area is formed in a band shape which extends in a second direction orthogonal to the first direction and has a projection section which selectively projects in the direction of the first defect area in the first direction. [2] Semiconductor device according to claim 1, wherein the second defect area is sandwiched between the first defect areas from both sides in the first direction, and where one pair of the leading sections projects in opposite directions. [3] Semiconductor device according to claim 2, wherein the second defect region has a first section extending in the second direction and having a first width in the first direction, and wherein the pair of projection sections projects from a center of the first section in the second direction to the two sides in the first direction. [4] Semiconductor device according to claim 3, wherein the pair of projection sections has an overall shape of a rhombus or a circle which projects uniformly to both sides in plan view with respect to the first section. [5] Semiconductor device according to claim 3 or 4, wherein the first width of the first section is 0.2 µm or more and 0.6 µm or less, and wherein a total second width of the pair of protrusion sections from a terminal section of one protrusion section to a terminal section of the other protrusion section is 1.2 µm or more and 1.6 µm or less. [6] Semiconductor device according to claim 5, wherein a width of the first defect region in the first direction is greater than the second width of the pair of projection sections. [7] Semiconductor device according to claim 1, comprising: a body region as the base defect region, which is formed in the surface layer section of the semiconductor region; wherein the first defect area is formed in a surface layer section of the body area; a body contact area as the second defect area, which is formed in the surface layer section of the body area that penetrates the first defect area and is connected to the body area; a channel that is formed in a region between the semiconductor region and the first defect region in the surface layer section of the body region; and a gate electrode that is formed on the channel across an insulating film. [8] Semiconductor device according to claim 7, wherein the majority of body areas are arranged in a striped shape that extends in the second direction, wherein each of the body regions has a plurality of first sections and a plurality of second sections alternating in the second direction, and where the majority of body contact areas are arranged at intervals for each of the first sections in order to skip each of the second sections in the second direction. [9] Semiconductor device according to claim 8, wherein the body contact area has a first section which crosses the first section in the second direction and has a first width in the first direction, and wherein the pair of projection sections projects from a center of the first section in the second direction to the two sides in the first direction. [10] Semiconductor device according to claim 9, wherein the pair of projection sections has an overall shape of a rhombus or a circle which projects uniformly to both sides in plan view with respect to the first section. [11] Semiconductor device according to claim 10, wherein the first width of the first section is 0.2 µm or more and 0.6 µm or less, and wherein a total second width of the pair of protrusion sections from a terminal section of one protrusion section to a terminal section of the other protrusion section is 1.2 µm or more and 1.6 µm or less. [12] Semiconductor device according to claim 11, wherein a width of the first defect region in the first direction is greater than the second width of the pair of protrusion sections. [13] Semiconductor device according to claim 1, comprising: a body region as the base defect region, which is formed in the surface layer section of the semiconductor region; wherein the second defect area is formed in a surface layer section of the body area; a body contact area as the first defect area, which is formed in the surface layer section of the body area, which penetrates the second defect area and is connected to the body area; a channel that is formed in an area between the semiconductor region and the second defect region in the surface layer section of the body region; and a gate electrode that is formed on the channel across an insulating film. [14] Semiconductor device according to claim 13, wherein the majority of body areas are arranged in a striped shape that extends in the second direction, wherein each of the body regions has a plurality of first sections and a plurality of second sections alternating in the second direction, and where the majority of body contact areas are arranged at intervals for each of the first sections in order to skip each of the second sections in the second direction. [15] Semiconductor device according to any one of claims 1 to 14, wherein the chip is a SiC chip. [16] Method for manufacturing a semiconductor device, comprising: a step of preparing a wafer formed by a wide bandgap semiconductor having a main surface on which a semiconductor region of a first conductivity type is formed, and of selectively forming a plurality of body regions at intervals in a first direction in a surface layer section of the semiconductor region by selectively implanting a defect of a second conductivity type into the semiconductor region; a step of forming a first mask that selectively covers each of the body regions, wherein the first mask has a first section extending in a second direction orthogonal to the first direction and having a first width in the first direction, and wherein the pair of projecting sections project from a center of the first section in the second direction to both sides in the first direction; a step of forming a first disturbance area in a surface layer section of the body area by implanting a disturbance of a first conductivity type into the body area through the first mask, and leaving behind a contact pattern area formed from a part of the body area in an area covered by the first mask; a step of forming a second mask which has an opening for selectively exposing the contact pattern area and which covers the first defect area; a step of forming a body contact area in the surface layer section of the body area by implanting a disturbance of a second conductivity type into the contact pattern area through the second mask; and a step of forming a gate electrode covering a channel formed in a region between the semiconductor area and the first defect area in the surface layer section of the body region. [17] Method for manufacturing a semiconductor device according to claim 16, further comprising: a step of the training, on the main surface, a hard mask which selectively has an opening in an area where the body area is to be trained; a step of forming a side wall on a lateral section of the hard mask to cover an area in which the channel is to be formed, after the body area has been formed by implanting the second conductivity type disturbance through the hard mask; a step of forming a mask material that covers the sidewall and the hard mask to fill the opening in the hard mask; and a step of forming the first mask by structuring the mask material. [18] Method for manufacturing a semiconductor device according to claim 16 or 17, wherein a length ratio (a height of the first section / the width of the first section) in the first section of the first mask is 5 or more and 25 or less.

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