A semiconductor device with an embedded electrical conductor connected between pins of one semiconductor device and another device

Abstract

A semiconductor package (10; 20) comprising: a housing body (1); a first die pad (2) at least partially encapsulated in the housing body (1), the first die pad (2) having a first main surface and a second main surface opposite the first main surface; a second die pad (3) at least partially encapsulated in the housing body (1), the second die pad (3) having a first main surface and a second main surface opposite the first main surface; a first semiconductor die (4) at least partially encapsulated in the housing body (1) and arranged on the first die pad (2), the first semiconductor die (4) having a first contact pad (4A) arranged on the first main surface of the first semiconductor die (4) and a second contact pad arranged on the second main surface of the first semiconductor die (4), the first semiconductor die (4) being connected to the first die pad (2) by means of the second contact pad;a further component (5) which is at least partially encapsulated in the housing body (1) and arranged on the second die pad (3), wherein the further component (5) comprises a first contact pad (5A) arranged on the first main surface of the further component (5) and a second contact pad arranged on the second main surface of the further component (5), wherein the further component (5) is connected to the second die pad (3) via the second contact pad; at least one first line (6.1) which is connected to the first contact pad (4A) of the first semiconductor die (4) and extends out of the housing body (1); at least one second conductor (7) which is connected to the second contact pad of the further device (5) and extends out of the housing body (1);andan electrical conductor (8) connected between the at least one first conductor (6.1) and the at least one second conductor (7), wherein the electrical conductor (8) is completely encapsulated in the housing body (1); whereinthe second main surface of the first die pad (4) and the second main surface of the second die pad (3) are not completely encapsulated in the housing body (1).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor package and a lead frame. BACKGROUND

[0002] Inverter power modules have evolved from a niche solution to a standard product in power electronics, particularly in the field of renewable energies. Adopting module and packaging concepts from existing products with a high level of maturity in their product life cycle is plausible if the complexity of the inverter power modules remains low. Implementing even a simple half-bridge with two power switching components in a single package precludes the use of established, production-efficient designs without adaptations, leading to limitations in various requirements such as power and temperature values, switching symmetry, signal routing capability, etc. Information on the background of the invention can be found, for example, in the documents DE 60214897 T2 and DE 102018112477 A1.

[0003] To implement a half-bridge using a conventional leadframe concept, two individual power switching devices are molded side by side using a copper substrate, often called a die pad or paddle, and the corresponding driver chips (dies), as well as power and signal pins. The power switching devices are connected at a phase node using various methods. For example, the phase connection can be achieved by a crossover between the high-side and low-side switches, e.g., using a copper clip on the front side of the chip, which results in high chip costs due to the necessary solderable metallizations on the front side. In another case, the phase connection is achieved by external routing on the customer side by creating an electrical connection within a printed circuit board (PCB) that electrically connects the pins assigned to the two power switching devices.This configuration allows for inductance reduction at the application or even system level.

[0004] For these and other reasons, there is a need for the present disclosure. SUMMARY

[0005] A first aspect of the present disclosure relates to a semiconductor package comprising a package body, a first die pad at least partially encapsulated in the package body, the first die pad having a first main surface and a second main surface opposite the first main surface, and a second die pad at least partially encapsulated in the package body, the second die pad having a first main surface and a second main surface opposite the first main surface, a first semiconductor die at least partially encapsulated in the package body and disposed on the first die pad, the first semiconductor die comprising a first contact pad disposed on the first main surface of the first semiconductor die and a second contact pad disposed on the second main surface of the first semiconductor die, the first semiconductor die being connected to the first die pad by the second contact pad.a further component that is at least partially encapsulated in the package body and arranged on the second die pad, wherein the further component comprises a first contact pad arranged on the first main surface of the further component and a second contact pad arranged on the second main surface of the further component, wherein the further component is connected to the second die pad via the second contact pad, at least one first conductor connected to the first contact pad of the first semiconductor chip and extending out of the package body, at least one second conductor connected to the second contact pad of the further component and extending out of the package body, and an electrical conductor connected between the at least one first conductor and the at least one second conductor, wherein the electrical conductor is completely encapsulated in the package body.

[0006] A second aspect of the present disclosure relates to a lead frame comprising a first die pad having a first main surface and a second main surface opposite the first main surface, a second die pad having a first main surface and a second main surface opposite the first main surface, at least one first conductor, at least one second conductor, and an electrical conductor connected between the at least one first conductor and the at least one second conductor. In another aspect, the first conductor and the second conductor each have a proximal end approaching the first die pad and the second die pad, respectively, and a distal end remote from the first die pad and the second die pad, respectively, and the electrical conductor is arranged perpendicular to the first conductor and the second conductor and proximate the proximal end of the first conductor and the second conductor.Such that after the lead frame is molded into a semiconductor package, this conductor is not exposed from the sidewall of the semiconductor package. In another aspect, the electrical conductor lies in a plane that differs from the plane of the first die pad and the second die pad, such that after the lead frame is molded into a semiconductor package, this electrical conductor can be fully embedded in the mold connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are provided to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily appreciated as they become better understood by reference to the following detailed description.

[0008] The elements in the drawings are not necessarily to scale. Like reference numbers indicate like or similar elements. Fig. 1 shows a perspective view of a semiconductor package comprising two semiconductor transistors forming a half-bridge circuit, with both dies arranged in a drain-down configuration. Fig. 2 shows a perspective view of an unpackaged semiconductor package with two semiconductor transistor wires forming a half-bridge circuit, one of the wires being arranged in a drain-down configuration and the other in a source-down configuration. Fig. 3 shows a perspective view of the semiconductor package of Fig. 2 in a housed configuration. Fig. 4 consists of Fig. 4A and Fig. 4B and shows schematic circuit diagrams of a half-bridge circuit consisting of two transistors (A) and a boost circuit consisting of one transistor and one diode (B). Fig. 5 consists of Fig. 5A and Fig. 5B and shows schematic circuit diagrams of a nested half-bridge circuit (A) and a nested boost circuit (B). Fig. 6 consists of Fig. 6A and Fig. 6B and shows schematic circuit diagrams of a half-bridge circuit consisting of two diodes (A) and a boost circuit consisting of two diodes (B). Fig. Figure 7 shows a schematic diagram of a circuit with a semiconductor transistor connected to a capacitor in a so-called Miller capacitor configuration. Fig. Figure 8 shows a schematic diagram of a circuit with a semiconductor transistor and a capacitor connected between source and drain. Fig. Figure 9 shows a schematic diagram of a circuit with a semiconductor transistor and an RC element connected between source and drain in a so-called RC snubber configuration. Fig. 10 shows a schematic diagram of a circuit with a semiconductor transistor, an RC element connected between source and drain and a parallel diode in a so-called RC snubber configuration with discharge. Fig. 11 shows a schematic diagram of a circuit with a semiconductor transistor connected to a clamping resistor. Fig. 12 includes the Fig. 12A to 12C and shows top and side view illustrations of a non-isolated SMD TSC semiconductor package (A), an isolated SMD TSC semiconductor package, and an SMD BSC semiconductor package (C). DESCRIPTION OF THE EMBODIMENTS

[0009] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which is shown by way of illustration certain embodiments in which the disclosure may be practiced. In this context, directional terms such as "top," "bottom," "front," "back," "forward," "rear," etc., are used with reference to the orientation of the described figure(s). Since components of the embodiments can be positioned in a number of different orientations, the directional terminology is for the purpose of illustration and is not limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure.The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0010] It is understood that the features of the various exemplary embodiments described herein may be combined with one another unless expressly stated otherwise.

[0011] As used in this description, the terms "connected," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" are not intended to imply that the elements or layers must be in direct contact with each other; intermediate elements or layers may be provided between the "connected," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" elements. However, according to the disclosure, the above terms may optionally also have the specific meaning that the elements or layers are in direct contact with each other, i.e., that no intermediate elements or layers are provided between the "connected," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" elements.

[0012] Furthermore, the word "over," used in reference to a part, element, or layer of material formed or disposed "over" a surface, may be used herein to mean that the part, element, or layer of material is disposed "indirectly upon" (e.g., placed, formed, deposited, etc.) the implied surface, with one or more additional parts, elements, or layers disposed between the implied surface and the part, element, or layer of material. However, the word "over," used in reference to a part, element, or layer of material formed or disposed "over" a surface, may optionally also have the specific meaning that the part, element, or layer of material is disposed "directly upon," i.e., in direct contact with, the implied surface.

[0013] Furthermore, the word "exemplary" is used herein to serve as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as being advantageous over other aspects or designs. Rather, the use of the word "exemplary" is intended to illustrate concepts in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated or clear from context, "X substitutes A or B" means any of the natural, inclusive permutations. That is, if X substitutes A, X substitutes B, or X substitutes both A and B, then "X substitutes A or B" is satisfied in each of the foregoing cases.Furthermore, the articles "a" and "an," as used in this application and the appended claims, can generally be interpreted to mean "one or more," unless otherwise stated or it is clear from the context that they refer to a sinusoidal shape. Also, at least one of A and B, or the like, generally means A or B, or both A and B.

[0014] While a particular feature or aspect of an embodiment of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for a given or particular application. To the extent that the terms "including," "having," "with," or other variations thereof are used either in the detailed description or in the claims, these terms, like the term "comprising," are to be construed as encompassing. Furthermore, it is to be understood that embodiments of the disclosure may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming means. Also, the term "exemplary" is to be construed merely as an example and not as the best or optimum.It should also be noted that for the sake of simplicity and better understanding, the features and / or elements illustrated herein are shown with certain dimensions relative to each other and that the actual dimensions may vary significantly from those illustrated here. DETAILED DESCRIPTION

[0015] Fig. 1 shows a perspective view of a semiconductor package with two semiconductor transistors forming a half-bridge circuit according to a first embodiment.

[0016] Fig. 1 shows in particular a semiconductor package 10 comprising a package body 1, a first die pad 2 which is at least partially encapsulated in the package body 1, wherein the first die pad 2 has a first main surface and a second main surface opposite the first main surface. Fig. 1, the first main surface is the upper main surface and the second main surface is the lower main surface of the first die pad 2. The semiconductor package 10 further comprises a second die pad 3 which is at least partially encapsulated in the package body 1, wherein the second die pad 3 has a first main surface and a second main surface opposite the first main surface. In the embodiment shown in Fig. 1, the first main surface is the upper main surface and the second main surface is the lower main surface of the second die pad 3.

[0017] The semiconductor package 10 further comprises a first semiconductor die 4 encapsulated in the package body 1 and arranged on the first die pad 2, wherein the first semiconductor die 4 comprises a source pad 4A arranged on the first main surface of the first semiconductor die 4 and a drain pad (not visible) arranged on the second main surface of the first semiconductor die 4, wherein the first semiconductor die 4 is connected to the drain pad with the first die pad 2, i.e. the die 4 is a so-called source-up die or drain-down die.

[0018] The semiconductor package 10 further comprises a second semiconductor die 5 encapsulated in the package body 1 and arranged on the second die pad 3, the second semiconductor die 5 comprising a source pad 5A arranged on the first main surface of the second semiconductor die 5 and a drain pad (not visible) arranged on the second main surface of the second semiconductor die 5, the second semiconductor die 5 being connected to the second die pad 3 via the drain pad.

[0019] The semiconductor package 10 further comprises a plurality of first conductors 6 and a plurality of second conductors 7. Both the first conductors 6 and the second conductors 7 have inner embedded sections, commonly referred to as conductor fingers. The conductor fingers have optionally been refined by special coatings compared to the outer sections of the conductors and thus have improved conductivity properties compared to the outer sections. An electrical conductor 8 is connected between the conductor fingers of two conductors 6.1 of the plurality of first conductors 6 and a conductor finger of one of the plurality of second conductors 7.

[0020] A thick bonding wire is connected between the source pad 4A and the electrical connector 8 and thus also to the two conducting fingers of the two lines 6.1 of the first plurality of lines 6. The four conductors 7 of the second plurality of second conductors 7 are all connected to the drain pad of the second semiconductor die 5, and the electrical connector 8 is connected to all conducting fingers of the second conductors 7. The electrical conductor 8 is completely encapsulated in the housing body 1. Those skilled in the art should understand that the thick bonding wire can be replaced by a clip or a tape or other suitable bonding means. In a further embodiment, the conductors 7 are physically led out of the second die pad 3, i.e., the conductors 7 and the die pad 3 are made of a single piece of metal. This greatly reduces the resistance and / or inductance between the conductors 7 and the die pad 3.In another embodiment, the electrical connector 8, the conductors 7, and the die pad 3 are fabricated from a single piece of metal, so that the resistance and / or inductance from the source line 6 to the top of the second die pad 3 is greatly reduced. Therefore, the inductance from the source pad 4A of the first die to the drain pad of the second die is greatly reduced.

[0021] The semiconductor package 10 according to the embodiment of Fig. 1 further comprises a lead frame, wherein the first die pad 2, the second die pad 3, the at least one first line 6, the at least one second line 7 and the electrical connector 8 are part of the lead frame.

[0022] The plurality of first conductors 6 also includes a conductor 6.2 connected to the gate pad of the first semiconductor thief 4 via a bonding wire, and an optional conductor 6.3 connected to an optional source sense pad of the first semiconductor thief 4 via a bonding wire.

[0023] Only a part of the conductors 6 of the first plurality of conductors 6, namely the source conductors 6.1, are connected to the electrical connector 8, while all conductors 7 of the second plurality of conductors 7 are drain conductors, so that preferably all of these conductors 7 should be connected to the electrical connector 8.

[0024] The semiconductor package 10 further comprises a third plurality of conductors 12, all connected to the drain pad of the first semiconductor die 4. And the semiconductor package 10 further comprises a fourth plurality of conductors 9, which comprises conductors 9.1 connected to a metal rod (lead finger) 11, which is connected to the source pad 5A of the second semiconductor die 5 by a thick bond wire. The fourth plurality of conductors 9 further comprises a conductor 9.2, which is connected to the gate pad of the second semiconductor chip 5 via a bond wire, and a conductor 9.3, which is connected to the source sense pad of the second semiconductor chip 5 via a bond wire. A person skilled in the art should understand that the so-called "metal rod 11" may have a different shape, i.e., it does not necessarily have to be longer when extending from the second die pad 3 to the first die pad 2, as in Fig. 1. A so-called "fused line" is also possible, meaning there is a single line pad connecting all source lines, and the bond wire / clip can land on the fused line. It is also possible for the multiple source lines to be separated from each other, so that the clip connects the source pad of the second die to all source lines (9.1).

[0025] According to the embodiment of the semiconductor package 10 of Fig. 1, each of the first semiconductors 4 and the second semiconductors 5 comprises a semiconductor transistor, in particular a power semiconductor transistor, wherein the first contact pad 4A of the first semiconductor 4 is a source pad 4A and the second contact pad of the first semiconductor 4 is a drain pad, and the second contact pad 5A of the second semiconductor 5 is a source pad 5A and the second contact pad of the second semiconductor 5 is a drain pad.

[0026] Furthermore, the first semiconductor die 4 may comprise a first power transistor forming a high-side switch of a half-bridge circuit, and the second semiconductor die 5 may comprise a second power transistor connected in series with the first power transistor 4 and forming a low-side switch of the half-bridge circuit.

[0027] In general, the semiconductor dies described here can be made from an elemental semiconductor material (e.g., Si) or from a wide bandgap or compound semiconductor material (e.g., SiC, GaN, SiGe, GaAs) and could be incorporated into electronic components such as an IGBT, an SFET, a CoolMOS, or a diode. In particular, as already mentioned, each of the semiconductor dies arranged on the first die pad 2 and the second die pad 3 can contain or correspond to a power semiconductor device and can therefore be referred to as a power semiconductor die. The term “power semiconductor die” can refer here to a semiconductor die that has at least one of the two properties of high-voltage blocking or high current-carrying capacity. A power semiconductor die can be designed for high currents with a maximum current value of several amperes, such as10 A, or a maximum current value of up to or over 1000 A. Likewise, voltages associated with such current values can range from a few volts to several tens, hundreds, or even thousands of volts.

[0028] In the present case, the power semiconductors can be used in particular in half-bridge configurations and / or boost configurations, such as buck-boost converters or boost converters. These configurations can be used for industrial products, for example, in one or more integrated servo motor converters or PFC (Power Factor Correction) boost stages. The addressed applications include automotive applications, industrial drive applications, EV (Electric Vehicle) chargers, etc. Exemplary circuits configured to be implemented in a semiconductor package according to the present disclosure are described in connection with the Fig. 4 to 11 shown and described.

[0029] The package body 1 can be made from a material comprising at least one mold compound, an epoxy, a filled epoxy, a glass fiber-filled epoxy, an imide, a thermoplastic, a thermosetting polymer, a polymer blend, a laminate, etc. Various techniques can be used to encapsulate the components of the assembly in the package body 2, e.g., at least one of the following: transfer molding, injection molding, powder molding, liquid molding, map molding, lamination, etc. In one non-limiting example, a mold compound forming the package body 1 can have a CTI (Comparative Tracking Index) value of greater than about 600 V.

[0030] A key advantage of the present disclosure is the fact that the electrical connection between the terminals of the two semiconductors is already established in the semiconductor package. It therefore does not have to be implemented on the customer side, i.e., in the customer substrate, such as a printed circuit board. The customer thereby gains a certain degree of freedom to use an upper portion of the printed circuit board for other purposes, e.g., to mount a cooling device there. A further advantage is that, since the connection between the low-side switch and the high-side switch is established within the package and, moreover, via a wider internal metal bridge, the resistance and / or inductance between the high-side switch and the low-side switch is greatly reduced compared to an external connection on the printed circuit board.

[0031] The first and second semiconductor transistor dies 4 and 5 can each have a corresponding gate pad on their respective first main surfaces. The semiconductor package 10 can then further comprise at least one gate driver device arranged on one or both conductors 6.2 or 9.2, namely on the conductors connected to the respective gate pads by bond wires. The semiconductor package can in particular comprise two gate driver elements for the two semiconductor transistor dies 4 and 5, one of which is arranged on a line 6.2 of the first plurality of lines and the other on a line 9.2 of the third plurality of lines. These gate driver devices can also be embedded in the housing body 1.

[0032] It should further be noted that the package body 1 includes a groove 1A formed in an upper surface of the package body 1 between the first chip 2 and the second chip 3. The groove 1A serves the purpose of reducing or, in the best case, avoiding harmful leakage currents between the first and second semiconductor dies 4 and 5 by increasing a creepage distance between them.

[0033] Other types of semiconductors may also be used as the first and second semiconductors, and more than two semiconductors may be implemented in the semiconductor package, as shown below.

[0034] Fig. 2 shows a perspective view of an unpackaged semiconductor package with two semiconductor transistors forming a half-bridge circuit according to a second embodiment, wherein one of the dies is arranged in a drain-down configuration and the other in a source-down configuration.

[0035] Specifically, Fig. 2 shows a semiconductor package 20 which corresponds to the semiconductor package 10 of Fig. 1, so that most of the reference numerals from Fig. 1 and with regard to the function of the corresponding elements, reference is made to the above description. In particular, the first semiconductor 4 is in a drain-down configuration as in Fig. 1 arranged.

[0036] A change compared to Fig. 1 is that the second semiconductor die 25 is arranged in a source-down configuration. Accordingly, the drain pad 25A of the second semiconductor chip 25 is arranged on an upper surface thereof, and the conductors 27 of a third plurality of conductors are all connected to a clip 22 that is connected to the drain pad 25A. The source pad, the gate pad, and the source sense pad are arranged on a lower surface of the semiconductor chip 25 and are shown in FIG. Fig. 2. The semiconductor package 10 further comprises a fourth plurality of conductors 29, which comprise conductors 29.1 connected to a metal land 21 (conductor finger) connected to the source pad of the second semiconductor die 25 by an interconnect, e.g., a copper clip or a thick bond wire (not shown). The fourth plurality of conductors 29 further comprises a conductor 29.2 connected to the gate pad of the second semiconductor die 25 via a bond wire, and a conductor 29.3 connected to the source sense pad of the second semiconductor die 25 via a bond wire. In this combined source-up die and source-down die configuration, the drain lines 27 are not physically connected to the second die pad to which the second die 25 is attached, and the electrical connector 8 connecting the source lines 6.1 of the high-side switch and the drain lines 27 of the low-side switch may be similar to the electrical connector 8 in some embodiments of . Fig. 1 should be implemented.

[0037] Fig. 3 shows a perspective view of the semiconductor package of Fig. 2 in a housed configuration. Fig. 3 thus shows the housing body 1, which in Fig. 2 was only shown in outline.

[0038] Furthermore, a third embodiment is possible in which both the first and the second semiconductor die use a source-down configuration, i.e., the source terminals of the two dies are in direct contact with the two die pads and the source terminal of the high-side switch is connected to the source lines that actually physically extend from the die pad, then the internal electrical conductor / internal electrical bridge physically connects at least one source terminal to the at least one drain terminal of the low-side switch, and there wires or a clip or other connection connect the drain lines to the drain terminal of the second die (source-down die), and the source terminal of the second die is physically connected to the die pad and is further physically connected to the source lines of the low-side switch.

[0039] Furthermore, a fourth configuration is possible in which a source-down configuration is used for the first semiconductor die, i.e., the high-side switch, and a drain-down configuration is used for the second semiconductor die, i.e., the low-side switch. For example, the source terminal of the first semiconductor die is arranged directly on the first die pad, which is physically connected to the source conductors. The drain conductors can be electrically connected to the drain terminal of the first semiconductor die by a clip, wires, or other connection. Then, the internal electrical conductor / bridge physically connects the source line of the high-side switch to at least one drain line of the low-side switch, with the drain lines actually being the physical extension of the second semiconductor die pad.For the second semiconductor die, its source terminal points upwards and is connected to the source lines of the low-side switch by a clip or wires or other means.

[0040] Fig. 4 includes Fig. 4A and Fig. 4B and shows schematic circuit diagrams of a half-bridge circuit consisting of two transistors (A) and a boost circuit consisting of two transistors (B).

[0041] Fig. Figure 4A shows a schematic diagram of a half-bridge circuit consisting of two semiconductor transistors. A first semiconductor transistor, acting as a high-side (HS) switch, is connected between a voltage source VCC and a switching node, and a second semiconductor transistor, acting as a low-side (LS) switch, is connected between the switching node and ground. The various possible configurations regarding source down and drain down of the first and second transistors were described above in connection with the Fig. 1 to 3.

[0042] Further embodiments are shown and described below. It will be clear that embodiments are possible in which, instead of the second semiconductor, the embodiments of the Fig. One to three other electronic or electrical components are used and can be connected to the first semiconductor. These components could be, for example, semiconductor diodes, capacitors, resistors, or RC elements.

[0043] Fig. Figure 4B shows a schematic diagram of a boost circuit consisting of a semiconductor transistor and a semiconductor diode. A semiconductor transistor has its source coupled to ground and its drain coupled to a switching node, and the switching node is coupled between a semiconductor diode and the semiconductor transistor.

[0044] Fig. 5 includes Fig. 5A and Fig. 5B and shows schematic circuit diagrams of a nested half-bridge circuit (A) and a nested boost circuit (B).

[0045] Fig. Figure 5A shows a schematic diagram of a nested half-bridge circuit with four semiconductor transistors. A first semiconductor transistor is connected between a voltage source VCC and a first switching node, and a second semiconductor transistor is connected between the first switching node and ground. A third semiconductor transistor is connected between the voltage source VCC and a second switching node connected to the first switching node, and a fourth semiconductor transistor is connected between the second switching node and ground.

[0046] Fig. Figure 5B shows a schematic diagram of a nested boost circuit with two semiconductor transistors and two semiconductor diodes. A first semiconductor transistor is connected between a first switching node and ground, the first switching node is connected to a first semiconductor diode and the first semiconductor transistor, a second semiconductor transistor is connected between a second switching node connected to the first switching node and ground, and the second switching node is connected between a second semiconductor diode and the second semiconductor transistor. An embodiment of the circuit of Fig. 5B may be implemented by using internal electrical connectors / conductors / bridges similar to those in some embodiments of the Fig. 1~3 can be implemented, e.g., one electrical connector internally connects the drain conductors of the first transistor and the anode of the first diode D1, and another electrical connector internally connects the drain conductors of the second transistor and the anode of the second diode D2, and all of these electrical connectors are embedded within the semiconductor package.

[0047] Fig. 6 includes Fig. 6A and Fig. 6B and shows schematic circuit diagrams of a half-bridge circuit consisting of two diodes (A) and a boost circuit consisting of two diodes (B).

[0048] Fig. Figure 6A shows a schematic circuit diagram with two semiconductor diodes. A first semiconductor diode is connected to a voltage source VCC by its cathode terminal and to a switching node by its anode terminal, and a second semiconductor diode is connected to the switching node by its cathode terminal and to ground by its anode terminal.

[0049] Fig. Figure 6B shows a schematic circuit diagram with four semiconductor diodes. A first semiconductor diode is connected by its cathode terminal to a voltage source VCC and by its anode terminal to a first switching node, a second semiconductor diode is connected by its cathode terminal to the first switching node and by its anode terminal to ground, a third semiconductor diode is connected by its cathode terminal to the voltage source VCC and by its anode terminal to a second switching node connected to the first switching node, and a fourth semiconductor diode is connected by its cathode terminal to the second switching node and by its anode terminal to ground. Similarly, in the embodiments of Fig. 6A and Fig. 6B similar internal electrical connectors can be used to connect the anode terminal of one diode directly to the cathode terminal of another diode or to two cathode terminals of two parallel diodes, etc.

[0050] Fig. Figure 7 shows a schematic diagram of a circuit with a semiconductor transistor connected to a capacitor in a so-called Miller capacitor configuration. A semiconductor transistor is coupled with its drain to a first terminal of a Miller capacitor and with its gate to a second terminal of the Miller capacitor. A semiconductor diode is also connected in parallel with the semiconductor transistor.

[0051] Fig. Figure 8 shows a schematic diagram of a circuit with a semiconductor transistor and a capacitor connected between its source and drain. Here, a semiconductor transistor is coupled by its drain to a first terminal of a capacitor and by its source to a second terminal of the capacitor.

[0052] Fig. Figure 9 shows a schematic diagram of a circuit with a semiconductor transistor and an RC element connected between source and drain in a so-called RC snubber configuration. A semiconductor transistor is coupled with its drain to a first terminal of a capacitor and with its source to a first terminal of a resistor. A second terminal of the resistor is then coupled to a second terminal of the capacitor. RC attenuators are known to be used to suppress a rapid voltage rise across a transistor.

[0053] Fig. Figure 10 shows a schematic diagram of a circuit with a semiconductor transistor, an RC element connected between source and drain, and a parallel-connected diode in a so-called RC snubber with discharge configuration. Similar to Fig. 9, a semiconductor transistor is coupled with its drain to a first terminal of a capacitor and with its source to a first terminal of a resistor. A second terminal of the resistor is then coupled to a second terminal of the capacitor. Furthermore, a diode is connected in parallel with the resistor. The capacitor's ability to absorb a surge current is more effective than in the embodiment of Fig. 9, because the surge current flows through the diode.

[0054] Fig. Figure 11 shows a schematic diagram of a circuit with a semiconductor transistor connected to a clamping resistor. As is well known, the switching behavior of the transistor can be influenced in any way by selecting a suitable clamping resistor.

[0055] Fig. 12 includes the Fig. 12A to 12C and shows representations of an SMD TSC non-isolated semiconductor package (A), an SMD TSC isolated semiconductor package and an SMD BSC semiconductor package (C) in top view and side view.

[0056] Fig. Figure 12A shows a top view and a side view of a semiconductor package which is in principle similar to that shown in Fig. 1 and described above. The semiconductor package of Fig. 12A is implemented in the form of a surface-mount, top-cooled, non-isolated semiconductor package with external gullwing conductors. The first or top surfaces of the two semiconductor dies are uncovered and open to the outside. This would allow the mounting of a heat sink on top of the semiconductor package, with the heat sink thus being in direct contact with the first or top surfaces of the first and second semiconductor dies.

[0057] Fig. Figure 12B shows a top view and a side view of a semiconductor package that is in principle similar to that shown in Fig. 1 and described above. The semiconductor package of Fig. 12B is implemented in the form of a surface-mount, top-cooled, insulated semiconductor package with external gull-wing conductors. The first or upper surfaces of the two semiconductor dies are covered by an electrically insulating but thermally conductive layer and are thus not exposed to the outside. This would also allow the attachment of a heat sink to the top of the semiconductor package, whereby the heat sink is thus not in direct contact with the first or upper surface of the first and second semiconductor dies, but effectively dissipates the heat by conduction through the electrically insulating layer.

[0058] Fig. Figure 12C shows a top view and a side view of a semiconductor package as described above in connection with Fig.1. The semiconductor package is configured as a surface-mounted, bottom-cooled semiconductor package, meaning that heat is dissipated via the die pad. EXAMPLES

[0059] Specific examples of the present disclosure are described below.

[0060] Example 1 is a semiconductor package comprising a package body, a first die pad at least partially encapsulated in the package body, the first die pad having a first main surface and a second main surface opposite the first main surface, a second die pad at least partially encapsulated in the package body, the second die pad having a first main surface and a second main surface opposite the first main surface, a first semiconductor die at least partially encapsulated in the package body and disposed on the first die pad, the first semiconductor die comprising a first contact pad disposed on the first main surface of the first semiconductor die and a second contact pad disposed on the second main surface of the first semiconductor die, the first semiconductor die being connected to the first die pad by the second contact pad, a further component,which is at least partially encapsulated in the housing body and arranged on the second die pad, wherein the further component comprises a first contact pad arranged on the first main surface of the further component and a second contact pad arranged on the second main surface of the further component, wherein the further component is connected to the second die pad by means of the second contact pad, at least one first conductor connected to the first contact pad of the first semiconductor chip and extending out of the housing body, at least one second conductor connected to the second contact pad of the further component and extending out of the housing body, and an electrical conductor connected between the at least one first conductor and the at least one second conductor, wherein the electrical conductor is completely encapsulated in the housing body.

[0061] Example 2 is the semiconductor package of Example 1, further comprising a lead frame, wherein the first die pad, the second die pad, the at least one first lead, the at least one second lead, and the electrical connector are part of the lead frame.

[0062] Example 3 is the semiconductor package according to example 1 or 2, further comprising a plurality of first conductors connected to the first contact pad of the first semiconductor chip and a plurality of second conductors, wherein the electrical conductor is connected between at least one of the plurality of first conductors and at least one of the plurality of second conductors.

[0063] Example 4 is the semiconductor package of Example 3, wherein the electrical conductor is connected between more than one of either the plurality of first conductors or the plurality of second conductors.

[0064] Example 5 is the semiconductor package according to any one of the preceding examples, wherein the thickness of the electrical conductor is in a range from 100 µm to 1 mm.

[0065] Example 6 is the semiconductor package according to any one of the preceding examples, wherein the first semiconductor chip comprises a first semiconductor transistor die and the further component comprises a second semiconductor transistor die, wherein the first contact pad of the first semiconductor chip is a source pad and the second contact pad of the first semiconductor chip is a drain pad and the first contact pad of the second semiconductor chip is a source pad and the second contact pad of the second semiconductor chip is a drain pad.

[0066] Example 7 is the semiconductor package according to any one of the preceding examples, wherein the first semiconductor chip comprises a first semiconductor transistor die and the further component comprises a second semiconductor transistor die, wherein the first contact pad of the first semiconductor chip is a source pad, and the second contact pad of the first semiconductor chip is a drain pad, and the first contact pad of the second semiconductor chip is a drain pad, and the second contact pad of the second semiconductor chip is a source pad.

[0067] Example 8 is the semiconductor package according to any one of the preceding examples, wherein the first semiconductor chip comprises a first semiconductor transistor die and the further device comprises a second semiconductor transistor die, wherein the first contact pad of the first semiconductor chip is a drain pad, and the second contact pad of the first semiconductor chip is a source pad, and the first contact pad of the second semiconductor chip is a source pad, and the second contact pad of the second semiconductor chip is a pad therein.

[0068] Example 9 is the semiconductor package according to any one of the preceding examples, wherein the first semiconductor chip comprises a first semiconductor transistor die and the further component comprises a second semiconductor transistor die, wherein the first contact pad of the first semiconductor chip is a drain pad, and the second contact pad of the first semiconductor chip is a source pad, and the first contact pad of the second semiconductor chip is a drain pad, and the second contact pad of the second semiconductor chip is a source pad.

[0069] Example 10 is the semiconductor package according to any one of the preceding examples, wherein both the first semiconductor die and the second semiconductor die comprise a power semiconductor transistor.

[0070] Example 11 is the semiconductor package according to any one of the preceding examples, wherein the first semiconductor chip comprises a first power transistor forming a low-side switch of a half-bridge circuit, and the further component comprises a second semiconductor chip comprising a second power transistor connected in series with the first power transistor and forming a high-side switch of the half-bridge circuit.

[0071] Example 12 is the semiconductor device according to any one of Examples 1 to 5, wherein the first semiconductor device comprises a semiconductor diode and the further device comprises a second semiconductor diode comprising a semiconductor diode.

[0072] Example 13 is the semiconductor package of Example 12, wherein the first semiconductor device comprises a power transistor forming part of a booster configuration, and the further device comprises a second semiconductor device comprising a power diode connected in series with the power transistor and forming part of the booster configuration.

[0073] Example 14 is the semiconductor package of Example 13, wherein the booster configuration comprises one or more of a PFC boost converter, a hexa-DPAK PFC boost, or an octa-DPAK PFC boost.

[0074] Example 15 is the semiconductor device package according to any one of Examples 1 to 5, wherein the further device comprises one or more of a passive device, a resistor, a capacitor, and an RC element.

[0075] Example 16 is the semiconductor package according to any one of the preceding examples, wherein the second main surface of the first die pad and the second main surface of the further component are completely encapsulated in the package body.

[0076] Example 17 is the semiconductor package according to any one of the preceding examples, wherein the second main surface of the first die pad and the second main surface of the further component are not completely encapsulated in the package body.

[0077] Example 18 is the semiconductor package according to any one of the preceding examples, wherein the first main surface of the first die pad and the first main surface of the second die pad are at least partially uncovered by the package body.

[0078] Example 19 is the semiconductor device of any one of Examples 6 to 9, further comprising at least one gate drive element disposed on one of the conductors connected to a gate of a semiconductor transistor die.

[0079] Example 20 is a lead frame comprising a first die pad having a first main surface and a second main surface opposite the first main surface, a second die pad having a first main surface and a second main surface opposite the first main surface, at least one first conductor, at least one second conductor, and an electrical conductor connected between the at least one first conductor and the at least one second conductor.

[0080] Example 21 is the lead frame of Example 20, further comprising a plurality of first conductors and a plurality of second conductors, wherein the electrical conductor is connected between at least one of the plurality of first conductors and at least one of the plurality of second conductors.

[0081] Example 22 is the lead frame of Example 21, wherein the electrical conductor is connected between more than one of the plurality of first conductors or the plurality of second conductors.

[0082] Example 23 is the lead frame of any one of Examples 20 to 22, wherein the thickness of the electrical conductor is in a range of 100 µm to 1 mm.

[0083] It should be added that the embodiments described above can also be combined with advanced insulation concepts developed by the applicant. In addition to the use of standard molded joints, these concepts include the additional application of further thermally conductive, electrically insulating components such as insulation layers between the housing or lead frame and a heat sink, as well as the use of DCB (Direct Bonded Copper), AMB (Active Metal Braze), or IMS (Insulated Metal Substrate) substrates.

[0084] Although specific embodiments have been shown and described herein, those skilled in the art will recognize that the specific embodiments shown and described may be replaced with a variety of alternative and / or equivalent implementations without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific embodiments described herein. Therefore, this disclosure is intended to be limited only by the claims and their equivalents. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] DE 60214897 T2

[0002] DE 102018112477 A1

[0002]

Claims

[1] Semiconductor package (10; 20), comprising: a housing body (1); a first die pad (2) at least partially encapsulated in the package body (1), the first die pad (2) having a first main surface and a second main surface opposite the first main surface; a second die pad (3) at least partially encapsulated in the package body (1), the second die pad (3) having a first main surface and a second main surface opposite the first main surface; a first semiconductor die (4) which is at least partially encapsulated in the package body (1) and arranged on the first die pad (2), wherein the first semiconductor die (4) has a first contact pad (4A) arranged on the first main surface of the first semiconductor die (4) and a second contact pad arranged on the second main surface of the first semiconductor die (4), wherein the first semiconductor die (4) is connected to the first die pad (2) by means of the second contact pad; a further component (5) which is at least partially encapsulated in the housing body (1) and arranged on the second die pad (3), wherein the further component (5) comprises a first contact pad (5A) arranged on the first main surface of the further component (5) and a second contact pad arranged on the second main surface of the further component (5), wherein the further component (5) is connected to the second die pad (3) by means of the second contact pad; at least one first line (6.1) connected to the first contact pad (4A) of the first semiconductor die (4) and extending out of the housing body (1); at least one second conductor (7) connected to the second contact pad of the further device (5) and extending out of the housing body (1); and an electrical conductor (8) connected between the at least one first conductor (6.1) and the at least one second conductor (7), wherein the electrical conductor (8) is completely encapsulated in the housing body (1); wherein the second main surface of the first die pad (4) and the second main surface of the second die pad (3) are not completely encapsulated in the housing body (1). [2] The semiconductor package (10; 20) of claim 1, further comprising a lead frame, wherein the first die pad (2), the second die pad (3), the at least one first conductor (6.1), the at least one second conductor (7) and the electrical connector (8) are part of the lead frame. [3] Semiconductor package (10; 20) according to claim 1 or 2, further comprising a plurality of first conductors (6.1) connected to the first contact pad (4A) of the first semiconductor die (4), and a plurality of second conductors (7), wherein the electrical conductor (8) is connected between at least one of the plurality of first conductors (6.1) and at least one of the plurality of second conductors (7). [4] Semiconductor package (10; 20) according to claim 3, wherein the electrical conductor (8) is connected between more than one of the plurality of first conductors (6.1) or the plurality of second conductors (7). [5] Semiconductor package (10; 20) according to one of the preceding claims, wherein a thickness of the electrical conductor (8) is in a range of 100 µm to 1 mm. [6] Semiconductor package (10) according to one of the preceding claims, wherein the first semiconductor chip (4) comprises a first semiconductor transistor (4) and the further device (5) comprises a second semiconductor transistor (5), wherein the first contact pad (4A) of the first semiconductor chip (4) is a source pad, and the second contact pad of the first semiconductor chip (4) is a drain pad, and the first contact pad (5A) of the second semiconductor chip (5) is a source pad and the second contact pad of the second semiconductor chip (5) is a drain pad. [7] Semiconductor package (20) according to one of the preceding claims, wherein the first semiconductor chip (4) comprises a first semiconductor transistor (4) and the further device (5) comprises a second semiconductor transistor (5), wherein the first contact pad (4A) of the first semiconductor chip (4) is a source pad, and the second contact pad of the first semiconductor chip (4) is a drain pad, and the first contact pad (5A) of the second semiconductor chip (5) is a drain pad and the second contact pad of the second semiconductor chip (5) is a source pad. [8] Semiconductor package according to one of the preceding claims, wherein the first semiconductor chip (4) comprises a first semiconductor transistor (4) and the further component (5) comprises a second semiconductor transistor (5), wherein the first contact pad (4A) of the first semiconductor chip (4) is a drain pad, and the second contact pad of the first semiconductor chip (4) is a source pad, and the first contact pad (5A) of the second semiconductor chip (5) is a source pad and the second contact pad of the second semiconductor chip (5) is a pad therein. [9] Semiconductor package according to one of the preceding claims, wherein the first semiconductor chip (4) comprises a first semiconductor transistor (4) and the further component (5) comprises a second semiconductor transistor (5), wherein the first contact pad (4A) of the first semiconductor chip (4) is a drain pad, and the second contact pad of the first semiconductor chip (4) is a source pad, and the first contact pad (5A) of the second semiconductor chip (5) is a drain pad and the second contact pad of the second semiconductor chip (5) is a source pad. [10] Semiconductor package (10; 20) according to one of the preceding claims, wherein both the first semiconductor die (4) and the second semiconductor die (5) comprise a power semiconductor transistor. [11] Semiconductor package (10; 20) according to one of the preceding claims, wherein the first semiconductor (4) comprises a first power transistor forming a low-side switch of a half-bridge circuit, and the further component (5) comprises a second semiconductor chip (5) which comprises a second power transistor which is connected in series with the first power transistor (4) and forms a high-side switch of the half-bridge circuit. [12] Semiconductor package according to one of claims 1 to 5, wherein the first semiconductor chip (4) comprises a semiconductor diode and the further component (5) comprises a second semiconductor chip (5) comprising a semiconductor diode. [13] Semiconductor package according to claim 12, wherein the first semiconductor (4) comprises a power transistor forming part of a booster configuration, and the further component (5) comprises a second semiconductor die (5) comprising a power diode connected in series with the power transistor and forming part of the booster configuration. [14] The semiconductor package of claim 13, wherein the booster configuration comprises one or more of a PFC boost converter, a hexa-DPAK PFC boost converter, or an octa-DPAK PFC boost converter. [15] The semiconductor package according to any one of claims 1 to 5, wherein the further component (5) comprises one or more of a passive component, a resistor, a capacitor and an RC element. [16] Semiconductor package (10) according to one of the preceding claims, wherein the first main surface of the first die pad (4) and the first main surface of the second die pad (5) are at least partially uncovered by the housing body (1). [17] Semiconductor package (10; 20) according to one of claims 6 to 9, further comprising at least one gate driver device arranged on one of the conductors (6.2, 9.2) connected to a gate of a semiconductor transistor die (4, 5). [18] Ladder frame, comprising a first die pad (2) having a first main surface and a second main surface opposite the first main surface; a second die pad (3) having a first main surface and a second main surface opposite the first main surface; at least one first conductor (6.1); at least one second conductor (7); and an electrical conductor (8) connected between the at least one first conductor (6.1) and the at least one second conductor (7), wherein the second main surface of the first die pad (4) and the second main surface of the second die pad (3) are not completely encapsulated in a housing body (1). [19] The leadframe of claim 18, further comprising a plurality of first conductors (6.1) and a plurality of second conductors (7), wherein the electrical conductor (8) is connected between at least one of the plurality of first conductors (6.1) and at least one of the plurality of second conductors (7). [20] Lead frame according to claim 19, wherein the electrical conductor (8) is connected between more than one of the plurality of first conductors (6.1) or the plurality of second conductors (7). [21] Lead frame according to one of claims 18 to 20, wherein a thickness of the electrical conductor (8) is in a range of 100 µm to 1 mm.

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