Electronic bridge housing with integrated photonic channel interface outside the bridge

Abstract

Circuit housing, including: a photonic interposer; an electric interposer; a die, including an analog / mixed-signal section and an electronic section, wherein the die partially overlaps both the photonic interposer and the electrical interposer, the analog / mixed-signal section is connected to the photonic interposer, and the electronic section is connected to the electrical interposer; and a plurality of electrical connections between the photonic interposer and the die.

Description

RELATED REGISTRATIONS

[0001] This application claims the priority and benefit of U.S. preliminary patent applications No. 63 / 437,639, filed on January 6, 2023, and No. 63 / 437,641, and this application claims the priority and benefit of U.S. preliminary patent application No. 63 / 437,641, filed on January 6, 2023. This application further claims the priority of U.S. patent application No. 18 / 217,898, filed on July 3, 2023, which is a partial continuation of U.S. patent application No. 18 / 076,196, filed on December 6, 2022, and a partial continuation of U.S. patent application No. 18 / 076,210, filed on December 6, 2022, and this application claims the priority and benefit of U.S. preliminary patent application No. 63 / 392,475, filed on July 26, 2022. All these applications are hereby incorporated in their entirety by reference. BACKGROUND

[0002] The demand for computing power for artificial intelligence (AI), such as machine learning (ML) and deep learning (DL), is growing faster than it can be met by increases in available computing capacity. This rising demand, coupled with the increasing complexity of AI models, necessitates connecting many dies into a system where they can exchange data with low latency and high speed. SUMMARY

[0003] This summary serves to introduce a selection of concepts that are described in more detail below. This summary is neither intended to identify principal or essential features of the claimed subject matter, nor to serve as an aid to limiting the scope of protection of the claimed subject matter.

[0004] Additional features and advantages of embodiments of the disclosure are set forth in the following description and are partly evident from the description or can be learned by carrying out such embodiments. The features and advantages of such embodiments can be realized and achieved by means of the means and combinations specifically specified in the appended claims. These and other features become clearer from the following description and the appended claims or can be learned by carrying out the embodiments set forth below.

[0005] At least one implementation of the techniques described herein relates to a circuit package comprising: a photonic interposer; a second interposer; a die that partially overlaps and is connected to the photonic and second interposer.

[0006] In some implementations, the die is a first die. In some implementations, the die is electrically connected to both the photonic and the second interposer. In some implementations, the die includes an analog / mixed-signal section to provide a first processing element for sending and / or receiving data using the photonic interposer, and a purely electrical section to provide a second processing element for sending and / or receiving data using the second interposer.

[0007] In some implementations, the die partially overlaps both the photonic and the second interposer in the vertical direction. In some implementations, the second interposer is a non-photonic interposer. In some implementations, the second interposer is an electrical interposer.

[0008] In some implementations, the second interposer is a second photonic interposer. In some implementations, one or more of the photonic interposer and the second interposer are photonic integrated circuits. In some implementations, the second interposer is an SI interposer. In some implementations, the second interposer is an SI bridge.

[0009] In some implementations, the photonic and the second interposer are separated by a potting compound. In some implementations, the photonic and the second interposer are adjacent. In some implementations, the photonic and the second interposer are directly adjacent. In some implementations, the photonic and the second interposer are abutting each other. In some implementations, the photonic and the second interposer do not overlap vertically.

[0010] In some implementations, the die is an ASIC die. In some implementations, the die is a processor die. In some implementations, the die is an ARM processor die. In some implementations, the die is an image processor die.

[0011] In some implementations, one or more of the photonic interposers and the second interposer are made of silicon or a silicon alloy. In some implementations, the photonic interposer and the second interposer are laterally surrounded by a potting compound. In some implementations, the potting compound is made of silicon or a silicon alloy. In some implementations, the potting compound comprises a material adapted to the thermal expansion of one or more of the photonic interposers and the second interposer.

[0012] In some implementations, the second interposer is a potting compound. In some implementations, the second interposer includes a through-hole via structure (THV). In some implementations, the second interposer includes a bonded through-hole array.

[0013] In some implementations, the circuit package also includes a second die. In some implementations, the second die does not vertically overlap the photonic interposer. In some implementations, the second die includes a general-purpose memory; in others, it includes a processor. In some implementations, the processor is at least an image, video, and general-purpose processor. In some implementations, the second die includes a high-bandwidth memory. In some implementations, the high-bandwidth memory is HBM3.

[0014] In some implementations, the circuit package further includes a third die. In some implementations, the third die includes one or more of a general-purpose memory, a high-bandwidth memory, HBM3, a processor, an image processor, a video processor, and a general-purpose processor. In some implementations, the third die does not overlap the photonic interposer vertically. In some implementations, the third die overlaps the photonic interposer vertically. In some implementations, the third die overlaps the photonic interposer and the second interposer vertically.

[0015] In some implementations, the circuit housing also contains a fourth die. In some implementations, the circuit housing also contains a second photonic interposer. In some implementations, the circuit housing contains a third photonic interposer. In some implementations, the circuit housing also contains a third non-photonic interposer. In some implementations, the circuit housing also contains a substrate.

[0016] In some implementations, one or more dies (e.g., the first die, the second die, the third die, the fourth die) contain one or more processing elements. In some implementations, the one or more processing elements contain one or more components of a CPU, a GPU, a TPU, a Tensor Engine, a Neural Network, an AI Accelerator, a Router, a Memory, a Switch, a Controller, an ASIC, an Image Processor, a Video Processor, and a Bus.

[0017] In some implementations, one or more components of the circuit enclosure described or claimed herein are connected to the substrate. In some implementations, the circuit enclosure further includes a rewiring layer. In some implementations, the rewiring layer electrically connects the die to one of the second die, the third die, or the fourth die, as described or claimed herein. In some implementations, the rewiring layer electrically connects a top surface of the die to a top surface of one or more of the second die, the third die, or the fourth die, as described or claimed herein. In some implementations, the rewiring layer electrically connects a bottom surface of the die to a top surface of one or more of the second die, the third die, or the fourth die, as described or claimed herein.In some implementations, the rewiring layer has lines of approximately 10 µm per free space. In some embodiments, the rewiring layer is less than 2 µm thick in the vertical direction. In some implementations, the rewiring layer is less than two layers thick in the vertical direction.

[0018] In some implementations, the circuit housing further comprises one or more optical elements. In some implementations, such elements comprise fiber array units. In some implementations, the optical elements are optically connected to one or more of the photonic interposers, the second interposer, the second photonic interposer, the third interposer, and the third photonic interposer as described or claimed herein. In some implementations, arbitrary rewiring layer materials are omitted or removed vertically below at least one portion of the one or more of the photonic interposers, the second interposer, the second photonic interposer, the third interposer, and the third photonic interposer as described or claimed herein.

[0019] At least one implementation of the techniques described herein relates to a circuit package containing a photonic interposer, an electrical interposer, and a first die electrically coupled to both the photonic and electrical interposers. The first die includes an analog / mixed-signal section to allow a first processing element therein to send and / or receive data via the photonic interposer, and an electronic section to allow a second processing element therein to send and / or receive data via the electrical interposer. The circuit package includes multiple vias in the electrical interposer to allow the second processing element to send and receive data to and from at least one additional die electrically coupled to the electrical interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To explain how the above-mentioned and other features of the disclosure can be obtained, a more detailed description is given below with reference to specific implementations illustrated in the accompanying drawings. For clarity, identical elements in the various accompanying figures have been identified by the same reference numbers. While some of the drawings may be schematic or exaggerated representations of concepts, at least some of the drawings may be to scale. Assuming that the drawings represent some exemplary implementations, the implementations are described and explained below with additional specificity and detail with reference to the accompanying drawings, wherein: Fig. Figure 1 shows a top view of an embodiment of a circuit housing according to at least one embodiment of the present disclosure. Fig. 2 shows a section view of the Fig. 1 embodiment of a circuit housing as shown in at least one embodiment of the present disclosure. Fig. Figure 3 shows a top view of an embodiment of a circuit housing according to at least one embodiment of the present disclosure. Fig. Figure 4-1 shows a sectional side view of an embodiment of a circuit housing according to at least one embodiment of the present disclosure. Fig. Figure 4-2 shows a sectional side view of an embodiment of a circuit housing according to at least one embodiment of the present disclosure. Fig. Figure 4-3 shows a sectional side view of an embodiment of a circuit housing according to at least one embodiment of the present disclosure. Fig. Figure 5 shows a sectional side view of an embodiment of a circuit housing according to at least one embodiment of the present disclosure. Fig. Figure 6 shows a top view of an embodiment of a circuit housing according to at least one embodiment of the present disclosure. Fig. Figure 7 shows an exemplary method for manufacturing a circuit housing. Fig. Figure 8 shows an exemplary method for manufacturing a circuit housing. Fig. Figure 9 shows an exemplary method for manufacturing a circuit housing. Fig. Figure 10 shows an exemplary method for manufacturing a circuit housing. Fig. Figure 11 shows an exemplary method for manufacturing a circuit housing. DETAILED DESCRIPTION

[0021] The present disclosure relates to circuit packages. Methods for their manufacture are described only by way of example. More precisely, the present disclosure relates to circuit packages comprising a die connected to a photonic interposer and a second interposer.

[0022] Photonic interposers are very expensive to manufacture and / or procure. At least one embodiment described and / or claimed herein reduces the overall cost of a circuit package by miniaturizing the photonic interposer. For example, dies that do not need to be connected to a photonic interposer can be connected to a non-photonic interposer (e.g., an electrical interposer), while one or more dies that need to be connected to the photonic interposer can be connected to both the photonic interposer and a second interposer (e.g., the non-photonic interposer or a second photonic interposer). Using a second interposer can reduce the overall cost of the circuit package because two smaller interposers may be less expensive to manufacture and / or procure than a single large interposer.Using a non-photonic interposer with a photonic interposer can further reduce costs, as a non-photonic interposer is cheaper to manufacture and / or procure than a photonic interposer of the same size.

[0023] Fig. Figure 1 shows a top view of an embodiment of an electrical bridge housing with an integrated bridge-external photonic channel interface (hereinafter referred to as circuit housing 100). Fig. 2 shows a section view of the Fig. The circuit housing 100 can be manufactured according to one or more of the methods described herein. For example, the circuit housing 100 can be manufactured according to the method described in Fig. 7 shown methods 600, according to which in Fig. 8 shown methods 700, according to which in Fig. 9 shown methods 800 and according to the in Fig. The 10 methods shown can produce 900 units.

[0024] The circuit housing 100 comprises a photonic interposer 110, a second interposer 120, and a die 130, which partially overlaps both and is connected to both the photonic interposer 110 and the second interposer 120. As shown, the die 130 overlaps both the photonic interposer 110 and the second interposer 120 in the vertical direction. According to at least one embodiment of the present disclosure, the photonic interposer 110 can be any type of interposer. For example, the photonic interposer 110 can comprise a photonic integrated circuit.

[0025] In some embodiments, the second interposer 120 can be a photonic interposer (e.g., a second photonic interposer). In some embodiments, one or more photonic interposers (e.g., the photonic interposer 110 or the second interposer 120) are photonically integrated circuits. In some embodiments, the second interposer 120 is a non-photonic interposer. Non-photonic interposers can, in some embodiments, comprise one or more silicon (SI) interposers, SI bridges, electronic interposers, other interposer materials, other bridge materials, or combinations thereof. In some embodiments, the photonic interposer 110 and the second interposer 120 are made of silicon or a silicon alloy.

[0026] In some embodiments, the photonic interposer 110 and the second interposer 120 are arranged adjacent to each other. For example, the photonic interposer 110 and the second interposer 120 may be separated only by a gap or a spacer (e.g., a potting compound). In some embodiments, the photonic interposer 110 and the second interposer 120 are directly adjacent to each other. For example, the photonic interposer 110 and the second interposer 120 may be separated only by a gap. In some embodiments, the photonic interposer 110 and the second interposer 120 abut each other. For example, the photonic interposer 110 and the second interposer 120 may be in direct contact with each other.

[0027] As in Fig. As shown in Figure 1, the photonic interposer 110 and the second interposer 120 do not overlap in the vertical direction. In some embodiments, the photonic interposer 110 and the second interposer 120 overlap at least partially in the vertical direction.

[0028] The die 130 can contain any suitable integrated circuit, such as an ASIC, a processor, an ARM processor, an image processor, a tensor engine, a neural compute engine, a video processor, a general-purpose processor, or combinations thereof. As shown, the die 130 can be larger than the photonic interposer 110 in at least one dimension. As shown, the die 130 is larger than the photonic interposer 110 in the x-direction. In some embodiments, the die 130 is larger than the photonic interposer 110 in two or more dimensions.

[0029] The die 130 can contain various sections. For example, the die 130 can contain an analog / mixed-signal section 132-1 and / or an electronic section 132-2. The analog / mixed-signal section 132-1 can contain a first processing element 134-1. The first processing element 134-1 can transmit and / or receive data using the photonic interposer 110. The electronic section 132-2 can contain a second processing element 134-2. The second processing element 134-2 can transmit and / or receive data using the second interposer 120. For example, the second interposer 120 can be an exclusively electrical interposer (e.g., not a photonic interposer), so that the second processing element 134-2 can transmit and / or receive data electrically using the second interposer 120.

[0030] According to at least one embodiment of the present disclosure, the first processing element 134-1 can comprise processing elements configured to communicate with elements of the photonic interposer 110. In some embodiments, information can be transmitted to the interposer 110 via a photonic channel and received at an opto-electrical (OE) interface between the photonic interposer 110 and the analog / mixed-signal section 132-1. The opto-electrical interface can be implemented, for example, by a photodetector (e.g., a photodiode) in the photonic interposer 110, which converts the optical signal into an electrical signal, in conjunction with associated electronics in the analog / mixed-signal section 132-1, which...The photonic interposer can include a transimpedance amplifier (TIA), an optional gain control for signal level normalization, and a slicer for bitstream extraction. The information can then be buffered electronically in a register, such as a first-in, first-out (FIFO) register. Alternatively, an electro-optical (EO) interface can be used in the same photonic channel to transmit data via the photonic interposer.

[0031] The first processing element 134-1 can communicate with the elements of the photonic interposer 110 using any type of connection. The circuit housing 100, for example, can contain electrical connection structures. The electrical connections can be any type of electrical connection, including one or more solder joints, wires, copper pillars, wire bonds, silicon vias (TSVs), transelectric vias (TDVs), rewired layers (RDLs), contact pads, any other electrical connection, and combinations thereof. In some embodiments, the electrical connection can be realized by means of a copper pillar embedded in a contact pad. The copper pillar can protrude from the contact pad to establish a connection with a photonic component on the photonic interposer 110.This can cause the electrical coupling of the electrical component with the photonic component. The contact surface can have a larger surface area than the cross-section of the copper column. In some embodiments, the copper column can be electrically connected to a cathode of a modulator. In some embodiments, the contact surface can have the shape of a polygon or a circle, and the copper column is fixed at a position on the contact surface that deviates from the center of the polygon or circle.

[0032] As explained here, the photonic interposer 110 can contain any type of photonic element. For example, the photonic interposer 110 can include a modulator. The modulator can be any type of modulator described here. For instance, the modulator can be a thermally stable modulator. In some examples, the modulator can be an electroabsorption modulator (EAM). The first processing element 134-1 of the analog / mixed-signal section 132-1 of the die 130 can include a driver. The driver can be connected to the modulator, for example, via an electrical connection. This allows the analog / mixed-signal section 132-1 of the die 130 to communicate with the modulator of the photonic interposer 110.

[0033] In some examples, the photonic interposer 110 can include a photodetector. The photodetector can be any type of photodetector, such as a photodiode. The first processing element 134-1 of the analog mixed-signal section 132-1 of the die 130 can include a transimpedance amplifier (TIA). The TIA and the photodetector can communicate with each other via an electrical connection. This allows the analog mixed-signal section 132-1 of the die 130 to communicate with the photonic interposer 110.

[0034] As in Fig. As shown in Figure 2, the Die 130 partially overlaps both the photonic interposer 110 and the second interposer 120 and is connected to them. As shown in Figure 2. Fig. As shown in Figure 2, the 130 vertically overlaps both the photonic interposer 110 and the second interposer 120. The analog mixed-signal section 132-1 vertically overlaps the photonic interposer 110, and the electronic section 132-2 vertically overlaps the second interposer 120.

[0035] In some embodiments, the photonic interposer 110 is optically connected to the die 130. For example, optical signals can be sent from the photonic interposer 110 to and received by the die 130, and / or sent by the die 130 and received by the photonic interposer 110. In embodiments where the second interposer is a photonic interposer, the second interposer 120 is optically connected to the die 130. For example, optical signals can be sent from the second interposer 120 to and received by the die 130, and / or sent by the die 130 and received by the second interposer 120.

[0036] In embodiments where the second interposer is a non-photonic interposer, the second interposer 120 is electrically connected to the die 130. For example, electrical signals can be sent from the second interposer 120 to and received by the die 130, and / or sent by and received by the die 130. In some embodiments, the second interposer 120 can include one or more substrate vias (TSVs) that are electrically connected to the die 130. For example, the second interposer 120 can be electrically connected via the TSVs to the portion of the die 130 that overlaps the second interposer 120. In some embodiments, the photonic interposer 110 can include one or more TSVs.

[0037] As in Fig. As shown in Figure 2, the circuit housing 100 can optionally include a second die 130-2. The second processing element 134-2 can be configured to communicate with the second die 130-2 via a communication path. The second die 130-2 can be electrically connected to the second interposer 120 via an electronic section of the communication path. This can allow the second die 130-2 to communicate with the second interposer 120 and / or the photonic interposer 110 via the communication path. In some embodiments, the second die 130-2 can be a third-party die or chip. In some embodiments, the second die 130-2 can be a different type of die or chip than the first die 130.

[0038] In some embodiments, the second die 130-2 can be electrically connected to the electronic section 132-2 of the die 130 via the communication path. For example, the second die 130-2 can be electrically connected via the second interposer 120 and / or be in electrical communication with the purely electrical section 132-2. In some embodiments, the second die 130-2 can be electrically connected via a communication path running through the second interposer 120 and / or be in electrical communication with the purely electrical section 132-2.

[0039] The second die 130-2 can include a third processing element 134-3. This can communicate with the second processing element 134-2 in the purely electrical section 132-2 via the communication path. For example, the third processing element 134-3 can receive signals and / or information from the purely electrical section 132-2 of the die 130 via the communication path.

[0040] In some embodiments, the second die 130-2 can be electrically connected to the analog / mixed signal section 132-1 of die 130 via the communication path. For example, the second die 130-2 can be electrically connected to the analog / mixed signal section 132-1 via the purely electrical section 132-2 and the second interposer 120 and / or be in electrical signal communication. In some embodiments, the second die 130-2 can be electrically connected to the analog / mixed signal section 132-1 and / or be in electrical signal communication via a communication path that runs through the second interposer 120 and the purely electrical section 132-2. This can allow the third processing element 134-3 to communicate with the first processing element 134-1 of the analog / mixed signal section 132-1.

[0041] In some embodiments, the second die 130-2 can be electrically connected to the photonic interposer 110 via the communication path and / or be in electrical signal communication. For example, the second die 130-2 can be electrically connected to the photonic interposer 110 via the analog / mixed-signal section 132-1, the purely electrical section 132-2, and the second interposer 120, and / or be in electrical signal communication. In some embodiments, the second die 130-2 can be electrically connected to the photonic interposer 110 and / or be in electrical signal communication via a communication path that runs through the second interposer 120, the purely electrical section 132-2, and the analog / mixed-signal section 132-1. This can enable the third processing element 134-3 to communicate with the first processing element 134-1 of the analog / mixed signal section 132-1.

[0042] In some embodiments, the second die 130-2 can be optically connected to other optical elements of the circuit housing 100 (for example, a fiber array unit, FAU) via the photonic interposer 110 and / or be in optical signal communication, and electrically connected to the photonic interposer 110 via the communication path and / or be in electrical signal communication. For example, the second die 130-2 can be optically connected to the other optical elements via the photonic interposer 110 and / or be in optical signal communication, and electrically connected to the photonic interposer 110 via the analog / mixed-signal section 132-1, the purely electrical section 132-2, and the second interposer 120 and / or be in electrical signal communication.In some examples, the second die 130-2 can be optically connected to the other optical elements of the circuit housing 100 via an optical section of the communication path that passes through the photonic interposer 110 and / or be in optical signal communication, and electrically connected to the photonic interposer 110 via the communication path that passes through the second interposer 120, the electronic section 132-2, and the analog / mixed-signal section 132-1 and / or be in electrical signal communication. This can enable the third processing element 134-3 to communicate with the other optical elements.

[0043] Fig. Figure 3 shows a top view of an embodiment of an electrical bridge housing with an integrated bridge-external photonic channel interface (hereinafter: circuit housing 200). The circuit housing 200 can be manufactured according to one or more of the methods described herein, e.g., according to the method described in Fig. 7 shown methods 600, which in Fig. 8 shown methods 700, which in Fig. 9 shown methods 800 and the one in Fig. 10 methods shown 900.

[0044] The circuit housing 200 comprises a photonic interposer 210, a second interposer 220, and a die 230, which partially overlaps both and is connected to the photonic interposer 210 and the second interposer 220. As shown, the die 230 overlaps both the photonic interposer 210 and the second interposer 220 vertically.

[0045] In some embodiments, the second interposer 220 can be a photonic interposer (e.g., a second photonic interposer). In some embodiments, one or more photonic interposers (e.g., the photonic interposer 210 or the second interposer 220) are photonically integrated circuits. In some embodiments, the second interposer 220 is a non-photonic interposer. Non-photonic interposers can, in some embodiments, comprise one or more silicon (SI) interposers, an SI bridge, other interposer materials, other bridge materials, or combinations thereof. In some embodiments, the photonic interposer 210 and the second interposer 220 are formed from silicon or a silicon alloy.

[0046] In some embodiments, the photonic interposer 210 and the second interposer 220 are arranged adjacent to each other. As shown, the photonic interposer 210 and the second interposer 220 can be separated only by a spacer (e.g., an optional potting compound 240). The optional potting compound 240 can surround one or more side faces of the photonic interposer 210 and / or the second interposer 220. As shown, the optional potting compound 240 surrounds all side faces of the photonic interposer 210 and the second interposer 220, including the space between the photonic interposer 210 and the second interposer 220. In some embodiments, the photonic interposer 210 and the second interposer 220 are arranged directly adjacent to each other.For example, the photonic interposer 210 and the second interposer 220 can be separated only by a gap and not by a spacer (e.g., potting compound 240). In some embodiments, the photonic interposer 210 and the second interposer 220 are in abutment. For example, the photonic interposer 210 and the second interposer 220 can be in direct contact with each other (e.g., without potting compound 240).

[0047] The die 230 can have various sections. For example, the die 230 can include an analog / mixed-signal section 232-1 and / or an electronic section 232-2. The analog / mixed-signal section 232-1 can include a first processing element 234-1. The first processing element 234-1 can send and / or receive data using the photonic interposer 210. For example, the first processing element 234-1 can send and / or receive data photonically using the photonic interposer 210. The electronic section 232-2 can include a second processing element 234-2. The second processing element can send and / or receive data using the second interposer 220. For example, the second interposer 220 can be a purely electrical interposer (e.g., a photon).(no photonic interposer), so that the second processing element 234-2 can send and / or receive data electrically using the second interposer 220.

[0048] As shown, the circuit housing 200 can optionally include a substrate 201 that is electrically connected to the photonic interposer 210 and / or the second interposer 220. As shown, the circuit housing 200 can optionally include a second die 230-2 and / or a third die 230-3.

[0049] The second Die 230-2 and / or the third Die 230-3 can contain one or more of a general-purpose memory, a high-bandwidth memory, HBM3, a processor, an image processor, a video processor, and a general-purpose processor.

[0050] In embodiments where the second interposer 220 is a non-photonic interposer, the second die 230-2 and / or the third die 230-3 are electrically connected to the second interposer 220, for example, via two or more TSVs. In embodiments where the second interposer 220 is a photonic interposer, the second die 230-2 and / or the third die 230-3 are optically connected to the second interposer 220.

[0051] In some embodiments, at least a section of the second interposer 220 below at least one die (e.g., the second die 230-2 or the third die 230-3) can be configured as a potting compound (such as the potting compound 240). The potting compound located below at least one die can include a potting compound via and / or a bond via array to facilitate communication with the at least one die.

[0052] As shown, the circuit housing 200 can optionally include at least one optical element (e.g., fiber array units, FAU 250). This is optically connected to the photonic interposer 210.

[0053] In some embodiments, as shown in Figure 3, the photonic interposer 210 and the second interposer 220 do not overlap vertically. In other embodiments, the photonic interposer 210 and the second interposer 220 overlap at least partially vertically. The analog / mixed-signal section 232-1 overlaps the photonic interposer 210 vertically, and the electronic section 232-2 overlaps the second interposer 220 vertically.

[0054] The die 230 can contain an ASIC, a processor, an image processor, a video processor, a general-purpose processor, or combinations thereof. As shown, the die 230 can be larger than the photonic interposer 210 in at least one dimension. As shown, the die 230 is larger than the photonic interposer 210 in the x-direction. In some embodiments, the die 230 is larger than the photonic interposer 210 in two or more dimensions.

[0055] Figure 4-1 is a sectional view of an embodiment of an electrical bridge enclosure with an integrated photonic channel interface located outside the bridge (hereinafter referred to as the circuit enclosure 300). The circuit enclosure 300 can be manufactured according to one or more of the methods described herein. For example, the circuit enclosure can be manufactured by the method described in Fig. 7 shown methods 600, which in Fig. 8 shown methods 700 and that in Fig. The 10 processes shown can be produced in 900 units.

[0056] As shown in Figure 4-1, a die 330 partially overlaps and is connected to both a photonic interposer 310 and a second interposer 320. As shown in Fig. As shown in 4-1, the die 330 overlaps both the photonic interposer 310 and the second interposer 320 in a vertical direction.

[0057] In some embodiments, the second interposer 320 can be a photonic interposer (e.g., a second photonic interposer). Photonic interposers (e.g., the photonic interposer 310 or the second interposer 320) are, in some embodiments, photonic integrated circuits (PICs). In some embodiments, the second interposer 320 is a non-photonic interposer. Non-photonic interposers can, in some embodiments, comprise a silicon (SI) interposer, an SI bridge, other interposer materials, other bridge materials, or combinations thereof. In some embodiments, the photonic interposer 310 and the second interposer 320 are formed from silicon or a silicon alloy.

[0058] As shown, the photonic interposer 310 and the second interposer 320 are adjacent to each other. For example, as shown, the photonic interposer 310 and the second interposer 320 are separated from each other only by an optional potting compound 340. In some embodiments, the photonic interposer 310 and the second interposer 320 are directly adjacent. For example, the photonic interposer 310 and the second interposer 320 may be separated from each other only by a gap. In some embodiments, the photonic interposer 310 and the second interposer 320 abut each other. For example, the photonic interposer 310 and the second interposer 320 may be in direct contact with each other (e.g., without the optional potting compound 340).

[0059] The die 330 can comprise various sections. For example, the die 330 can contain an analog mixed-signal section 332-1 and / or an electronic section 332-2. The analog mixed-signal section 332-1 can contain a first processing element 334-1. The first processing element 334-1 can send and / or receive data using the photonic interposer 310. For example, the first processing element 334-1 can send and / or receive data photonically via the photonic interposer 310. For example, the first processing element 334-1 can transmit and / or receive data via an electrical interface, as discussed herein. The electronic section 332-2 can contain a second processing element 334-2. The second processing element 334-2 can send and / or receive data via the second interposer 320. For example, the second interposer 320 can be a purely electric interposer (e.g.(no photonic interposer), so that the second processing element 334-2 can send and / or receive data electrically via the second interposer 320.

[0060] As shown, the circuit housing 300 can optionally contain a substrate 301 that is electrically connected to the photonic interposer 310 and / or the second interposer 320. An optional rewiring layer 360 can be applied to the substrate 301 to facilitate the electrical connection to the photonic interposer 310 and / or the second interposer 320.

[0061] As shown, the circuit housing 300 can optionally contain a second die 330-2. This and / or a third die can contain one or more of the following elements: a general-purpose data storage, a high-bandwidth storage, HBM3, a processor, an image processor, a video processor, and a general-purpose processor. The second processing element 334-2 can be configured to communicate with the second die 330-2 via a communication path. The second die 330-2 can contain a third processing element 334-3. The third processing element 334-2 can send and / or receive data via the second interposer 320. For example, the second interposer 320 can be a purely electrical interposer (e.g., not a photonic interposer), so the third processing element 334-3 can send and / or receive data electrically via the second interposer 320.

[0062] As discussed herein, the second die 330-2 can be electrically connected to the second interposer 320 via an electronic section of the communication path. This can enable the second die 330-2 to communicate with the second interposer 320 and / or the photonic interposer 310. In some embodiments, the second die 330-2 can be a third-party die or chip. In some embodiments, the second die 330-2 can be a different type of die or chip than the die 330.

[0063] In some embodiments, the second die 330-2 can be electrically connected to the purely electrical section 332-2 of the die 330 via the communication path. For example, the second die 330-2 can be electrically connected to the electronic section 332-2 via the second interposer 320. In some examples, the second die 330-2 can be electrically connected to the purely electrical section 332-2 via the communication path that runs through the second interposer 320.

[0064] The second die 330-2 can contain a third processing element 334-3. The third processing element 334-3 can communicate with the second processing element 334-2 in the electronic section 332-2 via the communication path. For example, the third processing element 334-3 can receive signals and / or information from the purely electrical section 332-2 of the die 330 via the communication path.

[0065] In some embodiments, the second die 330-2 can be electrically connected to the analog / mixed signal section 332-1 of die 330 via the communication path. For example, the second die 330-2 can be electrically connected to the analog / mixed signal section 332-1 via the electronic section 332-2 and the second interposer 320 and / or be in electrical signal communication. In some embodiments, the second die 330-2 can be electrically connected to the analog / mixed signal section 332-1 via the communication path that runs through the second interposer 320 and the electronic section 332-2. This allows the third processing element 334-3 to communicate with the first processing element 334-1 of the analog / mixed signal section 332-1.

[0066] In some embodiments, the second die 330-2 can be electrically connected to the photonic interposer 310 via the communication path. For example, the second die 330-2 can be electrically connected to the analog / mixed-signal section 332-1 via the electronic section 332-2 and the second interposer 320. In some embodiments, the second die 330-2 can be electrically connected to the photonic interposer 310 via the communication path that runs through the second interposer 320, the purely electrical section 332-2, and the analog / mixed-signal section 332-1. This allows the third processing element 334-3 to communicate with the first processing element 334-1 of the analog / mixed-signal section 332-1.

[0067] In some embodiments, the second die 330-2 can be optically connected to or in optical communication with the fiber array unit 350 via the photonic interposer 310, and can also be electrically connected to or in electrical communication with the photonic interposer 310 via the communication path. For example, the second die 330-2 can be optically connected to and / or in optical communication with the fiber array unit via the photonic interposer 310, and electrically connected to and / or in electrical communication with the photonic interposer 310 via the analog / mixed-signal section 332-1, the electronic section 332-2, and the second interposer 320.In some examples, the second die 330-2 can be optically connected to and / or in optical communication with the fiber array unit 350 of the circuit housing 300 via an optical section of the communication path that passes through the photonic interposer 310, and electrically connected to and / or in electrical communication with the photonic interposer 310 via the communication path that passes through the second interposer 320, the electronic section 332-2, and the analog / mixed-signal section 332-1. This allows the third processing element 334-3 to communicate with the fiber array unit 350.

[0068] The second die 330-2 can be connected to the second interposer 320 via an RDL layer 361. The RDL layer 361 can extend under a section of the second die 330-2, under the entire second die 330-2, over a section of the second interposer 320, over the entire extent of the second interposer 320, under a section of the photonic interposer 310, over a section of the optional potting compound 340, over a section of the photonic interposer 310, over a section of the optional potting compound 340 and a section of the photonic interposer 310, over the entire extent of the photonic interposer 310, under the entire extent of the die 330, over a section of the second interposer 320 and over a section of the optional potting compound 340 and under a section of the second die 330-2 and under a section of the die 330 and over a section of the photonic interposer 310, or over combinations thereof.In embodiments where the rewiring layer 361 extends over the photonic interposer 310, sections of the rewiring layer 361 can be removed. For example, sections of the rewiring layer 361 that obstruct optical communication with the photonic interposer 310 can be at least partially or completely removed from the photonic interposer 310 to facilitate optical communication with the photonic interposer.

[0069] In embodiments where the second interposer 320 is a non-photonic interposer, the second die 330-2 is electrically connected to the second interposer 320, for example, by means of an optional rewiring layer 361 and / or one or more silicon vias 370. In embodiments where the second interposer 320 is a photonic interposer, the second die 330-2 is optically connected to the second interposer 320.

[0070] In some embodiments, at least one section of the second interposer beneath at least one die (e.g., the second die 330-2 or an additional die) may contain a potting compound (such as potting compound 340). The potting compound beneath the at least one die may include a potting compound via and / or a bond via array to facilitate communication with the at least one die.

[0071] The circuit housing 300, as shown, can optionally contain at least one optical element (e.g., fiber array units). The one or more optical elements are optically connected to the photonic interposer 310. In some embodiments, the circuit housing 300 includes one fiber array unit 350 for each photonic interposer 310. According to at least one embodiment of the present disclosure, the fiber array unit 350 is connected to the photonic interposer 310 using fiber array unit connections that are sections of photonic channels. In some embodiments, the circuit housing 300 can contain several fiber array units 350, which, for example, also communicate with a single photonic interposer 310. In some examples, the circuit housing 300 can contain several fiber array units 250 that are connected to different photonic interposers 310.

[0072] According to at least one embodiment of the present disclosure, the fiber array unit 350 can communicate with the photonic interposer 310 via a fiber optic connection 343. The fiber optic connection can be of any type. For example, the fiber optic connection 343 can be optically coupled to light entering or leaving the photonic interposer via a photonic channel. It can, for example, be part of a bidirectional channel, which may include, for example, a waveguide or fiber structure.

[0073] As in Fig. As shown in Figure 4-1, the photonic interposer 310 and the second interposer 320 do not overlap vertically. In some embodiments, the photonic interposer 310 and the second interposer 320 overlap at least partially in the vertical direction.

[0074] The die 330 can contain an ASIC, a processor, an image processor, a video processor, a general-purpose processor, or combinations thereof. As shown, the die 330 can be larger than the photonic interposer 310 in at least one dimension. As shown, the die 330 is larger than the photonic interposer 310 in the x-direction. In some embodiments, the die 330 is larger than the photonic interposer 310 in two or more dimensions.

[0075] In some embodiments, the photonic interposer 310 is optically connected to the die 330. For example, optical signals can be sent from the photonic interposer 310 to the die 330 and received there, and / or sent from the die 330 and received by the photonic interposer 310.

[0076] In embodiments where the second interposer 320 is a photonic interposer, the second interposer 320 is optically connected to the die 330 and the second die 330-2. For example, optical signals can be emitted by the second interposer 320 and received by the die 330 and the second die 330-2, and / or sent by the die 330 and the second die 330-2 and received by the second interposer 320.

[0077] In embodiments where the second interposer 320 is a non-photonic interposer, the second interposer 320 is electrically connected to the die 330 and the second die 330-2. Electrical signals can, for example, be emitted by the second interposer 320 and received by the die 330 and / or the second die 330-2, and / or emitted by the die 330 and / or the second die 330-2 and received by the second interposer 320. In some embodiments, the second interposer 320 can include one or more TSVs 370s that are electrically connected to the die 330 and the second die 330-2. For example, the second interposer 320 can be electrically connected to the section of the die 330 that overlaps the second interposer 320, and / or to the second die 330-2 by the TSVs 370. In some embodiments, the photonic interposer 310 can contain one or more TSVs 370.

[0078] As explained herein, the second interposer 320 can be electrically connected to the purely electrical section 332-2 of the die 330 via electrical connection structures 333. The electrical connection 333 can be any type of electrical connection, including one or more solder joints, wires, copper pillars, wire bonds, silicon vias, dielectric vias, rewiring layers, contact pads, other electrical connection structures, and combinations thereof. In some embodiments, the electrical connection can be realized by means of a copper pillar embedded in a contact pad. The copper pillar can protrude from the contact pad to establish a connection with a photonic component on the photonic interposer 110. This can effect the electrical coupling of the electrical component with the photonic component.The contact surface can have a larger surface area than the cross-section of the copper column. In some embodiments, the copper column can be electrically connected to a cathode of a modulator. In some embodiments, the contact surface is shaped as a polygon or circle, and the copper column is placed on the contact surface at a position projecting from the center of the polygon or circle.

[0079] The electrical connection 333 can have a connection length corresponding to the distance between the purely electrical section 332-2 and the second interposer 320. The connection length of the electrical connection can take any value. For example, the connection length can be at most 50 micrometers, at most 60 micrometers, at most 70 micrometers, at most 80 micrometers, at most 90 micrometers, at most 100 micrometers, at most 110 micrometers, at most 120 micrometers, at most 130 micrometers, at most 140 micrometers, at most 150 micrometers, or any value in between. As a specific, non-restrictive example, the length of the connection can be less than 100 micrometers to enable fast and efficient communication between the electrical and photonic processing elements.

[0080] The electrical connection structure 333 can have a connection diameter. The connection diameter can be any value. For example, the connection diameter can be 10 micrometers or less, 15 micrometers or less, 20 micrometers or less, 25 micrometers or less, 30 micrometers or less, 35 micrometers or less, 40 micrometers or less, 45 micrometers or less, 50 micrometers or less, or any value in between.

[0081] Fig. Figure 4-2 is a sectional side view of an embodiment of a circuit housing 300. The circuit housing 300 can be manufactured according to one or more of the methods described herein, namely, for example, by the method described in Fig. 7 shown methods 600, by which in Fig. 8 shown methods 700 and by the in Fig. 10 methods shown 900.

[0082] As in Fig. As shown in Figure 4-2, a die 330 partially overlaps and is connected to both a photonic interposer 310 and a second interposer 320. As shown in Fig. As shown in Figure 4-2, the chip 330 vertically overlaps both the photonic interposer 310 and the second interposer 320.

[0083] The die 330 can contain various sections. For example, the die 330 can contain an analog / mixed-signal section 332-1 and / or a purely electrical section 332-2. The analog / mixed-signal section 332-1 can contain processing elements. The analog / mixed-signal section 332-1 can, for example, contain a driver 335 and / or a transimpedance amplifier 337. The processing elements of the analog / mixed-signal section 332 can transmit and / or receive data via the photonic interposer 310.

[0084] The photonic interposer 310 can include a modulator 339 and / or a photodetector 341. As discussed herein, the processing elements of the analog / mixed-signal section 332-1, including the driver 335 and the transimpedance amplifier 337, can transmit and / or receive data with the photonic interposer 310. For example, the driver 335 of the analog / mixed-signal section 332-1 can communicate with the modulator 339 of the photonic interposer 310. The driver 335 of the analog / mixed-signal section 332-1 can be connected to a first end of a first electrical connection 333-1. The modulator 339 of the photonic interposer 310 can be connected to a second end of the first electrical connection 333-1. In this way, the driver 335 of the analog / mixed signal section 332-1 and the modulator 339 of the photonic interposer 310 can communicate via the first electrical connection 333-1.

[0085] In some embodiments, the transimpedance amplifier 337 of the analog / mixed-signal section 332-1 can communicate with the photodetector 341 of the photonic interposer 310. The transimpedance amplifier 337 of the analog / mixed-signal section can be connected to a first end of a second electrical connection 333-2. The photodetector 341 of the photonic interposer 310 can be connected to a second end of the second electrical connection 333-2. In this way, the transimpedance amplifier 337 of the analog / mixed-signal section 332-1 and the photodetector 341 of the photonic interposer 310 can communicate via the second electrical connection 333-2.

[0086] As shown, the circuit housing 300 can optionally contain a substrate 301 that is electrically connected to the photonic interposer 310 and / or the second interposer 320. An optional rewiring layer 360 can be applied to the substrate 301 to enable the electrical connection to the photonic interposer 310 and / or the second interposer 320.

[0087] As shown, the circuit housing 300 can optionally contain a second die 330-2. The second die 330-2 can contain one or more general-purpose data storage units, high-bandwidth storage units, HBM3, processors, image processors, video processors, and general-purpose processors. The second die 330-2 can contain a second electronic section (similar to the purely electrical section 332-2) of the die 330. The second purely electrical section can contain one or more processing elements that can be configured to communicate with the second interposer 320 via a communication path. The second purely electrical section can transmit and / or receive data via the second interposer 320. For example, the second interposer 320 can be a purely electrical interposer (e.g.,(no photonic interposer), so that the second electronic section can transmit and / or receive data electrically using the second interposer 320.

[0088] As discussed herein, the second die 330-2 can be electrically connected to the second interposer 320 via an electronic section of a communication path. This can enable the second die 330-2 to communicate with the second interposer 320 and / or the photonic interposer 310. In some embodiments, the second die 330-2 can be a third-party die. In some embodiments, the second die 330-2 can be of a different type than the die 330.

[0089] In some embodiments, the second die 330-2 can be electrically connected to the purely electrical section 332-2 of the die 330 via the communication path. For example, the second die 330-2 can be electrically connected to and / or electrically communicate with the purely electrical section 332-2 via the second interposer 320. In some examples, the second die 330-2 can be electrically connected to the purely electrical section 332-2 via the communication path that runs through the second interposer 320.

[0090] The second die 330-2 can contain a third processing element 334-3. The third processing element 334-3 can communicate with the second processing element 334-2 in the electronic section 332-2 via the communication path. For example, the third processing element 334-3 can receive signals and / or information from the electronic section 332-2 of the die 330 via the communication path.

[0091] In some embodiments, the second die 330-2 can be electrically connected to the analog / mixed signal section 332-1 of die 330 via the communication path. For example, the second die 330-2 can be electrically connected to the analog / mixed signal section 332-1 via the electronic section 332-2 and the second interposer 320. In some examples, the second die 330-2 can be electrically connected to the analog / mixed signal section 332-1 via the communication path that runs through the second interposer 320 and the electronic section 332-2. This can allow the third processing element 334-3 to communicate with the first processing elements of the analog / mixed signal section 332-1, such as the driver 335 and / or the transimpedance amplifier 337.

[0092] In some embodiments, the second die 330-2 can be electrically connected to the photonic interposer 310 via the communication path. For example, the second die 330-2 can be electrically connected to the photonic interposer 310 via the analog / mixed-signal section 332-1 (including the driver 335 and / or the transimpedance amplifier (TIA) 337), the electronic section 332-2, and the second interposer 320. In some examples, the second die 330-2 can be electrically connected to the photonic interposer 310 via the communication path that passes through the second interposer 320, the electronic section 332-2, and the analog / mixed-signal section 332-1. In some examples, the second die 130-2 can be electrically connected to the photonic interposer 310 via the modulator 339 and / or the photodetector 341 of the photonic interposer 310, or be in electrical communication with it.

[0093] In some embodiments, the second die 330-2 can be optically connected to and / or optically communicated with the fiber array unit 350 via the photonic interposer 310, as well as electrically connected to and / or electrically communicated with the photonic interposer 310. For example, the second die 330-2 can be optically connected to and / or optically communicated with the fiber array unit 350 via the photonic interposer 310, and electrically connected to and / or optically communicated with the photonic interposer 310 via the analog / mixed-signal section 332-1, the electronic section 332-2, and the second interposer 320.In some examples, the second die 330-2 can be optically connected to and / or in optical communication with the fiber array unit 350 of the circuit housing 300 via an optical section of the communication path that passes through the photonic interposer 310, and electrically connected to and / or in electrical communication with the photonic interposer 310 via the communication path that passes through the second interposer 320, the electronic section 332-2, and the analog / mixed-signal section 332-1. This allows the third processing element 334-3 to communicate with the fiber array unit 350.

[0094] The second die 330-2 can be connected to the second interposer 320 via a rewiring layer 361.The rewiring layer 361 can extend under a section of the second die 330-2, under the entire second die 330-2, over a section of the second interposer 320, over the entire extent of the second interposer 320, under a section of the photonic interposer 310, over a section of the optional potting compound 340, over a section of the photonic interposer 310, over a section of the optional potting compound 340 and a section of the photonic interposer 310, over the entire extent of the photonic interposer 310, under the entire extent of the die 330, over a section of the second interposer 320 and over a section of the optional potting compound 340 and under a section of the second die 330-2, under a section of the die 330 and over a section of the photonic interposer 310, or over combinations thereof.In embodiments where the RDL layer 361 extends over the photonic interposer 310, sections of the rewiring layer 361 can be removed. For example, sections of the RDL layer 361 that obstruct optical communication with the photonic interposer 310 can be at least partially or completely removed to enable optical communication.

[0095] In embodiments where the second interposer 320 is an electrical interposer, the second die 330-2 is electrically connected to the second interposer 320, for example, by means of an optional rewiring layer 361 and / or one or more TSVs 370. In embodiments where the second interposer 320 is a photonic interposer, the second die 330-2 is optically connected to the second interposer 320.

[0096] In some embodiments, at least one section of the second interposer beneath at least one die (e.g., the second die 330-2 or an additional die) can be a potting compound (such as potting compound 340). The potting compound beneath the at least one die can include a potting compound via and / or a bond via array to facilitate communication with the at least one die.

[0097] Fig. Figure 4-3 is a sectional side view of an embodiment of a circuit housing 300. The circuit housing can be manufactured according to one or more of the methods described herein. For example, the circuit housing can be manufactured by the method described in Fig. 7 shown methods 600, by which in Fig. 8 shown methods 700 and by the in Fig. The 10 processes shown can be produced in 900 units.

[0098] As in Fig. As shown in Figure 4-3, a die 330 partially overlaps and is connected to both a photonic interposer 310 and a second interposer 320. As shown in Fig. As shown in Figure 4-3, the die 330 vertically overlaps both the photonic interposer 310 and the second interposer 320.

[0099] The die 330 can contain various sections. For example, the die 330 can contain an analog / mixed-signal section 332-1 and / or an electronic section 332-2. The analog / mixed-signal section 332-1 can contain one or more processing elements. The analog / mixed-signal section 332-1 can, for example, contain a driver 335 and / or a transimpedance amplifier (TIA) 337. The processing elements can transmit and / or receive data via the photonic interposer 310.

[0100] The photonic interposer 310 can include a modulator 339-1 and / or a photodetector 341. As discussed herein, the processing elements of the analog / mixed-signal section 332-1, including the driver 335 and the transimpedance amplifier (TIA) 337, can exchange data with the photonic interposer 310. For example, the driver 335 of the analog / mixed-signal section 332-1 can communicate with the modulator 339 of the photonic interposer 310. The driver 335 of the analog / mixed-signal section 332-1 can be connected to a first end of a first electrical connection 333-1. The modulator 339 of the photonic interposer 310 can be connected to a second end of the first electrical connection 333-1. In this way, the driver 335 of the analog / mixed signal section 332-1 and the modulator 339 of the photonic interposer 310 can communicate via the first electrical connection 333-1.

[0101] In some embodiments, the transimpedance amplifier 337 of the analog / mixed-signal section 332-1 can communicate with the photodetector 341 of the photonic interposer 310. The transimpedance amplifier 337 of the analog / mixed-signal section can be connected to a first end of a second electrical connection 333-2. The photodetector 341 of the photonic interposer 310 can be connected to a second end of the second electrical connection 333-2. In this way, the transimpedance amplifier 337 of the analog / mixed-signal section 332-1 and the photodetector 341 of the photonic interposer 310 can communicate via the second electrical connection 333-2.

[0102] As shown, the circuit housing 300 can optionally contain a substrate 301 that is electrically connected to the photonic interposer 310 and / or the second interposer 320. An optional rewiring layer (RDL) 360 can be applied to the substrate 301 to facilitate the electrical connection to the photonic interposer 310 and / or the second interposer 320.

[0103] As shown, the circuit housing 300 can optionally contain a second die 330-2. The second die can contain one or more of the following elements: a general-purpose data storage, a high-bandwidth storage, HBM3, a processor, an image processor, a video processor, and a general-purpose processor. The second die 330-2 can contain a second analog / mixed-signal section (similar to the analog / mixed-signal section 332-1) of the die 330. The second analog / mixed-signal section can contain one or more processing elements that can be configured to communicate with the photonic interposer 310 via a communication path. The second analog / mixed-signal section can send and / or receive data using the photonic interposer 310.For example, the photonic interposer 310 can be a photonically integrated circuit, so that the second analog / mixed signal section can electrically send and / or receive data via the photonic interposer 310.

[0104] In some embodiments, the second die 330-2 can be electrically connected to and / or electrically communicate with the analog / mixed-signal section 332-1 of die 330 via the communication path. For example, the second die 330-2 can be electrically connected to or electrically communicate with the analog / mixed-signal section 332-1 via the electronic section 332-2 and the second interposer 320. In some examples, the second die 330-2 can be electrically connected to and / or electrically communicate with the analog / mixed-signal section 332-1 via the communication path that runs through the second interposer 320 and the purely electrical section 332-2. This can enable the third processing element 334-3 to communicate with the first processing elements of the analog / mixed signal section 332-1, such as the driver 335 and / or the transimpedance amplifier 337.

[0105] In some embodiments, the second die 330-2 can be electrically connected to and / or in electrical communication with the photonic interposer 310 via the communication path. For example, the second die 330-2 can be electrically connected to and / or in electrical communication with the photonic interposer 310 via the analog / mixed-signal section 332-1 (including the driver 335 and / or the transimpedance amplifier 337), the electronic section 332-2, and the second interposer 320. In some examples, the second die 330-2 can be electrically connected to and / or in electrical communication with the photonic interposer 310 via the communication path that runs through the second interposer 320, the purely electrical section 332-2, and the analog / mixed-signal section 332-1.In some examples, the second die 130-2 can be electrically connected to the photonic interposer 310 via the modulator 339 and / or the photodetector 341 of the photonic interposer 310 and / or be in electrical communication.

[0106] In some embodiments, the second die 330-2 can be optically connected to the fiber array unit (FAU) 350 via the photonic interposer 310 and / or be in optical communication, and can also be electrically connected to the photonic interposer 310 via the communication path and / or be in electrical communication. For example, the second die 330-2 can be optically connected to the fiber array unit (FAU) 350 via the photonic interposer 310 and / or be in optical communication, and can also be electrically connected to the photonic interposer 310 via the analog / mixed-signal section 332-1, the electronic section 332-2, and the second interposer 320.In some embodiments, the second die 330-2 can be optically connected and / or optically communicated with the fiber array unit (FAU) 350 of the circuit housing 300 via an optical section of the communication path that passes through the photonic interposer 310, and electrically communicated with the photonic interposer 310 via the communication path that passes through the second interposer 320, the electronic section 332-2, and the analog / mixed-signal section 332-1. This allows the third processing element 334-3 to communicate with the fiber array unit 350.

[0107] As can be seen, the circuit housing 300 can further contain a third die 330-3. The third die 330-3 can contain a fourth processing element 334-4. The third die 330-3 can be connected to the photonic interposer 310. For example, the fourth processing element 334-4 can communicate with optical elements 345 of the photonic interposer 310. For example, the fourth processing element 334-4 can contain a driver and a transimpedance amplifier that communicate with the optical elements 345, including a modulator and a photodetector, as well as with the photonic interposer 310. The communication path can include an optical connection between the third die 330-3 and the die 330. For example, the optical elements 345 can be optically connected to the modulator 339 and the photodetector 341, which are connected to the drivers 335 and 337 of the analog / mixed signal section 332-1.This allows the third die 330-3 to communicate with the die 330 and / or the second die 330-2. The third die 330-3 can be an optical die or a die that includes optical elements to communicate with the photonic interposer 310.

[0108] The second die 330-2 and / or the third die 330-3 can be connected to the photonic interposer 310 via an RDL layer 361. The RDL layer 361 can extend under a section of the second die 330-2, under the entire second die 330-2, over a part of the photonic interposer 310, over the entire photonic interposer 310, under a part of the second interposer 320, over a part of the optional potting compound 340, over a part of the second interposer 320, over a part of the optional potting compound 340 and a part of the second interposer 320, over the entire second interposer 320, under the entire die 330, over a part of the photonic interposer 310 and over a part of the optional potting compound 340, as well as under a part of the second die 330-2 and under a part of the die 330 and over a part of the second interposer 320, or combinations thereof.In embodiments where the rewiring layer 361 extends over the photonic interposer 310, sections of the rewiring layer 361 can be removed. For example, sections that obstruct optical communication with the photonic interposer 310 can be at least partially or completely removed to enable optical communication.

[0109] Fig. Figure 5 shows a sectional side view of an embodiment of an electrical bridge enclosure with an integrated channel interface located outside the bridge (hereinafter referred to as circuit enclosure 400). The circuit enclosure 400 can be manufactured according to one or more of the methods described herein. For example, the circuit enclosure 400 can be manufactured by the method described in Fig. 7 illustrated methods 600 and by the in Fig. The 9 illustrated processes are produced in 800 units.

[0110] As in Fig. As shown in Figure 5, one of the 430s partially overlaps and is connected to both the photonic interposer 410 and the second interposer 420. As shown in Fig. As shown in Figure 5, the die 430 vertically overlaps both the photonic interposer 410 and the second interposer 420.

[0111] In some embodiments, the second interposer 420 can be a photonic interposer (e.g., a second photonic interposer). Photonic interposers (e.g., the photonic interposer 410 or the second interposer 420) are photonic integrated circuits in some embodiments. In some embodiments, the second interposer 420 is a non-photonic interposer. Non-photonic interposers can, in some embodiments, include a silicon (SI) interposer, an SI bridge, other interposer materials, other bridge materials, or combinations thereof. In some embodiments, the photonic interposer 410 and the second interposer 420 are made of silicon or a silicon alloy.

[0112] As shown, the photonic interposer 410 and the second interposer 420 are adjacent to each other. For example, as shown, the photonic interposer 410 and the second interposer 420 are separated from each other only by an optional potting compound 440. In some embodiments, the photonic interposer 410 and the second interposer 420 are directly adjacent. For example, the photonic interposer 410 and the second interposer 420 may be separated from each other only by a gap. In some embodiments, the photonic interposer 410 and the second interposer 420 abut each other. For example, the photonic interposer 410 and the second interposer 420 may be in direct contact with each other (e.g., without the optional potting compound 440).

[0113] The die 430 can contain various sections. For example, the die 430 can contain an analog mixed-signal section 432-1 and / or a purely electrical section 432-2. The analog mixed-signal section 432-1 can contain a first processing element 434-1. The first processing element 434-1 can send and / or receive data via the photonic interposer 410. For example, the first processing element 434-1 can send and / or receive data photonically via the photonic interposer 410. The electronic section 432-2 can contain a second processing element 434-2. The second processing element 434-2 can send and / or receive data via the second interposer 420. For example, the second interposer 420 can be an electronic interposer (e.g., not a photonic interposer), so that the second processing element 434-2 can send and / or receive data electrically via the second interposer 420.

[0114] As shown, the circuit housing 400 can optionally include a substrate 401 that is electrically connected to the photonic interposer 410 and / or the second interposer 420. An optional RDL layer 460 can be applied to the substrate 401 to facilitate electrical connection to the photonic interposer 410 and / or the second interposer 420. An additional optional RDL layer 461 can be applied to the substrate 401 above the first rewiring layer 460 to enable electrical connection to the photonic interposer 410 and / or the second interposer 420.

[0115] As shown, the circuit housing 400 can optionally contain a second die 430-2. The second die 430-2 and / or the third die 430-3 can contain one or more of the following elements: a general-purpose data storage, a high-bandwidth storage, HBM3, a processor, an image processor, a video processor, and a general-purpose processor. The second processing element 434-2 can be configured to communicate with the second die 430-2 via a communication path (shown in red). The second die 430-2 can contain a third processing element 434-3. The third processing element 434-3 can send and / or receive data via the second interposer 420. For example, the second interposer 420 can be an electronic interposer (e.g., not a photonic interposer), so that the third processing element 434-3 can send and / or receive data electrically via the second interposer 420.

[0116] As discussed herein, the second die 430-2 can be electrically connected to the second interposer 420 via an electronic section of the communication path. This can enable the second die 430-2 to communicate with the second interposer 420 and / or the photonic interposer 410. In some embodiments, the second die 430-2 can be a third-party die or chip. In some embodiments, the second die 430-2 can be a different type of die or chip than the die 430.

[0117] In some embodiments, the second die 430-2 can be electrically connected to and / or in electrical communication with the purely electrical section 432-2 of die 430 via the communication path. For example, the second die 430-2 can be electrically connected to and / or in electrical communication with the purely electrical section 432-2 via the second interposer 420. In some embodiments, the second die 430-2 can be electrically connected to and / or in electrical communication with the electronic section 432-2 via the communication path that runs through the second interposer 420.

[0118] The second die 430-2 can contain a third processing element 434-3. This can communicate with the second processing element 434-2 in the electronic section 432-2 via the communication path. For example, the third processing element 434-3 can receive signals and / or information from the electronic section 432-2 of the die 430 via the communication path.

[0119] In some embodiments, the second die 430-2 can be electrically connected to and / or in electrical communication with the analog / mixed signal section 432-1 of die 430 via the communication path. For example, the second die 430-2 can be electrically connected to and / or in electrical communication with the analog / mixed signal section 432-1 via the electronic section 432-2 and the second interposer 420. In some embodiments, the second die 430-2 can be electrically connected to and / or in electrical communication with the analog / mixed signal section 432-1 via the communication path that runs through the second interposer 420 and the electronic section 432-2. This allows the third processing element 434-3 to communicate with the first processing element 434-1 of the analog / mixed signal section 432-1.

[0120] In some embodiments, the second die 430-2 can be electrically connected to and / or in electrical communication with the optical elements 445 of the photonic interposer 410 via the communication path. For example, the second die 430-2 can be electrically connected to and / or in electrical communication with the photonic interposer 410 via the analog / mixed-signal section 432-1, the electronic section 432-2, and the second interposer 420. In some embodiments, the second die 430-2 can be electrically connected to and / or in electrical communication with the photonic interposer 410 via the communication path that runs through the second interposer 420, the electronic section 432-2, and the analog / mixed-signal section 432-1. This can enable the third processing element 434-3 to communicate with the optical elements 445 of the photonic interposer 410.

[0121] In some embodiments, the second die 430-2 can be optically connected to and / or in optical communication with the fiber array unit (FAU) 450 via the photonic interposer 410, and can also be electrically connected to and / or in electrical communication with the photonic interposer 410 via the communication path. For example, the second die 430-2 can be optically connected to and / or in optical communication with the fiber array unit 450 via the photonic interposer 410, and electrically connected to or in electrical communication with the photonic interposer 410 via the analog / mixed-signal section 432-1, the electronic section 332-2, and the second interposer 420.In some examples, the second die 430-2 can be optically connected to and / or in optical communication with the fiber array unit 450 of the circuit housing 400 via an optical section of the communication path that passes through the photonic interposer 410, and electrically connected to and / or in electrical communication with the photonic interposer 410 via the communication path that passes through the second interposer 420, the electronic section 432-2, and the analog / mixed-signal section 432-1. This allows the third processing element 434-3 to communicate with the fiber array unit 450.

[0122] The second die 430-2 can be connected to the second interposer 420 via an optional rewiring layer 462.The rewiring layer 462 can extend under a section of the second die 430-2, under the entire second die 430-2, over a section of the second interposer 420, over the entire extent of the second interposer 420, under a section of the photonic interposer 410, over a section of the optional potting compound 440, over a section of the photonic interposer 410, over a section of the optional potting compound 440 and a section of the photonic interposer 410, over the entire extent of the photonic interposer 410, under the entire extent of the die 430, over a section of the second interposer 420 and over a section of the optional potting compound 440 and under a section of the second die 430-2 and under a section of the die 430 and over a section of the photonic interposer 410, or over combinations thereof.

[0123] The rewiring layer 462 and / or the second interposer 420 can be combined with the photonic interposer 410 to create high-precision contact surfaces. For example, the connection (e.g., via the rewiring layer 462) between the die 430 and the photonic interposer 410, as well as between the die 430 and the second interposer 420, requires a high degree of precision due to the overlap of the die 430 with both interposers. The high-precision contact surfaces can have a top surface that has substantially the same vertical height above the photonic interposer 410 and the second interposer 420. The high-precision contact surfaces can eliminate one or more tolerance issues between the photonic interposer 410 and the second interposer 420 in one or more directions from the X-direction, the Y-direction, and the vertical direction.

[0124] In embodiments where the RDL layer 462 extends over the photonic interposer 410, sections of the RDL layer 462 can be removed. For example, sections of the RDL layer 462 that obstruct optical communication with the photonic interposer 410 can be at least partially or completely removed to enable optical communication.

[0125] In embodiments where the second interposer 420 is an electrical interposer, the second die 430-2 is electrically connected to the second interposer 420, for example, by means of an optional rewiring layer 462 and / or one or more TSVs 470. In embodiments where the second interposer 420 is a photonic interposer, the second die 430-2 is optically connected to the second interposer 420.

[0126] The circuit housing 400, as shown, can optionally contain one or more optical elements (e.g., fiber array units 450). The one or more optical elements are optically connected to the photonic interposer 410. As shown in Fig. As shown in Figure 5, the RDL layer 462 is removed beneath fiber array units 450 to form, for example, the optional aperture 490.

[0127] In some embodiments, at least one section of the second interposer 420 beneath at least one die (e.g., the second die 430-2 or an additional die) can be a potting compound. The potting compound located beneath at least one die can include a via and / or a bonded via array to support communication with the at least one die.

[0128] As in Fig. As shown in Figure 5, the photonic interposer 410 and the second interposer 420 do not overlap vertically. In some embodiments, the photonic interposer 410 and the second interposer 420 overlap at least partially in the vertical direction.

[0129] The die 430 can contain an ASIC, a processor, an image processor, a video processor, a general-purpose processor, or combinations thereof. As shown, the die 430 can be larger than the photonic interposer 410 in at least one dimension. As shown, the die 430 is larger than the photonic interposer 410 in the x-direction. In some embodiments, the die 430 is larger than the photonic interposer 410 in two or more dimensions.

[0130] In some embodiments, the photonic interposer 410 is optically connected to the die 430. For example, optical signals can be sent from the photonic interposer 410 to the die 430 and received there, and / or sent from the die 430 and received by the photonic interposer 410.

[0131] In embodiments where the second interposer 420 is a photonic interposer, the second interposer 420 is optically connected to the 430 and the second die 430-2. For example, optical signals can be emitted from the second interposer 420 and received by the die 430 and the second die 430-2, and / or emitted by the die 430 and the second die 430-2 and received by the second interposer 420.

[0132] In embodiments where the second interposer 420 is a non-photonic interposer, the second interposer 420 is electrically connected to the die 430 and the second die 430-2. Electrical signals can, for example, be emitted by the second interposer 420 and received by the die 430 and / or the second die 430-2, and / or emitted by the die 430 and / or the second die 430-2 and received by the second interposer 420. In some embodiments, the second interposer 420 can have one or more TSVs 470s that are electrically connected to the die 430 and the second die 430-2. For example, the second interposer 420 can be electrically connected to the section of the die 430 that overlaps the second interposer 420, and / or to the second die 430-2 by the TSVs 470. In some embodiments, the photonic interposer 410 can include one or more TSVs 470.

[0133] Fig. Figure 6 shows a top view of an embodiment of an electrical bridge enclosure with an integrated bridge-external photonic channel interface (hereinafter: circuit enclosure 500). The circuit enclosure 500 can be manufactured according to one or more of the methods described herein. For example, the circuit enclosure 500 can be manufactured according to the method described in Fig. 7 shown methods 600, which in Fig. 8 shown methods 700, which in Fig. 9 shown methods 800 and the one in Fig. The 10 methods shown can produce 900 units.

[0134] The circuit package 500 comprises several photonic interposers (e.g., the photonic interposer 510, a second 510-2, and a third 510-3), several additional interposers (e.g., a second interposer 520 and a third interposer 520-2), and several dies (e.g., die 530, second die 530-2, third die 530-3, fourth die 530-4, fifth die 530-5, and sixth die 530-6). One or more of the several dies may partially overlap and be connected to one or more of the several photonic interposers and / or one or more of the additional interposers.

[0135] The dies can contain multiple sections or just one. The die 530 comprises an analog / mixed-signal section 532-1 and an electronic section 532-1. The analog / mixed-signal section 532-1 can contain a first processing element 534-1. The first processing element 534-1 can send and / or receive data via the photonic interposer 510, namely using the photonic interposer 510. The electronic section 532-2 can contain a second processing element 534-2. The second processing element 534-2 can send and / or receive data via the second interposer 520. For example, the second interposer 520 can be a purely electrical interposer (e.g., not a photonic interposer), so that the second processing element 534-2 can send and / or receive data electrically via the second interposer 520.

[0136] The second Die 530-2 comprises several sections.The second Die 530-2 is shown with an electronic section above the second interposer 520, comprising a third processing element 534-3, which can photonically send and / or receive data via the second interposer 520; with an analog / mixed-signal section above the second photonic interposer 510-2, comprising a fourth processing element 534-4, which can photonically send and / or receive data via the second photonic interposer 510-2; with an electronic section above the third interposer 520-2, comprising a fifth processing element 534-5, which can electrically send and / or receive data via the third interposer 520-2; and shown with an analog / mixed-signal section above the third photonic interposer 510-3, which includes a sixth processing element 534-6, which can send and / or receive data photonically via the third photonic interposer 510-3.The third die 530-3 comprises an analog / mixed-signal section above the second photonic interposer 510-2 with a seventh processing element 534-7, which can send and / or receive data photonically via the second photonic interposer 510-2, and an electronic section above the third interposer 520-2 with an eighth processing element 534-8, which can send and / or receive data electrically via the third interposer 520-2. The fourth die 530-4 comprises only an electronic section above the third interposer 520-2 with a ninth processing element 534-9, which can send and / or receive data electrically via the third interposer 520-2. The fifth Die 530-5 comprises only an analog / mixed-signal section above the third photonic interposer 510-3 with a tenth processing element 534-10, which can send and / or receive data photonically via the third photonic interposer 510-3.More or fewer dies with more or fewer sections and / or more or fewer processing elements can be used, interacting electrophotonically, electrically, or otherwise with more or fewer interposers. All combinations are possible.

[0137] As shown, die 530 vertically overlaps both the photonic interposer 510 and the second interposer 520. The second die 530-2 vertically overlaps the second interposer 520, the second photonic interposer 510-2, the third photonic interposer 510-3, and the third interposer 520-2. Overlapping multiple interposers can enable communication between components while reducing the cost of a single photonic interposer sized to connect to all dies (e.g., the size of the dashed box surrounding all interposers).

[0138] In some embodiments, the multiple additional interposers (e.g., second interposer 520 and third interposer 520-2) can be a photonic interposer (e.g., a second photonic interposer). One or more photonic interposers (e.g., photonic interposer 510, second photonic interposer 510-2, third photonic interposer 510-3, second interposer 520, and third interposer 520-2) are photonic integrated circuits in some embodiments. In some embodiments, one or more of the additional interposers (e.g., second interposer 520 and third 520-2) are non-photonic interposers. Non-photonic interposers can, in some embodiments, comprise one or more silicon (SI) interposers, SI bridges, other interposer materials, other bridge materials, or combinations thereof.In some embodiments, one or more of the photonic interposers and / or one or more of the multiple additional interposers are formed from silicon or a silicon alloy.

[0139] In some embodiments, one or more of the photonic interposers and / or one or more of the multiple additional interposers are located next to each other. For example, one or more of the photonic interposers and / or one or more of the multiple additional interposers may be separated from each other only by a gap or a spacer (e.g., a potting compound). In some embodiments, one or more of the multiple photonic interposers or one or more of the multiple additional interposers may be directly adjacent to each other. For example, one or more of the multiple photonic interposers and / or one or more of the multiple additional interposers may be separated from each other only by a gap. In some embodiments, one or more of the multiple photonic interposers and / or one or more of the multiple additional interposers abut each other.For example, one or more of the multiple photonic interposers and / or one or more of the multiple additional interposers can be in direct contact. In some embodiments, two or more interposers can be adjacent, two or more interposers can be directly adjacent, two or more interposers can be abutting each other, or combinations thereof can occur.

[0140] As in Fig. As shown in Figure 5, one or more of the multiple photonic interposers and / or one or more of the multiple additional interposers do not overlap vertically. In some embodiments, one or more of the multiple photonic interposers and / or one or more of the multiple additional interposers overlap at least partially vertically.

[0141] The multiple dies can contain an ASIC, a processor, an image processor, a video processor, a general-purpose processor, or combinations thereof. The multiple dies can be larger in at least one dimension than one or more of the multiple photonic interposers and / or one or more of the multiple additional interposers. As shown, die 530 is larger in the x-direction than photonic interposer 510, and the second die 530-2 is larger than the second interposer 520-2 in its entirety. In some embodiments, one or more of the multiple dies are larger in two or more dimensions than one or more of the multiple photonic interposers and / or one or more of the multiple additional interposers.

[0142] In some embodiments, the circuit housing 500 may contain one or more optical elements, a substrate, various RDL layers, openings in one or more RDL layers, TSVs, any of the other components described herein, or combinations thereof.

[0143] In some embodiments, the RDL layers described herein may have lines of 10 micrometers per inch, less than 2 micrometers in the vertical direction, be less than two layers thick, or combinations thereof.

[0144] Fig. Figure 7 shows an exemplary method 600 for manufacturing a circuit housing (e.g., circuit housing 100, 200, 300, 400, 500). Method 600 includes, in step 610, connecting a photonic interposer (e.g., photonic interposer 110, 210, 310, 410, 510, 510-2, 510-3) and a second interposer (e.g., second interposer 120, 220, 320, 420, 520, third interposer). Method 600 includes connecting a die (e.g., die 130, 230, 330, 330-2, 430, 430-2, 530, 530-2, 530-3, 530-4) to both the photonic and the second interposer, wherein the die partially overlaps the photonic and second interposers. Method 600 also includes connecting an optical element (e.g., the fiber array unit FAU 250, 350, 450) to the photonic interposer.

[0145] Method 600 optionally includes the application of a potting compound (e.g., potting compound 240, 340, 440) to the photonic and the second interposer to form a rigid unit. In some embodiments, the potting compound consists of silicon or a silicon alloy. In some embodiments, the potting compound contains a material whose thermal expansion corresponds to the thermal expansion of one or more of the photonic and second interposers.

[0146] Method 600 optionally includes forming the second interposer as a potting compound. Method 600 optionally includes providing one or more substrate vias, potting compound vias, bond via arrays, or combinations thereof through the potting compound.

[0147] Method 600 optionally includes attaching a second die to at least one or more of the photonic interposers and the second interposer. Method 600 optionally includes attaching a third die to one or more of the photonic interposers, the second interposer, or a third interposer.

[0148] Fig. Figure 8 shows an exemplary method 700 for manufacturing a circuit housing (e.g., circuit housing 100, 200, 300, 400, 500). Method 700 optionally includes in step 710 the connection of a photonic interposer (e.g., photonic interposer 110, 210, 310, 410, 510, 510-2, 510-3) and a second interposer (e.g., second interposer 120, 220, 320, 420, 520, third interposer 510-2) on a substrate.

[0149] Procedure 700 involves connecting a photonic and a second interposer according to procedure 720. Procedure 700 optionally includes rigidly connecting a photonic and a second interposer according to procedure 730.

[0150] Procedure 700 optionally includes the application of a rewiring layer to a bottom surface of one or more of the photonic interposers and a second interposer according to procedure 740. Procedure 700 optionally includes the removal of the photonic and the second interposer from a support according to procedure 750. The procedure optionally includes the application of a rewiring layer to a top surface of the second interposer according to procedure 760.

[0151] Method 700 comprises joining a die according to step 770 (e.g., die 130, 230, 330, 330-2, 430, 430-2, 530, 530-2, 530-3, 530-4) to both the photonic and the second interposer, with the die partially overlapping both. Method 700 optionally comprises exposing a section of a top surface of the photonic interposer according to step 780. Exposing the section may include one or more of the following steps: laser drilling, etching, or clearing. Method 700 comprises, in step 790, joining an optical element (e.g., fiber array unit FAU 250, 350, 450) to the photonic interposer, optionally at the exposed location from step 780.

[0152] Method 700 optionally includes the application of a potting compound (such as potting compound 240, 340, 440) to the photonic interposer and the second interposer to form a rigid unit. In some embodiments, the potting compound consists of silicon or a silicon alloy. In some embodiments, the potting compound comprises a material that corresponds to the thermal expansion of one or more of the photonic interposers and the second interposer.

[0153] Method 700 optionally includes forming the second interposer as a potting compound. Method 700 optionally includes providing one or more substrate vias, potting compound vias, bond via arrays, or combinations thereof through the potting compound.

[0154] Method 700 optionally includes attaching a second die to one or more of the following elements: the photonic interposer and the second interposer. Method 700 optionally includes attaching a third die to one or more of the following elements: the photonic interposer, the second interposer, or a third interposer.

[0155] Fig. Figure 9 shows an exemplary process 800 for manufacturing a circuit housing (e.g., circuit housing 100, 200, 300, 400, 500). Process 800 optionally includes the application of a rewiring layer (e.g., RDL layer 460) to a substrate (e.g., substrate 201, 301, 401) according to step 810. Step 810 of process 800 includes connecting a photonic interposer (e.g., photonic interposer 110, 210, 310, 410, 510, 510-2, 510-3) and a second interposer (e.g., second interposer 120, 220, 320, 420, 520, third interposer 510-2).

[0156] Method 800 optionally includes the rigid connection of a photonic interposer and a second interposer according to step 830. Method 800 optionally includes the application of a rewiring layer to a section of the photonic interposer and the second interposer according to step 840.

[0157] In some cases, applying the rewiring layer to sections of the photonic interposer and the second interposer results in the formation of multiple high-precision contact surfaces on two or more of the following components: the photonic interposer, the second interposer, a second photonic interposer, a third interposer, and a third photonic interposer. In some cases, the formation of multiple high-precision contact surfaces facilitates the connection of the die to two or more of the following components: the photonic interposer, the second interposer, a second photonic interposer, a third interposer, and a third photonic interposer.In some cases, facilitating the connection of the die to two or more of the following components, namely the photonic interposer, the second interposer, a second photonic interposer, a third interposer, and a third photonic interposer, involves forming a top surface on the high-precision contact surfaces that has substantially the same vertical height. In some embodiments, the high-precision contact surfaces eliminate tolerance problems between two or more of the following components, namely the photonic interposer, the second interposer, a second photonic interposer, a third interposer, and a third photonic interposer, in one or more of the X-direction, the Y-direction, and the vertical direction.

[0158] Procedure 800 optionally includes exposing a section of a top surface of the photonic interposer according to step 850.

[0159] Method 800 comprises connecting a die according to step 860 (e.g., die 130, 230, 330, 330-2, 430, 430-2, 530, 530-2, 530-3, 530-4) to both the photonic interposer and the second interposer, with the die partially overlapping both. Method 800 comprises connecting an optical element (e.g., fiber array unit FAU 250, 350, 450) to the photonic interposer according to step 870.

[0160] Method 800 optionally includes the application of a potting compound (e.g., potting compound 240, 340, 440) to the photonic interposer and the second interposer to form a rigid unit. In some embodiments, the potting compound consists of silicon or a silicon alloy. In some embodiments, the potting compound comprises a material that accommodates the thermal expansion of one or more of the photonic interposers and the second interposer.

[0161] Method 800 optionally includes forming the second interposer as a potting compound. Method 800 optionally includes providing one or more substrate vias, potting compound vias, bond via arrays, or combinations thereof through the potting compound.

[0162] Method 800 optionally includes attaching a second die to one or more of the following elements: the photonic interposer and the second interposer. Method 800 optionally includes attaching a third die to one or more of the following elements: the photonic interposer, the second interposer, or a third interposer.

[0163] Fig. Figure 10 shows an exemplary method 900 for manufacturing a circuit housing (e.g., circuit housings 100, 200, 300, 400, 500). Method 900 comprises, in step 910, connecting a photonic interposer (e.g., photonic interposer 110, 210, 310, 410, 510, 510-2, 510-3) to an electrical interposer (e.g., the second interposer 120, 220, 320, 420, 520 and the third interposer 520-2). Procedure 900 includes in step 920 the provision of a die (e.g., die 130, 230, 330, 430, 530, 530-2, 530-3, 530-4, 530-5, 530-6) which is divided into a first and a second section (e.g., analog / mixed signal sections 132-1, 232-1, 332-1, 432-1, 532-1, electronic sections 132-2, 232-2, 332-2, 432-2, 532-2, or other sections).

[0164] Method 900 comprises, in step 930, connecting the first section of the die to the photonic interposer and the second section of the die to the electrical interposer. Method 900 comprises, in step 940, forming one or more vias in the electrical interposer configured to provide an electrical connection between the second section of the die and at least one other die. Method 900 comprises, according to step 950, connecting an optical element (e.g., the fiber array unit FAU 250, 350, 450) to the photonic interposer.

[0165] Fig.Figure 11 is an exemplary method 1000 for manufacturing a circuit housing (e.g., circuit housing 100, 200, 300, 400, 500). Method 1000 comprises, in step 1010, connecting a photonic interposer (e.g., photonic interposer 110, 210, 310, 410, 510, 510-2, 510-3) to an electrical interposer (e.g., the second interposer 120, 220, 320, 420, 520 and the third interposer 520-2). Method 1000 includes in step 1020 connecting an analog / mixed signal section (e.g. analog / mixed signal sections 132-1, 232-1, 332-1, 432-1, 532-1) of a die (e.g. die 130, 230, 330, 430, 530, 530-2, 530-3, 530-4, 530-5, 530-6) to the photonic interposer.

[0166] Method 1000 further comprises, in step 1030, connecting an electronic section (e.g., electronic sections 132-2, 232-2, 332-2, 432-2, 532-2) of the die to the electrical interposer. The die partially overlaps both the photonic and the electrical interposer. Method 1000 also comprises, according to step 1040, connecting an optical element (e.g., fiber array unit 250, 350, 450) to the photonic interposer.

[0167] In some cases, Exemplary Method 1000 includes connecting a driver of the analog / mixed-signal section of the die to a modulator of the photonic interposer. The modulator can be any modulator type, including a thermally stable modulator and / or an electroabsorption modulator. In some cases, Exemplary Method 1000 includes connecting a transimpedance amplifier (TIA) of the analog / mixed-signal section of the die to a photodetector of the photonic interposer.

[0168] In some cases, exemplary method 1000 includes rigidly connecting the photonic interposer to the electrical interposer. Method 1000 may include applying a potting compound to the photonic interposer and the electrical interposer to form a rigid unit. In some embodiments, the potting compound may be composed of silicon and / or a silicon alloy. In some embodiments, the potting compound comprises a material that accommodates the thermal expansion of one or more of the photonic interposers and the electrical interposer. In some cases, the electrical interposer is formed as a potting compound. In some embodiments, the electrical interposer includes a potting compound through-hole plating.

[0169] In some embodiments, the electrical interposer comprises a bonded via array. In some cases, Exemplary Method 1000 comprises forming the photonic interposer and the electrical interposer on a substrate. In some cases, Exemplary Method 1000 comprises depositing a rewiring layer on the underside of at least one of the following components: the photonic interposer and the electrical interposer. In some cases, the photonic and the electrical interposer are detached from the substrate.

[0170] In some cases, Exemplary Method 1000 includes applying a rewiring layer to the electrical interposer. In some cases, the rewiring layer is applied to the top surface of the electrical interposer. In some cases, Exemplary Method 1000 includes attaching the die to the rewiring layer on the top surface of the electrical interposer.

[0171] In some embodiments, a second die is attached to one or more of the following components: the photonic interposer and the electrical interposer. In some embodiments, a third die is attached to one or more of the following components: the photonic interposer, the electrical interposer, or a third interposer. In some embodiments, the third interposer may be a second photonic interposer. In some embodiments, the third interposer may also be a non-photonic interposer.

[0172] In some embodiments, one or more of the photonic interposers and the third interposer can be a photonic integrated circuit. In some embodiments, the electrical interposer is an SI interposer. In some embodiments, the electrical interposer is an SI bridge.

[0173] In some cases, Exemplary Method 1000 includes attaching a third die to one or more of the following components: the photonic interposer, the electrical interposer, and the third interposer. In some cases, Exemplary Method 1000 includes exposing a section of the top surface of one or more photonic, electrical, and third interposers. In some cases, exposing the section of the top surface of one or more photonic, electrical, and third interposers includes laser drilling, etching, or milling.

[0174] In some cases, Exemplary Method 1000 comprises depositing at least one optical element onto a section of the top surface of one or more of the following elements, namely the photonic interposer, the electrical interposer, and the third interposer. In some cases, depositing the one or more optical elements onto a section of the top surface of one or more of the photonic interposers, the electrical interposer, and the third interposer comprises directly depositing the one or more optical elements onto a section of a top surface of one or more of the photonic interposers, the electrical interposer, and the third interposer.In some cases, the direct application of one or more optical elements to a section of the top surface of one or more of the photonic interposer, electrical interposer and third interposer involves the direct application of one or more optical elements to the exposed section of one or more of the photonic interposer, electrical interposer and third interposer.

[0175] In some cases, Exemplary Method 1000 includes applying a rewiring layer to a substrate. In some cases, Exemplary Method 1000 includes attaching two or more of the photonic interposer, the electrical interposer, and the third interposer to the rewiring layer on the substrate. In some cases, Exemplary Method 1000 includes applying the rewiring layer to a section of two or more of the photonic interposer, the electrical interposer, and the third interposer. In some cases, applying the rewiring layer to a section of two or more of the photonic interposer, the electrical interposer, and the third interposer results in the formation of a plurality of high-precision contact surfaces on the two or more of the photonic interposer, the electrical interposer, and the third interposer.In some cases, forming multiple high-precision contact surfaces on two or more of the photonic interposer, the electrical interposer, and the third interposer facilitates the connection of the dies to these two or more interposers. In some cases, facilitating the connection of the dies to two or more of the photonic interposer, the electrical interposer, and the third interposer involves forming a top surface of the high-precision contact surfaces that are substantially at the same vertical height. In some embodiments, the high-precision contact surfaces eliminate tolerance problems between two or more of the photonic interposer, the electrical interposer, and the third interposer in one or more directions along the X-direction, the Y-direction, and the vertical direction.

[0176] At least one of the specific embodiments of the present disclosure is described herein. These described embodiments are examples of the techniques disclosed herein. To enable a concise description of these embodiments, not all features of an actual embodiment may be described in the description. It should be noted that, as with any engineering or design project, the development of such an actual implementation involves numerous embodiment-specific decisions to achieve the specific goals of the developers, such as compliance with system-related and business-related constraints, which may vary from one embodiment to another.It is also understood that while such development work may be complex and time-consuming, for the professional who benefits from this revelation it represents a routine task in the field of design, manufacturing and production.

[0177] In the preceding descriptions, the articles "a," "an," and "the" are to be understood as indicating that one or more of the elements in the preceding descriptions are present. The terms "comprising," "including," and "having" are to be understood as inclusive formulations and mean that, in addition to the listed elements, further elements may also be present. Furthermore, in this disclosure, references to "an embodiment" are not to be interpreted as excluding the existence of other embodiments that also have the specified features. For example, each element described herein in relation to one embodiment may be combined with any element of another embodiment described herein.Numbers, percentages, ratios, or other values ​​specified herein each include the stated value as well as values ​​that are "approximately" or "closely" corresponding to that value, as understood by a person skilled in the art in the embodiments of the present disclosure. A stated value should therefore be interpreted to include values ​​that are at least close enough to the stated value to perform a desired function or achieve a desired result. The stated value includes at least the variations that can be expected in a suitable manufacturing or production process and may include values ​​that are within 5%, within 1%, within 0.1%, or within 0.01% of a stated value.

[0178] A person with average knowledge in the relevant field should recognize, with regard to the present disclosure, that equivalent embodiments do not deviate from the nature and scope of the present disclosure and that various changes, substitutions, and modifications to the embodiments disclosed herein are made without departing from the inventive concept and scope of protection of the disclosure. Equivalent embodiments, including functional "means-plus-function" clauses, are intended to cover the structures described herein that perform the specified function, including both structural equivalents that operate in the same manner and equivalent structures that provide the same function.It is the applicant's express intention not to rely on means-plus functions or other functional claims, except those in which the words "means for" appear together with a related function. Any addition, deletion, or modification with respect to embodiments that falls within the scope and protection of the claims is covered by the claims.

[0179] The terms “approximately,” “about,” and “essentially,” as used herein, represent a quantity close enough to the specified value to still perform a desired function or achieve a desired result. The terms “approximately,” “about,” and “essentially” may refer, for example, to a quantity that is less than 5%, less than 1%, less than 0.1%, or less than 0.01% of a specified value. Furthermore, all directional references or frames of reference in the foregoing description are to be understood as relative directions or movements only. For example, any references to “above” and “below,” or “over” and “under,” are to be understood merely as describing the relative position or movement of the associated elements.

[0180] The present disclosure may be implemented in other specific forms without deviating from its essence or features. The described embodiments are to be considered illustrative and not limiting. The scope of the disclosure is therefore determined by the appended claims and not by the foregoing description. Modifications that fall within the scope of meaning and equivalence of the claims are included within their scope of protection. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 437,639

[0001] US 63 / 437,641

[0001] US 18 / 217,898

[0001] US 18 / 076,196

[0001] US 18 / 076,210

[0001] US 63 / 392,475

[0001]

Claims

[1] Circuit housing, comprising: a photonic interposer; an electric interposer; a die, including an analog / mixed-signal section and an electronic section, wherein the die partially overlaps both the photonic interposer and the electrical interposer, the analog / mixed-signal section is connected to the photonic interposer, and the electronic section is connected to the electrical interposer; and a plurality of electrical connections between the photonic interposer and the die. [2] Circuit housing according to claim 1, wherein the photonic interposer comprises a modulator. [3] Circuit housing according to claim 2, wherein the modulator is a thermally stable modulator. [4] Circuit housing according to claim 3, wherein the thermally stable modulator is an electroabsorption modulator (EAM). [5] Circuit housing according to one of claims 1-4, wherein the analog / mixed signal section includes a driver. [6] Circuit housing according to claim 5, wherein the plurality of electrical connections includes a first electrical connection which connects the photonic interposer to the analog / mixed signal section, and wherein the driver is connected to a first end of the first electrical connection. [7] Circuit housing according to claim 6, wherein the photonic interposer includes the modulator according to any one of claims 2-6, and wherein the modulator is connected to a second end of the first electrical connection. [8] Circuit housing according to one of claims 1-7, wherein the photonic interposer includes a photodetector. [9] Circuit housing according to claim 8, wherein the photodetector includes a photodiode. [10] Circuit housing according to one of claims 1-9, wherein the analog / mixed signal section includes a transimpedance amplifier. [11] Circuit housing according to claim 10, wherein the plurality of electrical connections includes a second electrical connection which connects the photonic interposer to the analog / mixed signal section, and wherein the TIA is connected to a first end of the second electrical connection. [12] Circuit housing according to claim 11, wherein the photonic section includes the photodetector according to one of claims 8 or 9, and wherein the photodetector is connected to a second end of the second electrical connection from the plurality of electrical connections. [13] Circuit housing according to one of claims 1-12, further comprising a second die with a processing element, wherein the processing element is electrically connected to the electrical interposer. [14] Circuit housing according to claim 13, wherein the second die is electrically connected to the electronic section via the electrical interposer. [15] Circuit housing according to claim 14, wherein the second die is electrically connected to the analog / mixed signal section via the electronic section and the electrical interposer. [16] Circuit housing according to claim 15, wherein the second die is electrically connected to the photonic interposer via the analog / mixed signal section, the electronic section and the electrical interposer. [17] Circuit housing according to claim 16, wherein the second die is electrically connected to the photonic interposer via a driver in the analog / mixed signal section. [18] Circuit housing according to claim 17, wherein the second die is electrically connected to the photonic interposer via a modulator in the photonic interposer. [19] Circuit housing according to one of claims 16-18, wherein the second die is electrically connected to the photonic interposer via the analog / mixed signal section, the electronic section and the electrical interposer and optically connected to a fiber array unit via the photonic interposer. [20] Circuit housing according to one of claims 1-19, wherein one or more of the plurality of electrical connections are shorter than 100 µm. [21] Circuit housing according to one of claims 1-20, wherein one or more of the plurality of electrical connections is one or more of one or more of solder joints, wire connections, copper pillars, wire bonds, substrate vias (TSVs), dielectric vias (TDVs), rewiring layers (RDLs) or contact pads. [22] Circuit housing according to one of claims 1-21, further comprising a fiber array unit between the photonic interposer and the die. [23] Circuit housing according to one of claims 1-22, wherein one or more of the modulators according to one of claims 2-7 or the photodetector according to one of claims 8 or 9 are connected to the FAU via an FAU connection. [24] Circuit housing according to claim 23, wherein the FAU connection is a bidirectional channel. [25] Circuit housing according to claim 24, wherein the bidirectional channel contains one or more waveguides. [26] Circuit housing according to one of claims 1-25, wherein the photonic interposer includes a photonic integrated circuit (PIC). [27] Circuit housing, comprising: a photonic interposer; a second interposer; and a die that partially overlaps and connects with both the photonic and the second interposer. [28] Circuit housing according to claim 27, wherein the die partially vertically overlaps both the photonic and the second interposer. [29] Circuit housing according to one of claims 27 or 28, wherein the second interposer is a non-photonic interposer. [30] Circuit housing according to one of claims 27-29, wherein the second interposer is a second photonic interposer. [31] Circuit housing according to one of claims 27-30, wherein one or more of the photonic interposer and the second interposer are photonic integrated circuits. [32] Circuit housing according to one of claims 27-31, further comprising a third interposer. [33] Circuit housing according to one of claims 27-32, wherein one or more of the second interposer and the third interposer is an SI interposer. [34] Circuit housing according to one of claims 27-33, wherein one or more of the second and third interposers is an SI bridge. [35] Circuit housing according to one of claims 27-34, wherein two or more of the photonic interposer, the second interposer and the third interposer are separated by a potting compound. [36] Circuit housing according to one of claims 27-35, wherein two or more of the photonic interposer, the second interposer and the third interposer are arranged adjacent to each other. [37] Circuit housing according to one of claims 27-36, wherein two or more of the photonic interposer, the second interposer and the third interposer are arranged directly adjacent to each other. [38] Circuit housing according to one of claims 27-37, wherein two or more of the photonic interposer, the second interposer and the third interposer directly abut each other. [39] Circuit housing according to one of claims 27-38, wherein two or more of the photonic interposer, the second interposer and the third interposer do not vertically overlap. [40] Circuit housing according to any one of claims 27-39, wherein the die is an ASIC die, a processor die, an ARM processor die, an image processor die, a tensor engine, a neural compute engine or combinations thereof. [41] Circuit housing according to one of claims 27-40, wherein one or more of the photonic interposer and the second interposer are formed from silicon or a silicon alloy. [42] Circuit housing according to one of claims 27-41, wherein the photonic interposer and the second interposer are laterally surrounded by a potting compound. [43] Circuit housing according to claim 42, wherein the potting compound is formed from silicon or a silicon alloy. [44] Circuit housing according to one of claims 42 or 43, wherein the potting compound contains a material adapted to a thermal expansion of one or more of the photonic interposer and the second interposer. [45] Circuit housing according to one of claims 27-44, wherein the second interposer is a potting compound. [46] Circuit housing according to claim 45, wherein the second interposer has a potting compound through-hole connection. [47] Circuit housing according to one of claims 45 or 46, wherein the second interposer comprises a bond via array. [48] ​​Circuit housing according to one of claims 27-47, further comprising a second die. [49] Circuit housing according to claim 48, wherein the second die does not vertically overlap the photonic interposer. [50] Circuit housing according to one of claims 48 or 49, wherein the second die contains a universal memory. [51] Circuit housing according to one of claims 48-50, wherein the second die contains a processor. [52] Circuit housing according to claim 51, wherein the processor is one or more of an image processor, video processor and a general-purpose processor. [53] Circuit housing according to one of claims 48-52, wherein the second die contains a high bandwidth memory. [54] Circuit housing according to claim 53, wherein the high bandwidth memory is an HBM3. [55] Circuit housing according to one of claims 27-54, further comprising a third die. [56] Circuit housing according to claim 55, wherein the third die contains at least one or more of a universal memory, a high bandwidth memory, HBM3, a processor, an image processor, a video processor and / or a universal processor. [57] Circuit housing according to one of claims 55 or 56, wherein the third die does not vertically overlap the photonic interposer. [58] Circuit housing according to one of claims 55 or 56, wherein the third die vertically overlaps the photonic interposer. [59] Circuit housing according to one of claims 55, 56 or 58, wherein the third die vertically overlaps the photonic interposer and the second interposer. [60] Circuit housing according to one of claims 27-59, further comprising a fourth die. [61] Circuit housing according to one of claims 27-60, further comprising a second photonic interposer. [62] Circuit housing according to one of claims 27-61, further comprising a substrate. [63] Circuit housing according to claim 62, wherein one or more of the components described or claimed herein are connected to the substrate. [64] Circuit housing according to one of claims 27-63, further comprising a rewiring layer. [65] Circuit housing according to claim 64, wherein the rewiring layer electrically connects the die to one or more of the second die, third die or fourth die as described or claimed herein. [66] Circuit housing according to claim 65, wherein the rewiring layer provides an electrical connection from the top of the die to a top of one or more of the second die, third die or fourth die, as described or claimed herein. [67] Circuit housing according to one of claims 65 or 66, wherein the rewiring layer provides an electrical connection from the underside of the die to a top side of one or more of the second die, third die or fourth die, as described or claimed herein. [68] Circuit housing according to one of claims 65-67, wherein the rewiring layer has a line of about 10 µm per space. [69] Circuit housing according to one of claims 65-68, wherein the rewiring layer is less than 2 µm thick in the vertical direction. [70] Circuit housing according to one of claims 65-69, wherein the rewiring layer is less than two layers thick in the vertical direction. [71] Circuit housing according to one of claims 27-70, further comprising one or more optical elements. [72] Circuit housing according to claim 71, wherein the one or more optical elements comprise optical elements that are optically connected to one or more of the photonic interposer, the second interposer, the second photonic interposer, the third interposer and the third photonic interposer as described or claimed herein. [73] Circuit housing according to one of claims 71 or 72, wherein any material of the rewiring layer on one or more of the photonic interposer, second interposer, second photonic interposer, third interposer and third photonic interposer as described and claimed herein is omitted or removed vertically below a section of one or more of the optical elements. [74] Circuit housing, comprising: a photonic interposer; an electric interposer; a first die electrically connected to both the photonic and the electrical interposer, the first die containing an analog / mixed-signal section to enable a first processing element therein to send and receive data using the photonic interposer, and an electronic section to enable a second processing element to send and receive data using the electrical interposer; and a plurality of vias in the electrical interposer to enable the second processing element to send and receive data to one or more additional dies that are electrically coupled to the electrical interposer. [75] Circuit housing according to claim 74, wherein the first and second processing element are selected from a group consisting of CPU, GPU, TPU, a tensor engine, a neural network, an AI accelerator, a router, a memory, a switch, a controller, an ASIC, an image processor, a video processor and a bus.

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