solar cell

Abstract

Solar cell, featuring: a substrate (20) wherein a front side of the substrate (20) has a first region (A1) and a second region (B1) arranged alternately, wherein the first region (A1) has a first pyramidal structure (31), the second region (B1) has a second pyramidal structure (32), and in a direction from a back side of the substrate (20) to the front side of the substrate (20) an apex of the first pyramidal structure (31) is higher than an apex of the second pyramidal structure (32), the first region (A1) has a first diffusion-doped region (41); the back of the substrate (20) has a third region (A2) and a fourth region (B2) arranged alternately, the solar cell has a tunnel layer (61) and a doped semiconductor layer (62) stacked sequentially on a side of the third region facing away from the substrate, and the fourth region (B2) has a third pyramid structure (33); a first electrode (50) arranged on the first region (A1), wherein the first electrode (50) is electrically connected to the first diffusion-doped region (41); and a second electrode (70) which is arranged on the third region (A2), wherein the second electrode (70) is electrically connected to the first doped semiconductor layer (62).

Description

TECHNICAL AREA

[0001] This application relates to the field of photovoltaics, in particular to a solar cell. BACKGROUND

[0002] Solar cells with tunnel oxide passivated contacts (TOPCon) are among the most important solar cells in the field of photovoltaics. Key research and development topics for TOPCon solar cells include reducing light loss due to reflection, improving photoelectric conversion efficiency, and increasing the power generation capacity of TOPCon solar cells. SUMMARY

[0003] Based on this, it is necessary to provide a solar cell to solve the problem of reflected light loss in existing TOPCon solar cells.

[0004] To achieve the aforementioned goal, this application, in a first aspect, provides a solar cell that includes: a substrate, wherein a front side of the substrate comprises a first region and a second region arranged alternately, the first region having a first pyramidal structure, the second region having a second pyramidal structure, and in a direction from a back side of the substrate to the front side of the substrate, a tip of the first pyramidal structure is higher than a tip of the second pyramidal structure, the first region having a first diffusion-doped region; the back side of the substrate having a third region and a fourth region arranged alternately, the solar cell having a tunnel layer and a doped semiconductor layer stacked sequentially on a side of the third region facing away from the substrate, and the fourth region having a third pyramidal structure; a first electrode arranged on the first region, wherein the first electrode is electrically connected to the first diffusion-doped region; and a second electrode located on the third region, the second electrode being electrically connected to the doped semiconductor layer.

[0005] Optionally, the solar cell also includes: a front-side passivation layer arranged at the front of the substrate, wherein the front-side passivation layer covers the first diffusion-doped region of the first region and the substrate in the second region; and a backside passivation layer located on the back side of the substrate, wherein the backside passivation layer covers the doped semiconductor layer on the third region and the substrate in the fourth region.

[0006] Optionally, a projection of the first region onto the substrate and a projection of the fourth region onto the substrate may have an overlapping region. A projection of the second region onto the substrate and a projection of the third region onto the substrate may also have an overlapping region.

[0007] Optionally, the width of the first region is in the range of 80 µm to 300 µm. The width of the second region is in the range of 450 µm to 900 µm. The width of the third region is in the range of 80 µm to 300 µm. The width of the fourth region is in the range of 450 µm to 900 µm.

[0008] Optionally, the ratio of the width of the first region to the width of the second region is in the range of 1:1 to 1:9. The ratio between the width of the third region and the width of the fourth region is in the range of 1:1 to 1:9.

[0009] Optionally, the base of the first pyramid structure is larger than the base of the second pyramid structure. The height of the first pyramid structure is greater than the height of the second pyramid structure.

[0010] Optionally, the length of a base edge of the third pyramid structure lies in the range of 0.5 µm to 4 µm. The height of the third pyramid structure lies in the range of 0.5 µm to 3 µm.

[0011] In an example that does not represent an embodiment of the invention, this application provides a method for manufacturing a solar cell, comprising: Providing a substrate and texturing one front side of the substrate to form an initial pyramid structure; Formation of an initial doped region at the front of the substrate; Removing a section of the initial doped region at intervals, wherein a region in which the initial doped region is retained serves as a first region, and a region in which the initial doped region is removed serves as a second region; and texturing the second region to form a second pyramidal structure on the second region, wherein, in a direction from a back side of the substrate to the front side of the substrate, a peak of the first pyramidal structure is higher than a peak of the second pyramidal structure; Performing a drive-in diffusion in the initial doped region to form a first diffusion-doped region in the first pyramid structure; Sequential formation of a tunnel layer, an intrinsic semiconductor layer, and a second silicon glass layer on the back of the substrate; Doping the intrinsic semiconductor layer to form a doped semiconductor layer; Removing a section of the tunnel layer, the doped semiconductor layer, and the second silicon glass layer stacked at intervals on the back side of the substrate, wherein a region in which the tunnel layer, the doped semiconductor layer, and the second silicon glass layer are retained serves as a third region, and a region in which the tunnel layer, the doped semiconductor layer, and the second silicon glass layer are removed serves as a fourth region; Texturing the fourth region to form a third pyramid structure on the fourth region; Removal of the second silicon glass layer on the third region; Forming a front passivation layer to cover the first diffusion-doped region of the first region and the substrate in the second region, and forming a rear passivation layer to cover the doped semiconductor layer on the third region and the substrate in the fourth region; Forming a first electrode on the first region, wherein the first electrode is electrically connected to the first diffusion-doped region; and Forming a second electrode on the third region, wherein the second electrode is electrically connected to the doped semiconductor layer.

[0012] Optionally, removing a section of the initial doped region at intervals includes: irradiating the initial doped region in the second region with a laser and subsequently texturing the second region to remove the initial doped region in the second region while simultaneously forming the second pyramid structure on the second region.

[0013] Removing a section of the tunnel layer, the doped semiconductor layer, and the second silicon glass layer stacked at intervals on the back side of the substrate includes: irradiating the tunnel layer, the doped semiconductor layer, and the second silicon glass layer on the fourth region with a laser, removing the second silicon glass layer on the fourth region by washing with an acidic solution, and removing the tunnel layer and the doped semiconductor layer on the fourth region during texturing of the fourth region.

[0014] Optionally, after performing the drive-in diffusion on the initial doped region, an oxide layer is formed on an area of ​​the second region and simultaneously a first silicon glass layer is formed on a side of the first diffusion-doped region facing away from the substrate.

[0015] Optionally, when removing the tunnel layer and the doped semiconductor layer on the fourth region, the oxide layer and the first silicon glass layer are removed.

[0016] According to the solar cell and its manufacturing process in this application, the reflection light loss on the front side is reduced by providing the first pyramid structure on the first region of the front side and the second pyramid structure on the second region of the front side, with the apex of the first pyramid structure being higher than the apex of the second pyramid structure; and by providing the third pyramid structure on the fourth region of the back side, the reflection light loss on the back side is also reduced, thereby improving the short-circuit current output and the overall photoelectric conversion efficiency of the solar cell and improving the bifaciality of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly describe the technical solutions in the embodiment of this application or in the prior art, the accompanying drawings necessary for describing the embodiments or the prior art are briefly presented below. The accompanying drawings in the following description show only some embodiments of this application, and those skilled in the field can derive other drawings from the accompanying drawings without creative effort. Fig. Figure 1 is a schematic structural view of a solar cell provided in one embodiment. Fig. Figure 2 is a process flow diagram for a method for manufacturing a solar cell. Fig. Figure 3 is a schematic view of a substrate in one embodiment. Fig. Figure 4 is a schematic view after texturing a front side of a substrate to form a first pyramid structure in one embodiment. Fig. Figure 5 is a schematic view after forming an initial doped region in the first pyramid structure in one embodiment. Fig. Figure 6 is a schematic view after laser irradiation of the initial doped region in a second region in one embodiment. Fig. Figure 7 is a schematic view after removing the initial doped region in the second region and forming a second pyramid structure on the second region in one embodiment. Fig. Figure 8 is a schematic view after forming an oxide layer and a first silicon glass layer to protect the front of the substrate in one embodiment. Fig. Figure 9 is a schematic view after polishing the back side of the substrate in one embodiment. Fig. Figure 10 is a schematic view after the sequential formation of a tunnel layer, an intrinsic semiconductor layer and a second silicon glass layer on the back of the substrate in one embodiment. Fig. Figure 11 is a schematic view after doping the intrinsic semiconductor layer to form a doped semiconductor layer in one embodiment. Fig. Figure 12 is a schematic view after laser irradiation of the second silicon glass layer on a fourth region in one embodiment. Fig. Figure 13 is a schematic view after removal of the tunnel layer, the doped semiconductor layer and the second silicon glass layer on the fourth region and texturing of the fourth region to form a third pyramid structure in one embodiment. Fig. Figure 14 is a schematic view after forming a front passivation layer and a rear passivation layer in one embodiment. REFERENCE NUMBERS

[0018] 20: Substrate; 31: First pyramid structure; 32: Second pyramid structure; 33: Third pyramid structure; 41: First diffusion-doped region; 41a: Initial doped region; 42: Front-side passivation layer; 421: First front-side passivation layer; 422: Second front-side passivation layer; 43: Oxide layer; 44: First silicon glass layer; 50: First electrode; 61: Tunnel layer; 62: Doped semiconductor layer; 62a: Intrinsic semiconductor layer; 63: Second silicon glass layer; 64: Back-side passivation layer; 641: First back-side passivation layer; 642: Second back-side passivation layer; 70: Second electrode; A1: First region; B1: Second region; A2: Third region; B2: Fourth region. DETAILED DESCRIPTION

[0019] To facilitate understanding of this application, it is described in more detail below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described here. Rather, these embodiments are provided to ensure that the disclosure of this application is thorough and complete.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as they are generally understood by a person skilled in the art in the field to which this application belongs. The terms used here in the description of this application serve only to describe specific embodiments and are not intended to limit this application.

[0021] In the description of this application, the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "top", "bottom", "front", "back", "left", "right", "vertical", "horizontal", "upper", "lower", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., are to be understood as indicating the orientations or positional relationships based on the drawings. These terms serve only to simplify the description of this application and to facilitate the description, and do not imply that the corresponding devices or elements must have the specific orientations or be designed or operated in the specific orientations, and therefore cannot be understood as limitations of this application.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying a relative meaning or the quantity or order of the specified technical elements. Therefore, the elements modified by "first" or "second" may explicitly or implicitly include at least one of the elements. In the description of this application, "multiple" or "multiple" means at least two, such as two, three, etc., unless specifically defined otherwise.

[0023] In this application, a first element, when described as being placed "on" or "below" a second element, may be in direct contact with the second element or in indirect contact with the second element via an intermediary, unless specifically defined otherwise. Furthermore, a first element described as being placed "on," "above," or "over" a second element may be placed directly above or diagonally above the second element, or simply at a higher horizontal level than the second element. When described as being placed "below" or "under" a second element, it may be an element placed directly below or diagonally below the second element, or simply at a lower horizontal level than the second element.

[0024] It should be noted that when an element is described as "attached" or "mounted" to another element, it may be attached or mounted to the other element directly or via an intermediate element. When an element is described as "connected" to another element, it may be connected to the other element directly or via an intermediate element. Terms such as "vertical," "horizontal," "top," "bottom," "left," "right," and the like, used herein, are purely illustrative and do not represent the only possible implementations of this application.

[0025] Currently, the back side of TOPCon solar cells uses a polished design to reduce defects and create a smooth surface. However, this polished back side also causes a portion of the light to be reflected off the cell, preventing it from being captured and converted into electrical energy. This exacerbates light loss due to reflection, reducing the short-circuit current output and overall photoelectric conversion efficiency of the TOPCon solar cell. More critically, the polished back side design limits the cell's bifacial power generation capability, resulting in unsatisfactory performance under bifacial illumination conditions and thus limiting the bifaciality of the TOPCon solar cell.

[0026] The term "bifaciality" refers to the ratio of the power generation efficiency of the rear side to that of the front side of the cell and is an important indicator for measuring the cell's power generation performance under different lighting conditions, especially when the rear side is also illuminated. An increase in reflected light loss means that the light energy received by the rear side is reduced, thus decreasing the efficiency of power generation on the rear side and further reducing the overall bifaciality of the cell.

[0027] In this application, the ‘first region’ refers to a functional region (i.e., an electrode region) on the front side of the substrate, which is used for attaching an electrode or for forming contact with an electrode and on which a doped structure or a conductive layer for collecting charge carriers is arranged.

[0028] In this application, the ‘second region’ refers to a non-functional region (i.e., a non-electrode region) on the front of the substrate in which no electrode is located, which serves to improve optical performance but is not directly involved in the electrode contact.

[0029] In this application, the ‘third region’ refers to a functional region (i.e., an electrode region) on the back side of the substrate, which is used for attaching an electrode or for forming contact with an electrode and on which a doped structure or a conductive layer is arranged for collecting charge carriers.

[0030] In this application, the “fourth region” refers to a non-functional region (i.e., a non-electrode region) on the back side of the substrate in which no electrode is located, which serves to improve optical performance but is not directly involved in the electrode contact.

[0031] In solar cells, the "pyramid structure" is a common surface texturing design that uses a chemical texturing process to create micrometer-sized pyramidal protrusions on the surface of a silicon substrate. In an ideal pyramidal protrusion, the "vertex" refers to the tip or highest point of the protrusion. The "base" refers to the lower plane or bottom section of the protrusion. The "base edge" refers to one of the straight edges that form the boundary of the base (usually a polygon) of the pyramidal protrusion. The "height" refers to the vertical distance from the base to the vertex.

[0032] In this application, the term "size of a base" refers to a geometric dimension of the base of the pyramid structure, used to represent the size of the base area of ​​the pyramid structure. The size of the base may include, but is not limited to, the length of a base edge of the pyramid structure, the length of a diagonal of the pyramid structure, or an area of ​​the base of the pyramid structure. Professionals may select appropriate parameters for representing the size of the base based on actual processes, measurement methods, or design requirements.

[0033] Therefore, this application provides a solar cell. The solar cell can be a TOPCon solar cell. As in Fig. As shown in Figure 1, the solar cell comprises a substrate 20, a first electrode 50, and a second electrode 70. The substrate 20 can be a silicon substrate. The substrate 20 can be doped with N-conducting ions. A front face of the substrate 20 comprises first regions A1 and second regions B1, arranged alternately. The first regions A1 have first pyramidal structures 31. The second regions B1 have second pyramidal structures 32. In a direction Y from the back of the substrate 20 to the front face of the substrate 20, the vertices of the first pyramidal structures 31 are higher than the vertices of the second pyramidal structures 32. The first region A1 has a first diffusion-doped region 41. The direction Y is the direction of the thickness of the substrate 20. It is understood that the substrate 20 has a plane XX, the plane XX is located inside the substrate 20, and the plane XX is perpendicular to the direction Y.Along direction Y, plane XX is positioned between the front and back sides of substrate 20. The distance between the apex of the first pyramid structure 31 and plane XX is greater than the distance between the apex of the second pyramid structure 32 and plane XX. The back side of substrate 20 comprises third regions A2 and fourth regions B2, arranged alternately. The solar cell includes a tunnel layer 61 and a doped semiconductor layer 62, stacked sequentially on the side of third region A2 facing away from substrate 20. Fourth region B2 has a third pyramid structure 33. The first electrode 50 is located on first region A1 and is electrically connected to the first diffusion-doped region 41. The second electrode 70 is located on third region A2 and is electrically connected to the doped semiconductor layer 62.

[0034] The front surface of substrate 20 comprises first regions A1 and second regions B1, arranged alternately. The first pyramidal structures 31 are formed on the first regions A1. The second pyramidal structures 32 are formed in the second regions B1. That is, both the first region A1 and the second region B1 exhibit a pyramidal structure to reduce light reflection at the front surface of the cell.

[0035] In the direction Y from the back of the substrate 20 to the front of the substrate 20, the vertices of the second pyramid structures 32 are lower than the vertices of the first pyramid structures 31, so that a portion of the light reflected by the second pyramid structures 32 is reflected to the first pyramid structures 31, absorbed by the first pyramid structures 31 and then converted into electrical energy, thereby improving the cell's ability to capture light from the front, reducing the reflection light loss at the front of the cell, converting more light energy into electrical energy, and improving the short-circuit current performance and the overall photoelectric conversion efficiency of the solar cell.

[0036] In the direction Y from the back of the substrate 20 to the front of the substrate 20, the vertices of the second pyramidal structures 32 can be lower than the vertices of the first pyramidal structures 31. This allows the light reflected from the second pyramidal structures 32 to the first pyramidal structures 31 to be amplified, thus reducing the reflection light loss at the front of the cell.

[0037] The first pyramidal structure 31 is formed with the first diffusion-doped region 41. The first diffusion-doped region 41 can be a region doped with conductive ions of type P. The first diffusion-doped region 41 and the substrate 20 form a PN junction. The first electrode 50 is located on the side of the first region A1 facing away from the substrate 20. The first electrode 50 is electrically connected to the first diffusion-doped region 41, forming a current path.

[0038] The back side of the substrate 20 comprises third regions A2 and fourth regions B2, arranged alternately. The fourth regions B2 have third pyramidal structures 33. The third pyramidal structures 33 can reduce the reflected light loss in the fourth regions B2. More light incident on the back side of the cell is converted into electrical energy, which improves the short-circuit current performance and the overall photoelectric conversion efficiency of the solar cell and increases the bifaciality of the solar cell.

[0039] For example, the length of a base edge of the third pyramid structure 33 lies in a range of 0.5 µm to 4 µm. Similarly, the height of the third pyramid structure 33 lies in a range of 0.5 µm to 3 µm. The length of the base edge of the third pyramid structure 33 can be, for example, 0.5 µm, 0.8 µm, 1 µm, 1.5 µm, 1.8 µm, 2 µm, 2.5 µm, 3 µm, 3.5 µm, 4 µm, or any value within a range defined by any two values ​​from the range specified above. The height of the third pyramid structure 33 can, for example, be 0.5 µm, 1 µm, 1.5 µm, 2 µm, 2.5 µm, 3 µm or a value within a range defined by any two amounts from the range specified above.

[0040] The tunnel layer 61 and the doped semiconductor layer 62 are stacked sequentially on a side of the third region A2 facing away from the substrate 20. The doped semiconductor layer 62 can be an intrinsic semiconductor layer 62a doped with conductive ions of type N. The doped semiconductor layer 62 can, for example, be an n-poly layer. The second electrode 70 is electrically connected to the doped semiconductor layer 62, forming a current path.

[0041] In the solar cell in the embodiments, the reflection light loss on the front side is reduced by providing the first pyramidal structures 31 on the first regions A1 of the front side and the second pyramidal structures 32 on the second regions B1 of the front side, and the apex of the first pyramidal structures 31 is higher than the apex of the second pyramidal structure 32; and by providing the third pyramidal structure 33 on the fourth region B2 of the back side, the reflection light loss on the back side is reduced, thereby improving the short-circuit current output and the overall photoelectric conversion efficiency of the solar cell and improving the bifaciality of the solar cell.

[0042] In some embodiments, a surface layer of the second region B1 is as in Fig. Figure 1 shows substrate 20 without the first diffusion-doped region 41. That is, at the front of the cell, the first diffusion-doped region 41 is formed only in the first region A1, and the PN junction exists only in the first region A1. This helps to reduce the lifetime loss of minority carriers caused by Auger recombination and also improves the photoelectric conversion efficiency of the cell.

[0043] Auger recombination is a non-radiative recombination process and the reverse of "impact ionization". When majority charge carriers recombine with minority charge carriers in a solar cell, the majority or minority charge carriers transfer energy or momentum to another minority or majority charge carrier through collision, causing that minority or majority charge carrier to undergo a transition.

[0044] In some embodiments, the solar cell comprises, as in Fig. Figure 1 also shows a front-side passivation layer 42. The front-side passivation layer 42 is arranged on the front side of the substrate 20. The front-side passivation layer 42 covers the first diffusion-doped region 41 of the first region A1 and the substrate 20 in the second region B1. The front-side passivation layer 42 is designed to protect the front side of the solar cell, reduce recombination losses across the surface, and improve the photoelectric conversion efficiency and stability of the solar cell.

[0045] The front-side passivation layer 42 can comprise at least one aluminum oxide layer, one silicon oxide layer, or one silicon nitride layer. Alternatively, the front-side passivation layer 42 can also comprise several stacked layers.

[0046] The front-side passivation layer 42 can, for example, comprise a first front-side passivation layer 421 and a second front-side passivation layer 422, which are stacked sequentially on the front side of the substrate 20. The first front-side passivation layer 421 is an aluminum oxide layer. The second front-side passivation layer 422 is a silicon nitride layer. The aluminum oxide layer can effectively prevent impurities and moisture in the external environment from attacking the interior of the cell. Furthermore, the aluminum oxide layer can reduce the number of dangling bonds on the surface of the substrate 20, thereby reducing the area recombination rate and improving the open-circuit voltage and short-circuit current of the cell. The aluminum oxide layer also exhibits good light transmittance, which reduces the light transmission loss at the front side.The silicon nitride layer has good light transmittance and antireflection properties, which reduces light transmission loss and refractive light loss at the front of the cell. The silicon nitride layer also has good insulating properties and corrosion resistance, which further reduces recombination loss across the surface of the substrate 20, allowing more light incident on the front of the substrate 20 to be absorbed by the solar cell and converted into electrical energy.

[0047] As in Fig. As shown in Figure 1, the solar cell further comprises a backside passivation layer 64. The backside passivation layer 64 is located on the back side of the substrate 20. The backside passivation layer 64 covers the doped semiconductor layer 62 in the third region A2 and the substrate 20 in the fourth region B2.

[0048] This means that in the embodiments, the tunnel layer 61, the doped semiconductor layer 62, and the backside passivation layer 64 are stacked sequentially on the base of the third region A2, while the base of the fourth region B2 is provided only with the backside passivation layer 64. This ensures the stability of the electrical performance of the fourth region B2 and avoids unnecessary leakage currents or disturbances.

[0049] The backside passivation layer 64 can comprise at least one aluminum oxide layer, one silicon oxide layer, or one silicon nitride layer. Alternatively, the backside passivation layer 64 can also comprise several stacked layers.

[0050] The backside passivation layer 64, for example, comprises a first backside passivation layer 641 and a second backside passivation layer 642, which are stacked sequentially on the back side of the substrate 20. The first backside passivation layer 641 is an aluminum oxide layer and the second backside passivation layer 642 is a silicon nitride layer.

[0051] In some embodiments, a projection of the first region A1 onto the substrate 20 and a projection of the fourth region B2 onto the substrate 20, as in Fig. Figure 1 shows an overlapping region, and a projection of the second region B1 on substrate 20 and a projection of the third region A2 on substrate 20 show an overlapping region.

[0052] This reduces charge recombination losses caused by metallized electrodes. The second region B1 and the fourth region B2 can absorb light more effectively and convert it into electrical current, while the first region A1 and the third region A2 help to store the electrical current, thus reducing loss and optimizing the solar cell's light absorption performance.

[0053] In some embodiments, the projection of the first region A1 falls as in Fig. Figure 1 shows the projection of the fourth region B2 onto the substrate 20. The projection of the third region A2 onto the substrate 20 falls within the projection area of ​​the second region B1 onto the substrate 20. This reduces recombination losses, optimizes charge collection, and improves the light absorption performance and reliability of the solar cell.

[0054] In some embodiments, the projection of the first region A1 on the substrate 20 overlaps with the projection of the fourth region B2 on the substrate 20, and the projection of the second region B1 on the substrate 20 overlaps with the projection of the third region A2 on the substrate 20.

[0055] In some embodiments, the width of the first region A1 is as in Fig. 1 shown in a range of 80 µm to 300 µm. The width of the first region A1 can be, for example, 80 µm, 100 µm, 120 µm, 150 µm, 200 µm, 220 µm, 250 µm, 280 µm, or 300 µm. The width of the second region B1 is in a range of 450 µm to 900 µm. The width of the second region B1 can be, for example, 450 µm, 480 µm, 500 µm, 550 µm, 600 µm, 650 µm, 700 µm, 750 µm, 800 µm, 850 µm or 900 µm.

[0056] The width of the third region A2 ranges from 80 µm to 300 µm. For example, the width of the third region A2 can be 80 µm, 100 µm, 120 µm, 150 µm, 200 µm, 220 µm, 250 µm, 280 µm, or 300 µm. The width of the fourth region B2 ranges from 450 µm to 900 µm. The width of the fourth region B2 can be, for example, 450 µm, 480 µm, 500 µm, 550 µm, 600 µm, 650 µm, 700 µm, 750 µm, 800 µm, 850 µm or 900 µm.

[0057] It should be noted that while the latitudes of the first region A1 and the third region A2 are the same, the latitudes of the first region A1 and the third region A2 may differ. Similarly, the latitudes of the second region B1 and the fourth region B2 may differ.

[0058] In some embodiments, the ratio between the width of the first region A1 and the width of the second region B1 ranges from 1:1 to 1:9. For example, the ratio of the width of the first region A1 to the width of the second region B1 can be 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, or 1:9. The ratio between the width of the third region A2 and the width of the fourth region B2 ranges from 1:1 to 1:9. For example, the ratio of the width of the third region A2 to the width of the fourth region B2 can be 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, or 1:9.

[0059] The base of the first pyramid structure 31 is larger than the base of the second pyramid structure 32. The height of the first pyramid structure 31 is greater than the height of the second pyramid structure 32.

[0060] The length of a base edge of the first pyramid structure 31 lies in the range of 0.5 µm to 4 µm. The height of the first pyramid structure 31 lies in the range of 0.5 µm to 3 µm.

[0061] The length of a base edge of the second pyramid structure 32 lies in the range of 0.5 µm to 4 µm. The height of the second pyramid structure 32 lies in the range of 0.5 µm to 3 µm.

[0062] In one example, the length of the base edge of the first pyramid structure 31 is 0.6 µm, and the height of the first pyramid structure 31 is 3 µm. The length of the base edge of the second pyramid structure 32 is 0.5 µm, and the height of the second pyramid structure 32 is 2 µm. In another example, the length of the base edge of the first pyramid structure 31 is 4 µm, and the height of the first pyramid structure 31 is 2.5 µm. The length of the base edge of the second pyramid structure 32 is 3 µm, and the height of the second pyramid structure 32 is 1.5 µm. In yet another example, the length of the base edge of the first pyramid structure 31 is 1.5 µm, and the height of the first pyramid structure 31 is 1.5 µm. The length of the base edge of the second pyramid structure 32 is 0.5 µm, and the height of the second pyramid structure 32 is 0.5 µm.

[0063] As in Fig. As shown in Figure 2, a process for manufacturing the solar cell comprises the following steps.

[0064] Step S101: Providing a substrate and texturing one front side of the substrate to form an initial pyramid structure.

[0065] As in Fig. As shown in Figure 3, the substrate 20 can be a substrate made of a semiconductor material, such as a silicon substrate, a silicon-germanium substrate, or a germanium substrate. The substrate 20 can be an N-substrate or a P-substrate. Both the front and back surfaces of the substrate 20 are relatively flat.

[0066] The substrate 20 provided in the embodiments is a silicon substrate 20. The substrate 20 is doped with N-conducting ions, i.e., the substrate 20 is an N-substrate.

[0067] As in Fig. As shown in Figure 4, the substrate 20 is structured to remove a damaged layer on its surface and to form the first pyramid structure 31 on the front of the substrate 20. In the embodiments, the first pyramid structure 31 is formed simultaneously on the back of the substrate 20.

[0068] For example, the length of a base edge of the first pyramid structure 31 is in a range of 0.5 µm to 4 µm, and the height of the first pyramid structure 31 is in a range of 0.5 µm to 3 µm.

[0069] Step S102: Formation of an initial doped region at the front of the substrate.

[0070] As in Fig. As shown in Figure 5, the substrate 20 is placed in a diffusion furnace and a boron source gas, such as BBr3, H3BO3, etc., is introduced into the diffusion furnace. The diffusion furnace is heated to decompose the boron source gas and release boron atoms. The boron atoms diffuse into the substrate 20 and form the initial doped region 41a in the first pyramidal structures 31. The initial doped region 41a is enriched with conductive phosphorus boron ions.

[0071] Step S103: Removing a section of the initial doped region at intervals, wherein a region in which the initial doped region is retained serves as a first region, and a region in which the initial doped region 41a is removed serves as a second region; and texturing the second region to form a second pyramidal structure on the second region, wherein, in a direction from a back side of the substrate to the front side of the substrate, a peak of the first pyramidal structure is higher than a peak of the second pyramidal structure.

[0072] In the embodiments, removing a section of the initial doped region 41a at intervals comprises: irradiating the initial doped region 41a in the second region B1 with a laser and subsequently texturing the second region B1 to remove the initial doped region 41a in the second region B1 and simultaneously forming the second pyramid structure 32 on the second region B1.

[0073] In the embodiments described above, the texturizing solution used during the texturizing process in step S103 can be an alkaline solution, such as an alkaline solution with a concentration of 1% to 5%, for example, a 1% to 5% sodium hydroxide solution or a 1% to 5% potassium hydroxide solution. In one example, the texturizing solution is a 1.5% to 2.5% sodium hydroxide solution. In another example, the texturizing solution is a 1% to 3% potassium hydroxide solution. The texturizing process involves the reaction at a temperature of 70°C to 90°C for 1 to 3 minutes.

[0074] As in Fig. As shown in Figure 6, the initial doped region 41a on the front face is irradiated with a laser to define the second regions B1 at intervals on the front face. The high-energy effect of the laser causes the material of the initial doped region 41a to dissolve into the second region B1.

[0075] Then, as in Fig. Figure 7 shows the second region B1 being structured. The substrate 20 is placed in a texturizing solution to remove the initial doped region 41a in the second region B1 and, in the process, to form the second pyramid structure 32 on the surface of the second region B1.

[0076] For example, the length of a base edge of the second pyramid structure 32 is in a range of 0.5 µm to 4 µm, and the height of the second pyramid structure 32 is in a range of 0.5 µm to 3 µm.

[0077] Since the initial doped region 41a is removed in the second region B1, the tips of the second pyramid structures 32 are lower than the tips of the first pyramid structures 31, and the surface layer of the second pyramid structures 32 is the silicon substrate, the lifetime loss of minority carriers caused by Auger recombination is effectively reduced, and the photoelectric conversion efficiency of the cell is also improved.

[0078] Step S104: Perform a drive-in diffusion in the initial doped region to form a first diffusion-doped region in the first pyramid structure.

[0079] With reference to Fig. 8. The substrate 20 can be placed in a high-temperature quartz tube furnace and heated to a preset temperature (e.g. 800 °C to 1200 °C) so that the boron ions in the initial doped region 40a can diffuse further into the substrate 20 and form the first diffusion-doped region 41.

[0080] Step S105: Sequential formation of a tunnel layer, an intrinsic semiconductor layer and a second silicon glass layer on the back of the substrate.

[0081] As in Fig. As shown in Figure 9, first the back of the substrate 20 is polished to expose the surface of the substrate 20 and to polish the back of the substrate 20 into a flat surface.

[0082] Then, as in Fig. As shown in Figure 10, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process can be used to sequentially deposit the tunnel layer 61, the intrinsic semiconductor layer 62a and the second silicon glass layer 63 on a side of the tunnel layer 61 facing away from the substrate 20.

[0083] The thickness of the tunneling layer 61 is set to 1 nm to 2 nm. Specifically, the tunneling layer 61 is a silicon oxide layer. The material of the intrinsic semiconductor layer 62a comprises polysilicon. The thickness of the intrinsic semiconductor layer 62a is 100 nm to 300 nm.

[0084] In the embodiments, the second silicon glass layer 63 is a phosphosilicate glass layer.

[0085] Step S106: Doping of the intrinsic semiconductor layer to form a doped semiconductor layer.

[0086] As in Fig. As shown in Figure 11, the intrinsic semiconductor layer 62a can be subjected to high-temperature annealing so that phosphorus ions in the second silicon glass layer 63 can diffuse into the intrinsic semiconductor layer 62a and form the doped semiconductor layer 62.

[0087] Step S107: Removing a section of the tunnel layer, the doped semiconductor layer and the second silicon glass layer stacked at intervals on the back of the substrate, with a region where the tunnel layer, the doped semiconductor layer and the second silicon glass layer are retained serving as a third region, and a region where the tunnel layer, the doped semiconductor layer and the second silicon glass layer are removed serving as a fourth region.

[0088] As in Fig. 12 and Fig. Figure 13 shows the removal of a section of the tunnel layer 61, the doped semiconductor layer 62 and the second silicon glass layer 63, which are stacked at intervals on the back side of the substrate 20: irradiation of the tunnel layer 61, the doped semiconductor layer 62 and the second silicon glass layer 63 on the fourth region B2 with a laser; removal of the second silicon glass layer 63 on the fourth region B2 by washing with an acidic solution; and removal of the tunnel layer 61 and the doped semiconductor layer 62 on the fourth region B2 during texturing of the fourth regions B2.

[0089] The second silicon glass layer 63 on the back side is irradiated with a laser, and the material of the second silicon glass layer 63, which was irradiated with the laser, dissolves and forms the fourth regions B2 at intervals on the back side. Then the back side of the substrate 20 is washed with an acidic solution to remove the second silicon glass layer 63 on the fourth regions B2 and to expose the doped semiconductor layer 62 on the fourth regions B2.

[0090] In some embodiments, when washing the back of the substrate 20 with an acidic solution, a hydrofluoric acid solution can be used, such as a hydrofluoric acid solution with 5% to 10% hydrofluoric acid.

[0091] Step S108: Texturing the fourth region to create a third pyramid structure on the fourth region.

[0092] As in Fig. As shown in Figure 13, the substrate 20 is placed in a texturing solution to remove the doped semiconductor layer 62 and the tunneling layer 61 on the fourth region B2, thereby forming the third pyramidal structure 33 on the surface of the fourth region B2. The third pyramidal structure 33 can reduce the reflection light loss in the fourth region B2. More light incident on the back side of the cell is converted into electrical energy, thereby increasing the short-circuit current and the overall photoelectric conversion efficiency of the solar cell and improving the bifaciality of the solar cell.

[0093] For example, the length of a base edge of the third pyramid structure 33 is in a range of 0.5 µm to 4 µm and the height of the third pyramid structure 33 is in a range of 0.5 µm to 3 µm.

[0094] In the embodiments described above, the texturizing solution used during the texturizing process in step S108 can be an alkaline solution, such as an alkaline solution with a concentration of 1% to 5%, for example, a 1% to 5% sodium hydroxide solution or a 1% to 5% potassium hydroxide solution. In one example, the texturizing solution is a 1.5% to 2.5% sodium hydroxide solution. In another example, the texturizing solution is a 1% to 3% potassium hydroxide solution. The texturizing process involves the reaction at a temperature of 70°C to 90°C for 1 to 3 minutes.

[0095] Step S109: Removing the second silicon glass layer on the third region.

[0096] As in Fig. As shown in Figure 13, in the embodiments the second silicon glass layer 63 on the third region A2 is corroded and removed during the texturing of the fourth region B2.

[0097] In other embodiments, the second silicon glass layer 63 can be retained on the third region A2, which is not restricted in this technical solution.

[0098] Step S110: Forming a front passivation layer to cover the first diffusion-doped region of the first region and the substrate in the second region, and forming a rear passivation layer to cover the doped semiconductor layer on the third region and the substrate in the fourth region.

[0099] As in Fig. As shown in Figure 14, the front-side passivation layer 42 and the back-side passivation layer 64 can be formed using the ALD or CVD process. The front-side passivation layer 42 and the back-side passivation layer 64 can be made of one or more of the following materials: aluminum oxide, silicon nitride, silicon oxynitride, etc. The front-side passivation layer 42 and the back-side passivation layer 64 can be formed in the same process.

[0100] Step S111: Forming a first electrode on the first region, the first electrode being electrically connected to the first diffusion-doped region.

[0101] With reference to Fig. 1. A conductive paste is screen-printed onto the front-side passivation layer 42 of the first region A1 and dried to form the first electrode 50. Then, the first electrode 50 is irradiated with a laser to electrically connect it to the initial diffusion-doped region 41 on the first region A1.

[0102] Step S112: Forming a second electrode on the third region, with the second electrode being electrically connected to the doped semiconductor layer.

[0103] With reference to Fig. 1. A conductive paste is screen-printed onto the backside passivation layer 64 of the third region A2 and dried to form the second electrode 70. Then, the second electrode 70 is irradiated with a laser to electrically connect it to the doped semiconductor layer 62 on the third region A2.

[0104] In some embodiments, after performing the drive-in diffusion as described in Fig. Figure 8 shows that an oxide layer 53 is formed on an area of ​​the second region B1 of the first doped region 41a, and simultaneously a first silicon glass layer 54 is formed on a side of the first diffusion-doped region 41 facing away from the substrate 20. Specifically, the substrate 20 can be thermally oxidized to form the oxide layer 53 on the area of ​​the second region B1 and the first silicon glass layer 54 on the side of the first diffusion-doped region 41 facing away from the substrate 20. In these embodiments, the first silicon glass layer 54 is a borosilicate glass layer. The oxide layer 53 and the first silicon glass layer 54 are formed to protect the front of the substrate 20 and to prevent damage to the front of the substrate 20 during processing of the back of the substrate 20.

[0105] In the embodiments, the oxide layer 53 and the first silicon glass layer 54 are also removed simultaneously with the removal of the tunnel layer 61 and the doped semiconductor layer 62 on the fourth region B2.

[0106] In the manufacturing process for the solar cell, front boron diffusion is carried out on the front of the substrate 20 to form the initial doped region 40a, then laser irradiation is applied to the initial doped region 40a to define the first regions A1 and the second regions B1, and the initial doped region 40a is removed in the second regions B1 by a texturing process, so that after the subsequent boron diffusion the first diffusion-doped region 41 is formed only in the first region A1, the lifetime loss of minority carriers caused by Auger recombination can be reduced and the photoelectric conversion efficiency of the cell can also be improved.In the embodiments, the oxide layer 53 is used to protect the front of the substrate 20, the phosphorus diffusion treatment is carried out on the back of the cell to form the doped semiconductor layer 62, then laser irradiation and texturing are carried out on the back of the substrate 20 to remove the doped semiconductor layer 62 on the fourth region B2, so that the doped semiconductor layer 62 on the third region A2 is retained, thereby improving the bifaciality of the cell and reducing parasitic light absorption.

[0107] In the manufacturing process for the solar cell, the formation of the first diffusion-doped region 41 in the first region A1 and the formation of the doped semiconductor layer 62 on the third region A2 increases the process window and improves controllability, thus reducing process difficulties and costs. Stepwise preparation allows the metallized regions on the front and back sides to be optimized separately, improving the overall performance of the cell.

[0108] The manufacturing process for the solar cell not only reduces parasitic light absorption but also improves the bifaciality of the cell through the double-sided texturing design, enabling the cell to maintain high photoelectric conversion efficiency under various lighting conditions.

[0109] The solar cell comprises a substrate, a first electrode, and a second electrode. The front side of the substrate includes a first region and a second region. The first region exhibits a first pyramidal structure. The second region exhibits a second pyramidal structure. An apex of the first pyramidal structure is positioned higher than an apex of the second pyramidal structure. The first region includes a first diffusion-doped region. The back side of the substrate includes a third region and a fourth region. A tunneling layer and a doped semiconductor layer are sequentially stacked on the side of the third region facing away from the substrate. The fourth region exhibits a third pyramidal structure.

Claims

[1] Solar cell, comprising: a substrate (20) wherein a front side of the substrate (20) has a first region (A1) and a second region (B1) arranged alternately, wherein the first region (A1) has a first pyramidal structure (31), the second region (B1) has a second pyramidal structure (32), and in a direction from a back side of the substrate (20) to the front side of the substrate (20) an apex of the first pyramidal structure (31) is higher than an apex of the second pyramidal structure (32), the first region (A1) has a first diffusion-doped region (41); the back of the substrate (20) has a third region (A2) and a fourth region (B2) arranged alternately, the solar cell has a tunnel layer (61) and a doped semiconductor layer (62) stacked sequentially on a side of the third region facing away from the substrate, and the fourth region (B2) has a third pyramid structure (33); a first electrode (50) arranged on the first region (A1), wherein the first electrode (50) is electrically connected to the first diffusion-doped region (41); and a second electrode (70) which is arranged on the third region (A2), wherein the second electrode (70) is electrically connected to the first doped semiconductor layer (62). [2] Solar cell according to claim 1, further comprising: a front-side passivation layer (42) arranged on the front side of the substrate (20), wherein the front-side passivation layer (42) covers the first diffusion-doped region (41) of the first region (A1) and the substrate (20) in the second region (B1); and a backside passivation layer (64) arranged on the back side of the substrate (20), wherein the backside passivation layer (64) covers the doped semiconductor layer (62) on the third region (A2) and the substrate (20) in the fourth region (B2). [3] Solar cell according to claim 1 or 2, wherein a projection of the first region (A1) onto the substrate (20) and a projection of the fourth region (B2) onto the substrate (20) have an overlapping region, and a projection of the second region (B1) onto the substrate (20) and a projection of the third region (A2) onto the substrate (20) have an overlapping region. [4] Solar cell according to one of claims 1 to 3, wherein the width of the first region (A1) is in a range of 80 µm to 300 µm, the width of the second region (B1) is in a range of 450 µm to 900 µm, the width of the third region (A2) is in a range of 80 µm to 300 µm and the width of the fourth region (B2) is in a range of 450 µm to 900 µm. [5] Solar cell according to claim 4, wherein the ratio of the width of the first region (A1) to the width of the second region (B1) is in a range of 1:1 to 1:9, and the ratio of the width of the third region (A2) to the width of the fourth region (B2) is in a range of 1:1 to 1:

9. [6] Solar cell according to one of claims 1 to 5, wherein the size of a base of the first pyramid structure (31) is larger than the size of a base of the second pyramid structure (32) and the height of the first pyramid structure (31) is larger than the height of the second pyramid structure (32). [7] Solar cell according to one of claims 1 to 6, wherein the length of a base edge of the third pyramid structure (33) is in a range of 0.5 µm to 4 µm and the height of the third pyramid structure (33) is in a range of 0.5 µm to 3 µm. [8] Solar cell according to one of claims 1 to 7, wherein the length of a base edge of the first pyramid structure (31) is in a range of 0.5 µm to 4 µm and the height of the first pyramid structure (31) is in a range of 0.5 µm to 3 µm. [9] Solar cell according to one of claims 1 to 8, wherein the length of a base edge of the second pyramid structure (32) is in a range of 0.5 µm to 4 µm and the height of the second pyramid structure (32) is in a range of 0.5 µm to 3 µm. [10] Solar cell according to any one of claims 1 to 9, wherein a projection of the first region (A1) on the substrate (20) falls within a region of a projection of the fourth region (B2) on the substrate (20); and a projection of the third region (A2) on the substrate (20) falls into an area of ​​a projection of the second region (B1) on the substrate (20).

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