System

Abstract

System (100, 200, 300, 400) for analyzing (105, 205, 305, 405) circuit arrangements (499) with high-performance semiconductors (498-1, 499-2), the system (100, 200, 300, 400) comprising: a computing device (101, 201, 301, 401) which can be coupled to one or more measuring probes (421-1, 421-2), the measuring probes (421-1, 421-2) being designed to each measure a measured variable (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2) in a circuit arrangement (499) to be tested detect, while at least one test pulse (211, 311) is supplied to the circuit arrangement (499); and a user interface (103, 203, 303, 403) which is designed to receive a user input (104, 204, 304, 404) from a user which characterizes an analysis (105, 205, 305, 405); wherein the computing device (101, 201, 301, 401) is designed to: receive the measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2) from the measuring probes (421-1, 421-2);to carry out the analysis (105, 205, 305, 405) identified by the user input (104, 204, 304, 404) with the received measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2); andoutput the measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2) and analysis results (106, 206, 306, 406) of the performed analysis (105, 205, 305, 405) via the user interface (103, 203, 303, 403);

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a system and a corresponding method. TECHNICAL BACKGROUND

[0002] The present disclosure is described below primarily in connection with the measurement of switching parameters of power semiconductors. In particular, the present disclosure is described with wide band gap (WBG) semiconductors, such as silicon carbide semiconductors (SIC) or gallium nitride semiconductors (GaN).

[0003] The measurement of the switching parameters of MOSFETs or IGBTs is typically performed using the double-pulse method. In such a measurement using the double-pulse method, two pulses are applied to the gate of the respective component at different times in an inductive clamp circuit, and the corresponding measured values ​​are recorded.

[0004] This process is usually performed manually and is very time-consuming, especially for a complete qualification of a circuit using WBG semiconductors. SUMMARY

[0005] One object of the disclosure is therefore to simplify the measurement of power semiconductors.

[0006] The problem is solved by the subject matter of the independent claims.

[0007] It is revealed: A system for analyzing circuit arrangements with high-performance semiconductors, the system comprising a computing device which can be coupled to one or more measuring probes, the measuring probes being designed to each detect at least one measured variable in a circuit arrangement to be tested while at least one test pulse is supplied to the circuit arrangement, and comprising a user interface which is designed to receive a user input from a user which characterizes an analysis, the computing device being designed to receive the measured variables from the measuring probes and to carry out the analysis characterized by the user input using the received measured variables, and to output the measured variables and analysis results of the carried out analysis via the user interface.

[0008] The present disclosure is based on the finding that during the testing of high-performance semiconductors, a large number of measurements are usually carried out manually and their results are manually compared by the respective test engineer.

[0009] When developing circuits with modern high-performance semiconductors, such as wide-band-gap semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), the circuits are typically tested in appropriate test setups under varying environmental conditions, such as changing voltages, currents, and temperatures. Such measurements can take several days for a single circuit.

[0010] The present disclosure takes this finding into account and provides a corresponding system and a corresponding method with which analyses of circuit arrangements with high-performance semiconductors, e.g. analyses of the switching parameters of such circuit arrangements, can be carried out simply and efficiently.

[0011] For this purpose, the system has a computing device which can be coupled to one or more measuring probes.

[0012] Each of the measuring probes can further be coupled to the circuit arrangement. For this purpose, the circuit arrangement can, for example, have corresponding test or measurement contacts. Within the scope of this disclosure, the term "measuring probe" includes all types of interfaces or elements that can establish a direct or indirect connection between a circuit arrangement and the computing device, so that the corresponding measured variables can be supplied to the computing device. Such measuring probes can also be referred to as probe heads.

[0013] The measuring probes record the respective measured variables in the circuit arrangement and feed them to the computing device. Recording the measured variables refers to continuous or permanent recording, particularly discrete-time recording, of the respective measured variable, so that the computing device can reproduce a corresponding waveform of the recorded measured variable.

[0014] The measurement probes can be conventional probes or probe heads used on oscilloscopes. The measurement probes can also be isolated probes or probe heads, or differential probes or probe heads.

[0015] The system further includes a user interface. The user interface may be any type of interface that allows a user to interact with the system. The user interface may receive user input indicating a corresponding analysis.

[0016] The computing device is coupled to the user interface and is configured to receive the measured variables from the measuring probes and to apply the analysis to the measured variables specified by the user input. The computing device is particularly configured to apply the analysis to measured variables that are acquired while at least one corresponding test pulse is applied to the circuit arrangement.

[0017] It is understood that more than one, i.e., two or more test pulses can be applied to the circuit arrangement. In particular, the test pulses can be used to perform a test using the so-called double-pulse method. In the double-pulse method, two consecutive pulses are applied to a circuit arrangement containing high-power semiconductors to test the switching behavior of the circuit arrangement, and in particular, one of the high-power semiconductors.

[0018] The analysis therefore refers in particular to analyses carried out as part of a test according to the double pulse method.

[0019] Via the user interface, the computing device can output analysis results for the analysis performed, and optionally also the measured variables and the test pulses, if these are recorded.

[0020] In some embodiments, the computing device can be arranged in a measuring device. In particular, the computing device can be arranged in the measuring device used for analyzing the circuit arrangement, e.g., in an oscilloscope.

[0021] The system according to the present disclosure may include not only the computing device, but also any measurement devices required in the respective application. In particular, the computing device may be arranged in a measurement device or a device coupled to a measurement device, e.g., a server, and may be indirectly coupled to the measurement probes.

[0022] In one embodiment, which can be combined with all other embodiments, a measuring device can be coupled to the measuring probes, convert the measured variables into digital values ​​and provide them to the computing device via a network.

[0023] The computing device may comprise or be provided as part of a dedicated processing element, for example, a processing unit, microcontroller, field-programmable gate array (FPGA), complex programmable logic device (CPLD), application-specific integrated circuit (ASIC), or the like. A corresponding program or configuration may be provided to implement the required functionality. The computing device may also be provided, at least in part, as a non-transitory computer program product containing computer-readable instructions that can be executed by a processing element. In a further embodiment, the computing device may be integrated as an additional function or method into the firmware or operating system of a processing element already present in the respective application, wherein the corresponding computer-readable instructions are provided.Such computer-readable instructions may be stored in a memory coupled to or integrated with the processing element. The processing element may retrieve and execute the computer-readable instructions from the memory. This also applies to any other elements, units, or functions disclosed herein as part of the system and method.

[0024] Furthermore, it is understood that any necessary supporting or additional hardware, such as a power supply circuit and a clock generator circuit, may be provided.

[0025] In general, any computer program or computer program product disclosed herein shall be deemed to be a non-transitory computer program product.

[0026] A metrology device according to the present disclosure can generally include any device used in a metrology application to acquire an input signal or generate an output signal, or to perform additional or supporting functions in a metrology application. A metrology device can also be implemented as a program or software application that runs as a metrology application on a computer or processor and can communicate with other metrology devices to perform a metrology task. A metrology application, also referred to as a measurement or test setup, can, for example, include at least one or more different metrology devices used for electrical, magnetic, or electromagnetic measurements, in particular on individual devices under test, also called DUTs.A measurement device according to the present disclosure can be configured to perform such electrical, magnetic, or electromagnetic measurements or signal generation on a test object, for example, in a measurement laboratory or in a production facility on the respective production line. An exemplary measurement setup can be used to qualify the individual test objects, i.e., to verify the proper electrical function of the respective test objects.

[0027] For this purpose, measurement devices can comprise at least one signal receiving part for detecting electrical, magnetic, or electromagnetic signals from the device under test and / or at least one signal generating part for generating electrical, magnetic, or electromagnetic signals that can be fed to the device under test. Such a signal receiving part can, for example, but not limited to, contain a front-end stage for detecting, filtering, attenuating, or amplifying electrical signals. The signal generating part can, for example, but not limited to, comprise corresponding signal generators, amplifiers, and filters. In embodiments, the signal is detected via the signal receiving part in a wired or contact-based manner. For this purpose, a corresponding measuring probe (also called a probe) can be connected to the measurement device via a corresponding cable.Likewise, in embodiments, the signal generation and output via the signal generation part takes place in a wired or contact-based manner. For this purpose, a corresponding signal output probe can be connected to the measuring device via a corresponding cable, or the signal is output directly via the cable, e.g., to a device under test. In further embodiments, the signal acquisition can take place contactlessly, e.g., via corresponding antennas, also called OTA or over-the-air. In further embodiments, the signal generation and output can take place contactlessly, e.g., via corresponding antennas, also called OTA or over-the-air. A combination of contact-based signal acquisition, contactless signal acquisition, contact-based signal generation and output, and contactless signal generation and output is also possible.

[0028] Furthermore, measurement devices for signal acquisition may include a signal processing unit that processes the acquired signals. This processing may include converting the acquired signals from analog to digital or vice versa, as well as any other type of digital signal processing, for example, converting time-domain signals to frequency-domain signals.

[0029] The measurement devices may also have a user interface to display the acquired signals to the user and allow the user to control the measurement devices. Of course, a housing enclosing the elements of the measurement device may be provided. It is understood that additional elements such as a power supply circuit and communication interfaces may be provided.

[0030] A measurement device can be a standalone device that can be operated without any additional elements in a measurement application to perform tests on a device under test. Of course, communication capabilities can also be provided to connect the measurement device to other measurement devices.

[0031] A measurement device can, for example, be a signal recording device such as an oscilloscope, in particular a digital oscilloscope, a spectrum analyzer, or a vector network analyzer. A measurement device can also include a signal generation device, e.g., a signal generator, in particular an arbitrary signal generator, also referred to as an arbitrary waveform generator, or a vector signal generator. Other possible measurement devices include devices such as calibration standards or measuring probe tips.

[0032] Of course, at least some of the possible functions, such as signal recording and signal generation, can be combined in a single measuring device.

[0033] In embodiments, the measurement device may comprise pure data acquisition devices capable of acquiring an input signal and transmitting the acquired input signal as a digital input signal to a corresponding data storage or application server. Such pure data acquisition devices do not necessarily have a user interface or a display. Instead, such pure data acquisition devices may be remotely controlled, e.g., via a corresponding data connection such as a network interface or a USB interface. The same applies to pure signal generation devices capable of generating an output signal without having a user interface or configuration input devices. Instead, in one embodiment that can be combined with all other embodiments, such signal generation devices may be remotely controlled via a data connection.

[0034] The computer system, which can automatically perform analyses requested by the user, makes it possible to automatically test a circuit arrangement using modern high-performance semiconductors and significantly reduce the time required compared to manual measurements.

[0035] Further embodiments and developments emerge from the dependent claims and from the description with reference to the figures. In particular, all embodiments mentioned herein can be combined with one another in any order or number, unless individual features are mutually exclusive. In particular, the dependent claims of one claim category can also be developed according to another claim category. The features described as device features can be implemented as corresponding functions of a method, and vice versa.

[0036] In an embodiment, which may be combined with all embodiments mentioned herein, the user input may indicate at least one of the following analyses: a switching parameter analysis, a switching time analysis, a diode reverse recovery analysis, a capacitance analysis, an energy loss analysis, a statistical switching summary measurement, and a static switching summary measurement.

[0037] The analysis that the computing device can perform can be any one or a combination of the above analyses and is not limited to these.

[0038] A switching parameter analysis can involve determining dynamic parameters of the circuit arrangement or the high-performance semiconductor. The dynamic switching parameters can include, for example, the output charge (Q(OSS)) and the reverse recovery charge (Qrr) of the intrinsic body diode of a high-performance semiconductor.

[0039] The switching time analysis can, for example, be designed to determine variables such as td(on) (duration of the rise in the gate-source voltage from, for example, 10% until the drop in the drain-source voltage to, for example, 90%), tr (fall time of the drain-source voltage from, for example, 90% to, for example, 10%) and td(off) (duration of the fall in the gate-source voltage from, for example, 90% until the rise in the drain-source voltage to, for example, 10%), tf (rise time of the drain-source voltage from, for example, 10% to, for example, 90%). Other percentage values ​​can be specified, for example, by the user.

[0040] Diode reverse recovery analysis can also be called reverse recovery analysis. Diode reverse recovery analysis can determine the reverse recovery time, also called reverse recovery time, of a body diode of a high-performance semiconductor. Diode reverse recovery analysis can also determine the reverse recovery charge.

[0041] The reverse recovery time Trr can be calculated for a test using the double-pulse method as the sum of ta + tb. Where ta is the time required during the second test pulse for the reverse current to rise from 0 A until the maximum reverse current is reached (usually represented as a negative current), and tb is the time at which an extrapolated tangent drawn to the rise of the reverse current from its maximum reaches the value 0 A. The time tb can also be defined as the time from the maximum reverse current until the reverse current reaches a predetermined percentage of the maximum reverse current, e.g., 30%, 20%, 10%, or 5%.

[0042] During a measurement, ta can be determined, for example, using an edge detection technique on the waveform of the measured quantities. A predefined hysteresis band, also called hysteresis range or interval, or range or interval, can be defined for the edge at 0A. The time measurement can start when this hysteresis band is left. For tb, a tangent line can be drawn to the zero current axis or the axis indicating 0A in order to analyze the blocking time when the reverse current recovers from its maximum reverse current. This tangent can, for example, run through the points at 90% and 25% of the maximum reverse current. These values ​​can be changed or set by a user via the user interface. The tangent can be calculated or defined by defining a straight line that runs through the corresponding points.Alternatively, the time tb from the maximum reverse current to a predetermined percentage value can be recorded as explained above.

[0043] The straight line equation passing through the two percentage values ​​A and B of the maximum reverse current Imax at times t1 and t2 is determined as follows: I(t)={Imax*[(B−A) / 100] / (t2−t1)}*t+{[(t1*B−t2*A) / 100]*lmax / (t1−t2)}

[0044] The time at which this line reaches 0A is calculated as: t0=(t1*B−t2*A) / (B−A) The lock recovery time is calculated as: tb=t0−tm where tm is the time required for the reverse current to reach its maximum value.

[0045] The reverse recovery charge can be determined as the integral over the reverse current, i.e., from t0, the time at which the reverse current begins to rise, to time ti, where ti can be the time at which the reverse current reaches 0 A. Time ti can also be a time at which the reverse current reaches a predetermined percentage of the maximum reverse current.

[0046] Capacitance analysis can be used to determine the capacitances of high-performance semiconductors and parasitic capacitances in the circuit arrangement.

[0047] The energy loss analysis is used to determine the switching losses in the circuit arrangement.

[0048] A statistical circuit overview measurement in conjunction with power semiconductor characterization can refer to the recording of the electrical properties of a high-power semiconductor, such as an IGBT or MOSFET, in which measured values ​​acquired in multiple measurements are statistically evaluated. A measurement can also be carried out under stationary conditions, i.e. without temporal changes in the control or load signals, also referred to as static characterization. A combination of statistical and static measurement is possible. "Static" in this context means that the high-power semiconductor is operated at a specific operating point, e.g. at a constant gate voltage or constant drain-source voltage, and in particular DC quantities are measured.

[0049] Different parameters can be determined, such as a forward characteristic, e.g. I_D vs. V_DS, a reverse characteristic, e.g. leakage current in the off-state, a threshold voltage or voltage, an on-resistance R_DS(on), or a gate charging behavior.

[0050] In another embodiment, which can be combined with all embodiments mentioned herein, in a switching parameter analysis, the user input can characterize at least one of the following switching parameters: a turn-on energy of a high-power semiconductor, a turn-off energy of a high-power semiconductor, a turn-on duration, a turn-off duration, a drain-source voltage of a high-power semiconductor, a gate-source voltage of a high-power semiconductor, a drain-source current of a high-power semiconductor, a control voltage of a high-power semiconductor, a channel voltage of a high-power semiconductor, and a channel current of a high-power semiconductor.

[0051] Using user input, a user can not only specify a complete analysis, but can also specify which parameters should be examined.

[0052] In a further embodiment, which can be combined with all embodiments mentioned herein, the user input can include at least one predefined parameter for the analysis from the following group: a predefined voltage level, a predefined current level, and a test parameter for the circuit arrangement. The test parameter can include a maximum voltage, a maximum current, a temperature range, and a number of pulses.

[0053] Using the predefined parameters, the user can configure the analysis. The user can specify values ​​that are relevant for the analysis, i.e., values ​​that must be known. The user can also specify values ​​that should be set in the system to perform the analysis and, for example, to generate the test pulses.

[0054] For example, the specified voltage and current levels can be specified as input values ​​for the analysis if the user has manually set them, e.g., on an external signal source. The voltage levels can refer to the switching voltage, i.e., the gate-source voltage of the respective high-performance semiconductor. The voltage levels can also refer to a supply voltage in the switching path of the circuit arrangement. The same applies to the current levels.

[0055] The test parameters can specify limit values, such as a maximum voltage, a maximum current, or a maximum temperature. The test parameters can also specify specifications, such as a voltage range, a current range, a temperature range, and a number of pulses for the respective test.

[0056] The test parameters can be used, in particular, to perform repeated automated test runs or analyses within the limits specified by the test parameters. For example, multiple analyses of the same type can be performed for different voltages, currents, and temperatures.

[0057] The computing device can evaluate the predefined parameters provided by the user and automatically adjust the appropriate conditions for each repetition. For this purpose, the system can incorporate appropriate signal sources and climate actuators, such as cooling elements and heaters.

[0058] In yet another embodiment, which can be combined with all embodiments mentioned herein, the computing device can be configured to determine at least one of the following system parameters based on the at least one predetermined parameter: trigger settings for the acquisition of the measured variables, settings for the horizontal configuration of the output of the acquired measured variables, and settings for the vertical configuration of the output of the acquired measured variables.

[0059] System parameters include parameters that do not directly serve to measure or record the measured values. The term "system parameters" refers to parameters that, for example, influence the display of the measured values ​​for a user.

[0060] Possible system parameters include trigger settings and settings for displaying measured values ​​in the horizontal and vertical directions. However, the possible system parameters are not limited to these options.

[0061] The trigger settings can include various parameters. For example, the trigger settings can be a trigger event, e.g., determining which signal or event serves as the trigger for the measurement, e.g., a rising edge, a falling edge, specific voltage or current values. The trigger settings can also affect the trigger level, also called threshold, i.e., the specific value at which the trigger event is triggered, e.g., 1 V, 5 A. Furthermore, the trigger settings can affect a trigger delay, which can represent a time delay between the trigger event and the start of the measurement, e.g., 10 ms. The trigger settings can also indicate a trigger mode, i.e., a choice between different trigger modes, such as single trigger (one-time measurement upon triggering) or continuous measurement (continuous measurement).

[0062] The settings for displaying the measured values, also called display settings, can be, for example, a horizontal scaling, e.g. in ms / div, a vertical scaling, i.e. an adjustment of the vertical scaling in V / div or A / div to display the signal physically correctly, a dimension, i.e. an adjustment of the labeling of the axes to clearly identify the displayed values, e.g. “Voltage (V)”, “Current (A)”, or a grid display, which means the activation or deactivation of a grid for better visual orientation when analyzing signals.

[0063] The computing device can automatically determine the system parameters from the predefined parameters. Therefore, the user does not have to manually adjust them and can perform the analysis efficiently.

[0064] In an embodiment which can be combined with all embodiments mentioned herein, the user interface can comprise at least one of the following options: a human-machine interface for input by a user and for output to a user, and a data interface.

[0065] The human-machine interface can include any type of interface through which a user can provide input or through which information can be communicated to the user. Such interfaces can include, but are not limited to, a keyboard, a mouse, a screen, a touchscreen, audio output devices and audio input devices, and virtual reality or augmented reality systems.

[0066] Such a human-machine interface can, for example, be implemented as a component of the computing device if the device is designed as a standalone device, e.g., a server or computer. If the computing device is integrated into another device, e.g., a measuring device, the human-machine interface can be the interface of this device.

[0067] The user interface can also be a data interface that enables interaction with the computing device or with the system, e.g. via a network.

[0068] The computing device or a device in which the computing device is arranged can be provided at least partially as a server, which is accessible to the user and other devices via the Internet. Such a server can also be integrated, for example, as an application, in a measuring device with a network interface. The computing device can therefore be designed, for example, as a server application that is executed by a server accessible via a network. Such an application can, for example, have a corresponding API that enables other applications to interact with the application. In such embodiments, the user interface can, for example, be designed as a user application that is executed on a user's device and communicates with the server or the application on the server via the API. Such an API can, for example,a SOAP API, a REST API, or a Graph QLAPI, but are not limited to these examples. Such an application can, for example, integrate a web server. The application can also run on the server together with a web server. Such a web server can forward requests to the application and return the requests generated by the application. The application can, for example, be written in C, C++, Java, Python, or JavaScript (Node.js), but are not limited to these programming languages.

[0069] The application may additionally or alternatively deliver the user interface as a web-based or HTML-based page, which can be displayed and operated using a browser application on a user's device.

[0070] In one embodiment, which can be combined with all embodiments mentioned herein, the system can further comprise a signal source configured to supply the at least one test pulse to the circuit arrangement in a controlled manner. The signal source can be coupled to the computing device, and the computing device can be configured to control the signal source, or vice versa.

[0071] Coupling and controlling the signal source with the computing device, or vice versa, enables further automation of the circuit analysis. For example, the computing device can automatically control the generation of test pulses by the signal source based on the respective user inputs. This significantly simplifies automated, repeated analysis of the circuit, as a complete test cycle with multiple analyses can be performed automatically. The control function can also be performed by the signal source, which can then control the computing device accordingly.

[0072] If the signal source and the computing device are provided as separate devices or elements in the system, they can be synchronized via a corresponding connection. For this purpose, for example, a corresponding connection can be provided between the signal source and the computing device.

[0073] In addition to synchronizing the signal source with the computing device, the test pulses can be supplied to the computing device, for example, via a separate measuring channel or a corresponding measuring probe.

[0074] Synchronization of the computing device with the signal source can also occur without an explicit connection. For example, the computing device can synchronize itself with the acquired measured values. To do this, it can monitor them, for example, for the occurrence of specified threshold values.

[0075] Synchronization between the signal source and the computing device improves the synchronicity of the measurement and enables improved measurement quality. Temporal synchronization is important, for example, for correctly capturing and evaluating the response of the DUT. Additional synchronization can also reduce latency that can occur during signal processing. These latencies can occur, for example, when calculating power from current and voltage. Such synchronization simplifies direct comparison of different measurements and enables better detection of anomalies. Furthermore, the results can be easily reproduced.

[0076] In a further embodiment, which can be combined with all embodiments mentioned herein, the signal source can be configured to output test pulses with a configurable shape.

[0077] Typically, test pulses have a predetermined shape, e.g. a rectangular shape, a sawtooth shape or a triangular shape.

[0078] If the signal source allows the shape of the test pulses to be freely defined, real pulses can be simulated, as they occur during actual operation of the circuit. The signal source can, for example, include a so-called arbitrary waveform generator.

[0079] In another embodiment, which can be combined with all embodiments mentioned herein, the system can further comprise a clock source which is designed to output a clock signal, wherein the clock source is coupled to the computing device and the signal source, or wherein the clock source is arranged in the computing device and is coupled to the signal source, or wherein the clock source is arranged in the signal source and is coupled to the computing device.

[0080] The clock source can be provided as a standalone element of the system and coupled to the computing device and the signal source. Alternatively, the clock source can be provided either in the computing device or in the signal source and coupled to the other element. For this purpose, the computing device or the signal source can have a corresponding clock signal output.

[0081] The clock signal can comprise a cyclic signal that can specify a clock for the arithmetic unit and the signal source. A trigger signal can be transmitted in addition to the clock signal or integrated into the clock signal.

[0082] In a further embodiment, which can be combined with all embodiments mentioned herein, the computing device and the signal source and the clock source can be arranged together in a measuring device.

[0083] The measuring device can be, for example, an oscilloscope or any other suitable measuring device. By integrating the computing unit, the signal source, and the clock source into a single measuring device, the computing unit can be synchronized with the signal source.

[0084] For example, appropriate signal lines can be provided internally in the measuring device.

[0085] Furthermore, the test pulses can be transmitted from the signal source directly to the computing device; this can also be done in digital form, e.g. through a common memory area to which the computing device and the signal source have access.

[0086] The measuring device can also have signal interfaces via which the measuring probes can be coupled to the measuring device.

[0087] In one embodiment, which can be combined with all embodiments mentioned herein, the measuring device can have trigger logic, and the trigger logic can be coupled to the computing device to control processing of the measured variables by the computing device. Alternatively, the trigger logic can be coupled to the signal source to control the generation of the at least one test pulse by the signal source, or the trigger logic can be coupled to the computing device to control processing of the measured variables by the computing device, and the trigger logic can be coupled to the signal source to control the generation of the at least one test pulse by the signal source.

[0088] The trigger logic is used to generate a trigger signal which can be fed to the computing device and the signal source.

[0089] The computing device can control the processing of the measurement signals based on the trigger signal. The signal source can control the generation of the test pulses based on the trigger signal.

[0090] The trigger logic can be a digital trigger logic of the measuring device, which generates a corresponding trigger signal and transmits it to the computing device and the signal source.

[0091] In one embodiment, which can be combined with all other embodiments, a shared memory area can be provided, which the trigger logic and the signal source can access. The term "shared memory area" can be understood to mean that a flag or marker for the occurrence of a trigger event, for example, can be stored directly in the measurement data together with the actual measurement data. This enables optimal synchronization throughout the signal chain, low latencies / runtimes are generated in the system, data consistency and integrity are improved, real-time data access is possible, synchronized operations are possible, centralized data management and flexibility in data analysis are enabled,

[0092] In yet another embodiment, which can be combined with all embodiments mentioned herein, the system can further comprise an adjustable source configured to supply the circuit arrangement with electrical energy. In particular, the computing device can be coupled to the adjustable source and configured to adjust a voltage level of the source or a current strength of the source, or a voltage level and a current strength of the source.

[0093] The adjustable source can, for example, provide the power supply for the circuit's load path. This makes it possible to dynamically adjust the voltage and current in the circuit's load path for repeated analyses.

[0094] In another embodiment, which can be combined with all embodiments mentioned herein, the system can further comprise a probe set comprising a first measuring probe and a second measuring probe, wherein the first measuring probe is configured to detect a drain-source voltage of a high-power semiconductor, and the second measuring probe is configured to detect a drain-source current of a high-power semiconductor. The probe set can optionally comprise a third measuring probe configured to detect a gate-source voltage of a high-power semiconductor. The measuring probes can be coupled to the computing device.

[0095] A probe set is a group of measuring probes used to perform a measurement on a high-performance semiconductor. If a single probe set is used in the system, for example, the low-side switch or the high-side switch of a circuit arrangement can be measured.

[0096] In a further embodiment, which can be combined with all embodiments mentioned herein, the system can have two probe sets, wherein one of the probe sets can be coupled to a high-side high-power semiconductor, and the other of the probe sets can be coupled to a low-side high-power semiconductor.

[0097] If two separate probe sets are used, two high-performance semiconductors of a circuit arrangement can be measured simultaneously.

[0098] Especially when automatically executing a test series with a large number of analyses, different analyses for the circuit arrangement can be created flexibly.

[0099] In yet another embodiment, which can be combined with all embodiments mentioned herein, the signal source can be configured to drive the high-side high-power semiconductor and the low-side high-power semiconductor with an adjustable dead time.

[0100] The dead time refers to the time during which none of the high-power semiconductors are switched on or on. Consequently, no current flows in the load path of the circuit during this dead time.

[0101] In another embodiment, which can be combined with all embodiments mentioned herein, the computing device can further be designed to apply at least one of the following functions to the measured variables: voltage limitation, current limitation, anti-aliasing filter, amplification, filtering, and averaging.

[0102] These functions can be a type of signal conditioning, which can, for example, mitigate the effects of signal noise. This can ensure that measurements are highly accurate. Noise reduction can also be achieved, for example, by using a hysteresis band control loop or a filter.

[0103] In an embodiment which can be combined with all embodiments mentioned herein, the computing device can further be designed to analyze whether the test pulses supplied to the circuit arrangement correspond to respective pulse specifications, and to output an error signal if the test pulses do not correspond to the respective pulse specifications.

[0104] The pulse specifications can, for example, be stored in a corresponding look-up table and can specify a shape and a duration for the test pulses.

[0105] If one of the test pulses does not correspond to the pulse specifications, the measurement or analysis can be marked as faulty and the computing device can output a corresponding error signal.

[0106] The pulse specifications can also specify the number of pulses for specific analyses, for example. If a user defines fewer or more than the specified test pulses for such a measurement, the computing device can also output the error signal.

[0107] In another embodiment, which can be combined with all embodiments mentioned herein, the computing device can further be designed to automatically identify a region of interest in the measured variables and, in particular, to highlight the region of interest when outputting it via the user interface.

[0108] The range of interest can be, for example, the range of measured quantities that characterizes a switching on, a switching off or a switching cycle with switching on and switching off phases of a high-performance semiconductor.

[0109] The computing device can identify the area of ​​interest based, for example, on the trigger signal explained above. The computing device can also determine the areas of interest through appropriate analysis of the measured variables.

[0110] In particular, when the measured variables are graphically output via a display device, such as an oscilloscope display, the computing device can control the output in such a way that a region of interest is zoomed in on when the measured variables are displayed on the display device. The user interface can allow the user to jump directly from one region of interest to another.

[0111] In one embodiment, which can be combined with all other embodiments, the computing device can overlay several of the regions of interest when outputting via the user interface, in particular when outputting graphically via a display device. TABLE OF CONTENTS OF THE DRAWINGS

[0112] The present disclosure is explained in more detail below with reference to the exemplary embodiments shown in the schematic figures of the drawings. Fig. 1 shows a block diagram of an embodiment of a system according to the present disclosure; Fig. 2 shows a block diagram of another embodiment of a system according to the present disclosure; Fig. 3 shows a block diagram of another embodiment of a system according to the present disclosure; Fig. 4 shows a block diagram of another embodiment of a system according to the present disclosure; Fig. 5 shows a flow diagram of an embodiment of a method according to the present disclosure; Fig. 6 shows a diagram of a possible current waveform for a diode reverse recovery analysis according to the present disclosure; Fig. 7 shows a block diagram of an embodiment of an oscilloscope that may serve as a measurement device according to the present disclosure; and Fig. 8 shows a block diagram of an embodiment of another oscilloscope that may serve as a measurement device according to the present disclosure.

[0113] In all figures, functionally identical elements and devices - unless otherwise indicated - have been provided with similar reference symbols which are identical at least in the two least significant digits (units and tens). DETAILED DESCRIPTION OF THE FIGURES

[0114] Fig. Figure 1 shows a block diagram of a system 100 for analyzing circuit arrangements with high-performance semiconductors. The system 100 comprises a computing device 101 coupled to a user interface 103. The explanations of further embodiments of the system disclosed herein apply analogously to the system 100.

[0115] The computing device 101 can be coupled to one or more measuring probes. These can each detect one measured variable 102-1, 102-2, or multiple measured variables in a circuit arrangement under test, in particular, but not exclusively, while at least one test pulse is being applied to the circuit arrangement.

[0116] The user interface 103 can receive a user input 104 from a user. The user input specifies an analysis 105 to be performed using the measured variables 102-1, 102-2.

[0117] For this purpose, the computing device 101 receives the measured variables 102-1, 102-2 from the measuring probes and performs the analysis 105 specified by the user input 104 with the received measured variables 102-1, 102-2. The analysis 105 can be implemented, for example, as a computer program product and process digital data in which the measured variables 102-1, 102-2 are provided.

[0118] The computing device 101 can output the measured variables 102-1, 102-2 and analysis results 106 of the performed analysis 105 via the user interface 103.

[0119] The user interface 103 can, for example, be the user interface of an oscilloscope that has the calculation direction. The user interface 103 can, for example, be designed as a human-machine interface for input by a user and for output to a user. Additionally or alternatively, the user interface 103 can be designed as a data interface.

[0120] The user input 104 may identify or specify at least one of the following analyses 105: a switching parameter analysis, a switching time analysis, a diode reverse recovery analysis, a capacitance analysis, an energy loss analysis, and a statistical switching summary measurement.

[0121] In a switching parameter analysis, the user input 104 may identify at least one of the following switching parameters: a turn-on energy of a high-power semiconductor, a turn-off energy of a high-power semiconductor, a turn-on duration, a turn-off duration, a drain-source voltage of a high-power semiconductor, a gate-source voltage of a high-power semiconductor, a drain-source current of a high-power semiconductor, a control voltage of a high-power semiconductor, a channel voltage of a high-power semiconductor, and a channel current of a high-power semiconductor.

[0122] The user input 104 may further include at least one predetermined parameter for the analysis 105 from the following group: a predetermined voltage level, a predetermined current level, a test parameter for the circuit arrangement, wherein the test parameter includes at least one of the following options: a maximum voltage, a maximum current, a temperature range, and a number of pulses.

[0123] The computing device 101 can determine at least one of the following system parameters based on the at least one predetermined parameter: trigger settings for the acquisition of the measured variables 102-1, 102-2, settings for the horizontal configuration of the output of the acquired measured variables 102-1, 102-2, and settings for the vertical configuration of the output of the acquired measured variables 102-1, 102-2.

[0124] The computing device 101 can further apply at least one of the following functions to the measured variables 102-1, 102-2: voltage limiting, current limiting, anti-aliasing filtering, amplification, filtering, and averaging. Furthermore, the computing device 101 can analyze whether the test pulses supplied to the circuit arrangement correspond to the respective pulse specifications and output an error signal if the test pulses do not correspond to the respective pulse specifications.

[0125] The computing device 101 can further automatically identify a region of interest in the measured variables 102-1, 102-2, and in particular highlight the region of interest when outputting via the user interface 103.

[0126] Fig. Figure 2 shows a block diagram of another system 200. System 200 is based on system 100. System 200 includes a computing device 201 coupled to a user interface 203. The explanations of further embodiments of the system disclosed herein apply analogously to system 200.

[0127] The system 200 further comprises a signal source 210, which is coupled to the computing device 201 and which can supply the at least one test pulse 211 to the circuit arrangement in a controlled manner. The signal source 210 can be controlled by the computing device 201. In embodiments, the signal source 210 can control the computing device 201 and supply it, for example, with trigger signals or the like.

[0128] The signal source 210 can output test pulses 211 with a configurable shape and can be designed, for example, as a so-called arbitrary waveform generator.

[0129] System 200 may further include a clock source 213. Clock source 213 may be coupled to computing device 201 and signal source 210. Alternatively, clock source 213 may be located in computing device 201 and coupled to signal source 210. Clock source 213 may also be located in signal source 210 and coupled to computing device 201.

[0130] It is understood that both the signal source 210 and the clock source 213 are optional.

[0131] In the system 200, the computing device 201 and the signal source 210 and the clock source 213 can be arranged together in a measuring device, e.g. an oscilloscope.

[0132] Fig. 3 shows a block diagram of another system 300. System 300 is based on system 200. Therefore, system 300 includes a computing device 301 coupled to a user interface 303. System 300 includes a signal source 310 coupled to computing device 301. System 300 includes a clock source 313. Clock source 313 is coupled to computing device 301 and signal source 310. System 300 further includes trigger logic 316 coupled to signal source 310 and computing device 310. The explanations of further embodiments of the system disclosed herein apply analogously to system 300.

[0133] The trigger logic 316 can be coupled to the signal source 310 to control the generation of the at least one test pulse 311 by the signal source 310. The trigger logic 316 can also be coupled to the computing device to control processing of the measured variables 302-1, 302-2 by the computing device 301.

[0134] Fig. 4 shows a block diagram of a system 400. The system 400 is based on the system 100. Therefore, the system 400 includes a computing device 401 coupled to a user interface 403. The explanations of further embodiments of the system disclosed herein apply analogously to the system 400.

[0135] The system 400 further includes an adjustable source 420. The source 420 is coupled to circuitry 499 for supplying it with electrical energy. The computing device 401 is coupled to the adjustable source 420 and can adjust a voltage level of the source 420 or a current level of the source 420, or a voltage level and a current level of the source 420.

[0136] The system 400 further includes a probe set comprising a first measuring probe 421-1 and a second measuring probe 421-2. The first measuring probe 421-1 can detect a drain-source voltage of a high-power semiconductor 489-2 of the circuit arrangement 499, and the second measuring probe 421-2 can detect a drain-source current of the high-power semiconductor 489-2. The high-power semiconductor 489-2 is the low-side switch of the circuit arrangement 499. The probe set can alternatively or additionally also be arranged on the high-side high-power semiconductor 489-1.

[0137] In embodiments, the probe set may include a third measuring probe, which may be configured to detect a gate-source voltage of the respective high-power semiconductor 498-1, 489-2. The measuring probes 421-1, 421-2 are each coupled to the computing device 401 and transmit corresponding measured variables 402-1, 402-1 to it.

[0138] In further embodiments, system 400 may include two probe sets. One of the probe sets may be coupled to high-side high-power semiconductor 498-1, and the other of the probe sets may be coupled to low-side high-power semiconductor 489-2.

[0139] Fig. 5 shows a flowchart of an embodiment of a method for analyzing circuit arrangements with high-performance semiconductors. The method comprises detecting S1 a respective measured variable in a circuit arrangement to be tested using one or more measuring probes, wherein the measuring probes are configured to detect the respective measured variable while at least one test pulse is supplied to the circuit arrangement, receiving S2 a user input from a user that identifies an analysis, executing S3 the analysis identified by the user input using the received measured variables, and outputting S4 the measured variables and analysis results of the executed analysis via a user interface.

[0140] The method can be further developed according to any of the further embodiments.

[0141] Fig. Figure 6 shows a diagram of a possible current waveform for a diode reverse recovery analysis according to the present disclosure. The current initially decreases for time tm until the maximum reverse current is reached. For the period tb, the current increases again. tb can be determined as explained above. A possible tangent to the slope of the reverse current is shown in dashed lines.

[0142] Fig. 7 shows a block diagram of an oscilloscope OSC1 that may be used in an embodiment of a system according to the present disclosure.

[0143] The OSC1 oscilloscope comprises a housing (HO) containing four measurement inputs (MIP1, MIP2, MIP3, and MIP4). These inputs are connected to a signal processor (SIP) for processing the measured signals. The SIP is connected to a display (DISP1) for displaying the measured signals to the user.

[0144] Although not explicitly shown, it should be understood that the OSC1 oscilloscope may also include signal outputs. Such signal outputs can be used, for example, to output calibration signals. Such calibration signals allow the calibration of the measurement setup before performing measurements. The process of calibrating and correcting measurement signals based on the calibration can also be referred to as "de-embedding" and may involve applying appropriate algorithms to the generated or measured signals.

[0145] In the oscilloscope OSC1, the signal processor SIP or an additional processing element can execute or implement the function of the computing device according to the present disclosure. Other elements, such as the user interface, signal source, clock source, and trigger logic, can also be implemented in or by elements of the oscilloscope OSC1. Of course, a communication interface for communication with other measurement devices can be provided in the oscilloscope OSC1.

[0146] Fig. Figure 8 shows a block diagram of an oscilloscope (OSC), which may be an implementation of a measurement device according to the present disclosure. The oscilloscope (OSC) is implemented as a digital oscilloscope. However, it should be noted that the present disclosure may also be implemented with any other type of oscilloscope.

[0147] The oscilloscope OSC comprises, for example, five general sections: the vertical system (VS), the triggering section (TS), the horizontal system (HS), the processing section (PS), and the display (DISP). It is understood that the division into five general sections represents a logical division and in no way restricts the placement and implementation of the oscilloscope OSC elements.

[0148] The VS vertical system is primarily used to offset, attenuate, and amplify a signal to be acquired. For example, the signal can be modified to fit within the available display area of ​​the DISP display or to have a user-configured vertical size.

[0149] For this purpose, the vertical system VS includes a signal conditioning section SC with an attenuator ATT and a digital-to-analog converter (DAC), which are connected to an amplifier AMP. The amplifier AMP is connected to a filter FI1, which in the example shown is provided as a low-pass filter. The vertical system VS also includes an analog-to-digital converter (ADC), which receives the output of the filter FI1 and converts the received analog signal into a digital signal.

[0150] The attenuator ATT and the amplifier AMP serve to adapt the amplitude of the signal to be acquired to the operating range of the analog-to-digital converter (ADC). The digital-to-analog converter (DAC) modifies the DC component of the input signal to be acquired so that it fits within the operating range of the analog-to-digital converter (ADC). The filter FI1 serves to filter out unwanted high-frequency components of the signal to be acquired.

[0151] The trigger section TS operates with the signal provided by the amplifier AMP. The trigger section TS includes a filter FI2, which in this version is implemented as a low-pass filter. The filter FI2 is connected to a trigger system TS1.

[0152] The trigger section (TS) is used to capture predefined signal events and allows the horizontal system (HS) to, for example, display a stable view of a repeated waveform or simply display waveform sections containing the respective signal event. It should be understood that the predefined signal event can be configured by a user via a user input on the oscilloscope (OSC).

[0153] Possible predefined signal events may include, but are not limited to, the signal crossing a predefined trigger threshold in a predefined direction, i.e., with a rising or falling edge. Such a trigger condition is also referred to as an edge trigger. Another trigger condition is called "glitch triggering," and triggers when a pulse occurs in the signal being acquired whose width is greater or less than a predefined time.

[0154] To ensure an exact match of the trigger signal with the waveform shown on the DISP display, a common time base can be provided for the analog-to-digital converter ADC and the trigger system TS1.

[0155] It is understood that, although not explicitly shown, the trigger system TS1 may comprise at least one of the following components: configurable voltage comparators for setting the trigger thresholds, fixed voltage sources for setting the required edge, corresponding logic gates such as an XOR gate and flip-flops for generating the trigger signal.

[0156] The trigger section TS is provided as an analog trigger section for example. It should be understood that the oscilloscope OSC can also be equipped with a digital trigger section. Such a digital trigger section operates not with the analog signal provided by the amplifier AMP, but with the digital signal provided by the analog-to-digital converter ADC.

[0157] A digital trigger section may include a processing element, such as a processor, a DSP, a CPLD, an ASIC, or an FPGA, to implement digital algorithms for detecting a valid trigger signal.

[0158] The horizontal system HS is connected to the output of the trigger system TS1 and is mainly used to position and scale the signal to be acquired horizontally on the display DISP.

[0159] The oscilloscope OSC further includes a processing section (PS), which implements digital signal processing and data storage for the oscilloscope. The processing section PS includes an acquisition processing element (ACP), which is connected to the output of the analog-to-digital converter (ADC) and the output of the horizontal system (HS), as well as to a memory (MEM), and a post-processing element (PPE).

[0160] The acquisition processing element (ACP) manages the acquisition of digital data from the analog-to-digital converter (ADC) and the storage of the data in the memory (MEM). The acquisition processing element (ACP) may, for example, comprise a processing element that has a digital interface to the analog-to-digital converter (ADC) and a digital interface to the memory (MEM). The processing element may, for example, comprise a microcontroller, a DSP, a CPLD, an ASIC, or an FPGA with appropriate interfaces. In a microcontroller or DSP, the functionality of the acquisition processing element (ACP) may be implemented as computer-readable instructions executed by a CPU. In a CPLD or FPGA, the functionality of the acquisition processing element (ACP) may be configured in the CPLD or FPGA instead of having software executed by a processor.

[0161] The processing section PS also includes a communication processor CP and a communication interface COM.

[0162] The communication processor CP can be a device that manages data transfer to and from the oscilloscope OSC. The communication interface COM can be designed for any suitable communication standard, such as Ethernet, Wi-Fi, Bluetooth, NFC, an infrared communication standard, and a visible-light-based communication standard.

[0163] The communication processor CP is connected to the memory MEM and can use the memory MEM to store and retrieve data.

[0164] Of course, the communication processor CP can also be connected to any other element of the oscilloscope OSC in order to retrieve device data or to provide device data received, for example, from a management server.

[0165] The post-processing element (PPE) can be controlled by the acquisition processing element (ACP) and can access the memory (MEM) to retrieve data to be displayed on the display (DISP). The post-processing element (PPE) can prepare the data stored in the memory (MEM) so that the display (DISP) can display the data to a user, for example, as a waveform. The post-processing element (PPE) can also implement analysis functions such as cursors, waveform measurements, histograms, or mathematical functions.

[0166] The display DISP controls all aspects of signal representation for a user and, although not explicitly shown, may include any component required to receive data to be displayed and control a display device to display the data as desired.

[0167] It is understood that the oscilloscope OSC, although not shown, may include a user interface through which a user can interact with the oscilloscope OSC. Such a user interface may include dedicated input elements such as buttons and switches. The user interface may also be provided, at least in part, as a touch-sensitive display device.

[0168] In the oscilloscope OSC, one of the processing elements, also called a computing element, in the processing section PS or an additional processing element can execute or implement the function of the computing device according to the present disclosure. Other elements, such as the user interface, signal source, clock source, and trigger logic, can also be implemented in or by elements of the oscilloscope OSC.

[0169] It is understood that all elements of the oscilloscope OSC that perform digital data processing can be provided as dedicated elements. Alternatively, at least some of the functions described above can be implemented in a single hardware element, such as a microcontroller, DSP, CPLD, or FPGA. In general, the logical functions described above can be implemented in any suitable hardware element of the oscilloscope OSC and do not necessarily need to be divided into the various sections described above.

[0170] The processes, methods, or algorithms disclosed herein may be transferred to or implemented by a computing device, controller, or computer. These may include any existing programmable electronic control unit or dedicated electronic control unit. Likewise, the processes, methods, or algorithms may be stored as data and instructions that can be executed by a controller or computer in many forms, including, but not limited to, information permanently stored on non-writable storage media such as read-only devices and information modifiably stored on writable storage media such as floppy disks, magnetic tapes, compact discs, random access memory, and other magnetic and optical media. The processes, methods, or algorithms may also be implemented in a software-executable object.Alternatively, the processes, methods, or algorithms may be embedded, in whole or in part, in suitable hardware components such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), state machines, controllers, or other hardware components or devices, or a combination of hardware, software, and firmware components.

[0171] Although exemplary embodiments are described above, it should be understood that these embodiments do not encompass all possible forms of implementation of the present disclosure covered by the claims. The terms used in the specification are for the purpose of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the disclosure. As described above, the features of various embodiments may be combined to form further embodiments of the invention that may not be explicitly described or illustrated.While various embodiments may be described as advantageous or preferred over other embodiments or prior art implementations with respect to one or more desired characteristics, those skilled in the art will recognize that one or more properties or features may be altered in favor of desired overall system characteristics depending on the specific application and implementation. These properties may include, but need not be limited to, cost, strength, durability, life cycle cost, marketability, appearance, packaging, size, maintainability, weight, manufacturability, ease of assembly, etc.Thus, to the extent that embodiments have been described as less desirable than other embodiments or prior art implementations with respect to certain features, those embodiments still fall within the scope of the disclosure and may be desirable for certain applications.

[0172] With respect to the processes, systems, methods, heuristics, etc. described herein, it is understood that although the steps of such processes, etc., have been described in a particular order, such processes may be performed in a different order than that described herein. Likewise, it is understood that certain steps may be performed concurrently, other steps may be added, or certain steps described herein may be omitted. In other words, the descriptions of the processes herein are illustrative of particular embodiments and should in no way be construed to limit the claims.

[0173] In summary, it is understood that the disclosed subject matter may be modified and varied without departing from the scope of the present disclosure.

[0174] All terms used in the claims are intended to be given their broadest reasonable interpretations and their common meanings as understood by those familiar with the technologies described herein, unless expressly stated otherwise. In particular, the use of singular articles such as "a," "a," "the," "said," etc., should be read to include one or more of the specified elements, unless a claim expressly excludes the contrary. OTHER EMBODIMENTS

[0175] Embodiment 1. A method for analyzing circuit arrangements with high-performance semiconductors, the method comprising: detecting (S1) a respective measured variable in a circuit arrangement to be tested with one or more measuring probes, wherein the measuring probes are designed to detect the respective measured variable while at least one test pulse is supplied to the circuit arrangement; Receiving (S2) a user input from a user indicating an analysis; Executing (S3) the analysis identified by the user input with the received measured values; and Outputting (S4) the measured values ​​and analysis results of the performed analysis via a user interface.

[0176] Embodiment 2. The method of embodiment 1, wherein the user input identifies at least one of the following analyses: a switching parameter analysis; a switching time analysis; a diode reverse recovery analysis; a capacity analysis; an energy loss analysis; and a statistical switching overview measurement.

[0177] Embodiment 3. The method according to embodiment 2, wherein in a switching parameter analysis the user input identifies at least one of the following switching parameters: a turn-on energy of a high-performance semiconductor; a turn-off energy of a high-performance semiconductor; a duty cycle; a switch-off time; a drain-source voltage of a high-performance semiconductor; a gate-source voltage of a high-power semiconductor; a drain-source current of a high-performance semiconductor; a control voltage of a high-performance semiconductor; a channel voltage of a high-performance semiconductor; and a channel current of a high-performance semiconductor.

[0178] Embodiment 4. The method according to any one of embodiments 2 and 3, wherein the user input comprises at least one predetermined parameter for analysis from the following group: a predetermined voltage level; a predetermined current level; a test parameter for the circuit arrangement; where the test parameter has: a maximum voltage; a maximum current; a temperature range; and a number of pulses.

[0179] Embodiment 5. The method of embodiment 4, further comprising determining at least one of the following system parameters based on the at least one predetermined parameter: Trigger settings for recording the measured values; Settings for the horizontal configuration of the output of the recorded measured values; and Settings for the vertical configuration of the output of the recorded measured values.

[0180] Embodiment 6. The method according to any one of the preceding embodiments, wherein the user interface comprises at least one of the following options: a human-machine interface for input by a user and output to a user; and a data interface.

[0181] Embodiment 7. Method according to one of the preceding embodiments, further comprising the controlled generation of the at least one test pulse and the supplying of the generated at least one test pulse to the circuit arrangement.

[0182] Embodiment 8. The method of embodiment 7, wherein the test pulses are output with a configurable shape.

[0183] Embodiment 9. The method of any of embodiments 7 and 8, further comprising generating a clock signal; wherein at least two functions from the group of receiving the measurement data, performing the analysis, and generating the test pulses are synchronized based on the clock signal.

[0184] Embodiment 10. The method according to embodiment 9, wherein the method is carried out by a metrological device.

[0185] Embodiment 11. The method according to embodiment 10, wherein the measuring device has a trigger logic; and wherein the trigger logic controls processing of the measured variables by the computing device; or wherein the trigger logic controls the generation of the at least one test pulse by the signal source; or wherein the trigger logic controls processing of the measured variables by the computing device, and wherein the trigger logic controls the generation of the at least one test pulse by the signal source.

[0186] Embodiment 12. The method according to any one of the preceding embodiments, further comprising supplying the circuit arrangement with electrical energy by an adjustable source; and in particular comprising setting a voltage level of the source or a current strength of the source or a voltage level and a current strength of the source.

[0187] Embodiment 13. Method according to one of the preceding embodiments, further comprising detecting a drain-source voltage of a high-power semiconductor, and a drain-source current of a high-power semiconductor, and in particular a gate-source voltage of a high-power semiconductor as measured variables.

[0188] Embodiment 14. The method according to embodiment 13, further comprising detecting a drain-source voltage of a high-side high-power semiconductor, and a drain-source current of a high-side high-power semiconductor, and in particular a gate-source voltage of a high-side high-power semiconductor as measured variables; and detecting a drain-source voltage of a low-side high-power semiconductor, and a drain-source current of a low-side high-power semiconductor, and in particular a gate-source voltage of a low-side high-power semiconductor as measured variables.

[0189] Embodiment 15. The method according to embodiment 7 and according to any one of embodiments 13 and 14, wherein the high-side high-power semiconductor and the low-side high-power semiconductor are controlled with an adjustable dead time.

[0190] Embodiment 16. Method according to any one of the preceding embodiments, wherein at least one of the following functions is further applied to the measured variables: a voltage limiter; a current limit; Anti-aliasing filter; a reinforcement; a filtering; and an averaging.

[0191] Embodiment 17. Method according to one of the preceding embodiments, further comprising analyzing whether the test pulses supplied to the circuit arrangement correspond to respective pulse specifications, and outputting an error signal if the test pulses do not correspond to the respective pulse specifications.

[0192] Embodiment 18. The method of any preceding embodiment, further comprising automatically identifying a region of interest in the measured variables, and in particular highlighting the region of interest when outputting via the user interface. LIST OF REFERENCE SYMBOLS 100, 200, 300, 400 systems 101, 201, 301, 401 computing device 102-1, 102-2, 202-1, 202-2 Measured quantity 302-1, 302-2, 402-1, 402-2 Measured quantity 103, 203, 303, 403 user interface 104, 204, 304, 404 User input 105, 205, 305, 405 Analysis 106, 206, 306, 406 Analysis result 210, 310 signal source 211, 311 test pulse 213, 313 Clock source 214, 314 clock signal 316 Trigger logic 317 Trigger signal 420 Source 421-1, 421-2 measuring probe 499 Circuit arrangement 498-1, 489-2 High-performance semiconductors S1 - S4 process steps OSC1 oscilloscope HO housing MIP1, MIP2, MIP3, MIP4 measurement input SIP signal processor DISP1 Display OSC Oscilloscope VS vertical system SC signal conditioning section ATT attenuator DAC digital-to-analog converter AMP amplifier FI1 Filter ADC analog-to-digital converter TS trigger section AMP2 amplifier FI2 filter TS1 trigger system HS horizontal system PS processing section ACP capture processing element MEM memory PPE post-processing element DISP Display

Claims

[1] System (100, 200, 300, 400) for analyzing (105, 205, 305, 405) circuit arrangements (499) with high-performance semiconductors (498-1, 489-2), the system (100, 200, 300, 400) comprising: a computing device (101, 201, 301, 401) which can be coupled to one or more measuring probes (421-1, 421-2), wherein the measuring probes (421-1, 421-2) are designed to each detect a measured variable (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2) in a circuit arrangement (499) to be tested, while at least one test pulse (211, 311) is supplied to the circuit arrangement (499); and a user interface (103, 203, 303, 403) configured to receive a user input (104, 204, 304, 404) from a user indicating an analysis (105, 205, 305, 405); wherein the computing device (101, 201, 301, 401) is designed: to receive the measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2) from the measuring probes (421-1, 421-2); to carry out the analysis (105, 205, 305, 405) identified by the user input (104, 204, 304, 404) with the received measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2); and to output the measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2) and analysis results (106, 206, 306, 406) of the performed analysis (105, 205, 305, 405) via the user interface (103, 203, 303, 403). [2] The system (100, 200, 300, 400) of claim 1, wherein the user input (104, 204, 304, 404) identifies at least one of the following analyses (105, 205, 305, 405): a switching parameter analysis; a switching time analysis; a diode reverse recovery analysis; a capacity analysis; an energy loss analysis; and a statistical switching overview measurement. [3] System (100, 200, 300, 400) according to claim 2, wherein in a switching parameter analysis the user input (104, 204, 304, 404) identifies at least one of the following switching parameters: a turn-on energy of a high-performance semiconductor (498-1, 489-2); a turn-off energy of a high-performance semiconductor (498-1, 489-2); a duty cycle; a switch-off time; a drain-source voltage of a high-performance semiconductor (498-1, 489-2); a gate-source voltage of a high-performance semiconductor (498-1, 489-2); a drain-source current of a high-performance semiconductor (498-1, 489-2); a control voltage of a high-performance semiconductor (498-1, 489-2); a channel voltage of a high-performance semiconductor (498-1, 489-2); and a channel current of a high-performance semiconductor (498-1, 489-2). [4] System (100, 200, 300, 400) according to one of claims 2 and 3, wherein the user input (104, 204, 304, 404) comprises at least one predetermined parameter for the analysis (105, 205, 305, 405) from the following group: a predetermined voltage level; a predetermined current level; a test parameter for the circuit arrangement (499); where the test parameter has: a maximum voltage; a maximum current; a temperature range; and a number of pulses. [5] System (100, 200, 300, 400) according to claim 4, wherein the computing device (101, 201, 301, 401) is designed to determine at least one of the following system parameters based on the at least one predetermined parameter: Trigger settings for the acquisition of measured values (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2); Settings for the horizontal configuration of the output of the acquired measured values (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2); and Settings for the vertical configuration of the output of the acquired measured values (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2). [6] System (100, 200, 300, 400) according to one of the preceding claims, wherein the user interface (103, 203, 303, 403) has at least one of the following options: a human-machine interface for input by a user and output to a user; and a data interface. [7] System (100, 200, 300, 400) according to one of the preceding claims, further comprising a signal source (210, 310) which is designed to supply the at least one test pulse (211, 311) to the circuit arrangement (499) in a controlled manner; wherein the signal source (210, 310) is coupled to the computing device (101, 201, 301, 401); and wherein the computing device (101, 201, 301, 401) is designed to control the signal source (210, 310) or vice versa. [8] System (100, 200, 300, 400) according to claim 7, wherein the signal source (210, 310) is configured to output test pulses (211, 311) having a configurable shape. [9] System (100, 200, 300, 400) according to one of claims 7 and 8, further comprising a clock source (213, 313) configured to output a clock signal (214, 314); wherein the clock source (213, 313) is coupled to the computing device (101, 201, 301, 401) and the signal source (210, 310); or wherein the clock source (213, 313) is arranged in the computing device (101, 201, 301, 401) and is coupled to the signal source (210, 310); or wherein the clock source (213, 313) is arranged in the signal source (210, 310) and is coupled to the computing device (101, 201, 301, 401). [10] System (100, 200, 300, 400) according to claim 9, wherein the computing device (101, 201, 301, 401) and the signal source (210, 310) and the clock source (213, 313) are arranged together in a measuring device. [11] The system (100, 200, 300, 400) of claim 10, further comprising trigger logic (316); wherein the trigger logic (316) is coupled to the computing device in order to control processing of the measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2) by the computing device (101, 201, 301, 401); or wherein the trigger logic (316) is coupled to the signal source (210, 310) to control the generation of the at least one test pulse (211, 311) by the signal source (210, 310); or wherein the trigger logic (316) is coupled to the computing device in order to control processing of the measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2) by the computing device (101, 201, 301, 401), and wherein the trigger logic (316) is coupled to the signal source (210, 310) in order to control the generation of the at least one test pulse (211, 311) by the signal source (210, 310). [12] System (100, 200, 300, 400) according to one of the preceding claims, further comprising an adjustable source (420) which is designed to supply the circuit arrangement (499) with electrical energy; in particular wherein the computing device (101, 201, 301, 401) is coupled to the adjustable source (420) and is designed to adjust a voltage level of the source (420) or a current intensity of the source (420) or a voltage level and a current intensity of the source (420). [13] System (100, 200, 300, 400) according to one of the preceding claims, further comprising a probe set comprising a first measuring probe (421-1, 421-2) and a second measuring probe (421-1, 421-2), wherein the first measuring probe (421-1, 421-2) is configured to detect a drain-source voltage of a high-power semiconductor (498-1, 489-2), and the second measuring probe (421-1, 421-2) is configured to detect a drain-source current of a high-power semiconductor (498-1, 489-2); wherein the probe set comprises in particular a third measuring probe (421-1, 421-2) which is designed to detect a gate-source voltage of a high-performance semiconductor (498-1, 489-2); and wherein the measuring probes (421-1, 421-2) are coupled to the computing device (101, 201, 301, 401). [14] The system (100, 200, 300, 400) of claim 13, further comprising two probe sets, one of the probe sets being coupled to a high-side high-power semiconductor (498-1, 489-2), and the other of the probe sets being coupled to a low-side high-power semiconductor (498-1, 489-2). [15] System (100, 200, 300, 400) according to claim 7 and according to one of claims 13 and 14, wherein the signal source (210, 310) is designed to control the high-side high-power semiconductor (498-1, 489-2) and the low-side high-power semiconductor (498-1, 489-2) with an adjustable dead time. [16] System (100, 200, 300, 400) according to one of the preceding claims, wherein the computing device (101, 201, 301, 401) is further configured to apply at least one of the following functions to the measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2): a voltage limiter; a current limit; Anti-aliasing filter; a reinforcement; a filtering; and an averaging. [17] System (100, 200, 300, 400) according to one of the preceding claims, wherein the computing device (101, 201, 301, 401) is further designed to analyze whether the test pulses (211, 311) supplied to the circuit arrangement (499) correspond to respective pulse specifications, and to output an error signal if the test pulses (211, 311) do not correspond to the respective pulse specifications. [18] System (100, 200, 300, 400) according to one of the preceding claims, wherein the computing device (101, 201, 301, 401) is further configured to automatically identify an area of interest in the measured variables (102-1, 102-2, 202-1, 202-2, 302-1, 302-2, 402-1, 402-2), and in particular to highlight the area of interest when outputting via the user interface (103, 203, 303, 403).

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