System for reusable formal verification of IP (Intellectual Property) libraries with automated property integration and traceability mapping

Abstract

A system for the reusable formal verification of intellectual property (IP) with automated ownership integration and traceability attribution, consisting of: a non-volatile storage subsystem configured to store a variety of formal verification properties in a canonical intermediate representation, each property associated with metadata including design applicability tags, signal binding templates, clock domain parameters, and request identifiers; an automated processing unit for property integration, configured to retrieve one or more stored formal verification properties from the non-volatile memory subsystem, perform syntax and semantic normalization to adapt the retrieved properties to a target design under verification (DUV), resolve signal hierarchy differences through a signal name normalization module, and apply clock domain matching via a clock mapping controller; a traceability mapping engine implemented on one or more dedicated processing cores and configured to manage bidirectional mapping records between functional or safety requirements and their associated formal verification properties, dynamically update these mapping records when properties or verification results change, and export compliance reports in an industry-standard requirements exchange format; and a high-speed connection and interface controller configured to connect the automated property integration processing unit and traceability mapping engine to external electronic design automation (EDA) tool environments via a communication interface that includes at least one of the PCIe and Ethernet interfaces.

Description

Technical field

[0001] The present invention relates to the field of electronic design automation (EDA) and formal verification systems used in semiconductor design and verification processes. More specifically, the invention relates to a hardware-implemented system that facilitates the storage, reuse, automated integration, and traceability of formal verification properties, statements, and constraints through a structured verification IP library. BACKGROUND OF THE INVENTION

[0002] System-on-a-chip (SoCs) and complex integrated circuits (ICs) often integrate numerous blocks of intellectual property (IP), each requiring rigorous formal verification to ensure design correctness before mass production. Traditional formal verification workflows rely heavily on property checkers, temporal logic statements, and formal proofs, often implemented manually or embedded in simulation testbenches. While commercial formal verification tools allow for some property reuse, this is frequently limited by project-specific constraints, syntax differences, and proprietary tool formats.

[0003] Existing approaches also lack sufficient support for the cross-project reuse of properties, as formal verification properties are often tightly bound to specific naming conventions, signal hierarchies, or clock domains of a particular design. This leads to significant rework when the same property is applied to a different project or design variant. Furthermore, dedicated hardware-assisted integration and mapping engines are lacking that can automatically normalize the property syntax, integrate it into a design's verification environment, and maintain a synchronized traceability map from requirements to verification results.

[0004] Therefore, there is a need for a machine-based system that can host a reusable IP library for formal verification, perform automated property integration across heterogeneous design environments, and maintain end-to-end traceability mapping in accordance with industry verification standards, while also being implemented as a hardware-accelerated verification device.

[0005] The development of formal verification methods in electronic design automation has been driven by the increasing complexity of integrated circuit architectures, the critical need for functional correctness, and the high costs associated with post-silicon fabrication defects. As semiconductor system-on-chip (SoCs) now integrate billions of transistors and numerous heterogeneous subsystems, simulation-based verification approaches have proven insufficient to fully cover all possible design states and input conditions.Formal verification, which employs mathematical proof techniques to check the correctness of a design against a specific set of properties or specifications, has proven to be an important complement to simulation, particularly in safety-critical and mission-critical applications such as automotive electronics, aerospace control systems, and medical devices. In these fields, the ability to mathematically guarantee that certain properties will always hold true is not only a matter of design quality but also a regulatory requirement.

[0006] Existing solutions for formal verification typically involve writing properties or assertions in temporal logic languages ​​such as SystemVerilog Assertions (SVA) or Property Specification Language (PSL) and applying them to a design under verification (DUV) using formal property validation tools. These properties can express functional constraints, protocol compliance, safety rules, and security requirements, and are comprehensively evaluated by formal verification engines. In practice, however, the verification process is highly fragmented, and each project or team often develops its own set of properties from scratch.While certain EDA vendors provide libraries with protocol checkers or assertion IPs, these are often tightly tailored to specific standards such as AMBA, PCIe or USB, leaving them with the flexibility to be used in a wide range of custom or cross-domain designs.

[0007] One of the biggest limitations of current approaches is the lack of standardized, reusable property libraries that can be easily ported from one design environment to another. Formal properties are typically tightly bound to the naming conventions, signal hierarchies, and timing schemes of the original design for which they were written. Therefore, reusing a property in a different design or a new project variant often requires significant manual adjustments to adapt it to the new signal names, hierarchical paths, and timing relationships. This manual adjustment is error-prone and wastes valuable development time. Not only does this delay the project flow, but it also carries the risk of subtle verification gaps if properties are mismapped.

[0008] Another challenge lies in the heterogeneity of formal verification tools and processes. Different teams within the same organization may use different EDA toolchains, each with its own syntax, semantics, and integration procedures for formal properties. This heterogeneity makes property reuse difficult, as a property written for one tool often cannot be directly applied to another without syntax changes or tool-specific wrapper scripts. Even where cross-tool property migration is possible, differences in supported functions, solution capabilities, and proof strategies can lead to inconsistencies in verification results. This reduces confidence in the consistency and completeness of verification coverage across projects.

[0009] Furthermore, regulated industries have a strict requirement for traceability between high-level functional or safety requirements and the verification artifacts. In current formal verification processes, this traceability is often established manually using spreadsheets or requirements management tools that are only loosely integrated with the verification environment. This manual process is cumbersome, prone to human error, and difficult to keep up-to-date as designs and verification artifacts evolve over time. If a property is changed, renamed, or replaced, the corresponding traceability links must be manually updated, which is often neglected under time pressure. This results in outdated or incomplete traceability records that can jeopardize compliance audits and certification processes.

[0010] Another drawback of existing solutions is the lack of automated mechanisms for integrating properties into the DUV environment. Once a property is identified for use, engineers must manually write binding files or instantiation code to connect the property to the relevant signals in the design. This requires precise knowledge of the design's signal hierarchy and clocking, as well as careful handling of resets, releases, and other environmental constraints. Binding errors can result in properties being evaluated incorrectly or not at all, leading to inaccurate verification results. While some tools offer basic automation of property binding, their scope is often limited and fails with complex hierarchical designs, parameterized modules, or multiple asynchronous clock domains.

[0011] Scalability also presents a significant limitation in existing formal verification frameworks. In large projects with hundreds or thousands of properties, manually managing property integration, versioning, and traceability becomes a considerable burden. Without centralized management and automation, different teams may duplicate properties, use inconsistent versions, or apply outdated statements that no longer meet the intended requirements. This duplication not only wastes resources but can also mask verification deficiencies, as teams may believe they are covering a requirement when the applied property is incomplete or outdated.

[0012] In addition to organizational inefficiencies, the lack of performance optimization in property processing leads to technical bottlenecks. Current solutions rely on software-driven parsing, binding, and mapping of properties, which can be slow for large designs. Parsing and normalizing properties across different formats and languages, as well as adapting them to different tool environments, is computationally intensive. Purely software-based approaches can limit verification throughput, especially in design environments where fast turnaround times are required for continuous integration and regression verification.

[0013] Some commercial verification IP packages strive to develop reusable verification IPs in the form of assertion-based checkers. However, these are mostly monolithic and limited in their flexibility. For example, a protocol checker's IP is typically hard-coded to monitor specific sets of signals and cannot be easily adapted to a protocol variant or an internal user-defined extension. The inability to parameterize properties at a higher level of abstraction further limits their reusability. Even when parameterization is possible, its scope is often insufficient to handle complex modifications such as merging or splitting clock domains, restructuring data paths, or adjusting latency tolerances.

[0014] Several open-source initiatives have attempted to create portable property libraries. However, these efforts face challenges regarding adoption, maintenance, and industrial applicability. Open libraries may lack rigorous validation against industry-standard designs, and their integration into proprietary EDA workflows can be hampered by licensing restrictions or incompatibilities. As a result, companies either forgo their use entirely or invest significant resources in their internal adaptation and validation, thereby negating the intended cost and time benefits.

[0015] Another issue is the preservation of verification knowledge. In many organizations, the knowledge of why a property was written a certain way, how it relates to requirements, and what design assumptions it encodes is enshrined in the minds of individual verification engineers. When these engineers leave the project or the company, this knowledge is often lost, and future teams have to reverse engineer the intent of the properties or rewrite them from scratch. This leads to repeated effort and potential loss of verification coverage. A robust system for reusable formal verification IP must not only store the property itself but also preserve the associated metadata, justifications, and requirement links in a machine-readable, queryable format.

[0016] Formal verification has become an indispensable part of modern hardware design workflows. However, the infrastructure for reusing verification IP across projects, automating its integration into diverse design environments, and maintaining robust traceability to requirements remains underdeveloped. Existing solutions are hampered by tool heterogeneity, a lack of standardized property representations, reliance on manual customization and mapping processes, inadequate integration with requirements management systems, and the absence of dedicated hardware acceleration for property processing. These limitations combine to create inefficiencies, verification gaps, compliance risks, and missed opportunities for productivity gains in large, safety-critical hardware design projects.There is a clear technical need for a system that addresses these shortcomings by combining the management of reusable formal verification IPs with automated property integration and traceability mapping, and implementing it in a performance-optimized, hardware-supported architecture that works seamlessly in heterogeneous EDA environments. Summary of the invention

[0017] The present invention describes a machine-based system comprising a structured, reusable IP library for formal verification, stored in fast, non-volatile memory; an automated processing unit for property integration, implemented in a reconfigurable logic structure; and a traceability mapping engine implemented with dedicated processor cores. The system receives formal verification properties, assertions, and constraints in heterogeneous formats from multiple projects, normalizes them to a canonical intermediate property representation, and stores them in the library along with associated metadata such as applicable design hierarchies, signal mapping templates, and version histories.

[0018] When applied to a target design under verification (DUV), the system's automated property integration unit retrieves relevant properties, resolves name discrepancies using a hardware-based signal matching module, applies a clock domain adjustment via a clock mapping controller, and inserts the properties into the formal verification workspace of the DUV. Simultaneously, the traceability mapping engine compares each integrated property against its original functional requirement, updates the verification coverage matrix, and stores bidirectional mapping records in a relational mapping database.

[0019] The entire system is housed in a rack-mountable hardware device that features fast DDR5 memory, FPGA-based parsing accelerators, a multi-core CPU cluster for traceability calculations, and a dedicated interface controller for integration with industry-standard EDA tools via PCIe and Ethernet connections.

[0020] The main objective of the present invention is to provide a system and device that enable the creation, storage, and reuse of formal verification intellectual property in a standardized and portable format. This allows properties, assertions, and constraints to be applied across projects and in heterogeneous environments for electronic design automation without time-consuming manual rework. The invention also aims to integrate automated property integration that adapts verification properties to the specific signal hierarchy, clock domains, and tool-specific syntax of a target design. This eliminates the need for labor-intensive manual binding and reduces the likelihood of integration errors.

[0021] Another objective is to implement the entire solution in a hardware-based device that combines high-speed memory, reconfigurable logic accelerators, and dedicated processor cores to enable performance-optimized property parsing, normalization, and traceability mapping at scale. This physical instantiation allows deployment in high-performance verification environments, design verification farms, or integrated EDA hardware platforms, ensuring minimal latency and high throughput in property management workflows. Furthermore, the invention aims to preserve the verification knowledge embedded in the properties by storing not only the property definitions but also the associated metadata, design applicability, rationale, and version history in a queryable format.This ensures that organizational verification intelligence is maintained across design cycles and personnel changes. By achieving these goals, the invention provides a comprehensive, reusable, and auditable formal verification IP framework that streamlines verification workflows, improves cross-project reuse, ensures regulatory compliance, and significantly reduces verification time in the development of complex integrated circuits. BRIEF DESCRIPTION OF THE FIGURE

[0022] These and other features, aspects, and advantages of the present invention will be better understood if the following detailed description is read with reference to the accompanying drawing, in which the same symbols consistently represent the same parts. The following applies: Fig. Figure 1 shows a block diagram of a system for the reusable formal verification of an IP library with automated property integration and traceability mapping.

[0023] Experts will also recognize that the elements in the drawing are shown for the sake of simplicity and are not necessarily to scale. For example, the flowcharts illustrate the process by highlighting the main steps to enhance understanding of the aspects of this disclosure. Furthermore, with regard to the design of the device, one or more components of the device may be represented in the drawing by conventional symbols, and the drawing may show only the specific details relevant to understanding the embodiments of this disclosure, so as not to clutter the drawing with details that are readily apparent to those skilled in the art after reading this description. Detailed description of the invention

[0024] For a better understanding of the inventive principles, reference is made below to the embodiment shown in the drawing, which is described in specific terminology. However, this does not limit the scope of the invention. Changes and further modifications of the illustrated system, as well as further applications of the inventive principles, are possible, as would normally occur to a person skilled in the art in the field of invention.

[0025] It is clear to the person skilled in the art that the preceding general description and the following detailed description are exemplary and explanatory of the invention and are not intended as a limitation of it.

[0026] References in this specification to “an aspect”, “another aspect”, or similar expressions mean that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, occurrences of the expressions “in one embodiment”, “in another embodiment”, and similar expressions in this specification may all refer to the same embodiment, but need not.

[0027] The terms "includes," "include," or other variations thereof are intended to cover non-exclusive inclusion, so that a process or method that includes a list of steps may not only contain those steps but may also include other steps not expressly listed or inherent in such process or method. Likewise, the statement "includes..." in the case of one or more devices, subsystems, elements, structures, or components does not, without further limitations, preclude the existence of other devices, subsystems, elements, structures, components, or additional devices, subsystems, elements, structures, or components.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by a person skilled in the art in the field of the invention. The system, methods, and examples provided here serve only for illustration and are not to be construed as a limitation.

[0029] Embodiments of the present disclosure are described in detail below with reference to the attached drawing.

[0030] In Fig.Figure 1 shows a block diagram of a system for a reusable IP library for formal verification with automated property integration and traceability mapping. The system 100 comprises: a non-volatile storage subsystem (102) configured to store multiple formal verification properties in a canonical intermediate representation, each property associated with metadata including design applicability tags, signal binding templates, clock domain parameters, and request identifiers;an automated property integration processing unit (104) implemented in a reconfigurable logic structure and configured to retrieve one or more stored formal verification properties from the non-volatile memory subsystem, to perform syntax and semantic normalization to adapt the retrieved properties to a target design under verification (DUV), to resolve signal hierarchy differences by means of a signal name normalization module (104a) and to apply a clock domain adjustment via a clock allocation controller (104b);a traceability mapping engine (106) implemented on one or more dedicated processing cores and configured to manage bidirectional mapping records between functional or safety requirements and the associated formal verification properties, to dynamically update the mapping records when properties or verification results change, and to export compliance reports in an industry-standard requirements exchange format; and a high-speed connectivity and interface controller (108) configured to couple the automated property integration processing unit and the traceability mapping engine to external electronic design automation (EDA) tool environments via a communication interface that includes at least one PCIe and one Ethernet.

[0031] In one embodiment, the non-volatile storage subsystem (102) comprises a redundant array of non-volatile storage devices arranged in a parallel access configuration, and wherein a metadata indexing controller is configured to perform a multi-threaded retrieval of properties and associated metadata to enable concurrent property integration operations for multiple verification projects without read latency conflicts.

[0032] In one embodiment, the automated property integration processing unit (104) also includes a tool-specific formatting module configured to translate the normalized properties into a syntax compatible with a variety of heterogeneous formal verification tools, and wherein the formatting module can be dynamically reconfigured via hardware logic updates to support newly introduced EDA tool syntaxes without recompiling the entire engine firmware.

[0033] In one embodiment, the signal name normalization module (104a) of the automated property integration processing unit uses a pattern matching circuit implemented in the hardware description language (HDL) that compares canonical property signal identifiers with DUV-specific signal paths, performs fuzzy matching based on hierarchical proximity and naming conventions, and resolves mismatched signals through a hardware-based template substitution mechanism.

[0034] In one embodiment, the clock allocation controller (104b) of the automated property integration processing unit comprises multi-clock domain synchronization logic configured to detect clock enable conditions, reset signals, and phase relationships in the DUV and to adjust the property time semantics accordingly, ensuring that adapted properties maintain logical equivalence to their original canonical form across different clock architectures.

[0035] In one embodiment, the traceability mapping engine (106) also includes a graph database implemented in persistent storage. The graph database is optimized for storing and querying requirement-property relationships, verification coverage matrices, and evidence result histories, and is configured to support real-time traversal queries for compliance audits.

[0036] In one embodiment, the traceability mapping engine (106) is also configured to interface to an external requirements management system via a secure API bridge, automatically ingest functional and security requirement definitions, associate these definitions with one or more properties retrieved from the non-volatile storage subsystem, and update the external requirements management system with changes in the verification status triggered by the results of the proof execution.

[0037] In one embodiment, the high-speed interconnect and interface controller (108) is also configured to implement a Direct Memory Access (DMA) protocol between the automated property integration processing unit and the formal verification environment of the DUV, thereby enabling zero-copy property insertion into the tool workspace and reducing property loading times during large-scale verification runs.

[0038] In one embodiment, it is implemented as a rack-mountable hardware application and includes: a variety of hot-swappable FPGA accelerator modules implementing the automated processing unit for property integration; a multi-core CPU cluster implementing the traceability mapping engine; a high-speed DDR5 memory array for caching properties; and a management controller configured to monitor the thermal, power, and resource utilization of the modules and to perform the remote deployment of property libraries over secure, encrypted channels.

[0039] In one embodiment, the non-volatile storage subsystem (102) is further configured to store for each formal verification property an associated justification file containing human-readable documentation of the intended design coverage of the property, the justification of the requirement mapping, and the environment assumptions, wherein the justification file is indexed and retrievable together with the canonical property representation to preserve the verification knowledge across design cycles.

[0040] In the present disclosure, all subsystems and modules mentioned in the claims are implemented as hardware-based components integrated into the physical enclosure of the machine. The AI ​​processing subsystem comprises tangible computer hardware, including one or more general-purpose central processing units (GPUs), hardware AI accelerators such as GPUs, TPUs, or ASIC-based inference engines, and non-volatile memory for model storage. The multimodal data acquisition interface includes dedicated hardware parsers, sensor-coupled OCR units, and physical interface controllers for the structured and unstructured acquisition of health data. The compliance reasoning processor is implemented as a processor board that houses a hardware-based triple-store database engine with a semantic query coprocessor.The secure hardware enclave is a physically isolated security chip or processor area embedded on the motherboard, containing cryptographic processors, secure key storage elements, and tamper-proof circuitry. The audit trail reconstruction unit is implemented using a hardware-based version control engine coupled with a blockchain node processor board for ledger commitment. The interaction console consists of physical display panels, a hardware microphone array, and an integrated audio signal processor. The network and interoperability module includes physical communication controllers, transceivers, and protocol-specific hardware accelerators.

[0041] The system of the present invention is implemented as a hardware-based device configured for managing reusable intellectual property for formal verification, automated integration of properties into various design environments, and maintaining traceability between requirements and verification artifacts. The architecture combines fast, non-volatile memory, reconfigurable logic for property processing, and a dedicated processing cluster for traceability calculations. All components are interconnected via a low-latency, high-bandwidth interface controller, enabling seamless coupling with external electronic design automation (EDA) tools.The physical form factor of the system is that of a rack-mountable device, enabling its use in verification farms or as part of a larger design verification infrastructure.

[0042] The automated Property Integration Processing Unit (APIE) is implemented in an FPGA framework and uses reconfigurable hardware logic to perform computationally intensive property parsing, normalization, and binding operations. When a property is retrieved from the library, the APIE first calls the Signal Name Normalization Unit (SNN-U), which implements a hardware-based pattern matching algorithm that enables both exact and fuzzy matches. This algorithm works by calculating hierarchical path similarity values ​​between canonical property signal identifiers and target signal names in the Design Under Verification (DUV), taking into account factors such as lexical similarity, prefix / suffix matches, and design hierarchy depth. If no direct match can be found, the SNN-U consults the stored parameterized binding templates to perform a template substitution.In this process, mismatched identifiers are replaced by equivalent signal references derived from the module and port definitions of the DUV.

[0043] Once the signal bindings are resolved, the property is passed to the Clock Domain Adapter Unit (CDA-U), which checks the property's timing semantics as well as the clock and reset architecture of the DUV. The CDA-U contains synchronization detection logic that analyzes the DUV's structural netlist to identify relevant clock gating signals, asynchronous resets, and activation conditions. Using this information, the CDA-U adjusts the property's timing qualifiers to ensure that the modified property retains its intended logical behavior when applied to a different clock scheme. For example, a property originally bound to a single synchronous clock domain can be adapted to function correctly in a multi-clock domain environment by introducing cross-domain synchronization constraints or by replicating the property with modified clock bindings.

[0044] After adaptation, the property is processed by the Tool-Specific Formatter (TSF) module within the APIE, which translates the canonical property representation into the syntax and semantics of the selected formal verification tool. This translation process is dynamically reconfigurable: The TSF is implemented using reprogrammable logic tables that can be updated via secure channels to support new or revised EDA tool syntaxes without requiring a complete firmware rebuild of the FPGA. In one embodiment, the APIE can operate in batch mode, processing multiple properties concurrently. The engine's Dependency Resolution Unit sequences the integration to accommodate dependencies between properties, for example, by ensuring that auxiliary definitions are inserted before dependent properties.

[0045] The modified and formatted properties are then introduced into the DUV's formal verification environment via the High-Speed ​​Interconnect and Interface Controller (HSI-IC). This controller supports PCIe Gen5 and high-speed Ethernet connectivity and implements Direct Memory Access (DMA) operations to transfer property files to the verification tool's workspace without intermediate copies. This reduces loading times during large verification runs. In certain configurations, the HSI-IC supports zero-copy streaming, allowing properties to be fed directly into the proof engine during live verification sessions.

[0046] In parallel with the integration process, the Traceability Mapping Engine (TME) operates on a multicore CPU cluster with persistent memory optimized for graph databases. The TME maintains a bidirectional mapping between each formal verification property and the functional or security requirements it is designed to verify. During property integration, the TME retrieves the associated requirement identifiers from the property's metadata and links them to the verification session context. Once verification results are generated, the TME dynamically updates the verification status of each requirement and stores coverage metrics, pass / fail status, and any additional diagnostic data. This continuous update function ensures that the traceability records remain synchronized with the actual verification status of the project.

[0047] The graph database underlying the TME enables efficient traversal queries during compliance audits. This allows auditors to quickly retrieve all properties of a specific requirement or, conversely, identify all requirements verified by a particular property. The system supports compliance reporting in industry-standard requirement exchange formats such as ReqIF, XML, or JSON and can digitally sign these reports to ensure authenticity and integrity. Furthermore, the TME features a secure API bridge that provides a direct interface to external requirements management tools such as IBM DOORS or Jama Connect. This bridge allows requirement definitions to be automatically imported into the system and verification status updates to be sent back to the requirements management system without manual intervention.

[0048] The system also includes mechanisms for safeguarding verification knowledge across design cycles. Each stored property can be linked to a rationale file—a readable documentation artifact that details the property's intent, the applicable design constraints, and any underlying assumptions. This rationale is indexed along with the property and its metadata, allowing future teams to retrieve both the property and its original verification context. This safeguard ensures that the purpose and rationale of each property remain accessible even during personnel changes or project evolution.

[0049] In a typical workflow, when starting a new verification project, the verification engineer queries the Formal Verification IP Library Module for properties relevant to the project's design metadata. The requested properties, along with their metadata, are retrieved in parallel from the non-volatile memory subsystem and transferred to the APIE. The APIE normalizes signal names, adjusts clock domains, and translates the properties into the syntax of the formal verification tool. The HSI IC then inserts the adjusted properties directly into the verification environment. The TME establishes traceability links to requirements, monitors proof execution, and updates the coverage records in real time. Upon completion of the verification cycle, the system can generate a comprehensive, bidirectional compliance report, which is signed and ready for submission to certification authorities.

[0050] By combining high-speed property retrieval, hardware-accelerated adaptation, dynamic tool syntax translation, real-time traceability, and secure integration with external requirements management systems, the invention provides a unified platform for reusable formal verification IP that operates efficiently in heterogeneous EDA environments. The hardware-based implementation not only accelerates computationally intensive property processing tasks but also ensures deterministic performance in large-scale deployments. This makes it particularly suitable for continuous integration verification workflows in safety-critical and high-security semiconductor development.

[0051] The invention comprises a physical device that integrates hardware and software subsystems to provide reusable formal verification of IP management with automated integration and traceability mapping.

[0052] The drawing and the preceding description show examples of embodiments. Those skilled in the art will recognize that one or more of the described elements can be combined to form a single functional element. Alternatively, certain elements can be divided into several functional elements. Elements of one embodiment can be added to another embodiment. For example, the sequence of the processes described here can be changed and is not limited to the manner described here. Furthermore, the actions of a flowchart need not be implemented in the sequence shown; nor does it necessarily have to be performed by all actions. Actions that are not dependent on other actions can also be performed in parallel with the other actions. The scope of the embodiments is in no way limited by these specific examples.Numerous variations are possible, whether explicitly stated in the specification or not, such as differences in structure, dimensions, and material use. The range of embodiments is at least as broad as specified in the following claims.

[0053] Advantages, further benefits, and problem solutions have been described above with reference to specific embodiments. However, the advantages, benefits, problem solutions, and all components that can lead to an advantage, benefit, or solution occurring or becoming more apparent are not to be construed as critical, necessary, or essential features or components of individual or all claims. REFERENCES 100 A system for a reusable IP library for formal verification with automated property integration and traceability mapping. 102 Non-volatile storage subsystem 104 Automated Property Integration Processing Unit 104a Module 104b Clock mapping controller 106 Traceability Mapping Engine 108 High-speed connection and interface controllers

Claims

[1] A system for reusable formal verification of intellectual property (IP) with automated ownership integration and traceability attribution, consisting of: a non-volatile storage subsystem configured to store a variety of formal verification properties in a canonical intermediate representation, each property associated with metadata including design applicability tags, signal binding templates, clock domain parameters, and request identifiers; an automated processing unit for property integration, configured to retrieve one or more stored formal verification properties from the non-volatile memory subsystem, perform syntax and semantic normalization to adapt the retrieved properties to a target design under verification (DUV), resolve signal hierarchy differences through a signal name normalization module, and apply clock domain matching via a clock mapping controller; a traceability mapping engine implemented on one or more dedicated processing cores and configured to manage bidirectional mapping records between functional or safety requirements and their associated formal verification properties, dynamically update these mapping records when properties or verification results change, and export compliance reports in an industry-standard requirements exchange format; and a high-speed connection and interface controller configured to connect the automated property integration processing unit and traceability mapping engine to external electronic design automation (EDA) tool environments via a communication interface that includes at least one of the PCIe and Ethernet interfaces. [2] System according to claim 1, wherein the non-volatile storage subsystem comprises a redundant array of non-volatile storage devices arranged in a parallel access configuration, and wherein a metadata indexing controller is configured to perform a multi-threaded retrieval of properties and associated metadata to enable concurrent property integration operations for multiple verification projects without read latency conflicts. [3] System according to claim 1, wherein the automated processing unit for property integration further comprises a tool-specific formatting module configured to translate the normalized properties into a syntax compatible with a variety of heterogeneous formal verification tools, and wherein the formatting module is dynamically reconfigurable via hardware logic updates to support newly introduced EDA tool syntaxes without recompiling the entire engine firmware. [4] System according to claim 1, wherein the signal name normalization module of the automated property integration processing unit uses a pattern matching circuit implemented in the hardware description language (HDL) that compares canonical property signal identifiers with DUV-specific signal paths, performs fuzzy matching based on hierarchical proximity and naming conventions, and resolves mismatched signals by means of a hardware-based template substitution mechanism. [5] System according to claim 1, wherein the clock allocation controller of the automated property integration processing unit comprises multi-clock domain synchronization logic configured to detect clock enable conditions, reset signals and phase relationships in the DUV and to adjust the property time semantics accordingly, thereby ensuring that adapted properties maintain logical equivalence to their original canonical form across different clock architectures. [6] System according to claim 1, wherein the traceability mapping engine further comprises a graph database implemented in a persistent storage medium, wherein the graph database is optimized for storing and querying request-property relationships, verification coverage matrices and evidence result histories and is configured to support real-time traversal queries for compliance audits. [7] System according to claim 1, wherein the traceability mapping engine is further configured to establish an interface to an external requirements management system via a secure API bridge, automatically ingest functional and security requirement definitions, associate these definitions with one or more properties retrieved from the non-volatile storage subsystem, and update the external requirements management system with changes in the verification status triggered by the results of the proof execution. [8] System according to claim 1, wherein the high-speed connection and interface controller is further configured to implement a Direct Memory Access (DMA) protocol between the automated property integration processing unit and the formal verification environment of the DUV, thereby enabling zero-copy property insertion into the tool workspace and reducing property loading times during large-scale verification runs. [9] System according to claim 1, implemented as a rack-mountable hardware device, comprising: a variety of hot-swappable FPGA accelerator modules that implement the automated processing unit for property integration; a multi-core CPU cluster that implements the traceability mapping engine; a high-speed DDRS storage array for caching properties; and a management controller configured to monitor the heat, energy and resource usage of the modules and to perform the remote deployment of property libraries via secure, encrypted channels. [10] System according to claim 1, wherein the non-volatile storage subsystem is further configured to store for each formal verification property an associated justification file containing human-readable documentation of the intended design coverage of the property, the justification of the requirement mapping and the environment assumptions, wherein the justification file is indexed and retrievable together with the canonical property representation to preserve the verification knowledge across design cycles.

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