AI-accelerated computing card for edge computing

Abstract

AI-accelerated computing card for edge computing, characterized by the fact that it includes the following: an AI-accelerated computing card chip located at the network edge, wherein the AI-accelerated computing card chip is encapsulated in a protective housing, wherein the chip of the AI-accelerated computing card comprises a reference voltage source SVG integrated on a mainboard, a first line switch LineSwitch1 of a transconductance amplifier circuit TCA, a comparator COMP of the transconductance amplifier circuit TCA, a register REG of a sense amplifier circuit SAC, a second line switch LineSwitch2 of the sense amplifier circuit SAC, a third line switch LineSwitch3 of the sense amplifier circuit SAC, multipliers MUX1, MUX3 of the sense amplifier circuit SAC and a counter CNT.

Description

Technical field

[0001] The present utility model relates to the technical field of accelerated computing cards, in particular to an AI-accelerated computing card for edge computing. Background technology

[0002] AI-accelerated computing cards for edge computing are hardware acceleration modules specifically designed to perform AI inference tasks at the network edge (device-side or near the device). Typically available as PCIe cards, M.2 modules, chip modules, or integrated on motherboards, they are designed to deliver efficient, low-latency, and power-efficient AI computing performance in resource-constrained edge environments. These accelerator cards significantly enhance AI processing capabilities on edge devices through dedicated hardware architectures—such as tensor cores, sparse computing, and support for low-precision quantization—thus driving the expansion of AI applications from the cloud to the edge.

[0003] To protect the mainboard of the AI-accelerated computing card for edge computing, it must be housed in a protective enclosure. This enclosure also serves as the primary component for cable bundling and routing. The glands inside the enclosure must each be securely fastened with a leadscrew and an insulated platform. During assembly, each leadscrew must be tightened individually, making the process complex and inefficient. Furthermore, using tools such as wrenches in the confined space proves extremely impractical, significantly increasing the time and labor required by the assembly personnel. Content of the invention

[0004] To solve the aforementioned problems, this utility model provides an AI-accelerated computing card for edge computing. This effectively circumvents the disadvantages of existing technologies, where the lead screws of the stuffing boxes inside the protective housing containing the mainboard of the AI-accelerated computing card for edge computing must be tightened individually during assembly, making the process complex and inefficient. Furthermore, the use of tools such as wrenches in the confined space proves extremely impractical, significantly increasing the time and labor required by assembly personnel.

[0005] To overcome the shortcomings of the prior art, the present utility model provides a solution for an AI-accelerated computing card for edge computing, which looks like this: An AI-accelerated computing card for edge computing, comprehensive: an AI-accelerated computing card chip located at the network edge, wherein the AI-accelerated computing card chip is encapsulated in a protective housing, wherein the chip of the AI-accelerated computing card comprises a reference voltage source SVG integrated on a mainboard, a first line switch LineSwitch1 of a transconductance amplifier circuit TCA, a comparator COMP of the transconductance amplifier circuit TCA, a register REG of a sense amplifier circuit SAC, a second line switch LineSwitch2 of the sense amplifier circuit SAC, a third line switch LineSwitch3 of the sense amplifier circuit SAC, multipliers MUX1, MUX3 of the sense amplifier circuit SAC and a counter CNT.

[0006] Preferably, the reference voltage source SVG is used as the reference voltage source for the switches and the comparator, which controls the switching on and off of the circuit or provides a comparison threshold. where the first line switch, LineSwitchl, which is connected to the reference voltage source SVG, serves to implement the gating / switching of multiple signal paths, while in the context of AI acceleration it selects different computing units / data channels to adapt them to different computing tasks, wherein the comparator COMP connected to the first line switch LineSwitch1 compares the bit line signal with the reference voltage of the reference voltage source SVG and converts the analog signal output by a storage and computing unit into a digital level.

[0007] Preferably, both the register REG and the second line switch LineSwitch2 are connected to the comparator COMP, wherein the register REG serves for the temporary storage of digital signals, for data buffering and for synchronizing the timing, and the second line switch LineSwitch2 serves for the implementation of gating / switching of multiple signal paths. where the register REG is also connected to the second line switch LineSwitch2, while both the second line switch LineSwitch2 and the third line switch LineSwitch3 are connected to the multipliers MUX1 and MUX3, where the third line switch LineSwitch3 is used to implement the gating / switching of multiple signal paths, while the multipliers MUX1 and MUX3 are used to select a signal from multiple inputs for output.

[0008] Preferably, the third line switch LineSwitch3 is connected to the counter CNT, which is used for counting clock / event signals, for timing control, for calculating cycle statistics or for recording cumulative count values ​​during AI acceleration.

[0009] Preferably, the protective housing comprises a platform, a stuffing box, a locking block and a cover block.

[0010] Preferably the platform comprises a hollow chamber for mounting the stuffing box and further a line connection connected to the hollow chamber, wherein several barbs are integrally connected to the side walls of the hollow chamber.

[0011] Preferably, the barb comprises an inclined guide wall and a step, each arranged on its two vertical sides, wherein the step rests against the upper wall of the stuffing box after the stuffing box has been mounted on the platform.

[0012] Preferably, the platform comprises a pair of opposing side walls, each with a plug and a socket on its outer surface.

[0013] Preferably, a leadscrew is attached to the stuffing box.

[0014] Preferably, the locking block is detachably mounted on the platform and arranged near the line connection, the locking block serving to shield the line connection, wherein a boundary section is provided between the locking block and the platform, the boundary section comprising a boundary opening formed on one side of the locking block and the platform and a boundary plate formed on the opposite side that fits the boundary opening.

[0015] Preferably, the cover block and the platform are fastened via a clamping screw, the clamping screw being provided with a through-hole for the wire passage, while a locking section is arranged between the cover block and the platform, the locking section comprising locking holes formed at two pairs of oppositely arranged corner points of the platform, and further comprising locking plates formed on the cover block and fitting the locking holes, the inner surface of the locking plate being provided with a rib.

[0016] The advantageous effects of the present utility model are as follows: 1. The protective housing of this utility model, with its plug and socket, enables a simple and secure connection of multiple protective housings in a horizontal orientation. This meets the requirements for bundling varying numbers of cables and increases operational flexibility. The combination of a wedge-shaped groove and a wedge-shaped element provides a larger contact area and a positioning function, ensuring that the assembled structure remains robust and resistant to disassembly after connection. 2. The protective housing of the present utility model, through the combination of locking holes and insert blocks, enables the pre-positioning and initial stabilization of the cover block before tightening the leadscrew, thereby facilitating assembly. Description of the drawings Fig. Figure 1 is a schematic representation of the structure of the chip of the AI-accelerated computing card for the AI-accelerated computing card for edge computing of the present utility model; Fig. Figure 2 schematically shows the installation of the platform, the stuffing box and the locking block of the AI-accelerated computing card for edge computing of the present utility model; Fig. Figure 3 is a partially three-dimensional schematic representation of point X in Fig. 2; Fig. Figure 4 is a schematic exploded view of the platform, stuffing box and locking block of the chip of the AI-accelerated computing card for the AI-accelerated computing card for edge computing of the present utility model; Fig. Figure 5 is a schematic representation of the floor plan of the platform of the present utility model; Fig. Figure 6 is a three-dimensional schematic representation of the cover block of the present utility model from one angle; Fig. Figure 7 is a three-dimensional schematic representation of the cover block of the present utility model from a different perspective. Detailed descriptions

[0017] The present utility model will now be described in more detail with reference to the attached drawings and embodiments.

[0018] As in the Fig. 1 to Fig. Figure 7 shows an AI-accelerated computing card for edge computing according to the present utility model, comprising the following: a chip of the AI-accelerated computing card, which is located at the network edge (device-side or near the device), wherein the chip of the AI-accelerated computing card is encapsulated in a protective housing.

[0019] As in Fig. Figure 1 shows that the chip of the AI-accelerated computing card comprises a reference voltage source SVG integrated on a mainboard, a first line switch LineSwitch1 of a transconductance amplifier circuit TCA, a comparator COMP of the transconductance amplifier circuit TCA, a register REG of a sense amplifier circuit SAC, a second line switch LineSwitch2 of the sense amplifier circuit SAC, a third line switch LineSwitch3 of the sense amplifier circuit SAC, multipliers MUX1, MUX3 of the sense amplifier circuit SAC and a counter CNT.

[0020] In a preferred, but not limiting, embodiment of the present utility model, the reference voltage source SVG is used as the reference voltage source for the switches and the comparator, which controls the switching on and off of the circuit or provides a comparison threshold. where the first line switch, LineSwitchl, which is connected to the reference voltage source SVG, serves to implement the gating / switching of multiple signal paths, while in the context of AI acceleration it dynamically selects different computing units / data channels to adapt them to different computing tasks (such as matrix multiplication, activation, etc.), wherein the comparator COMP connected to the first line switch LineSwitch1 compares the bit line signal BL_S or BLB_S with the reference voltage (SV) of the reference voltage source SVG and converts the weak analog signal output by a storage and computing unit into a digital level (which is used for quantizing / deciding analog computation results during AI acceleration).

[0021] In a preferred, but not limiting, embodiment of the present utility model, both the register REG and the second line switch LineSwitch2 are connected to the comparator COMP, wherein the register REG serves for the temporary storage of digital signals (such as comparator outputs or counter results), for data buffering, for timing synchronization, and for ensuring the temporal consistency of the data during the AI ​​calculation processes, and the second line switch LineSwitch2 serves to implement the gating / switching of multiple signal paths. where the register REG is also connected to the second line switch LineSwitch2, while both the second line switch LineSwitch2 and the third line switch LineSwitch3 are connected to the multipliers MUX1 and MUX3, where the third line switch LineSwitch3 is used to implement the gating / switching of multiple signal paths, while the multipliers MUX1 and MUX3 are used to select a signal from multiple inputs for output, thus enabling flexible assignment of data paths during AI acceleration (e.g., selection of different processing cores or different input characteristics).

[0022] In a preferred, but not limiting, embodiment of the present utility model, the third line switch LineSwitch3 is connected to the counter CNT, which is used for counting clock / event signals, for timing control, for calculating cycle statistics, or for recording cumulative count values ​​during AI acceleration (such as feature map accumulation operations within neural networks).

[0023] The sense amplifier circuit (SAC) amplifies the weak analog signals on the bit lines (outputs from the memory and processing unit), thus improving the signal-to-noise ratio. It serves as a core module for reading data within the memory and processing architecture (and ensures the efficient readout of analog computational results during AI acceleration). The transconductance amplifier circuit (TCA) converts input voltage signals into output current signals with adjustable gain. During AI acceleration, it performs signal conditioning for analog calculations and controls current-based computations (corresponding to the current-based operations of the memory and processing unit).

[0024] In a preferred, but not limiting, embodiment of the present utility model, the protective housing comprises a platform 2, a stuffing box 3, a locking block 8 and a cover block 24.

[0025] In a preferred, but not limiting, embodiment of the present utility model and as described in the Fig. 2 and Fig. As shown in Figure 4, the platform 2 comprises a hollow chamber for mounting the stuffing box 3 and a line connection 4 connected to the hollow chamber, with several barbs 5 being integrally connected to the side walls of the hollow chamber.

[0026] In a preferred, but not limiting, embodiment of the present utility model and as described in the Fig. As shown in Figure 3, the barb 5 comprises an inclined guide wall 6 and a step 7, each arranged on its two vertical sides, with the step 7 bearing against the upper wall of the stuffing box 3 after the stuffing box 3 has been mounted on the platform 2.

[0027] In a preferred, but not limiting, embodiment of the present utility model and as described in the Fig. As shown in Figure 5, the platform 2 comprises a pair of opposing side walls 21, the outer surfaces of which are each provided with a plug 22 and a socket 23. When a pair of adjacent protective housings is connected, the plug 22 of one protective housing engages with the socket 23 of the other protective housing. In the context of the present application, the socket 23 is a wedge-shaped groove and the plug 22 is a wedge-shaped element that fits the wedge-shaped groove. The socket 23 and the plug 22 can also be triangular-prismatic, cylindrical, rectangular, or in other shapes.

[0028] In a preferred, but not limiting, embodiment of the present utility model, a leadscrew 30 is attached to the stuffing box 3. The line connection 4 can not only have a cylindrical shape, but can also be rectangular, prismatic, or other shapes.

[0029] In a preferred, but not limiting, embodiment of the present utility model and as described in the Fig. Figure 2 shows the locking block 8 detachably mounted on the platform 2 and arranged near the line connection 4. The locking block 8 serves to shield the line connection 4. A boundary section is provided between the locking block 8 and the platform 2. This boundary section comprises a boundary opening 9 formed on one side of the locking block 8 and the platform 2, and a boundary plate 10 formed on the opposite side, which fits the boundary opening 9. In the present application, both the input and output connections of the platform 2 are each equipped with the locking block 8.

[0030] In a preferred, but not limiting, embodiment of the present utility model and as described in the Fig. 2, Fig. 6 and Fig. Figure 7 shows the cover block 24 and the platform 2 fastened via a clamping screw 25, the clamping screw 25 being provided with a through-opening 26 for the wire passage, while a locking section is arranged between the cover block 24 and the platform 2, wherein, as shown in the Fig. 5 and Fig. Figure 6 shows the locking section comprising locking holes 27 formed at two pairs of opposite corner points of the platform 2 and further comprising locking plates 28 formed on the cover block 24 and fitting the locking holes 27, the inner surface of the locking plate 28 being provided with a rib 29.

[0031] The protective housing of the present utility model is inserted directly into the hollow chamber via barbs and the stuffing box 3. Guided by the inclined guide wall 6, it is plastically deformed before snapping into place at the designated position below the step 7. This enables efficient assembly, as no additional components such as leadscrews, nuts, etc., are required, thereby reducing the complexity of the housing and the cost of manufacturing the components.

[0032] The advantageous effects of the present utility model are as follows: 1. The protective housing of this utility model, with its plug and socket, enables a simple and secure connection of multiple protective housings in a horizontal orientation. This meets the requirements for bundling varying numbers of cables and increases operational flexibility. The combination of a wedge-shaped groove and a wedge-shaped element provides a larger contact area and a positioning function, ensuring that the assembled structure remains robust and resistant to disassembly after connection. 2. The protective housing of the present utility model, through the combination of locking holes and insert blocks, enables the pre-positioning and initial stabilization of the cover block before tightening the leadscrew, thereby facilitating assembly.

[0033] The present utility model has been described with reference to illustrative embodiments. Those skilled in the art will recognize that the disclosure is not limited to the embodiments described above. Various modifications, changes, and substitutions can be made without altering the scope of the present utility model.

[0034] An AI-accelerated computing card for edge computing, belonging to the technical field of accelerated computing cards, comprising: an AI-accelerated computing card chip located at the network edge, wherein the AI-accelerated computing card chip is encapsulated in a protective housing, a platform comprising a hollow chamber for mounting a gland and further comprising a line connector connected to the hollow chamber, with several barbs integrally connected to the side walls of the hollow chamber. The barb comprises an inclined guide wall and a step, each arranged on its two vertical sides, the step bearing against the upper wall of the gland after the gland is mounted to the platform.This effectively circumvents the disadvantages of existing technologies, where the lead screws of the stuffing boxes inside the protective housing containing the mainboard of the AI-accelerated edge computing card must be tightened individually during assembly, making the process complex and inefficient. Furthermore, the use of tools such as wrenches in the confined space proves extremely impractical, significantly increasing the time and labor required by the assembly personnel.

Claims

[1] AI-accelerated computing card for edge computing, characterized by that it includes the following: an AI-accelerated computing card chip located at the network edge, wherein the AI-accelerated computing card chip is encapsulated in a protective housing, wherein the chip of the AI-accelerated computing card comprises a reference voltage source SVG integrated on a mainboard, a first line switch LineSwitch1 of a transconductance amplifier circuit TCA, a comparator COMP of the transconductance amplifier circuit TCA, a register REG of a sense amplifier circuit SAC, a second line switch LineSwitch2 of the sense amplifier circuit SAC, a third line switch LineSwitch3 of the sense amplifier circuit SAC, multipliers MUX1, MUX3 of the sense amplifier circuit SAC and a counter CNT. [2] AI-accelerated computing card for edge computing according to claim 1, characterized by, that the reference voltage source SVG is used as the reference voltage source for the switches and the comparator, which controls the switching on and off of the circuit or provides a comparison threshold, where the first line switch, LineSwitchl, which is connected to the reference voltage source SVG, serves to implement the gating / switching of multiple signal paths, while in the context of AI acceleration it selects different computing units / data channels to adapt them to different computing tasks, wherein the comparator COMP connected to the first line switch LineSwitch1 compares the bit line signal with the reference voltage of the reference voltage source SVG and converts the analog signal output by a storage and computing unit into a digital level. [3] AI-accelerated computing card for edge computing according to claim 2, characterized by, that both the register REG and the second line switch LineSwitch2 are connected to the comparator COMP, the register REG being used for temporary storage of digital signals, data buffering and timing synchronization, and the second line switch LineSwitch2 being used for gating / switching multiple signal paths, where the register REG is also connected to the second line switch LineSwitch2, while both the second line switch LineSwitch2 and the third line switch LineSwitch3 are connected to the multipliers MUX1 and MUX3, where the third line switch LineSwitch3 is used to implement the gating / switching of multiple signal paths, while the multipliers MUX1 and MUX3 are used to select a signal from multiple inputs for output. where the third line switch LineSwitch3 is connected to the counter CNT, which is used for counting clock / event signals, for timing control, for calculating cycle statistics, or for recording cumulative count values ​​during AI acceleration. [4] AI-accelerated computing card for edge computing according to claim 3, characterized by that the protective housing includes a platform, a stuffing box, a locking block and a cover block. [5] AI-accelerated computing card for edge computing according to claim 4, characterized by that the platform comprises a hollow chamber for mounting the stuffing box and further a conduit connection connected to the hollow chamber, wherein several barbs are integrally connected to the side walls of the hollow chamber. [6] AI-accelerated computing card for edge computing according to claim 5, characterized by, that the barb comprises an inclined guide wall and a step, each arranged on its two vertical sides, the step being located against the upper wall of the stuffing box after the stuffing box has been mounted on the platform. [7] AI-accelerated computing card for edge computing according to claim 6, characterized by that the platform comprises a pair of opposing side walls, each with a plug and a socket on its outer surface. [8] AI-accelerated computing card for edge computing according to claim 7, characterized by that a leadscrew is attached to the stuffing box. [9] AI-accelerated computing card for edge computing according to claim 8, characterized by, that the locking block is detachably mounted on the platform and arranged near the line connection, wherein the locking block serves to shield the line connection, wherein a limiting section is provided between the locking block and the platform, the limiting section comprising a limiting opening formed on one side of the locking block and the platform and a limiting plate formed on the opposite side which fits the limiting opening. [10] AI-accelerated computing card for edge computing according to claim 9, characterized by, that the cover block and the platform are fastened via a clamping screw, the clamping screw being provided with a through-hole for the wire passage, while a locking section is arranged between the cover block and the platform, the locking section comprising locking holes formed at two pairs of opposite corner points of the platform, and further comprising locking plates formed on the cover block and fitting the locking holes, the inner surface of the locking plate being provided with a rib.

Images