CIRCUIT FOR MONITORING A DATA PROCESSING SYSTEM

Description

AREA

[0001] The present invention relates to a circuit for monitoring a data processing system. In particular, the present invention relates to resetting a data processing unit of the system from any fault state to a defined operating state. BACKGROUND

[0002] In devices controlled by microcontrollers, an external "watchdog" is often used for program execution monitoring. This watchdog triggers a control signal (reset signal) if an application within the controller is no longer executing correctly. This control signal allows both the microcontroller and the device it controls to be reset.

[0003] For this purpose, an external "watchdog" is often connected to a port pin of the microcontroller and triggered by the application within the controller at a defined time interval (i.e., addressed via a signal). If the time interval deviates from the defined interval, the "watchdog" can then infer an improper execution of the application and reset the microcontroller and the device controlled by the microcontroller to a defined operating state (which, for example, corresponds to the state of the microcontroller immediately after it is switched on). For example, US 2007 / 240019 A1 describes a procedure for reactivating a stuck I2C bus. A monitor monitors the I2C bus data and clock lines and detects whether the bus is stuck. To do this, the monitor measures the packet transactions on the bus to determine whether a maximum transaction time has elapsed while the lines are in a stuck state.To reactivate a stuck bus, individual slave devices and bus masters can then be selectively reset via the monitor.

[0004] EP2458503 discloses a system comprising: a first data processing unit and a second data processing unit, wherein the first data processing unit has a first communication interface and the second data processing unit has a second communication interface, and the first communication interface and the second communication interface are connected by means of a signal line; and a monitoring unit which is connected to the signal line by means of a monitoring line. In a further embodiment, EP2458503 shows that the regularity of the occurrence of data transmission phases is monitored and, in the event of a deviation, the reset signal is triggered. SUMMARY

[0005] The present invention is based on the objective of improving the state of the art.

[0006] A system according to the invention comprises a first data processing unit and a second data processing unit, wherein the first data processing unit has a first communication interface and the second data processing unit has a second communication interface, and the first communication interface and the second communication interface are connected by means of a signal line, and a monitoring unit which is configured and provided for resetting the first data processing unit and / or the second data processing unit to a defined operating state by means of a reset signal, wherein the monitoring unit is connected to the signal line by means of a monitoring line and is further configured and provided for monitoring a signal transmitted from the first communication interface to the second communication interface via the signal line.which signals a data transmission phase between the first communication interface and the second communication interface by means of a predetermined voltage level of the signal, to monitor the regularity of the occurrence of data transmission phases and to trigger the reset signal in case of a deviation.

[0007] For the purposes of this description and the claims, the term "data processing unit" shall be understood to mean, in particular, an electronic device that processes digitally encoded data (according to a predetermined scheme), i.e., converts input data into output data or determines output data from input data. Furthermore, for the purposes of this description and the claims, the term "communication interface" shall be understood to mean, in particular, an interface (e.g., a connector) that enables the exchange of digitally encoded data between electronic devices. Finally, for the purposes of this description and the claims, the term "signal line" shall be understood to mean, in particular, a wired, current-conducting line through which electrical signals can be exchanged between electronic devices.Furthermore, the term "data transmission phase" within the scope of the present description and the claims shall in particular be understood to mean a continuous period of time, limited by a beginning and an end, during which data is exchanged between electronic devices.

[0008] Preferably, the first data processing unit comprises a microcontroller and the second data processing unit comprises a shift register.

[0009] For the purposes of this description and the claims, the term "microcontroller" shall be understood to mean, in particular, a semiconductor chip comprising a processor. Furthermore, for the purposes of this description and the claims, the term "shift register" shall be understood to mean, in particular, serially connected memory elements whose memory contents can be shifted from one memory element to the next in a single operating cycle.

[0010] Preferably, the first communication interface comprises a first synchronous serial interface and the second communication interface comprises a second synchronous serial interface.

[0011] For the purposes of this description and the claims, the term "synchronous serial interface" shall be understood to mean in particular an interface which is designed to establish a connection between two electronic devices, wherein a first signal line is supplied with a transmission clock signal and a second signal line is supplied with a data signal synchronized with the transmission clock signal.

[0012] Preferably, the first communication interface has a first Serial Peripheral Interface (SPI), and the second communication interface has a second SPI, and the monitored signal is a load signal of the first SPI.

[0013] Preferably, the signal line has a first and a second section whose potential is decoupled from each other by a potential separation, wherein the first section is connected to the first communication interface and the second section is connected to the second communication interface.

[0014] Preferably, the system further comprises a third data processing unit, wherein the third data processing unit has a third communication interface and the first communication interface and the third communication interface are connected by means of a second signal line, wherein the monitoring unit is further configured and provided to reset the third data processing unit from any error state to a defined operating state by means of a second reset signal, wherein the monitoring unit is connected to the second signal line by means of a second monitoring line and is further configured and provided to receive a second signal transmitted from the first communication interface to the third communication interface via the second signal line.which signals a data transmission phase between the first communication interface and the third communication interface by means of a predetermined voltage level of the second signal, to monitor the regularity of the occurrence of transmission phases and to trigger the second reset signal in case of a deviation.

[0015] A method according to the invention comprises monitoring a signal transmitted from a first communication interface of a first data processing unit via a signal line to a second communication interface of a second data processing unit, which signals data transmission phases between the first communication interface and the second communication interface by means of a predetermined voltage level, for regularity of the occurrence of data transmission phases and triggering a reset signal, which resets the first data processing unit and / or the second data processing unit to a defined operating state, in case of a deviation from regularity.

[0016] Preferably, the first data processing unit comprises a microcontroller and the second data processing unit comprises a shift register.

[0017] Preferably, the first communication interface has a first Serial Peripheral Interface (SPI), and the second communication interface has a second SPI, and the monitored signal is a load signal of the first SPI.

[0018] Preferably, the method further comprises receiving measurement data by the first data processing unit, generating control data based on the received measurement data by the first data processing unit, signaling a first data transmission phase between the first communication interface and the second communication interface by means of the predetermined voltage level of the signal, and transmitting the control data from the first communication interface to the second communication interface during the first data transmission phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The invention is explained below in detail by means of exemplary embodiments, with reference to drawings in which: Fig. 1 a first preferred embodiment of the system according to the invention; Fig. 2 a second preferred embodiment of the system according to the invention; Fig. 3 a third preferred embodiment of the system according to the invention; Fig. 4 a fourth preferred embodiment of the system according to the invention; and Fig. 5 It shows a flowchart of a process for monitoring a data processing unit.

[0020] In the drawings, identical elements are indicated by identical reference symbols, and similar elements are indicated by reference symbols supplemented with a Latin reference symbol. DETAILED DESCRIPTION

[0021] Fig. 1 Figure 100 shows a system comprising a first data processing unit 200 (master) and a second data processing unit 300 (slave). The first data processing unit 200 includes a first Serial Peripheral Interface (SPI) communication interface 210, and the second data processing unit 300 includes a second SPI communication interface 310. The first SPI communication interface 210 and the second SPI communication interface 310 are interconnected by means of signal lines 400a-400d. It should be noted, however, that the invention is not limited to two data processing units 200 and 300 connected by an SPI bus or to a specific number of signal lines 400, but can also be implemented using other synchronous serial interfaces or, more generally, interfaces that signal data transmission phases via a signal line 400b-400d.

[0022] As in Fig. 1 As shown, the four signal lines 400a-400d comprise a signal line 400a for transmitting a clock signal (Serial Clock, SCLK), a signal line 400b for transmitting data from the first data processing unit 200 to the second data processing unit 300 (Master Output Slave Input, MOSI), a signal line 400c for transmitting data from the second data processing unit 300 to the first data processing unit 200 (Master Input Slave Output, MISO), and a signal line 400d for transmitting a signal (LOAD) which signals a data transmission phase between the first communication interface 200 and the second communication interface 300 (e.g., by a predetermined voltage level of the signal line 400d).

[0023] Although Fig. 1 If only a first data processing unit 200 and a second data processing unit 300 are shown, it is understood that the system 100, as in Fig. 2 As shown, the system can include further data processing units 300a (slaves) whose communication interfaces 310a are also connected to signal lines 400a, 400b, and 400c, and which have a separate signal line 400e for transmitting a signal that indicates a data transmission phase between the first communication interface 210 and the communication interface 310a of the respective further data processing unit 300a. In this case, the signals indicating data transmission phases between the first communication interface 210 and the communication interface 310a of the respective further data processing unit 300a can be uniquely assigned to the respective further data processing unit 300a, whereas signals transmitted via signal lines 400a-400c (without further indications) do not allow for a unique assignment.

[0024] As in Fig. 1 und Fig. 2 As shown, system 100 also includes a monitoring unit 500, which is connected to the second data processing unit 300 via a signal line 510. The monitoring unit 500 is configured and designed to reset the second data processing unit 300 from an error state to a defined operating state by means of a reset signal (RESET) transmitted via signal line 510. For this purpose, the monitoring unit 500 monitors the signals (LOAD) transmitted via signal line 400d.

[0025] Monitoring the signals transmitted via signal line 400d (LOAD) allows, in the presence of the aforementioned additional data processing units 300a, which are also connected to signal lines 400a-400c, targeted monitoring of the communication between the first data processing unit 200 and the second data processing unit 300, and a selective reset of the second data processing unit 300 based on this monitoring. However, monitoring only the signals transmitted via signal line 400b and / or signal line 400c (MOSI and / or MISO) would, without further evidence, only allow the reset of the second data processing unit 300 connected to the first data processing unit 200 and the additional data processing units 300a and 400c.of the entire system 100 (including the first data processing unit 200), since monitoring the signals transmitted via signal line 400b and / or signal line 400c (MOSI and / or MISO) alone would not reveal, without further evidence, whether the communication between the first data processing unit 200 and the second data processing unit 300, or between the first data processing unit 200 and one of the further data processing units 300a, is disrupted or has failed in the event of a disturbance or (partial) failure of communication.

[0026] To detect a fault condition, the monitoring unit 500 is connected to the signal line 400d via a monitoring line and is further configured and designed to monitor the signal (LOAD) transmitted from the first communication interface 210 via the signal line 400d to the second communication interface 310, which signals a data transmission phase between the first communication interface 210 and the second communication interface 310, for regularity in the occurrence of data transmission phases and, in the event of a deviation, to conclude that a fault condition exists. If a fault condition is assumed to exist, the second data processing unit 300 can then be reset from the fault condition to a defined operating state by means of the reset signal.

[0027] A deviation from the regularity of data transmission phases can occur, for example, when a lower and / or upper limit regarding the number of data transmission phases in a specific time period or within a predetermined number of operating cycles of the first data processing unit 200 is exceeded or fallen below. Furthermore, a deviation from the regularity of data transmission phases can occur when there is a (significant) variation in the number of data transmission phases in a specific time period or within a predetermined number of operating cycles of the first data processing unit 200.

[0028] Furthermore, a deviation from the regularity of data transmission phases can occur if the duration of a pause between data transmission phases falls below or exceeds a lower and / or upper limit, or varies (significantly). Moreover, the above conditions can be combined, so that, for example, a deviation from the regularity of data transmission phases is considered to exist if several conditions are met simultaneously, within a predetermined time period, or within a predetermined number of work cycles of the first data processing unit 200.

[0029] Furthermore, it is understood that the monitoring unit 500 can be connected to the first data processing unit 200 via the signal line 520 and can be configured and designed to reset the first data processing unit 200 from an error state to a defined operating state by means of a reset signal (RESET). For example, the signal line 520 can be connected to the signal line 510 so that both the first data processing unit 200 and the second data processing unit 300 can be reset to the defined operating state by the reset signal (RESET).

[0030] The signal line 520 can also be a separate signal line 520 and the monitoring unit 500 can also be configured to, in the event of a deviation from the regularity of the occurrence of data transmission phases, first reset only the second data processing unit 300 to the defined operating state by means of the reset signal and only in the event of a recurrence of an error condition, e.g. within a specified time period or within a specified number of data transmission phases, reset the first data processing unit 200 and the second data processing unit 300 to the defined operating state.

[0031] Furthermore, as in Fig. 3 As shown, a potential isolation 600 is provided between the first SPI communication interface 210 and the second SPI communication interface 310. Depending on whether the first data processing unit 200 or the second data processing unit 300 is being monitored, the monitoring line can then be located between the first data processing unit 200 and the potential isolation 600, or, as shown in Fig. 3 As shown, the signal line 400d is connected between the galvanic isolation 600 and the second data processing unit 300. This avoids the need to add a separate galvanic isolation to the monitoring line or the signal line 510.

[0032] As in Fig. 4 As shown, the second data processing unit 300 can comprise an output shift register 320 and an input shift register 330. The output shift register 320 is connected to signal line 400b and the input shift register 330 to signal line 400c. This means that during the data transmission phase, data is written from the first data processing unit 200 to the output shift register 320 and read from the input shift register 330. Resetting the second data processing unit 300 to its defined operating state can then, for example, involve clearing the contents of the output shift register 320.

[0033] In particular, the first data processing unit 200 can read measurement data from the input shift register 330 during a data transmission phase and generate control data based on the read measurement data. The control data can then be written to the output shift register 320 during the data transmission phase or a subsequent data transmission phase.

[0034] Fig. 5Figure 1 shows a flowchart of a process for monitoring the first data processing unit 200. At step 700, the process begins monitoring signal line 400d for the regularity of data transmission phases. If a deviation from this regularity is detected, the first data processing unit 200 and / or the second data processing unit 300 are reset to a defined operating state at step 800. The type of fault is irrelevant. Rather, it is sufficient to assume any fault condition that can be resolved by resetting the first data processing unit 200 and / or the second data processing unit 300. REFERENCE MARK LIST

[0035] 100, 100a System 200 Data processing unit 210 Communication interface 300 Data processing unit 310 Communication interface 320 Output shift register 330 Input shift register 400 Signal line 500 Monitoring unit 510, 510a Signal line 520 Signal line 600 Potential isolation 700, 800 Process steps

Claims

1. A system (100, 100a), comprising: a first data processing unit (200) and a second data processing unit (300), wherein the first data processing unit (200) comprises a first communication interface (210) and the second data processing unit (300) comprises a second communication interface (310), and the first communication interface (210) and the second communication interface (310) are connected by a signal line (400d); and a monitoring unit, which is configured and provided to reset the first data processing unit (200) and / or the second data processing unit (300) to a defined operating state via a reset signal; wherein the monitoring unit (500) is connected to the signal line (400d) by a monitoring line; and the monitoring unit (500) is further configured and provided to monitor a signal transmitted from the first communication interface (210) via the signal line (400d) to the second communication interface (310), the signal signaling a data transmission phase between the first communication interface (210) and the second communication interface (310) through a predetermined voltage level of the signal, for a regularity of an occurrence of data transmission phases and to trigger the reset signal in case of a deviation.

2. The system (100, 100a) of claim 1, wherein the first data processing unit (200) comprises a microcontroller and the second data processing unit (300) comprises a shift register (320, 330).

3. The system (100, 100a) of claim 1 or 2, wherein the first communication interface (210) comprises a first Synchronous Serial Interface and the second communication interface (310) comprises a second Synchronous Serial Interface.

4. The system (100, 100a) of any one of claims 1 to 3, wherein the first communication interface (210) comprises a first Serial Peripheral Interface, SPI, and the second communication interface (310) comprises a second SPI, and the monitored signal is a load signal of the first SPI.

5. The system (100, 100a) of any one of claims 1 to 4, wherein the signal line (400) comprises a first and a second section, the potential of which is decoupled from each other by a potential separation (600), wherein the first section is connected to the first communication interface (210) and the second section is connected to the second communication interface (310).

6. The system (100, 100a) of any one of claims 1 to 5, further comprising: a third data processing unit (300a), wherein the third data processing unit (300a) comprises a third communication interface (310a) and the first communication interface (210) and the third communication interface (310a) are connected by a second signal line (400e), wherein the monitoring unit (500) is further configured and provided to reset the third data processing unit (300a) to a defined operating state via a second reset signal, wherein the monitoring unit (500) is connected to the second signal line (400e) by a second monitoring line and is further configured and provided to monitor a second signal transmitted from the first communication interface (210) via the second signal line (400e) to the third communication interface (310a), the second signal signaling a data transmission phase between the first communication interface (210) and the third communication interface (310a) by a predetermined voltage level of the second signal, for a regularity in an occurrence of data transmission phases and to trigger the second reset signal in case of a deviation.

7. A method for monitoring a first data processing unit (200), comprising: monitoring (700) a signal transmitted from a first communication interface (210) of the first data processing unit (200) via a signal line (400d) to a second communication interface (310) of a second data processing unit (300), the signal signaling data transmission phases between the first communication interface (210) and the second communication interface (310) by a predetermined voltage level, for a regularity of an occurrence of data transmission phases; and triggering (800) a reset signal which resets the first data processing unit (200) and / or the second data processing unit (300) to a defined operating state, in the event of a deviation from the regularity.

8. The method of claim 7, wherein the first data processing unit (200) comprises a microcontroller and the second data processing unit (300) comprises a shift register (320, 330).

9. The method of claim 7 or 8, wherein the first communication interface (210) comprises a first Serial Peripheral Interface, SPI, and the second communication interface (310) comprises a second SPI, and the monitored signal is a load signal of the first SPI.

10. The method of any one of claims 7 to 9, further comprising: receiving measurement data by the first data processing unit (200); generating control data based on the received measurement data by the first data processing unit (200); signaling a first data transmission phase between the first communication interface (210) and the second communication interface (310) by the predetermined voltage level of the signal; and transferring the control data from the first communication interface (210) to the second communication interface (310) during the first data transmission phase.