MULTI-CORE PROCESSOR AND METHOD FOR DYNAMIC ADJUSTMENT OF A SUPPLY VOLTAGE AND A CLOCK FREQUENCY

Description

[0001] The invention relates to a multi-core processor for dynamically adjusting a supply voltage and a clock frequency, which has a plurality of processor elements, wherein in each processor element at least one processor core, an internal memory, a switching network and a level converter are arranged in a voltage-variable area.

[0002] The invention also relates to a method for dynamically setting a supply voltage and a clock frequency, in which, in a multi-core processor having a plurality of processor elements, a setting of a required supply voltage U and a required clock frequency f is made for each processor element for each cycle of processing a number of events by a processor core of the processor element.

[0003] So-called event-based simulations are well known, for example, for computer applications in the field of so-called neuromorphic computer systems, in which a simulation of spiking neural networks is carried out. Technical applications in which event-based simulations play a role include image processing, audio and video processing, mobile robotics (e.g., navigation), or data classification. For such simulations, appropriate, program-controlled processors are used to process the data.

[0004] As in many other areas of technology, it is desirable in such simulations to reduce power dissipation for these applications and thus, for example, to maximize the data throughput and computing capacity of these systems given the available resources. System-limiting resources can include, for example, a power supply with limited performance or a limited battery life. Constraints can also arise from a cooling system, which is limited by its passive or active cooling capacity.

[0005] A multi-core processor, used for event-based simulations, for example, typically consists of a number of processor elements, each with a processor core, interconnected. Such a connection can be established, for example, via a connection network such as a bus system or a network-on-chip.

[0006] An alternative is the use of so-called multi-processor or multi-processor systems, whereby the multi-core processors belonging to a multi-processor system in turn have at least two processor elements with respective processor cores for processing data.

[0007] To save energy in such systems, a state-of-the-art approach is known, for example, to dynamically scale the supply voltage and clock frequency of one or more processor cores. This dynamic scaling is also referred to as "Dynamic Voltage and Frequency Scaling," abbreviated to DVFS.

[0008] With such dynamic scaling, the supply voltage and / or clock frequency of at least one processor core is increased whenever the computing power requirement increases. This operating mode requires a lot of energy per task or cycle.

[0009] If the computing power requirement decreases or is low, the supply voltage and / or clock frequency of a processor core is reduced. In this operating mode, less energy is required per task or cycle.

[0010] For the purpose of dynamic scaling, pairs or value pairs consisting of a specific supply voltage or a supply voltage level and an associated clock frequency are usually formed, which are also referred to as Performance Level PL.

[0011] The required computing power per processor core can vary, for example, depending on the input signal of an event-based simulation, in which, for example, input signals from the neural network or video data are to be processed, and therefore cannot generally be predicted. The input signals of the neural network or the video data represent the events to be processed by one or more processor cores in such a simulation.

[0012] Since the requirements of one or more processor cores cannot be predicted with such input signals, it is also not possible to use state-of-the-art approaches in which a central controller such as a central power management controller or a task scheduler determines the supply voltage and / or the clock frequency of the processor cores.

[0013] Therefore, there is a need to decide individually for each processor core what supply voltage it should operate at. Likewise, there is a need to decide individually for each processor core what clock frequency it should operate at. Both decisions depend on the current number of events being processed, or to be processed, i.e., on the current load on a processor core.

[0014] In multi-core processors, a specific number n of different supply voltages are provided in a so-called supply voltage network. Thus, several supply voltages with different levels, such as U 1 = 0.7 volts, U 2 = 0.85 volts, or U 3 = 1.0 volt, are available for each processor element and thus for each processor core.

[0015] From these provided supply voltages, each processor core can be assigned a supply voltage at which it should currently operate. Such a selection or assignment of a supply voltage to a specific core is described, for example, in S. Höppner, C. Shao, H. Eisenreich, G. Ellguth, M. Ander, R. Schüffny, "A Power Management Architecture for Fast Per-Core DVFS in Heterogeneous MPSoCs," IEEE International Symposium on Circuits and Systems, 2012, pp. 261-264.

[0016] When assigning a supply voltage, however, it is important to note that the supply voltage lines for the multi-core processor are subject to a limitation regarding their maximum permissible current. This limitation is caused by the maximum output current of the voltage regulator and an IR drop on the supply voltage lines on the chip itself. IR drop refers to the unwanted, static and / or dynamic reduction of the local supply voltage at the logic cells of the digital circuit, caused by the voltage drop across the ohmic resistors of the supply voltage network. This voltage drop is caused by the current flow itself.

[0017] Thus, for example, a suitable control method must be used to ensure that the supply voltage lines are not overloaded by the individual connections of individual processor cores to the available supply voltages U 1 or U 2 or U 3. The three supply voltages specified here are intended as examples and not as a limitation of the number of supply voltages.

[0018] According to the current state of the art, systems with multi-core processors or multi-processor systems for event-based simulations are currently implemented without power management. An example of such a system can be found in E. Painkras, LA Plana, J. Garside, S. Temple, F. Galluppi, C. Patterson, DR Lester, AD Brown, and SB Furber, "Spinnaker: A 1-w 18-core system-on-chip for massively-parallel neural network simulation," IEEE Journal of Solid-State Circuits, vol. 48, no. 8, pp. 1943-1953, Aug 2013.

[0019] According to the state of the art, multi-core processors for mobile communications applications, for example, have a central control unit, such as a core manager or a task scheduler, whereby this central control unit can distribute tasks among different processing cores, also referred to as processing elements. However, this requires a priori knowledge of the required computing load and processing times in order to set the performance level (PL), i.e., the supply voltage and / or frequency for a processing core. In this context, methods, for example, for a performance estimation based on the algorithm or source code, are known from US Pat. Nos. 7,685,446 B2 and 8,671,413 B2.

[0020] The term computing load or processor load refers to the processes currently running or waiting for certain events on a computer system, i.e. generally the current utilization of, for example, a multi-core processor.

[0021] Methods are also known in which a central event queue in the system-on-chip is used to determine the voltage and / or frequency levels of individual processor cores. An example of such a solution is described in US Pat. No. 8639862 B2, entitled "System-on-chip queue status power management."

[0022] DE 102009019824 A1 discloses a method in which the processor load is determined based on the number of events occurring within a time interval, and a corresponding supply voltage and clock frequency are set. This setting is performed by a central controller.

[0023] DE 10 2005 047619 A1 discloses a data processing system and a method for controlling a data processing system. The problem to be solved is to create an efficient way to reduce the energy consumption of embedded systems with a plurality of processing nodes.

[0024] To achieve this, a data processing arrangement comprising a plurality of processing elements is provided, in which each processing element is assigned a data memory, and each processing element is configured to process the data stored in the data memory assigned to it or to store the results of the data processing performed by the processing element in the data memory. Each processing element is further assigned a fill level unit configured to generate a fill level signal, by means of which information about the amount of data stored in the data memory assigned to the processing element is signaled.Furthermore, each processing element is assigned a control unit which is configured to control the processing power of the processing element based on the fill level signal generated by the fill level unit assigned to the processing element.

[0025] It is also known from the state of the art that processors can change the supply voltage based on their current computing load by reprogramming external voltage regulators.

[0026] The dimensioning of the supply voltage lines for multi-core processors is usually done for a maximum current per line, which occurs when all processor elements operate with their processor cores connected to one of these lines.

[0027] The disadvantages of this known state of the art are that if dynamic scaling of the supply voltage and the clock frequency of one or more processor cores is omitted, high power dissipation occurs in the case of low activity of the connected network or the simulation being performed.

[0028] When centrally dynamically scaling or adjusting the supply voltage and clock frequency of one or more processor cores, it is necessary to know the processes and the computing load of individual processor cores.

[0029] However, in event-based simulations, these processes and the computational load depend significantly on dynamically changing network activities and input signals during operation. Therefore, it is not possible to determine them in advance.

[0030] The object of the invention is to provide a multi-core processor and a method for dynamically setting a supply voltage and a clock frequency, which enables an individual setting of a supply voltage and a clock frequency for each processor core of a multi-core processor, depending on a current computing load.

[0031] It should also be ensured that none of the supply voltage lines used to provide different supply voltages for the processor cores of a multi-core processor are overloaded.

[0032] The problem is solved by a multi-core processor having the features according to claim 1 of the independent claims. Further developments are specified in the dependent claims 2 to 4.

[0033] The problem is also solved by a method having the features according to claim 5 of the independent patent claims. Further developments are specified in the dependent patent claims 6 to 10.

[0034] The invention provides that each processor core has a local clock generator. Furthermore, a switching network is provided for connecting the processor core to one of several available supply voltage lines, on which, for example, the voltages U 1 = 0.7 volts, U 2 = 0.85 volts, and U 3 = 1.0 volts are provided by means of a voltage supply unit.

[0035] It is also planned that each processor core will have a power management controller (PMC), which is also referred to as an internal supply voltage frequency control arrangement. This internal supply voltage frequency control arrangement controls the switching network and the clock generator in the processor element and thus sets the currently required supply voltage U 1 , or U 2 or U 3 as well as the currently required clock frequency f 1 or f 2 or f 3 for the associated processor core depending on a currently determined computing load for the associated processor element. This makes it possible for each processor core to be individually adapted to current requirements, i.e. to a changing number of events to be processed in a specific cycle or time window.

[0036] It is provided that the internal supply voltage frequency control arrangement is controlled by means of a control signal and thus adjusts the switching network and the clock generator in the processor element accordingly. This control signal is generated by the processor core itself and transmitted to the internal supply voltage frequency control arrangement. In an unclaimed example to facilitate understanding of the invention, it can be provided that the internal supply voltage frequency control arrangement is also controlled by means of a control signal generated outside the processor element, which is transmitted, for example, via a corresponding bus system such as a network-on-chip to the internal supply voltage frequency control arrangement. This control signal thus sets the performance level, i.e., the supply voltage level and the clock frequency, for the processor core.

[0037] To generate this control signal using the processor core itself, events received, for example, via a network-on-chip, are written to a local queue memory. Based on the fill level of the local queue memory, i.e., the number of events to be processed, the current computing load is determined at specified times. Generally, a small number of received and therefore processed events means a low computing load for the processor core, while a very large number of events to be processed represents a high computing load. This is especially true because the processing of events must usually be carried out within a specified time window, i.e., a cycle, in order to enable real-time processing of the events.

[0038] It is intended that the local queue memory is a memory arranged in the processor element, which is connected to the processor core, the internal memory of the processor element and to a level converter.

[0039] It is also planned that the local queue memory will be implemented via software using the processor core's data memory. Furthermore, it is planned that the local queue memory will be implemented by a hardware module that uses either the processor's data memory or a separate memory. This hardware module could be, for example, an external supply voltage frequency control device connected to the processor core via the network-on-chip bus system.

[0040] The current computing load is intended to be determined at specified times based on the fill level of the local queue memory. To regularly generate these times, a timer is implemented using software. Alternatively, these times can be generated using a timer implemented in hardware. It is also possible to use a global timer, also implemented in hardware, to generate these times. This global timer is connected to the processor core and the internal supply voltage frequency control system via the network-on-chip bus system for transmitting the times.

[0041] To implement switching of the supply voltage level and the clock frequency for the processor core based on a determined computing load, i.e., the fill level of the local queue memory, it is planned to use a table (look-up table) in which so-called limit or threshold values ​​for the fill level of the local queue memory for switching to a specific supply voltage or a specific clock frequency are stored. Such a table can be implemented in software, for example, stored in the processor element, or using a separate hardware module. In these cases, the determined fill level F of the local queue memory is an input variable for the table, from which the supply voltage U and the clock frequency f for the processor core can be read as output variables.

[0042] An alternative to implementing supply voltage and clock frequency switching for the processor core is to use a formula to calculate the supply voltage and clock frequency based on the current fill level F of the local queue memory. Such a formula can be implemented, for example, in software within the processor element or in a separate hardware module.

[0043] In an example of such a formula, three performance levels PL1, PL2, and PL3 can be provided, each representing three different combinations of a supply voltage U and a clock frequency f. For example, the performance level PL1 sets a supply voltage U1 and a clock frequency f1 for the processor core, enabling the processing of a small number of events with a low fill level F of the local queue memory.

[0044] With the performance level PL2, for example, a supply voltage U 2 and a clock frequency f 2 are set for the processor core, which enables processing of an average number of events with an average fill level F of the local queue memory.

[0045] With the performance level PL3, for example, a supply voltage U 3 and a clock frequency f 3 are set for the processor core, which enables the processing of a large number of events with a high fill level F of the local queue memory.

[0046] In one embodiment, a supply voltage U 1 of 0.7 volts at a clock frequency f 1 of 125 MHz can be specified for the performance level PL1, a supply voltage U 2 of 0.85 volts at a clock frequency f 2 of 333 MHz for the performance level PL2 and a supply voltage U 3 of 1.0 volts at a clock frequency f 3 of 500 MHz for the performance level PL3.

[0047] The general rule is U 1 < U 2 < U 3 and f 1 < f 2 < f 3 .

[0048] To determine the supply voltage U and clock frequency f for the processor core, the following formula is used: PL = PL 1 , wenn F < F th 1 PL = PL 2 , wenn F th 1 ≤ F < F th 2 PL = PL 3 , wenn F th 2 ≤ F

[0049] Where F th 1 a first threshold and F th 2 is a second threshold and the first threshold F th 1 less than the second threshold F th 2 is.

[0050] Since the current computing load is determined based on the fill level of the local queue memory at specified times for a so-called cycle of a specific length, the performance level PL is also switched at these specified times. Switching the performance level PL at these times can, for example, be a switch from PL 1 to PL 2 if the fill level F of the queue memory has increased in the current cycle compared to the previous cycle. Switching the performance level PL at these times can, for example, be a switch from PL 3 to PL 2 if the fill level F of the queue memory has decreased in the current cycle compared to the previous cycle.If the fill level F of the queue memory has not changed or has not changed significantly in the current cycle compared to the previous cycle, the performance level PL, which was PL 2, for example, remains at the same value and is therefore PL 2 again.

[0051] The fill level F and the first threshold F th 1 and the second threshold F th 2 can, for example, be percentage values. For example, a fill level F of 100 percent would correspond to the maximum number of events to be processed in a cycle. The first threshold F th 1 could be, for example, 25 or 33 percent and the second threshold F th 2 can be set at 66 or 75 percent, for example, whereby a specialist can determine a suitable allocation of the threshold values F th 1 and F th 2 adapted to current requirements.

[0052] For example, the current performance level can be reset after the number of events to be processed has been completely processed.

[0053] According to the invention, a switching from a set performance level to a lower performance level occurs after the events in the processor core have been processed and before the specified time at the end of the cycle is reached. This means that a reset of the supply voltage U and the clock frequency f set at time t occurs after the events to be processed by the processor core in the current cycle have been processed, with the reset occurring to a lower or the smallest provided supply voltage U 1 and the smallest provided frequency f 1 .

[0054] This early switching back of the performance level, i.e., setting a lower supply voltage U and a lower clock frequency f for the processor core, leads to additional energy savings and reduces heat generation in the processor core. This early switching back of the performance level can encompass one or more performance levels (PL). The switch can therefore occur to the next lower performance level, for example, from PL 2 to PL 1, or the next lower performance level, for example, from PL 3 to PL 1.

[0055] In a further embodiment of the invention, the connection of each processor core to one of the supply voltages U 1 or U 2 or U 3 is controlled by a central supply voltage network controller in order to prevent overloading of one of the supply voltage lines providing the voltages U 1 , U 2 and U 3 or of a unit generating the voltages. For this purpose, this central supply voltage network controller is connected to the processor cores and thus to the processors and the internal supply voltage frequency control arrangements in the processor cores via a bus system such as a network-on-chip.

[0056] This central supply voltage network control manages the resources of the supply voltage network and limits the maximum possible number of processors that can be connected to one of the supply voltage lines, i.e. to one of the voltages U 1 , U 2 and U 3 via the switching network.

[0057] This limitation can be implemented by the supply voltage network controller, for example, by a processor core requesting the supply voltage network controller using a token. If the switchover to a specific supply voltage line currently requested by the processor is confirmed by the supply voltage network controller, the processor's supply voltage is switched to the requested supply voltage via the processor core's switching network, controlled by the processor.

[0058] If the switchover to a specific supply voltage line currently requested by the processor is not authorized by the supply voltage network controller because the maximum number of connections to this supply voltage line has already been made by other processor cores, the supply voltage of this processor core will not be switched via the switching network. In this case, the processor can submit a new request to the supply voltage network controller and, for example, request a switchover to another supply voltage line with a lower supply voltage. Such authorization allocation is known from the prior art and will therefore not be discussed in further detail.

[0059] It is also provided that the central supply voltage network controller generates a control signal for the internal supply voltage frequency control arrangement, which, transmitted via the bus system, controls the internal supply voltage frequency control arrangement and thus selects a supply voltage and a frequency. Thus, the selection of a requested and approved performance level can be made without the processor.

[0060] The implementation of this central supply voltage network control is possible in both a software and a hardware solution.

[0061] Thus, the invention realizes a local determination of the voltage and frequency level of a processor core, based on the fill level of a queue memory, at defined time intervals determined by a timer for each cycle.

[0062] This enables autonomous switching of the processor core's own supply voltage and clock frequency, with the available resources being monitored by a central supply voltage network controller.

[0063] The above-explained features and advantages of this invention will be better understood and appreciated after careful study of the following detailed description of the preferred, non-limiting exemplary embodiments of the invention with the accompanying drawings, which show: Fig. 1: a block diagram of a processor with multiple processor elements, Fig. 2: a block diagram of a processor element with a dynamic setting of a supply voltage and a clock frequency, Fig. 3: a temporal representation of a sequence of an event-based simulation with a dynamic setting of a supply voltage and a clock frequency in a non-claimed example to facilitate understanding of the invention, Fig. 4: a temporal representation of a sequence of an event-based simulation with a dynamic setting of a supply voltage and a clock frequency in an embodiment of the invention, Fig. 5: a representation of a dynamic setting of a supply voltage and a clock frequency as a function of currently incoming events in a simulation and Fig. 6: a representation of three histograms with the respective number of cycles required per performance level.

[0064] The Figure 1 shows a block diagram of the multi-core processor 1 from the prior art, which has a number m of processor elements 2. Each of these processor elements 2 includes a processor core 3, an electronic memory 4, which can be, for example, a so-called SRAM (static random-access memory, SRAM), a local clock generator 5, an internal supply voltage frequency control arrangement 6 and a switching network 7. In the example of Figure 1 the processor elements 2a, 2b to 2m are shown, which have an identical structure.

[0065] The m processor elements 2a, 2b, ..., 2m can be connected to each other and to external units via a bus system 8, which can also be implemented as a network-on-chip, for transmitting data.

[0066] The bus system 8 can be connected, for example, to an external clock generator 9. Furthermore, an external supply voltage frequency control arrangement 10, a first interface 11 for connection to an external memory 12, or a second interface 13, for example, for connection to an external router, can be arranged on this bus system 8.

[0067] In the Figure 2 A block diagram of a processor element 2a with a dynamic adjustment of a supply voltage and a clock frequency according to the invention is shown. Each processor element 2a, 2b, ..., 2m includes a processor core 3, an electronic memory 4, a local clock generator 5, an internal supply voltage frequency control arrangement 6, and a switching network 7.

[0068] To implement the invention, each processor element 2 has a local queue memory 14, in which the events 24 to be processed by the processor core 3, which arise, for example, within an event-based simulation, are stored. This local queue memory 14 is implemented in a hardware solution in the example and is connected to the processor core 3, the internal memory 4, and a level converter 21 via corresponding data or bus lines.

[0069] For coupling the processor elements 2 to the bus system 8, a bus interface 15 is provided, as shown in the Figure 2 is shown.

[0070] The internal supply voltage frequency control arrangement 6 is connected by its control lines to the internal clock generator 5 and the switching network 7. Using suitable control signals, the internal supply voltage frequency control arrangement 6 controls the connection of a currently required supply voltage U 1 , or U 2 or U 3 to the processor core 3 via the switching network 7 and the generation of a clock frequency f 1 or f 2 or f 3 required in the current cycle via the internal clock generator 5. An adaptation unit 16 such as a look-up table can optionally be arranged between the internal supply voltage frequency control arrangement 6 and the internal clock generator 5.By means of such an adaptation unit 16, an adaptation can be carried out between the control signal output by the internal supply voltage frequency control arrangement 6 for selecting a frequency f to be currently set and the format or signal required by the internal clock generator 5 for providing the desired frequency f.

[0071] The supply voltages U 1 , U 2 and U 3 are provided by a voltage supply unit 17. Examples are shown in the Figure 2Three different voltages U 1 , U 2 , and U 3 are shown. A restriction to three possible voltages is not intended. The voltage supply lines, which form a supply voltage network 18, are connected to the inputs of the switching networks 7 of the processor elements 2a, 2b, ... 2m. It is provided that, by means of the control signal of the internal supply voltage frequency control arrangement 6, one of the provided supply voltages U 1 , or U 2 , or U 3 is switched through to the respective processor element 2a, 2b, ... 2m or the respective processor 3 by means of the switching networks 7.

[0072] The switching of a supply voltage U 1 , or U 2 , or U 3 to the respective processor core 3 also means switching this supply voltage to a so-called voltage-variable area 22 of the processor element 2. This voltage-variable area 22 includes not only the processor core 3 but also the internal memory 4 connected to the processor core 3 and the local queue memory 14, i.e., all components contained in the box represented by a solid line below the switching network 7.

[0073] A level converter 21 is provided to adjust a signal level between the modules in the voltage-variable range 22, which can be operated with one of the three provided voltages U 1 , or U 2 or U 3 , and the modules in the processor element 2 arranged outside the voltage-variable range 22 and operated with a constant supply voltage. This level converter 21, which is also referred to as a level converter or level shifter, ensures, for example, in the schematic diagram of the Figure 2 for adjusting the levels between the voltage variable area 22 and the internal clock generator 5 as well as the voltage variable area 22 and the bus interface 15.

[0074] To set a required supply voltage for the modules in the voltage-variable range 22 as well as a required clock frequency for the processor core 3, it is provided that the fill level of the local queue memory 14, i.e. the number of events 24 to be processed and thus the current computing load, is determined at specified times under the control of the processor 3. Depending on the fill level F of the local queue memory 14, the processor 3 determines, for example by means of a stored formula or a comparison with stored threshold values, a performance level to be set for the subsequent cycle of processing the events 24, as the required supply voltage U and the required frequency f.This information about the required performance level determined by the processor 3 is transmitted via the first transmission path 19 to the internal supply voltage frequency control arrangement 6, which controls the setting of the switching network 7 for selecting a supply voltage U 1 , or U 2 or U 3 and the frequency generator 5 for generating the frequency f 1 or f 2 or f 3 for the next cycle.

[0075] In a non-claimed example to facilitate understanding of the invention, it can be provided that the supply voltage frequency control arrangement 6 is controllable from outside the processor element 2 via a second transmission path 20 via the bus interface 15 and the bus system 8. This variant of an external control is provided for the case that the checking of the fill level F of the local queue memory 14 is carried out at specified times by means of an external supply voltage frequency control arrangement 10, which in the Figure 2 is not shown. A representation of the external supply voltage frequency control arrangement 10 connected to the bus system 8 can be found in the Figure 1 This alternative enables a form of control of the supply voltage and frequency for processor 3 that is known from the prior art.

[0076] In the Figure 3is a temporal representation of a sequence of an event-based simulation with a dynamic setting of a supply voltage and a clock frequency in a non-claimed example to facilitate the understanding of the invention.

[0077] In a temporal progression, several consecutive cycles 23 are shown on the abscissa, in each of which a current number of events 24 is to be processed by the processor core 3 of a processor element 2. The first cycle 23a is designated cycle k, the second cycle 23b cycle k+1, and the third cycle 23c cycle k+2. The cycles 23 have the same duration, which in the example of the Figure 3 with t sys = 1 ms is specified.

[0078] At the beginning of the processing of events 24, which occur, for example, in an event-based simulation, the highest performance level PL3 is set at time t = 0. This performance level PL3 is assigned the highest supply voltage U 3 and the highest clock frequency f 3 that can be generated by the internal clock generator 5. This enables the processing of a very large number of events 24 in the first cycle 23a.

[0079] During processing 25a of the Figure 3 events 24 not shown in the first cycle 23a, the local queue memory 14 is filled with the eight events 24 to be processed in the subsequent second cycle 23b, for example. The processor core 3 checks at a specified time t1 the fill level F of the local queue memory 14 and determines the performance level PL required for the subsequent second cycle 23b depending on this current fill level F. In the example, the performance level PL2 for the subsequent second cycle 23b was determined by the processor core 3, which at the time t 1 is set by means of the internal supply voltage-frequency control arrangement 6. Thus, for example, the voltage U 2 is selected as the supply voltage and an average clock frequency f 2 that can be generated by the internal clock generator 5 is selected as the frequency f, since the number of eight events 24 to be processed or the computing load is lower than in the first cycle 23a.

[0080] In the second cycle 23b, the eight events 24 are processed in the set performance level PL2, while at the same time the local queue memory 14 is filled with the four events 24 to be processed in the subsequent third cycle 23c. In the example, at the time t 2 for the subsequent third cycle 23c, the performance level PL1 is determined by the processor core 3, which at the time t 2 is set by means of the internal supply voltage frequency control arrangement 6. This performance level PL1, to which the smallest supply voltage U 1 and the smallest clock frequency f 1 that can be generated by the internal clock generator 5 are assigned, is sufficient for processing the number of four events 24 to be processed in the third cycle 23c, which number is further reduced compared to the previous second cycle 23b.

[0081] In this described procedure, the process is repeated in the third and subsequent cycles 23, which are Figure 3 are not shown, continued.

[0082] The Figure 4 shows a temporal representation of a sequence of an event-based simulation with a dynamic setting of a supply voltage and a clock frequency in an embodiment of the invention.

[0083] The process of dynamically setting a supply voltage and a clock frequency essentially corresponds to the explanations for Figure 3 , to which reference is hereby made. The difference in the execution in the Figure 4lies in the fact that a check of the processing of events 24 in each cycle 23 within the processing time 25a, 25b, 25c, ....etc. is carried out to determine whether the last event 24 to be processed has been processed by processor core 3. In the event that the last event 24 has been processed, the current performance level is switched to the lowest performance level, for example, PL1. In a special case in which processor element 2 or processor 3 is already operating at the lowest performance level PL1, the lowest performance level PL1 remains set.

[0084] In the example of Figure 4 is started at the beginning of the processing of events 24 at the time t 0 the performance level PL3 is set. If the last event 24 to be processed is processed in the processing 25a, the processing 25a is terminated and a reset 26 of the event at the time t0 is performed. Advantageously, the reset 26 is performed such that the lowest or smallest performance level, PL1 in the example, is set. This resetting of the performance level for the time remaining in the current cycle 23a achieves further energy savings and a further reduction in the heat generation of the processor cores 3.

[0085] At the time t1, according to the method already described above, the performance level currently determined by the processor core 3 based on the fill level of the local queue 14 is set, which in this example should be the performance level PL3. Subsequently, the processing 25b of the events 24 to be processed in the second cycle 23b begins in the usual way. After the processing of the last event 24, the processing 25b is terminated and the currently set performance level PL3 is reset 26 to the performance level PL1 in which the processor element 2 or the processor core 3 remains until the end of the second cycle 23b, until the time t 2 a currently determined performance level is set. The performance level at the time t The Performance Level PL3 set to 0 is used in the first cycle 23a for a duration of Δ t SP ( k ) is retained. The t1 set Performance Level PL3 is used in the second cycle 23b for a duration of Δ t SP ( k + 1) maintained as it is in the Figure 4 is shown.

[0086] In the Figure 5 a representation of a dynamic setting of a supply voltage and a clock frequency depending on currently occurring events 24 is shown in an example simulation.

[0087] The Figure 5 shows in an upper representation a temporal progression of the occurrence of events 24 to be processed in an event-based simulation. In the upper part of the Figure 5The occurrence of events 24 assigned an identification number (ID) is shown over time. For example, a more frequent occurrence of certain events 24 can be seen in a range of approximately 7 ms to 15 ms. A particularly strong occurrence of events 24 can be observed in a range of approximately 49 ms to 50 ms. At this time, almost all of the 250 possible events occur simultaneously.

[0088] By means of a dot-dot line in the lower part of the Figure 5 The number of received events is shown as 24. The solid line represents the currently set performance level PL for a processor element 2, which can be switched between the performance levels PL1, PL2 and PL3. The selection and switching of the performance level PL takes place according to an already set Figure 3 or Figure 4 explained procedure.

[0089] It can be seen that the current performance level PL depends on the number of events 24 to be processed. For example, with a large number of approximately 150 events 24 to be processed, processor core 3 activates performance level PL3 in a range of approximately 49 ms to 50 ms. For example, with a medium number of approximately 65 events 24 to be processed, performance level PL2 is sufficient in the range after approximately 7 ms to 15 ms to reliably process all pending events 24 within the time available in a cycle 23. This reliable processing of events 24 within a cycle 23 ensures real-time processing of the events 24 occurring during a simulation.

[0090] In the Figure 6 A representation of three histograms with the respective number of cycles required for each Performance Level PL is shown. In the lowest representation of the Figure 6It can be seen that in a performed and analyzed event-based simulation, 89.0 percent of all cycles 23 were processed with a set performance level of PL1. The most frequently occurring duration Δ t SP , which was required to process all events 24 that occurred within one cycle 23, is 0.4 ms.

[0091] In the middle representation of the Figure 6 It can be seen that in this event-based simulation, 9.7 percent of all cycles 23 were processed with a set performance level of PL2. The most frequently occurring duration Δ t SP , which was required to process all events 24 that occurred within a cycle 23, is 0.3 ms in Performance Level PL2.

[0092] In the top view of the Figure 6It can be seen that in this event-based simulation, 1.3 percent of all cycles 23 were processed with a set performance level of PL2. The most frequently occurring duration Δ t SP , which was required to process all events 24 that occurred within a cycle 23, is 0.6 ms in Performance Level PL3.

[0093] A possible application example of an event-based simulation described here could be an application with a camera and an evaluation of the current camera image. For this purpose, the camera's detection area can be divided into several subareas, each of these subareas being assigned to a processor element 2 or a processor core 3 for processing the events 24 occurring in the respective subarea. For example, if a multi-core processor 1 with four processor elements 2 is available, a division into four subareas can be made. In the case of a multi-core processor 1 with eight processor elements 2, a division into eight subareas can be made, and so on.

[0094] Since the occurrence of events 24, which can be a change in a parameter such as the illuminance of a pixel of the camera, is unpredictable and of varying intensity in the various sub-areas, the method presented is used for the dynamic setting of a supply voltage and a clock frequency, i.e. a performance level PL , by the respective processor core 3 of the respective processor element 2 depending on the number of its events 24 to be processed for the individual control of each individual processor element 2.

[0095] Although event-based simulations are described as examples in this description, the application of the invention is not limited to this form alone.

[0096] Generally, the method is applicable when the computational load of a processor element 2 cannot be globally predicted, but rather arises dynamically during system operation based on input data. This input data does not necessarily have to represent events in a temporal sense. For example, the method is also conceivable for classifying large amounts of data (databases), where the event then refers, for example, to the occurrence of a specific pattern in the data sets to be processed, which can lead to additional computational steps.

[0097] This also applies, for example, to the classification of image data using deep learning methods, i.e., the application of neural networks. Here, the event represents the transmission of a weighted synaptic signal from one neuronal layer of the network to another, even if there is no explicit temporal reference.

[0098] In typical applications of the invention in multiprocessor systems in modern CMOS technologies, such as 28nm CMOS or 22nm CMOS, typical supply voltage values ​​are in the range of 0.40V to 1.00V and clock frequencies of the processor are in the range of 50 MHz to 2 GHz.

[0099] Some of the specific advantages of dynamically adjusting a supply voltage and a clock frequency are listed below: Executing event processing in event-based simulations in the processor element, such as a processor core, with the minimum required supply voltage and / or clock frequency. This significantly reduces power dissipation. It is used for event-based simulations in which the computing load of individual processor cores is unpredictable because it depends on the input signals (events). It prevents overloading of the supply voltage networks during system operation. LIST OF REFERENCE SYMBOLS

[0100] 1 Multi-core processor 2, 2a, 2b, ..., 2m Processor element 3 Processor core 4 Internal memory (e.g. SRAM) 5 Internal clock generator 6 Internal supply voltage frequency control arrangement 7 Switching network 8 Bus system (e.g. implemented as network-on-chip) 9 External clock generator 10 External supply voltage frequency control arrangement 11 First interface 12 External memory 13 Second interface 14 Local queue memory 15 Bus interface 16 Matching unit (look-up table) 17 Power supply unit 18 Power supply network 19 First transmission path 20 Second transmission path 21 Level converter 22 Voltage variable range 23, 23a, 23b, 23c Cycle 24 Event 25, 25a, 25b, 25cProcessing event 26Resetting the set performance level PL

Claims

1. A multi-core processor (1) for dynamically setting a supply voltage and a clock frequency which has several processor elements (2), wherein at least one processor core (3), an internal memory (4), a switching network (7) and a level converter (21) are arranged in every processor element (2) in a voltage-variable region (22), characterised in that a local queue memory (14) is arranged in the voltage-variable region (22) of the processor element (2) for storing events (24) to be processed by the processor core (3), wherein a number of events (24) to be processed stored in the local queue memory (14) is determined, in that the local queue memory (14) is connected to the processor core (3), the internal memory (4) and the level converter (21), in that a local clock generator (5) for setting a required clock frequency f for every cycle (23) is arranged in every processor core (3), in that the processor core (3) is connected to the switching network (7) setting a required supply voltage U for every cycle (23) for connecting the processor core (3) to one of several available supply voltage lines of a supply voltage network (18), in that the supply voltage network (18) is connected to a supply voltage unit (17) for providing several voltages and in that every processor core (3) is adapted so that the setting of the required supply voltage U and the required clock frequency f for every cycle (23) controlled by the processor core (3) of the respective processor element (2) is carried out as a function of a determination of a number of events (24) stored in an internal queue memory (14) and to be processed, and in that a resetting of the set supply voltage U and the clock frequency f is carried out after a processing of the events to be processed in the current cycle by the processor core, wherein the resetting is to a smaller or the smallest provided supply voltage U1 and the smallest provided frequency f1.

2. The multi-core processor (1) according to claim 1, characterised in that an internal supply voltage-frequency control arrangement (6) which can be controlled by the associated processor core (3) is arranged in each processor element (2).

3. The multi-core processor (1) according to claim 2, characterised in that the internal supply voltage-frequency control arrangement (6) is connected to the switching network (7) and an internal clock generator (5).

4. The multi-core processor (1) according to claim 3, characterised in that an adaptation unit (16) is arranged between the internal supply voltage-frequency control arrangement (6) and the internal clock generator (5).

5. A method for dynamically setting a supply voltage and a clock frequency, wherein a selection of a required supply voltage U from a number of provided supply voltages U1, U2, ...Ux and a selection of a required clock frequency f from a number of provided clock frequencies f1, f2, ... fy is carried out for a processor element (2) in a multi-core processor (1) with several processor elements (2) at a time t for a cycle (23) of a processing of a number of events (24) through a processor core (3), characterised in that the setting of the required supply voltage U and the required clock frequency f for every cycle (23) controlled by the processor core (3) of the respective processor element (2) is carried out as a function of a determination of a number of events (24) stored in an internal queue memory (14) and to be processed and in that a resetting of the supply voltage U and the clock frequency f set at the time t is carried out after a processing of the events (24) to be processed in the current cycle (23) by the processor core (3), wherein the resetting is to a smaller or the smallest provided supply voltage U1 and the smallest provided frequency f1.

6. The method according to claim 5, characterised in that the determination of the number of events (24) stored in the internal queue memory (14) and to be processed is carried out once per cycle (23) at the specified time t.

7. The method according to claim 5 or 6, characterised in that the setting of the required supply voltage U and the required clock frequency f is carried out once per cycle (23) at the specified time t for a temporally subsequent cycle (23).

8. The method according to any one of claims 5 to 7, characterised in that the supply voltage U and the clock frequency f are determined by means of a table from the number of events (24) stored in the internal queue memory (14) and to be processed.

9. The method according to any one of claims 5 to 7, characterised in that the supply voltage U and the clock frequency f are determined by means of a formula or threshold values from the number of events (24) stored in the internal queue memory (14) and to be processed.

10. The method according to any one of claims 5 to 9, characterised in that a filling level F is determined and a first threshold value Fth1 and a second threshold value Fth2 set by means of the number of the events (24) stored in the internal queue memory (14) and to be processed, wherein Fth1 < Fth2, in that in case F < Fth1, the supply voltage U1 and the clock frequency f1 is set for the subsequent cycle (23), in that in case Fth1 ≤ F < Fth2, the supply voltage U2 and the clock frequency f2 is set for the subsequent cycle (23), in that in case Fth2 < F, the supply voltage U3 and the clock frequency f3 is set for the subsequent cycle (23), wherein U1 < U2 < U3 and f1 < f2 < f3.