INPUT / OUTPUT UNIT FOR DATA ACQUISITION IN A FIELDBUS SYSTEM

Description

[0001] The invention relates to an input / output unit for data acquisition in a fieldbus system. This includes the use of the input / output unit for acquiring the course of a digital signal by a microcontroller.

[0002] Such input / output units are used in a variety of ways in the fieldbus sector. Fieldbus systems are used in automation technology, process and process engineering, and generally for the control of machines and systems, including robots. There, they are used to acquire measured values ​​from sensors and to output switching signals for system control. In particular, fieldbus systems have long been used to replace the previously common parallel wiring of binary signals and analog signal transmission for sensors with digital transmission technology.

[0003] The input / output units in the fieldbus area are typically equipped with standard microcontrollers that have so-called "general purpose inputs / outputs" (GPIO ports). A typical I / O application consists, for example, in the need to sample the state of a digital input at very short intervals in order to read the digital data. It is not always possible to transmit the data to the fieldbus system controller via the fieldbus at the required sampling rate. In this case, an "oversampling" technique in conjunction with data packetization is required. A signal is sampled at the required short time interval, the sampled values ​​are buffered in a memory, and transmitted cyclically at a high transmission rate in packets and at longer time intervals (depending on the higher-level fieldbus system and its access conditions).Typically, the microcontroller's CPU samples the state of a GPIO port in the "traditional" way. Each time the sampling time arrives, the state of the standard GPIO port is captured and buffered state by state (bit by bit) in a register. This requires calling "complicated" bit shifting routines to accumulate the individual states so that they can be sent in packets. The sampling times are usually specified using a timer component in the microcontroller by generating a corresponding clock signal. Timers are also programmed for certain bit or word shift operations. These generate a timer interrupt after the previously specified time has elapsed. This interrupt calls the corresponding interrupt service routines (ISRs), which are then processed by the CPU.

[0004] Document EP 1 873 597 A1 describes a connection module for connecting a sensor to a fieldbus. The connection module comprises at least one sensor interface for connecting the connection module to a sensor interface, at least one bus interface for connecting the connection module to a fieldbus interface, and a circuit for data exchange.

[0005] Document DE10 2016 109 363 A1 concerns a host port for a serial peripheral interface. The SPI interface is used as the serial interface.

[0006] Document DE10 2014 209 625 A1 discloses the use of an SPI interface in a microcontroller that is also equipped with a direct memory access controller (DMA controller). Data is transferred back and forth between the microcontroller and an external memory via the SPI interface using the DMA controller.

[0007] Document US 2009 024 776 A1 describes a microcontroller that is also equipped with an SPI interface and a DMA controller. The DMA controller transfers the data received from the SPI interface to the CPU core.

[0008] The overview article on SPI and DMA transfer, "Using DMA with High-Performance Peripherals to Maximize System Performance," by John Mangino (WW TMS470 Catalog Applications, SPNA 105, January 2007), also describes the use of DMA controllers to reduce the CPU load during data transfers over SPI interfaces. Data received from an SPI interface is written to memory by the external DMA controller.

[0009] However, the known solutions have the disadvantage that processor registers are used for intermediate storage when transferring data from an I / O unit to the main memory. The data is first read from the processor into its internal register and then moved to the main memory in a subsequent step. This requires routines triggered by timer modules to be processed, which require many clock cycles during which the processor is unavailable for executing other instructions. This reduces the execution speed of running programs. In the known solutions, in which data is transferred from an SPI interface to the memory via direct memory access, data output via the fieldbus is not considered.

[0010] There is therefore a need for an improved input / output unit for fieldbus systems that avoids these disadvantages. This was recognized in the context of the invention.

[0011] This object is achieved by an input / output unit for data acquisition in fieldbus systems according to claim 1.

[0012] The dependent claims contain advantageous developments and improvements of the invention according to the following description of these measures.

[0013] The solution according to the invention consists in an input / output unit for data acquisition in a fieldbus system according to claim 1.

[0014] The input / output unit comprises a microcontroller (e.g., a standard microcontroller) having at least one integrated synchronous serial bus interface and a control unit for direct memory access. The solution is characterized in that a signal source for a digital signal can be connected to a data input of a first synchronous serial bus interface of the at least one synchronous serial bus interface, and in that the first synchronous serial bus interface reads the data present at the data input at a first clock rate. The first clock rate for reading the data corresponds to the data transmission rate of the first synchronous serial bus interface.

[0015] Collecting and arranging the individual states (bit by bit) into data packets is thus much easier to implement because the bit shifting routines become superfluous and timer interrupts are eliminated.

[0016] Furthermore, the solution is that the control unit for the direct memory access forwards the read data signals as data words to a buffer, and from time to time retrieves them from the buffer and forwards them to a second synchronous serial interface or another bus interface, wherein the second synchronous serial interface or the other bus interface is connected to a fieldbus interface, and outputs the data words at a higher clock rate than the first clock rate during data acquisition by the first synchronous serial bus interface.

[0017] This solution offers the advantage that no CPU-intensive routines need to be called to acquire data at the digital input and to package and forward the data via the fieldbus. The CPU is freed from the data acquisition and forwarding process and can perform other tasks. A microcontroller with a less powerful CPU could also be used, making the I / O unit more cost-effective.

[0018] Another advantageous feature is that the data words are fetched from the buffer in packets. The DMA controller can be programmed accordingly, so that no CPU routines need to be executed for this.

[0019] The invention can be implemented particularly advantageously with microcontrollers in which the at least two synchronous serial interfaces are of the SPI type, corresponding to Serial Peripheral Interface. This interface is very common and is frequently used in microcontrollers.

[0020] In a preferred variant, the input / output unit is designed such that the data input is connected to the MISO input, corresponding to Master In, Slave Out of the first SPI interface, and the SCLK, MOSI, and CS outputs, corresponding to Serial Clock, Master Out, Slave In, and Chip Select of the first SPI interface, are either not connected or are grounded. The first SPI interface is thus operated unconventionally as a master, although it is not connected to other chips that also contain SPI interfaces.

[0021] It is also very advantageous if the input / output unit is programmed so that the second clock rate is at least a factor higher than the first clock rate, corresponding to a multiple of the first clock rate, where the multiple is determined by the word length of the data words. This measure ensures that the acquired data can be transmitted in packets over the fieldbus.

[0022] In an extended embodiment, the chip select signal is connected to one or more additional SPI interfaces instead of being grounded or left unconnected. This allows one or more additional SPI interfaces to be selected from a number of SPI interfaces, where the data present at the data input (MISO) is read at the first clock rate and forwarded to the buffer. This allows multiple digital inputs to be captured in the same way and output via the fieldbus.

[0023] In an advantageous embodiment, the data packets generated by the input / output unit have a transmission format with a header, HD, a transport data field, TF, and a payload field, PL. The header contains address information, the transport data field contains a sequence number and / or a timestamp, and the payload field contains a number of data words compiled in the data packet. This makes it easy to retrieve the chronological order of the data packets for detecting the digital signal in the higher-level controller. The data packets are individually numbered. The packet number is assigned as a sequence number and is thus incremented with each new data packet transmitted to the fieldbus interface.

[0024] Further advantageous variants involve an input / output unit, with the other bus interface being a UART, USART, I2C, or USB interface. These are already integrated into some standard microcontrollers.

[0025] An embodiment of the input / output unit according to the invention can be used to capture the course of a digital signal by a microcontroller having at least one integrated synchronous serial bus interface with full-duplex functionality. When the input / output unit is used, the microcontroller reads in a digital signal present at a digital data input of a first synchronous serial bus interface of the at least one integrated synchronous serial bus interface at a clock rate that corresponds to a data transmission rate of the first synchronous serial bus interface. The at least one synchronous serial bus interface is of the SPI interface type, corresponding to Serial Peripheral Interface.

[0026] A special feature is that the data outputs of the synchronous serial bus interface, which are normally connected to the signal source to which the data input is connected for full-duplex operation, are not connected to the signal source to establish a full-duplex connection. This allows the acquisition of the digital signal to be carried out in a way that minimizes processor load.

[0027] The integrated synchronous serial bus interface is preferably operated in a master mode, where it sets the clock rate for reading the digital signal. If the clock rate is high enough, the digital signal can be captured with correspondingly good resolution.

[0028] The microcontroller with at least one integrated synchronous serial bus interface with full-duplex functionality can be characterized in that the microcontroller is adapted to perform the function of the input / output unit according to the invention. The microcontroller is adapted, on the one hand, by appropriately wiring the inputs and outputs of the integrated synchronous serial interface and, on the other hand, by software in which the data outputs of the integrated synchronous serial interface are not operated.

[0029] Several embodiments of the invention are illustrated in the drawings and are explained in more detail below with reference to the figures.

[0030] They show: Fig. 1 shows a fieldbus system with the two components I / O unit and controller; Fig. 2 shows a block diagram of a standard microcontroller that can be used in electronic components for fieldbus systems; Fig. 3 shows a first block diagram with an I / O unit in which a standard microcontroller is used in a first manner according to the invention; Fig. 4 shows a signal diagram illustrating the "oversampling" technique when reading in a digital signal; Fig. 5 shows the data transmission process when outputting the read-in digital signal from the second bus interface to a fieldbus interface; and Fig. 6 shows a second block diagram with an I / O unit in which a standard microcontroller is used in a second manner according to the invention.

[0031] The present description illustrates the principles of the inventive disclosure. It is thus understood that those skilled in the art will be able to devise various arrangements that, while not explicitly described herein, embody principles of the inventive disclosure and are also intended to be protected within their scope.

[0032] Fig. 1shows a simple fieldbus system with only two components. Reference number 10 denotes an input / output unit (I / O unit). Reference numbers 20 and 30 denote a controller and the fieldbus itself. I / O units are used in a variety of ways and are used to record measured values. Sensor signals are often recorded. Reference number 17 denotes a sensor. Various types of sensors can be used in automation, process engineering, or other machine control applications. These include speed sensors, temperature sensors, light sensors, infrared sensors, touch sensors, microphones, cameras, etc., and the list is not exhaustive. The principle of fieldbus systems is that the measured values ​​are recorded locally by the I / O unit at the various sensors of the machine or system, while the machine or system is controlled in the control unit 20, e.g.This is done by a centrally located PLC controller. The I / O data is transmitted to the control unit 20 via the fieldbus 30. Various common fieldbus variants can be used as the fieldbus. Examples of fieldbus systems include Interbus, Profibus, Profinet, Ethernet, EtherCAT, CAN bus, HART, etc.

[0033] In addition to I / O units used to acquire sensor signals, I / O units are also used to send control signals that then switch specific actuators. Examples include actuators, pumps, valves, electric motors, etc.

[0034] There are applications for I / O units in which signals, such as the state of a digital or analog input signal, must be sampled at very short intervals. For this purpose, standard microcontrollers with so-called general-purpose inputs / outputs (GPIOs) are often used in the I / O units. This enables the periodic acquisition / output of digital or analog signals. Due to the increased traffic volume on the connected fieldbus 30, on which a wide variety of other data is also transmitted, and the associated bus allocation conflicts, it is not always possible to transmit the read data to the controller at the required time interval according to the desired sampling rate when reading the data. In this case, the so-called "oversampling" technique is used, which, however, should not be confused with the technique of the same name used in A / D or D / A conversion.A signal is sampled at the short time interval required by the controller. The data is buffered and transmitted cyclically at a high transmission rate in blocks, but at longer time intervals (depending on the higher-level fieldbus system). Data therefore always arrives at the controller in blocks. If the faster transmitted data is reset to the required time frame, the data is then available in the controller in the same format as it was read into the I / O unit.

[0035] The Fig. 2shows a block diagram of such a standard microcontroller. It is the L8051XC1 microcontroller from Intel. The microcontroller is designated by the reference number 100. It contains the following components: CPU 110, timer module 112, real-time clock 114, monitoring circuit 116, interrupt controller 118, coprocessor 120, serial interface 122, general-purpose I / O unit 124, SPI interface 126, I2C interface 128, debugging unit 130, and power supply unit 132. The functionality for reading digital data is as follows.

[0036] Typically, the state of a digital input, e.g., one of the GPIO inputs, is sampled "classically." Each time the sampling time is reached, the state of a standard GPIO input 124 is captured and stored state by state (bit by bit) in a buffer. Fig. 2The buffer is allocated in the externally connected memory module 140. Alternatively, an internal buffer could also be provided. In both cases, however, "complicated" bit shifting routines must be called by the CPU 110 to store the individual bit states so that they can be sent collectively in blocks. The times for sampling the desired GPIO input 124 are usually specified by the timer module 112 of the microcontroller 100, such that after a predetermined time has elapsed, a timer interrupt calls the corresponding routine(s). The same is also required when reading the data from the buffer. The CPU 110 must compile the data into data packets, which are then transmitted via the external bus 134 to the fieldbus interface 150.Here, too, the corresponding routines for reading the data from memory chip 140 and arranging it into data packets must be called. However, this also places a load on CPU 110.

[0037] The Fig. 3 shows a first embodiment of the inventive solution how a CPU-friendly I / O operation can be carried out with a standard microcontroller. Fig. 3another standard microcontroller 11. This can, for example, be of the following commercially available type Cortex Mx, where x is a natural number [0, 1, 2, ...]. The commercially available microcontrollers of the type STM32T103xC, -xD or -xE from the manufacturer STMicroelectronics are mentioned as an example. The microcontroller is equipped with internal memory, where the buffer 18 can also be allocated. The reference number 12 designates a first SPI interface and the reference number 14 a second SPI interface. The CPU-friendly I / O operation is possible by using the SPI interfaces 12, 14 for the I / O process. The SPI interfaces 12, 14 correspond to a peripheral component of the now standardized SPI bus, which is sometimes present twice or three times in most microcontrollers. However, this peripheral component is used differently than intended.In accordance with its original intended operation, no plausible data is generated. However, the idea described here can be used to easily implement the required oversampling. The prerequisite is that the standard microcontroller has at least one SPI interface. In the example shown, it has two SPI interfaces.

[0038] The SPI (Serial Peripheral Interface) interface has been standardized. It is a synchronous, serial data bus that can be used to interconnect digital circuits according to the master-slave principle. Further details on the SPI interface are known from US patent US 4,816,996, which is expressly incorporated by reference for the detailed disclosure.

[0039] There are three common lines to which each participant is connected: 1. SCLK (Serial Clock), this clock is output by the master for synchronization. 2. MOSI (Master Output, Slave Input), when operating as a master, it is an output; when operating as a slave, it is an input. 3. MISO (Master Input, Slave Output), when operating as a master, it is an input; when operating as a slave, it is an output.

[0040] Additionally, there may be a fourth common line, the so-called chip select signal. 4. CS (Chip Select)

[0041] In a multi-slave system, the SPI master can select a slave via the CS signal. A chip select signal is not required for the actual oversampling of a digital input.

[0042] However, it is also possible to use this signal to "trigger" certain processes in the SPI slave, so that usable data is already available at the beginning of the data transfer, i.e. at the time when the serial clock signal starts to clock.

[0043] Alternatively, this signal can also be used to select the digital inputs for oversampling on an I / O unit with multiple digital inputs, e.g., "one out of eight," via the chip select signal. Alternatively, depending on the microcontroller's performance, digital inputs could be selected as "2 out of 8," "3 out of 8," etc., where the oversampling technique is used.

[0044] The first SPI interface 12 is used to read the data. This SPI interface 12 is operated in SPI master mode. The signals at the SCLK and MOSI (Master Out, Slave In) inputs / outputs are "empty." In the case shown, they are simply connected to ground. Only the MISO (Master In, Slave Out) input / output is connected to a signal source 17 (a sensor that outputs a digital signal). It thus serves as a "digital input." The data now read by the SPI interface 12 operating in SPI master mode represents the states of the digital signal source 17 after level adjustment, which was performed using a corresponding level adjustment circuit 13. The data is sampled and read at a sampling rate that corresponds to the data transmission rate of the SPI master 12. Various SCLK frequencies can be programmed.The frequency range that can be set with a conventional SPI interface is between several kHz and several MHz. This data is forwarded via the second SPI interface 14 to the fieldbus interface 15. For this purpose, the module for the fieldbus interface 15 also contains an SPI interface 14.

[0045] The "oversampling" technique is now further enhanced with the help of Fig. 4explained in more detail. The digital signal shown in the top line is output by signal source 17. Typical examples of such signal sources are sensors that generate a digital output signal. This can be, for example, a light barrier. This digital signal is to be acquired. This is done using the SPI interface 12. This is operated in master mode, and a clock frequency is set that is high enough to perform oversampling of the digital signal. The SCLK clock signal SCLK, which is used for sampling, is in the Fig. 4 shown in the middle line. The sample values ​​are shown in the line below. Eight sample values ​​are combined into one data word. The data words are shown in hexadecimal notation in the bottom line. Conventionally, one sampling process would suffice to read the respective digital state. With oversampling, each digital state is read multiple times.

[0046] Collecting and arranging the individual read-in bit states (bit by bit) into data words is thus significantly easier to implement because the bit shifting routines become superfluous and the necessary timer interrupts, which burden the CPU 110, are eliminated. The data words are fetched from the SPI interface 12 using a DMA module 16 located on the chip of the microcontroller 11. This module can write the data to the buffer 18 without involvement of the CPU (not shown).

[0047] The data is output to the connected fieldbus interface 15 via the second SPI interface 14. The DMA module 16 is programmed to retrieve the data from the buffer 18 in the correct packet size and output it to the second SPI interface 14. The second SPI interface 14 is programmed to transmit the retrieved data packets to the fieldbus interface 15 in a time-organized manner at a faster data rate, i.e., a higher SCLK clock rate. This significantly reduces the load on the CPU, allowing it to make its computing power available for other tasks because the SPI modules 12, 14, and the DMA controller 16 operate in the background. It is advantageous to transmit fieldbus-dependent management data in addition to the read data words.To easily check the chronological order of the digital signal's data packets in the higher-level controller 20, a timestamp or packet number can be added. The packet number is assigned as a sequence number and is incremented with each new data packet transmitted to the fieldbus interface. The timestamp can also be entered. Alternatively, it can also be updated each time the data packet is output to the fieldbus by the fieldbus interface 15.

[0048] The Fig. 5shows the structure of the DP data packets. The first section of the packet format, the HD header, contains the management data, such as the destination and sender addresses. The middle section, the TF transport data field, contains the timestamp and the packet number. This is followed by the actual payload field with the data words. For example, the PL payload field can contain eight data words. The time interval between the data packets is also shown.

[0049] In the Fig. 6 A second embodiment of the inventive implementation of the CPU-friendly I / O operation with a standard microcontroller is shown. The same reference numerals designate the same components as in Fig. 3One difference is that the microcontroller 11 does not use a second SPI interface to output the read data words to the fieldbus interface 15, but rather a different serial or parallel bus interface. It is shown that a serial interface in the form of a UART interface is used for this purpose. Accordingly, a UART module 19 is used in the module 15 for the fieldbus interface, which is connected to the UART module 19 via, for example, the TX and RX lines.

[0050] In further embodiments, other serial or parallel interfaces could be used. Examples include a USART interface, an RS232 interface, a 12C interface, a USB interface, or a Firewire interface.

[0051] It should be understood that the proposed exemplary use and associated devices may be implemented in various forms of hardware, software, firmware, special-purpose processors, or a combination thereof. In a preferred variant, microcontrollers with integrated RAM memory and integrated I / O interfaces are employed. Special-purpose processors may include application-specific integrated circuits (ASICs), reduced instruction set computers (RISCs), and / or field-programmable gate arrays (FPGAs). Preferably, the device is implemented as a combination of hardware and software. The software is preferably installed as an application program on a program storage device.Typically, it is a machine based on a computer platform that includes hardware such as one or more central processing units (CPUs), random access memory (RAM), and one or more input / output (I / O) interfaces. An operating system is also typically installed on the computer platform. The various processes and functions described here may be part of the application program or a portion executed by the operating system. List of reference symbols Input / output unit 10 Standard microcontroller 11 1. SPI interface 12 Level adjustment circuit 13 2. SPI interface 14 Fieldbus interface 15 DMA controller 16 Data input 17 cache 18 UART interface 19 Control unit 20 Fieldbus 30 Standard microcontroller 100 CPU 110 Timer module 112 Real-time clock module 114 Monitoring circuit 116 Interrupt controller 118 Co-processor 120 Serial interface 122 GPIO ports 124 SPI interface 126 12C interface 128 Debugging unit 130 Power supply unit 132 System bus 134 external storage 140 Fieldbus interface 150 Selection pin CS Data package DP headboard HD Transport subdata field TF Payload field PL

Claims

1. An input / output unit (10) for data acquisition in a field bus system, having a microcontroller which has at least one integrated synchronous serial bus interface (12, 14) and a control unit (16) for direct memory access, characterized in that a signal source (17) for a digital signal can be connected to a digital data input (MISO) of a first synchronous, serial bus interface (12) of the at least one integrated synchronous, serial bus interface (12, 14), in that the first synchronous, serial bus interface (12) is configured to read in the digital signal present at the data input (MISO) at a first clock rate which corresponds to a data transmission rate of the first synchronous, serial bus interface (12), the at least one synchronous, serial bus interface (12) being of a type of SPI interface, corresponding to Serial Peripheral Interface, in that the control unit (16) for direct memory access is configured to forward the read-in digital signals as data words to a buffer memory (18), and to fetch them from the buffer memory (18) from time to time, and to forward them to a second synchronous serial bus interface (14) of the at least one integrated synchronous serial bus interface (12, 14) or to another bus interface (19), wherein the second (14) or the other bus interface (19) can be connected to a fieldbus interface (15) and is configured to output the data words to the fieldbus interface (15) at a higher clock rate than the first clock rate during data acquisition by the first synchronous serial interface (12).

2. The input / output unit (10) according to claim 1, wherein the data words are fetched from the buffer (18) in packets.

3. The input / output unit (10) according to claim 1 or 2, wherein the signal source (17) can be connected to a MISO input (MISO), corresponding to Master In, Slave Out of the SPI interface (12), and the outputs SCLK, MOSI and CS, corresponding to Serial Clock, Master Out - Slave In and Chip Select of the SPI interface (12), are not connected or can be connected to ground.

4. The input / output unit (10) according to one of claims 1 to 3, wherein the second clock rate is higher than the first clock rate by at least such a factor that it corresponds to a multiple of the clock rate of the first clock rate, wherein the multiple is determined by the word length of the data words.

5. The input / output unit (10) according to claim 3, wherein the chip select signal, instead of being connected to ground or not connected, is used to select one or more further SPI interfaces from a number of SPI interfaces, in which the data present at the data input (MISO) is read in at the first clock rate and forwarded to the buffer (18).

6. The input / output unit (10) according to one of the preceding claims, wherein data packets generated by the input / output unit (10) have a transmission format with a header part (HD), a transport part data field (TF) and with a user data field (PL), wherein address information is contained in the header part (HD), a sequence number and / or a time stamp in the transport part data field (TF) and a number of the data words compiled in the data packet in the user data field (PL).

7. The input / output unit (10) according to one of the preceding claims, wherein the other bus interface (19) is a bus interface of the type of a UART, USART, I2C or USB interface.