POWER CONVERTER DEVICE WITH A POWER CONVERTER FEATURING AN ANPC TOPOLOGY AND WITH A CONTROL DEVICE

Description

[0001] The invention relates to a power converter device comprising a power converter having a first, second, third, fourth, fifth, and sixth power semiconductor switch, each having a first and a second load current connection, and comprising a control device designed to control these power semiconductor switches. The second load current connection of the first power semiconductor switch is electrically connected to the first load current connection of the second power semiconductor switch and to the first load current connection of the fifth power semiconductor switch. The second load current connection of the second power semiconductor switch is electrically connected to the first load current connection of the third power semiconductor switch.The second load current terminal of the third power semiconductor switch is electrically connected to the first load current terminal of the fourth power semiconductor switch and to the first load current terminal of the sixth power semiconductor switch. The second load current terminal of the fifth power semiconductor switch is electrically connected to the second load current terminal of the sixth power semiconductor switch. The power converter has an ANPC topology (Active Neutral Point Clamped topology).

[0002] Such a power converter device is known from JP H05-211776 A and US 2019 / 0013743 A1. The disadvantage is that at the switching instant, in addition to the second and fourth power semiconductor switches being switched in opposite directions to the first and third power semiconductor switches, the fifth and sixth power semiconductor switches are also switched in opposite directions at approximately the same time (see FIG 2 and FIG 3 the JP H05-211776 A and FIG 1 and FIG 2 US 2019 / 0013743 A1). In a real technical implementation of the control of the fifth and sixth power semiconductor switches, these switch, e.g. due to different switching times and different lengths of the control lines to the power semiconductor switches, in an uncontrolled manner either shortly before the switching time at which the second and fourth power semiconductor switches are switched in opposite directions to the first and third power semiconductor switches or shortly after this, which is technically undesirable. From US 2019 / 0013743 A1, it is known that at the switching time at which the second and fourth power semiconductor switches are switched in opposite directions to the first and third power semiconductor switches, the fifth power semiconductor switch is switched off very slightly before this switching time, although the intersection point of the triangular modulation signal with the sinusoidal target signal actually (see FIG 2 US 2019 / 0013743 A1) specifies simultaneous switching off of the fifth power semiconductor switch at this switching time. A disadvantage of the control of the power semiconductor switches proposed in US 2019 / 0013743 A1 is that it is not very flexible, since the relevant switching time always coincides with the zero crossing of the sinusoidal target signal.

[0003] From the publication "Three-Level Two-Stage Decoupled Active NPC Converter With Si IGBT and SIC MOSFET", ZHANG DI ET AL, IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, IEEE, Vol. 54, No. 6, November 1, 2018, pages 6169-6178, a power converter having an ANPC topology is known in which the power semiconductor switches that turn on and off at a high frequency are designed as MOSFETs and the power semiconductor switches that turn on and off at a low frequency are designed as IGBTs.

[0004] From DE 10 2018 219 270 A1 an inverter is known with a first input connection pole to which a positive intermediate circuit potential is applied during operation of the inverter, with a second input connection pole to which a center potential is applied during operation of the inverter, with a third input connection pole to which a negative intermediate circuit potential is applied during operation of the inverter, with an output connection pole to which an output potential is output during operation of the inverter, with a choke and with several switching means.

[0005] From the publication "Voltage Balancing Control of Three-Level Active NPC converter using SHE-PWM", SRIDHAR R PULIKANTI ET AL, IEEE TRANSACTIONS ON POWER DELIVERY, Vol. 26, No. 1, 1 January 2011, pages 258-267, is a power converter with an ANPC topology in which pulse width modulation is used to control the power semiconductor switches, in which certain harmonic current oscillations are suppressed.

[0006] The object of the invention is to provide a power converter device which enables more flexible control of the power semiconductor switches.

[0007] This object is achieved by a power converter device having a power converter which has a first, second, third, fourth, fifth and sixth power semiconductor switch, each having a first and a second load current connection, and having a control device which is designed to control these power semiconductor switches, wherein the second load current connection of the first power semiconductor switch is electrically connected to the first load current connection of the second power semiconductor switch and to the first load current connection of the fifth power semiconductor switch, wherein the second load current connection of the second power semiconductor switch is electrically connected to the first load current connection of the third power semiconductor switch,wherein the second load current terminal of the third power semiconductor switch is electrically conductively connected to the first load current terminal of the fourth power semiconductor switch and to the first load current terminal of the sixth power semiconductor switch, wherein the second load current terminal of the fifth power semiconductor switch is electrically conductively connected to the second load current terminal of the sixth power semiconductor switch, wherein the control device is designed to control the power semiconductor switches in such a way that, the first and third power semiconductor switches are switched on and off simultaneously, and the second and fourth power semiconductor switches are switched on and off simultaneously, wherein the second and fourth Power semiconductor switches are switched on and off in opposition to the first and third power semiconductor switches, wherein the first and third power semiconductor switches are switched off at main switch-off times, and the first and third power semiconductor switches are switched on and off at a first frequency, and the fifth and sixth power semiconductor switches are switched on and off in opposition to each other, and in a respective period in which the first and third power semiconductor switches or the second and fourth power semiconductor switches are switched on simultaneously, the fifth and sixth power semiconductor switches are switched on and off several times, characterized in that that the control device is designed to control the power semiconductor switches in such a way that the fifth power semiconductor switch is switched off before the respective main switch-off time and is only switched on again after the respective main switch-off time or the fifth

[0008] power semiconductor switch is switched on before the respective main switch-off time and is only switched off again after the respective main switch-off time, wherein the control device is designed to switch the first, second, third and fourth power semiconductor switches on and off using a sinusoidal target signal having a second frequency and to switch the fifth and sixth power semiconductor switches on and off in a pulse-width modulated manner using the sinusoidal target signal and a modulation signal (M) having a third frequency, wherein the second frequency corresponds to the first frequency, wherein the control device is designed such that the first and third power semiconductor switches are switched on when the target signal has a positive value and are switched off when the target signal has a negative value, wherein, if the modulation signal has a higher value than the target signal, the fifth power semiconductor switch is switched off and, if the modulation signal has a lower value than the target signal, the fifth power semiconductor switch is switched on, wherein the third frequency is an integer multiple of the second frequency, wherein the modulation signal is phase-shifted with respect to the target signal, or the third frequency is higher than the second frequency, wherein the third frequency is not an integer multiple of the second frequency.

[0009] The control device is designed to switch the first, second, third and fourth power semiconductor switches on and off using a sinusoidal target signal having a second frequency and to switch the fifth and sixth power semiconductor switches on and off in a pulse width modulated manner using the sinusoidal target signal and a modulation signal having a third frequency, wherein the control device is designed such that the first and third power semiconductor switches are switched on when the target signal has a positive value and are switched off when the target signal has a negative value, wherein if the modulation signal has a higher value than the target signal, the fifth power semiconductor switch is switched off and if the modulation signal has a lower value than the target signal, the fifth power semiconductor switch is switched on.Using the setpoint signal and the modulation signal, the control signals for switching the power semiconductor switches on and off are generated in a simple manner.

[0010] If the third frequency is an integer multiple of the second frequency, wherein the modulation signal is phase-shifted relative to the target signal, the fifth power semiconductor switch is very reliably switched off before the respective main switch-off time and is not switched on again until after the respective main switch-off time, or the fifth power semiconductor switch is switched on before the respective main switch-off time and is not switched off again until after the respective main switch-off time.

[0011] If the third frequency is higher than the second frequency, where the third frequency is not an integer multiple of the second frequency, the fifth power semiconductor switch is very reliably switched off before the respective main switch-off time and is not switched on again until after the respective main switch-off time, or the fifth power semiconductor switch is switched on before the respective main switch-off time and is not switched off again until after the respective main switch-off time.

[0012] It proves advantageous if the semiconductor material from which the first, second, third, and fourth power semiconductor switches are formed is made of silicon, and the semiconductor material from which the fifth and sixth power semiconductor switches are formed is made of silicon carbide or gallium nitride. This reduces switching losses, since power semiconductor switches formed on the basis of silicon carbide or gallium nitride have lower switching losses than power semiconductor switches formed on the basis of silicon.

[0013] Furthermore, it proves advantageous if the fifth and sixth power semiconductor switches are designed as MOSFETs. This reduces the switching losses of the power converter.

[0014] Furthermore, it proves advantageous if the power converter has a capacitor, wherein a first terminal of the capacitor is electrically connected to the first load current terminal of the fifth power semiconductor switch, and a second terminal of the capacitor is electrically connected to the first load current terminal of the sixth power semiconductor switch. This reduces electrical voltage oscillations occurring during operation of the power converter.

[0015] It should be noted that, in the sense of the invention, the term "simultaneous" does not mean exact mathematical simultaneity, but the term "simultaneous" is to be understood in a technical sense, so that, for example, deviations from mathematical simultaneity that occur due to TOT times that must be observed to avoid bridge short circuits, different switching delay times of the power semiconductor switches and different control signal delays are neglected.

[0016] Embodiments of the invention are explained below with reference to the figures below. FIG 1 shows a power converter device according to the invention, FIG 2 shows signals occurring in a conventional power converter device, FIG 3 and FIG 4 show signals occurring in an embodiment of a power converter device according to the invention, and FIG 5 and FIG 6 show signals occurring in a further embodiment of a power converter device according to the invention.

[0017] In FIG 1 1 shows a power converter device 1 according to the invention with a power converter 2 and with a control device 3. The power converter 2 has first, second, third, fourth, fifth and sixth power semiconductor switches T1, T2, T3, T4, T5 and T6, each of which has a first and a second load current connection L1 and L2. The second load current connection L2 of the first power semiconductor switch T1 is electrically connected to the first load current connection L1 of the second power semiconductor switch T2 and to the first load current connection L1 of the fifth power semiconductor switch T5. The second load current connection L2 of the second power semiconductor switch T2 is electrically connected to the first load current connection L1 of the third power semiconductor switch T3.The second load current terminal L2 of the third power semiconductor switch T3 is connected to the first load current terminal L1 of the fourth power semiconductor switch T4 and to the first load current terminal L1 of the sixth.

[0018] The second load current terminal L2 of the fifth power semiconductor switch T5 is electrically connected to the second load current terminal L2 of the sixth power semiconductor switch T6.

[0019] The power converter 2 has a positive potential connection DC+, which is electrically connected to the first load current connection L1 of the first power semiconductor switch T1, a negative potential connection DC-, which is electrically connected to the second load current connection L2 of the fourth power semiconductor switch T4, a neutral potential connection N, which is electrically connected to the second load current connection L2 of the second power semiconductor switch T2 and an alternating potential connection AC, which is electrically connected to the second load current connection L2 of the fifth power semiconductor switch T5. The power converter 2 thus has an ANPC topology. It is provided that between the positive potential connection DC+ or the first load current connection L1 of the first power semiconductor switch T1 and the neutral potential connection N ora first DC voltage Udc1 is applied to the second load current terminal L2 of the second power semiconductor switch T2 and a second DC voltage Udc2 is applied between the neutral potential terminal N or the second load current terminal L2 of the second power semiconductor switch T2 and the second load current terminal L2 of the fourth power semiconductor switch T4.

[0020] A diode D1, D2, D3, D4, D5 or D6 is preferably connected electrically anti-parallel to the respective power semiconductor switch T1, T2, T3, T4, T5 or T6, wherein the diode D1, D2, D3, D4, D5 or D6, in particular if the power semiconductor switch in question is designed as a MOSFET, can also be an integral part of the respective power semiconductor switch T1, T2, T3, T4, T5 or T6.

[0021] The electrical operation of power converter 2 is generally known state of the art. By appropriately switching the power semiconductor switches T1, T2, T3, T4, T5, and T6 on and off, the AC potential terminal can be electrically connected to the first or second DC voltage terminal DC+ or DC-, or to the neutral potential terminal N.

[0022] The semiconductor material from which the first, second, third and fourth power semiconductor switches T1, T2, T3 and T4 are formed is preferably made of silicon and the semiconductor material from which the fifth and sixth power semiconductor switches T5 and T6 are formed is preferably made of silicon carbide or gallium nitride.

[0023] The fifth and sixth power semiconductor switches T5 and T6 are preferably designed as MOSFETs. The first, second, third and fourth power semiconductor switches T1, T2, T3 and T4 can be designed as IGBTs, for example. In the exemplary embodiment, the first load current connections L1 of the first, second, third and fourth power semiconductor switches T1, T2, T3 and T4 are designed as collector connections and the second load current connections L2 of the first, second, third and fourth power semiconductor switches T1, T2, T3 and T4 are designed as emitter connections. Furthermore, in the exemplary embodiment, the first load current connections L1 of the fifth and sixth power semiconductor switches T5 and T6 are designed as drain connections and the second load current connections L2 of the fifth and sixth power semiconductor switches T5 and T6 are designed as source connections.

[0024] The power converter 2 preferably has a capacitor C1. A first terminal of the capacitor C1 is electrically connected to the first load current terminal L1 of the fifth power semiconductor switch T5, and a second terminal of the capacitor C1 is electrically connected to the first load current terminal L1 of the sixth power semiconductor switch T6. The capacitor C1 serves as a snubber capacitor.

[0025] The control device 3 is designed to control the power semiconductor switches T1, T2, T3, T4, T5, and T6. For this purpose, the control device 3 has outputs that are electrically connected to control terminals G1, G2, G3, G4, G5, and G6 of the power semiconductor switches T1, T2, T3, T4, T5, and T6, which are designed here as gate terminals. The control device 3 generates control signals for controlling the power semiconductor switches T1, T2, T3, T4, T5, and T6, or more precisely, for switching the power semiconductor switches T1, T2, T3, T4, T5, and T6 on and off.

[0026] In FIG 2 are those of a conventional power converter device that uses a power converter with an ANPC topology (see FIG 1 ) and a conventional control device. The FIG 2 The four switching signals shown below show the switching on and off of the power semiconductor switches T1, T2, T3, T4, T5 and T6, whereby when the respective power semiconductor switch is switched on, the respective switching signal has a HIGH level and when the respective power semiconductor switch is switched off, the respective switching signal has a LOW level. Based on the switching signals, the control device generates the control signals for the power semiconductor switches T1, T2, T3, T4, T5 and T6. The conventional control device is designed to control the power semiconductor switches T1, T2, T3, T4, T5 and T6 in such a way that the first and third power semiconductor switches T1 and T3 are switched on and off simultaneously, and the second and fourth power semiconductor switches T2 and T4 are switched on and off simultaneously, wherein the second and fourth power semiconductor switches T2 and T4 are switched on and off in opposition to the first and third power semiconductor switches T1 and T3, wherein the first and third power semiconductor switches T1 and T3 are switched off at main switch-off times t0, and the first and third power semiconductor switches T1 and T3 are switched on and off at a first frequency, and the fifth and sixth power semiconductor switches T5 and T6 are switched on and off in opposition to one another, and in a respective period in which the first and third power semiconductor switches T1 and T3 or the second and fourth power semiconductor switches T2 and T4 are switched on simultaneously,the fifth and sixth power semiconductor switches T5 and T6 are switched on and off several times.

[0027] The switching signals from the conventional control device are generated using a sinusoidal target signal S having a second frequency and a modulation signal M having a third frequency (see FIG 2 upper signals). The setpoint signal S and the modulation signal M are generated internally by the standard control device. If the AC potential connection AC is connected to an AC network, the setpoint signal S is preferably generated based on the time profile of the AC network's mains voltage. The first frequency corresponds to the second frequency.

[0028] The conventional control device is designed to switch the first, second, third and fourth power semiconductor switches T1, T2, T3 and T4 on and off based on the target signal S and to switch the fifth and sixth power semiconductor switches T5 and T6 on and off in a pulse width modulated manner based on the target signal S and the modulation signal M. The conventional control device is further designed such that the first and third power semiconductor switches T1 and T3 are switched on when the target signal S has a positive value and are switched off when the target signal S has a negative value, wherein if the modulation signal M has a higher value than the target signal S, the fifth power semiconductor switch T5 is switched off and if the modulation signal M has a lower value than the target signal S, the fifth power semiconductor switch T5 is switched on.

[0029] The third frequency is, as is customary in technology, an integer multiple of the second frequency, and the modulation signal M is not phase-shifted relative to the target signal S. The disadvantage here is that at the main switch-off time t0, at which the first and third power semiconductor switches T1 and T3 are switched off and thus the second and fourth power semiconductor switches T2 and T4 are switched on, the fifth and sixth power semiconductor switches T5 and T6 are simultaneously switched in opposite directions. In a real technical implementation of the control of the fifth and sixth power semiconductor switches T5 and T6, these switch, e.g.Due to different switching times and different lengths of the control lines running from the standard control device to the power semiconductor switches T1, T2, T3, T4, T5, and T6, uncontrolled switching occurs either shortly before the respective main switch-off time t0 or shortly after it, which is technically undesirable. Since, for example, the switching speeds of the power semiconductor switches are temperature-dependent, no defined switching behavior of the power converter occurs in the immediate temporal range around the main switch-off time t0.

[0030] The control device 3 according to the invention is, as exemplified in FIG 3 bis FIG 6 shown, designed to control the power semiconductor switches T1, T2, T3, T4, T5, and T6 in such a way that the fifth power semiconductor switch T5 is switched off before the respective main switch-off time t0 and is only switched on again after the respective main switch-off time t0 or the fifth power semiconductor switch T5 is switched on before the respective main switch-off time t0 and is only switched off again after the respective main switch-off time t0.

[0031] The control device 3 according to the invention corresponds to the conventional control device described above, including advantageous embodiments, with the exception of the formation of the modulation signal M.

[0032] Within the scope of an embodiment of the control device 3 according to the invention, as exemplified in FIG 3 and FIG 4 shown, the third frequency is an integer multiple of the second frequency, whereby, in contrast to the conventional control device, the modulation signal M is phase-shifted compared to the target signal S. The second frequency corresponds to the first frequency. In FIG 3 the modulation signal M is phase-shifted in the negative direction compared to the target signal S, which causes the fifth power semiconductor switch T5 to be switched off before the respective main switch-off time t0 and to be switched on again only after the respective main switch-off time t0. FIG 4 the modulation signal M is phase-shifted in the positive direction compared to the target signal S, which causes the fifth power semiconductor switch T5 to be switched on before the respective main switch-off time t0 and to be switched off again only after the respective main switch-off time t0.

[0033] Within the scope of a further embodiment of the control device 3 according to the invention, as exemplified in FIG 5 and FIG 6 shown, the third frequency is higher than the second frequency, where the third frequency is not an integer multiple of the second frequency. The second frequency is the same as the first frequency. In FIG 5 and FIG 6 the third frequency is not an integer multiple of the second frequency, which causes the fifth power semiconductor switch T5 to be switched off before the respective main switch-off time t0 and to be switched on again only after the respective main switch-off time t0 ( FIG 5 ) or that the fifth power semiconductor switch T5 is switched on before the respective main switch-off time t0 and is only switched off again after the respective main switch-off time t0 ( FIG 6 ).

Claims

1. Converter device comprising a converter (2), which has a first, second, third, fourth, fifth and sixth power semiconductor switch (T1, T2, T3, T4, T5, T6) each having a first and a second load current connection (L1, L2), and comprising a control device (3) designed to actuate said power semiconductor switches (T1, T2, T3, T4, T5, T6), wherein the second load current connection (L2) of the first power semiconductor switch (T1) is electrically conductively connected to the first load current connection (L1) of the second power semiconductor switch (T2) and to the first load current connection (L1) of the fifth power semiconductor switch (T5), wherein the second load current connection (L2) of the second power semiconductor switch (T2) is electrically conductively connected to the first load current connection (L1) of the third power semiconductor switch (T3), wherein the second load current connection (L2) of the third power semiconductor switch (T3) is electrically conductively connected to the first load current connection (L1) of the fourth power semiconductor switch (T4) and to the first load current connection (L1) of the sixth power semiconductor switch (T6), wherein the second load current connection (L2) of the fifth power semiconductor switch (T5) is electrically conductively connected to the second load current connection (L2) of the sixth power semiconductor switch (T6), wherein the control device (3) is designed to actuate the power semiconductor switches (T1, T2, T3, T4, T5, T6) in such a way that - the first and third power semiconductor switch (T1, T3) are switched on simultaneously and switched off simultaneously, and - the second and fourth power semiconductor switch (T2, T4) are switched on simultaneously and switched off simultaneously, wherein the second and fourth power semiconductor switch (T2, T4) are switched on and switched off contrary to the first and third power semiconductor switch (T1, T3), wherein the first and third power semiconductor switch (T1, T3) are switched off at main switch-off times (t0), and - the first and third power semiconductor switch (T1, T3) are switched on and off at a first frequency, and the fifth and sixth power semiconductor switch (T5, T6) are switched on and switched off contrary to one another, and - the fifth and sixth power semiconductor switch (T5, T6) are switched on and switched off multiple times in a respective period in which the first and third power semiconductor switch (T1, T3) or the second and fourth power semiconductor switch (T2, T4) are switched on simultaneously, wherein the control device (3) is designed to actuate the power semiconductor switches (T1, T2, T3, T4, T5, T6) in such a way that the fifth power semiconductor switch (T5) is switched off before the respective main switch-off time (t0) and is switched on again only after the respective main switch-off time (t0) or the fifth power semiconductor switch (T5) is switched on before the respective main switch-off time (t0) and is switched off again only after the respective main switch-off time (t0), wherein the control device (3) is designed to switch the first, second, third and fourth power semiconductor switch (T1, T2, T3, T4) on and off based on a sinusoidal target signal (S) having a second frequency and to switch the fifth and sixth power semiconductor switch (T5, T6) on and off in a pulse-width-modulated manner based on the sinusoidal target signal (S) and a modulation signal (M) having a third frequency, wherein the second frequency matches the first frequency, wherein the control device (3) is designed so that the first and third power semiconductor switch (T1, T3) are switched on if the target signal (S) has a positive value and are switched off if the target signal (S) has a negative value, wherein the fifth power semiconductor switch (T5) is switched off if the modulation signal (M) has a higher value than the target signal (S) and the fifth power semiconductor switch (T5) is switched on if the modulation signal (M) has a lower value than the target signal (S), wherein the third frequency is an integer multiple of the second frequency, wherein the modulation signal (M) is phase-shifted with respect to the target signal (S), or the third frequency is higher than the second frequency, wherein the third frequency is not an integer multiple of the second frequency.

2. Converter device according to one of the preceding claims, wherein the semiconductor material from which the first, second, third and fourth power semiconductor switch (T1, T2, T3, T4) are formed is formed from silicon and the semiconductor material from which the fifth and sixth power semiconductor switch (T5, T6) are formed is formed from silicon carbide or gallium nitride.

3. Converter device according to either of the preceding claims, wherein the fifth and sixth power semiconductor switch (T5, T6) are in the form of MOSFETs.

4. Converter device according to any one of the preceding claims, wherein the converter (2) has a capacitor (C1), wherein a first connection of the capacitor (C1) is electrically conductively connected to the first load current connection (L1) of the fifth power semiconductor switch (T5) and a second connection of the capacitor (C1) is electrically conductively connected to the first load current connection (L1) of the sixth power semiconductor switch (T6).