CRYOSATIBLE QUANTUM COMPUTING ARRANGEMENT AND METHOD FOR FABRICING A CRYOSATIBLE QUANTUM COMPUTING ARRANGEMENT

Description

[0001] The present invention relates to a cryo-compatible arrangement of microelectrical components and a method for producing a cryo-compatible arrangement for quantum computing applications. The cryo-compatible connection is characterized in that it allows the circuits to be pre-tested at room temperature (PT) or down to approximately -70°C (test mode) and then transition to the superconducting state upon cooling in the cryogenic temperature range (operating mode). Furthermore, the present invention relates to a three-dimensional, integrated structure for controlling ions (ion qubits) in an ion trap on a chip (ion trap chip) and a procedure for cryo-compatible vertical system integration of heterogeneous microelectronic components for quantum computing applications.

[0002] For quantum computers and quantum computing, ions, or ion qubits, or qubits, are integrated with suitable control / readout systems using wiring techniques. For the required cryogenically compatible integration methods and integrated structures, state-of-the-art solder joints are used, as they enable low-temperature processing without degradation of qubits, for example, superconducting transmons (a type of superconducting charge qubit) based on Josephson junctions. However, these conventionally used solders do not meet the requirements for a high input / output count (I / O count) and high wiring density with minimal standoff distances. Therefore, future focus will be on scaling of quantum computing components.

[0003] WO 2017 / 015432 A1 relates to a superconducting integrated circuit. The circuit comprises at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate, and at least one conductive material comprising a substantially low-stress polycrystalline titanium nitride (TiN) material.

[0004] WO 2017 / 070417 A1 relates to interconnect structures for constructing semiconductor structures comprising superconducting integrated circuits. A multilayer semiconductor structure comprises a first semiconductor structure and a second semiconductor structure, wherein at least one of the first and second semiconductor structures is provided as a superconducting semiconductor structure. The multilayer semiconductor structure further comprises one or more interconnect structures. Each of the interconnect structures is arranged between the first and second semiconductor structures and coupled to respective interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures comprises a plurality of interconnect sections. At least one of the interconnect sections comprises either a superconducting or partially superconducting material.

[0005] US 2018 / 102469 A1 relates to a CSP structure (CSP = Chip Scale Packaging) for a light-emitting diode and to a module with direct backlighting.

[0006] XP 011 134 449 relates to the tuning of the tungsten thin film superconducting transition temperature for the fabrication of photon number resolving detectors.

[0007] There is therefore a need for a cryo-compatible quantum computing device that has a contacting arrangement that is as easy to implement as possible, easy to test and (in essence) scalable, and for a corresponding manufacturing process for such a cryo-compatible quantum computing device.

[0008] This need is met by the subject matter of independent patent claims 1 and 13.

[0009] Advantageous embodiments and further developments of the present application are the subject of the dependent patent claims. Summary of the invention

[0010] A core idea of ​​embodiments of the present invention is to provide a cryo-compatible quantum computing arrangement in which the interconnects and / or feedthroughs, e.g., TSVs, of the vertically integrated arrangement of heterogeneous microelectronic components each comprise, between a first and a second contact element, a layer element comprising a first material that is superconducting at a quantum computer operating temperature, and a fill element comprising a second material that is electrically conductive. This applies to some metallic interconnects, as long as the temperature is low enough (e.g., in the mK range). However, there are crystal modifications that transition to the superconducting state even at higher temperatures. This is the case, for example, with the β-tungsten modification.To utilize the β-modification of tungsten, the integrated wiring in the TSVs, for example, features a layered structure with titanium nitride and tungsten. Titanium nitride itself also becomes superconducting at low temperatures (approximately 1.6 K).

[0011] According to one embodiment, the filling element fills at least 50% (or at least 70, 90, or 99%) of the respective volume of the conductive feedthroughs along the cross section between the first and second main surface regions of the substrate structure. The filling element can also completely fill the respective volume (= remaining volume of the feedthroughs provided with the layer element).

[0012] According to the inventive approach, however, by using a combination of integrated wiring, the microelectrical components for quantum computer applications are controlled using 3D TSV technology (TSV = Through Silicon Via), wherein the conductive TSV feedthroughs are at least partially or completely filled with a layer structure of electrically conductive material and also a material that is superconducting at quantum computer operating temperature. To utilize the β-modification of tungsten, the integrated wiring in the TSVs, for example, has the layer structure, e.g., with a superconducting material, such as titanium nitride (or with another superconducting material) and an electrically conductive material, such as tungsten or a tungsten-based material (or with another electrically conductive material).

[0013] An embodiment according to the present invention comprises a cryogenic-compatible quantum computing arrangement, for example, a three-dimensional structure for controlling ion trap qubits in an ion trap chip, for example, for operation in the cryogenic temperature range, comprising a microelectrical quantum computing component and another microelectrical component. The microelectrical quantum computing component comprises a substrate structure, for example, made of silicon and / or silicon dioxide, with a plurality of first contact elements and a plurality of conductive vias, for example, through-silicon vias (TSVs), through the substrate structure.

[0014] According to one embodiment of the present invention, the filler element fills the conductive feedthroughs at least partially or completely with an electrically conductive material, such as tungsten. For example, the filler element can also comprise an electrically conductive material such as niobium (Ni), tantalum (Ta), titanium nitride (TiN), platinum (Pt), palladium (Pd), nickel (Ni), copper (Cu), aluminum (Al), titanium (Ti), or lead (Pb), or an electrically conductive alloy.

[0015] By filling the conductive feedthroughs (TSVs) at least partially or completely (except for the superconducting layer element) with the electrically conductive filler element, such as tungsten, a high conductivity of the TSVs can be achieved even at relatively high temperatures (in the cryogenic temperature range) above the transition point of superconductivity, in comparison to, for example, titanium nitride-metallized TSVs. This allows for relatively simple testability of the microelectronic components and verification of their functionality even before the microelectronic components are used at application temperatures below the transition temperature for superconductivity. Due to the high conductivity of the tungsten-filled feedthroughs (TSVs), a reliable functional test can be carried out even in a temperature range around 70°K (nitrogen temperature), i.e.below the boiling point of nitrogen at 77.4 K (-195.8 °C).

[0016] For example, at least partially filled TSVs can be filled with an electrically conductive material, such as tungsten, to at least 20%, 50%, 70%, 90%, or even completely. The greater the filling level of the TSVs with tungsten, the higher the conductivity of the TSVs at temperatures above the transition point of superconductivity.

[0017] In general, cryogenics covers the temperature range below -150 °C. Technically accessible temperatures are below 77.4 K (-195.8 °C), the boiling point of nitrogen, 20.4 K (for example, using hydrogen), and 4.2 K (for example, using helium). Lower temperatures in the cryogenic temperature range can be achieved, for example, by reducing pressure and the associated change in boiling points. Furthermore, it is possible to reach a temperature of approximately 1 K using helium. To achieve correspondingly lower temperatures, for example, approximately 1 mK, a comparatively expensive isotope, 3He, or a helium mixture is used.Due to the fact that copper does not become superconducting in any temperature range, the conductive feedthroughs (TSVs) are filled with the layer element that is superconducting at a quantum computer operating temperature and with the fill element that is electrically conductive, so that a correspondingly high electrical conductivity can be provided both within the cryogenic temperature ranges and outside the cryogenic temperature ranges.

[0018] The layer element can, for example, comprise one or more of the following materials: tungsten, technetium, tantalum, niobium, Nb 3 Ge, MoN, MgB 2 , K 3 C 60 , gallium, lead, AuPb, aluminum, (and the following metallic nitrides) TiN, ZrN, HfN, VN, NbN, TaN, MoN, WN. Of these, NbN has the highest critical temperature with T C ~ 17K, while TiN has a transition temperature T C ~ 4.8K.

[0019] The test mode of the quantum computing device, for example, comprises a temperature range at room temperature from, for example, 295.15 K (at 22°C) to, for example, 203.15 K (-70°C). The cooling mode of the quantum computing device, for example, comprises a temperature range from the corresponding 203.15 K (-70°C) to the corresponding 10 K (-263.15°C). In other words, during the cooling mode, the temperature of the quantum computing device is cooled from room temperature or the temperature of the test mode to the operating temperature, corresponding to the operating mode of the quantum computing device. The operating mode, for example, comprises a temperature range below 10 K or starting or partially overlapping from 10 K (-263.15°C) to, for example, 0.001 K (-273.149°C).

[0020] In summary, the test mode of the cryogenic-compatible quantum computing device is carried out in a relatively easy-to-adjust temperature range, utilizing the high electrical conductivity of the filler material of the conductive feedthroughs, while the operating mode is carried out in the cryogenic temperature range, utilizing the superconductivity of the layer element of the conductive feedthroughs.

[0021] According to the present invention, the layered element may comprise a beta modification of tungsten, and the filler element may comprise a tungsten material. Tungsten becomes superconducting at a temperature of approximately 0.015 K (15 mK) and below, while the beta tungsten modification already becomes superconducting at a temperature of approximately 4 K and below. Titanium nitride itself also becomes superconducting at low temperatures (approximately 1.6 K). Furthermore, the layered element may additionally comprise a niobium material, a titanium nitride material, and a tantalum material. The superconductivity of the aforementioned materials is thus achieved in the operating mode of the quantum computing device.

[0022] To preserve the β-modification of tungsten during manufacturing, TSVs are filled with a layer stack that permanently compresses the tungsten. For example, to preserve the beta-modification of the tungsten of the layer element, the tungsten can be arranged as a layer in the conductive vias of the substrate, with, for example, another layer of a further material having a higher coefficient of thermal expansion than the tungsten material being arranged adjacent to the layer element of the beta-tungsten material. This is the case, for example, when using tungsten with an adjacent titanium nitride layer (as the further layer) or between titanium nitride layers (as the further layers).

[0023] According to a further exemplary embodiment outside the invention, the layer stack can also comprise niobium (as a layer element) with an adjacent titanium nitride layer (as the further layer) or can be arranged between titanium nitride layers (as the further layers), or can comprise tantalum (as a layer element) with an adjacent titanium nitride layer (as the further layer) or can be arranged between titanium nitride layers (as the further layers). For example, the further layer or layers can comprise tungsten disulfide (WS2), platinum (Pt), palladium (Pd), nickel (Ni), aluminum (Al), and / or aluminum oxide (Al2O3) in addition to (= instead of) titanium nitride (TiN). The layer thicknesses of the layer stack and the filler element can at least partially fill the through-hole and, taken together, correspond to the cross-section of the through-hole.Using the method according to the invention, which will be explained in the further course of the description, for example, both the layer stack mentioned above and the tungsten can be deposited into the through-hole.

[0024] The conductive vias (TSVs) are electrically connected to associated first contact elements of the microelectrical quantum computing component at a first main surface region of the substrate structure. For example, each individual via of the microelectrical quantum computing component is associated with a respective first contact element. In other words, each individual conductive via on the first main surface of the substrate structure can be associated with a first contact element and electrically connected. The further microelectrical component comprises a plurality of second contact elements that are associated with and electrically connected to the conductive vias (TSVs) on a second main surface region of the substrate structure of the microelectrical quantum computing component.Thus, an electrical connection is provided from the first contact elements of the microelectronic quantum computing component to the second contact elements of the further microelectrical component.

[0025] According to a further embodiment, the contact elements are designed as bond bumps or bond pillars. In other words, the contact elements, which serve as an electrical connection between the microelectrical quantum computing component and the further microelectrical component, can, for example, have a correspondingly spherical or columnar shape and an angular (e.g., rectangular), round (e.g., circular), and / or elliptical cross-sectional shape, although this list is not intended to be exhaustive. Furthermore, depending on the requirements, it is possible to form the electrical connection as a bump and to maintain it, for example, by means of adhesion, for example by applying an adhesive material between the contact elements and the microelectrical component.

[0026] According to a further embodiment, the contact connection, for example the electrical connection of the conductive feedthroughs, between the contact elements of the microelectric quantum computing component may comprise a cryo-compatible interdiffusion metal connection.

[0027] According to a further embodiment, the contact elements on the second main surface region of the substrate structure have interdiffusion metal connections with the contact elements of the further microelectric component. By having cryo-compatible interdiffusion metal connections between the TSVs and the correspondingly assigned first contact elements and / or second contact elements on the first main surface region of the substrate structure and on the second main surface region of the substrate structure, a correspondingly stable electrical connection can be provided, so that superconductivity can be realized from cryo-compatible materials at the application temperatures of quantum computing, for example, in the range of 10-1000 mK.

[0028] Embodiments provide an arrangement in which the contact elements of the microelectronic quantum computing component are connected to a plurality of TSVs in a parallel circuit, for example, to reduce resistance. For example, by connecting at least part of the arrangement in parallel, a resulting resistance value (conductance) can be adjusted. This means that, depending on the application, the resulting resistance value can be adjusted or reduced accordingly by a defined number of TSVs connected in parallel.

[0029] According to a further embodiment, the plurality of conductive feedthroughs (TSVs) are electrically insulated from the substrate structure by means of an insulating material, for example, on the sidewalls of the feedthroughs, for example, by disposing a dielectric material, for example, a dielectric, between the substrate structure and the TSV. For example, the insulating material and optionally also the tungsten-based layer sequence can be deposited onto the sidewalls of the TSVs using the manufacturing method according to the invention, so that, for example, an interdiffusion metal connection can be created.

[0030] Another embodiment according to the present invention includes conductive vias (TSVs) that have a diameter in the range of 0.8 µm to 1.5 µm. Furthermore, the TSVs can have a minimum TSV spacing between them, ranging from 1.6 µm to 3 µm. For example, the TSV depth into the substrate can be at least 6 µm to 10 µm. Furthermore, the conductive via can have an aspect ratio of 10:1 to 20:1 to achieve the highest possible integration density in the substrate, so that the high wiring density can drive a high number of qubits.

[0031] An embodiment according to the present invention further comprises a method for manufacturing a cryogenic-compatible quantum computing device, for example, for operation in the cryogenic temperature range. For example, the method comprises providing the substrate structure with a plurality of first contact elements. The method further comprises forming conductive vias (TSVs), for example, using Bosch etching, DRIE, or a wet etching process. The method may further comprise applying an insulating layer or an insulating material, for example, to the sidewalls of the vias. For example, the insulating material may comprise silicon dioxide and be applied to the sidewalls of the conductive vias using plasma-enhanced chemical vapor deposition (PECVD).The method may further comprise filling the TSVs with tungsten material into the conductive via using the chemical vapor deposition (PVD) process. The method may further comprise chemical mechanical polishing (CMP) to remove impurities on the microelectric quantum computing component. The method further comprises contacting the first contact elements with the tungsten-filled contact hole and the plurality of second contact elements, so that a three-dimensional structure for controlling ion trap qubits for operation in the cryogenic temperature range can be provided.

[0032] For example, using the method, a cryogenically compatible intermetallic bond with high integration density of TSVs can be provided, based on metal interdiffusion processes and / or solid-liquid diffusion (SLID) processes, allowing the number of controlled ion trap qubits to be increased by more than two orders of magnitude. Advantageously, the use of the method is excellently suited for the scaling required in quantum computers.

[0033] Furthermore, embodiments allow the method to produce or achieve a common layer of two different atom types from formerly separate regions using a metal interdiffusion process, for example, based on the Nb / TiN / Au metal system. For example, the atoms of the first contact element and the atoms of the tungsten material can bond by diffusion to compensate for concentration differences in the materials. This has shown that the integration density in the substrate structure can be increased, allowing the number of controlled ion trap qubits to be increased by more than two orders of magnitude. Therefore, the method is excellently suited for the scaling in the cryogenic temperature range required for quantum computing.

[0034] Embodiments create a cryogenically compatible quantum computing device in which the layer element comprises a compressively strained beta modification of tungsten. Tungsten layers exhibit both the stable body-centered cubic α phase and the metastable β phase.

[0035] Embodiments provide a cryogenically compatible quantum computer arrangement in which, adjacent to the layer element with the beta modification of the tungsten material, another layer with a further material is arranged that has a higher coefficient of thermal expansion than the tungsten material. Thus, the tungsten still exhibits the beta modification even at larger layer thicknesses.

[0036] Embodiments create a cryogenically compatible quantum computer arrangement in which, adjacent to the layer element with the beta modification of the tungsten material, a further layer of another material is arranged on both sides, each layer having a higher coefficient of thermal expansion than the tungsten material. Thus, the tungsten still exhibits the beta modification even at larger layer thicknesses.

[0037] To achieve the high critical temperature of tungsten, it is advantageous if the deposited tungsten always remains under a corresponding compressive stress, for example during the cooling process for the cryogenic temperature range of quantum computing applications. This maintains or stabilizes the metastable β phase of tungsten, which has a higher critical temperature than other tungsten phases, such as the stable body-centered cubic α phase. Preferably, the tungsten layer (beta-tungsten layer) can be embedded between materials that have a higher coefficient of thermal expansion than tungsten, such as titanium nitride (TiN), tungsten disulfide (WS 2 ), platinum (Pt), palladium (Pd), nickel (Ni), aluminum (Al) and / or aluminum oxide (Al 2 O 3 ).

[0038] According to a further embodiment of the present invention, the method can be performed in the manufacturing process during the front-end-of-line (FEOL) processes or during the back-end-of-line (BEOL) processes. For example, the bonding can take place in the FEOL using solid-liquid interdiffusion soldering (SLID).

[0039] The method is based on the same considerations as the device described above and can optionally be supplemented with all features, functionalities, and details that are also described herein with regard to the device according to the invention. The method can be supplemented with the aforementioned features, functionalities, and details both individually and in combination.

[0040] In this respect, the invention concept delivers a cryogenically compatible quantum computing setup with relatively little effort, offering an improved compromise between scaling, temperature range of superconductivity, and implementation effort. Furthermore, the effort (and resulting costs) of testing can be kept low due to the cryogenic environment. Short description of the characters

[0041] Exemplary embodiments are explained below with reference to the accompanying drawings. They show: Fig. 1A shows a schematic sectional view of a cryo-compatible quantum computing arrangement according to an embodiment; Fig. 1B shows a schematic sectional view of the conductive feedthrough of the cryo-compatible quantum computing arrangement with a layer element and a filling element according to an embodiment; Fig. 2 shows a schematic sectional view of a conductive feedthrough with an insulating material and a tungsten material according to an embodiment; Fig. 3 shows a schematic sectional view of a conductive feedthrough with a layer stack on each of the side walls according to an embodiment; Fig. 4 shows a schematic sectional view of a conductive feedthrough with interconnected layer stacks according to an embodiment; Fig. 5 shows a schematic sectional view of a conductive feedthrough with a further embodiment of a layer stack according to an embodiment, and Fig.6 shows an exemplary basic flow diagram of the manufacturing method according to the invention according to an embodiment. Detailed description of embodiments of the invention

[0042] Before the following embodiments of the present invention are explained in more detail with reference to the drawings, it is pointed out that identical, functionally identical or equivalent elements, objects and / or structures in the different figures are provided with the same reference numerals, so that the description of these elements shown in different embodiments is interchangeable or can be applied to one another.

[0043] The exemplary embodiments described below are described in conjunction with a multitude of details. However, exemplary embodiments can also be limited without these detailed features. Furthermore, for clarity, exemplary embodiments are described using sectional views as a substitute for a detailed illustration. Furthermore, details and / or features of individual exemplary embodiments can easily be combined with one another, unless explicitly stated otherwise.

[0044] It is understood that when an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "coupled" to another element, no intervening elements are present. Other terms used to describe the relationship between elements should be interpreted similarly (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0045] Within the scope of the description presented, elements made of a specific material or material combination comprise at least 90%, 95%, or 99% of the specified material or material combination, or even completely. Thus, the specified materials may also contain another component or components (materials) to the specified small extent. This can occur, for example, due to application processes, etc.

[0046] To simplify the description of the various embodiments, the figures feature a Cartesian coordinate system x, y, z, with the directions x, y, z being arranged orthogonally to one another. In the embodiments, the xy plane corresponds to the main surface area of ​​a carrier or substrate (= reference plane = xy plane), with the vertical upward direction relative to the reference plane (xy plane) corresponding to the "+z" direction, and the vertical downward direction relative to the reference plane (xy plane) corresponding to the "-z" direction. In the following description, the term "lateral" means a direction parallel to the x and / or y direction, i.e., parallel to the xy plane, with the term "vertical" indicating a direction parallel to the + / -z direction.

[0047] Fig. 1shows a cryo-compatible quantum computing arrangement 100. The arrangement 100 comprises a microelectronic quantum computing component 110 with a substrate structure 10, a plurality of first contact elements 20-1, and a plurality of conductive feedthroughs (TSVs) 30 through the substrate structure 10. The conductive feedthroughs 30 are electrically connected, for example, at a first main surface 10-1 of the substrate structure 10 to associated first contact elements 20-1 of the microelectronic quantum computing component 110. Furthermore, the quantum computing arrangement 100 comprises a further microelectronic component 120 with a plurality of second contact elements 20-2, wherein at a second main surface region 10-2 of the substrate structure 10, the conductive feedthroughs 30 are electrically connected to associated second contact elements 20-2 of the further microelectronic component 120.The conductive feedthroughs 30 each have, between the first contact element 20-1 and the second contact element 20-2, a layer element 30-1 with a first material that is superconducting at a quantum computer operating temperature, e.g., below 10 K, and a filling element 30-2 with a second material that is electrically conductive.

[0048] According to one embodiment, the filling element fills at least 50% (or at least 70, 90, or 99%) of the respective volume of the conductive feedthroughs along the cross section between the first and second main surface regions of the substrate structure. The filling element can also completely fill the respective volume (= remaining volume of the feedthroughs provided with the layer element).

[0049] According to one embodiment, the cryo-compatible quantum computing arrangement 100 is provided, for example, for controlling ion-trap qubits in an ion-trap chip and comprises the microelectrical quantum computing component 110 with the substrate structure 10, the plurality of first contact elements 20-1, and the plurality of conductive vias (TSVs) 30 through the substrate structure 10. The conductive vias (TSVs) 30 are filled, for example, with a tungsten-based material in order to provide, for example, greater conductivity of the TSVs 30 even at higher temperatures above the transition point of superconductivity. The TSVs 30 are arranged, for example, on a first main surface 10-1 of the substrate structure 10 such that they are directly arranged and electrically connected to the first contact elements 20-1 of the microelectrical quantum computing component 110.Each individual feedthrough 30 can be assigned to a first contact element 20-1 or directly attached thereto. For example, the plurality of second contact elements 20-2 of the further microelectrical component 120 can be arranged such that each feedthrough 30 is assigned to the second contact elements 20-2 on the second main surface region 10-2 or directly attached thereto. In this way, an electrical connection or a through-hole through the substrate structure 10 can be provided, creating an interconnection or intermediate connection.

[0050] As in Fig. 1AAs shown, the diameter (width) of component 20-1 (corresponding to the x-axis) can differ from the diameter (width) of component 20-2. Alternatively, the diameters of components 20-1 and 20-2 can be of the same size or can be the same, so that, for example, the area of ​​component 20-1 corresponds to the area of ​​TSV 30. This allows the area of ​​the electrical connection to be minimized, so that a high integration density of the through-holes 30 in substrate structure 10 can be achieved. For example, first contact elements 20-1 can differ from second contact elements 20-2 in shape and material, provided they are electrically connected to the associated TSV 30. Additionally or alternatively, contact elements 20-1 and / or 20-2 can be formed as bond bumps or bond pillars, respectively, whereby the electrical connection can be established.

[0051] As further stated in Fig. 1A As shown, a planar substrate structure 10, or planar main surfaces 10-1 and 10-2, is used for a cryogenic quantum computing device 100. Alternatively, an uneven and / or stepped substrate structure 10 can be provided for the conductive vias 30. In some implementations, the thickness "D" of the substrate structure 10 (= vertical extension of the conductive vias 30) can be configured differently (corresponding to the z-axis) using a stepped substrate structure 10, although this is not mandatory.

[0052] The conductive vias (TSVs), for example, have a diameter in the range of 0.8 µm to 1.5 µm. Furthermore, the TSVs can have a minimum TSV spacing between them, ranging from 1.6 µm to 3 µm. For example, the TSV depth into the substrate can be at least 6 µm to 10 µm. Furthermore, the conductive via can have an aspect ratio of 10:1 to 20:1 to achieve the highest possible integration density in the substrate, so that the high wiring density can control a large number of qubits.

[0053] The interconnects are manufactured, for example, using a cryogenically compatible intermetallic bonding process with very high integration density, using metal interdiffusion processes, e.g., based on the Nb / TiN / Au metal system. This approach enables scalability of the contact arrangements in quantum computing applications, since, for example, the number of controlled ion trap qubits can be increased by several orders of magnitude (in principle, arbitrarily) using application-optimized interconnection technology in combination with tungsten TSVs.

[0054] The contact connection between the contact elements 20-1 of the microelectronic quantum computing component 110 can, for example, comprise a cryogenically compatible interdiffusion metal connection. According to one embodiment, interdiffusion metal connections can additionally or alternatively be present at the first main surface region 10-1 of the substrate structure 10 with the contact elements 20-2 of the further microelectronic component 120. The interdiffusion metal connections at the first main surface region 10-1 and at the contact connections between the contact elements 20-1 enable a high integration density of the conductive feedthroughs 30 in the substrate structure 10 of the microelectronic quantum computing component 100 in order to increase the number of ion trap qubits to be controlled.

[0055] According to one embodiment, the contact elements 20-1 of the microelectronic quantum computing component 110 are connected, for example, to a plurality of conductive feedthroughs 30 in a parallel circuit.

[0056] According to one embodiment, the plurality of conductive feedthroughs 30 are electrically insulated from the substrate structure 10, for example by means of an insulating material 34.

[0057] According to one embodiment, the filling element completely fills the conductive feedthroughs 30, for example, with a tungsten material.

[0058] According to one embodiment, the layer element comprises a beta modification of tungsten, wherein the filler element comprises a tungsten material.

[0059] According to one embodiment, to maintain the beta modification of the tungsten of the layer element, the tungsten is arranged as a layer 30-1 in the conductive feedthroughs 30 of the substrate 10, for example, wherein a further layer 5; 7 of a further material having a higher thermal expansion coefficient than the tungsten material is arranged adjacent to the layer element of the beta-tungsten material 30-1.

[0060] According to one embodiment, adjacent to the layer element with the beta modification of the tungsten material 30-1, for example, a further layer 5; 7 with a further material is arranged, which has a higher thermal expansion coefficient than the tungsten material.

[0061] According to one embodiment, adjacent to the layer element with the beta modification of the tungsten material 30-1, for example, a further layer 5; 7 with a further material is arranged on both sides, each of which has a higher thermal expansion coefficient than the tungsten material.

[0062] As already explained, at least partially or completely filling the TSVs with tungsten also increases their conductivity at temperatures already higher than the transition point of superconductivity. Titanium nitride has significantly poorer conductivity in this temperature range. The superconductivity of TSVs can therefore be achieved in the temperature range of 10–1000 mK used in quantum computing. Furthermore, a functional test of the tungsten-filled or lined feedthroughs (TSVs) of the cryogenic quantum computing device can be reliably performed at temperatures around 70°K (nitrogen temperature) before the interconnections or rewiring are used at application temperatures below superconductivity. This simplifies the complex, cost-intensive testing and thus significantly reduces the production costs of the ion trap chip.Furthermore, the cryogenic-compatible quantum computing device can be tested at the wafer level, for example, on a die-on-chip wafer, and then deployed functionally at the cryogenic temperatures of the quantum computing application. This eliminates the need for complex testing in special cryogenic test systems at temperatures below superconductivity. In other words, the complex cooling using helium, for example, helium-3 or helium-4, for the cryogenic temperature range below the transition point for superconductivity can be avoided.

[0063] Fig. 1Bshows a schematic sectional view of the conductive feedthrough 30 with a layer element 30-1 and a filler element 30-2 according to an embodiment. For example, the filler element 30-2 can fill at least 50% of the respective volume of the conductive feedthroughs 30 along the cross section between the first main surface region 10-1 and the second main surface region 10-2 of the substrate structure 10. The conductive feedthroughs 30 run as already shown in Fig. 1Ashown between the first and second contact elements and, as already explained, extend through the entire substrate structure 10. For example, the layer element 30-1 can comprise a first material that is superconducting at a quantum computer operating temperature, i.e., in the operating mode of the quantum computing arrangement. The fill element 30-2 comprises an electrically conductive material or an electrically conductive alloy, such as tungsten, niobium (Ni), tantalum (Ta), titanium nitride (TiN), platinum (Pt), palladium (Pd), nickel (Ni), copper (Cu), aluminum (Al), titanium (Ti), or lead (Pb), or an electrically conductive alloy. This list is not intended to be exhaustive.

[0064] The layer element 30-1 of the TSVs 30, which is superconducting at cryogenic temperatures, can be, for example, tungsten layers with a beta structure or sandwich structures made of thin tungsten and other thin layers of cryo-compatible materials in order to realize superconductivity at the application temperatures of the quantum computer (10-1000 mK range) in helium or helium-mixed cryostats.

[0065] In a layer stack 8 with the layer element 30-1 and a further adjacent layer or multiple layers, the layer element can, for example, comprise tungsten with an adjacent titanium nitride layer (as the further layer) or can be arranged between titanium nitride layers (as the further layers). Furthermore, the layer stack can also comprise niobium (as a layer element) with an adjacent titanium nitride layer (as the further layer) or can be arranged between titanium nitride layers (as the further layers) or can comprise tantalum (as a layer element) with an adjacent titanium nitride layer (as the further layer) or can be arranged between titanium nitride layers (as the further layers). For example, the further layer or the further layers can comprise tungsten disulfide (WS2), platinum (Pt), palladium (Pd), nickel (Ni), aluminum (Al) and / or aluminum oxide (Al2O3) in addition to (= instead of) titanium nitride (TiN).According to one exemplary embodiment, the layer element 30-1 or the layer stack 8 comprising the layer element 30-1 can cover part of the wall region or the entire wall region of the feedthrough 30 as a layer, while the filler element 30-2 at least partially (at least 50%) or completely fills the remaining volume of the feedthrough 30. The layer element 30-1 or the layer stack can thus partially or regionally (or laterally completely) enclose the filler element 30-2 between the first contact element 20-1 and the second contact element 20-2, with both the layer element 30-1 and the filler element 30-2 extending from the first contact element 20-1 to the second contact element 20-2 and connecting them to one another.According to a further exemplary embodiment, the layer element 30-1 or the layer stack comprising the layer element can completely cover the wall region of the feedthrough 30 as a layer, while the filler element 30-2 at least partially (at least 50%) or even completely fills the remaining volume of the feedthrough 30. The layer element 30-1 can also completely enclose the filler element 30-2 (e.g., in a jacket-like manner), with both the layer element 30-1 and the filler element 30-2 extending from the first contact element 20-1 to the second contact element 20-2 and connecting them to one another.

[0066] Fig. 2shows a schematic sectional view of a TSV 30 formed continuously in the substrate structure 10. According to one embodiment, the TSVs 30 can be electrically insulated from the substrate structure 10 by means of an insulating material 34 or an insulating layer on the side walls 30-3 and 30-4 of the feedthroughs 30 and can be at least partially or completely filled with the filling element 30-2 and the layer element 30-1. Fig. 2illustrates, for example, the insulated conductive feedthrough 30, which is completely filled with a tungsten material. For example, the insulating material 34 can comprise silicon dioxide, glass, plastic, and / or titanium nitride. By means of the insulating material 34 on the sidewalls 30-3 and 30-4 of the feedthrough 30, electrical isolation can be enabled, so that the electrically conductive connection from the first contact elements 20-1 to the second contact elements 20-2 can be provided. For example, the contact elements 20-1 of the microelectric quantum computing component 110 can be connected to a plurality of TSVs 30 in a parallel circuit, for example, to reduce resistance. Embodiments further provide that the filling element 30-2 or the layer element 30-1 is attached directly adjacent to the insulating layer 34.In addition, it is possible that, for example, TSVs that can be connected in parallel in sections or individually can be interconnected (connected to one another), for example by providing an area, a row or arrangement, e.g. nxm with n ≥ 2 and m ≥ 2 and n, m are integers, such as 2x2, 3x3, 4x4 or 5x5, etc., of TSVs that can be connected in parallel.

[0067] Fig. 3shows a schematic sectional view of a cryogenically compatible quantum computing arrangement according to an embodiment with a layer stack 8 on the side walls 30-3 and 30-4 of the TSVs 30. The visible stack 8 comprises the layer element 30-1 and the other adjacent layers 5, 7. The tungsten material can have different structures or phases using the method, temperature, and application according to the invention. As already explained, the tungsten phases (alpha phase and beta phase) have different transition temperatures. In other words, tungsten in the alpha phase or in the alpha structure has a lower transition temperature than the beta structure or in the beta phase of tungsten. In order to keep the implementation effort as low as possible, the beta structure (beta phase) of tungsten is preferable to alpha tungsten, so that the highest possible transition temperature of tungsten is achieved.The superconductivity of TSVs can thus be achieved in the temperature range of 10–1000 mK, the application temperature for quantum computing. Furthermore, functional testing of the tungsten-based feedthroughs (TSVs) of the cryogenic-compatible quantum computing array can be reliably performed at temperatures around 70°K (nitrogen temperature).

[0068] According to embodiments, to achieve the high critical temperature of tungsten, the tungsten is constantly kept under compressive stress during the cooling process. This allows the beta phase of the tungsten to be obtained, which has a higher critical temperature than other tungsten phases. Therefore, the tungsten layer 30-1 is embedded between another layer 5 and 7 of another material that has a higher thermal expansion coefficient than the tungsten material 30-1.

[0069] As in Fig. 3As shown, the tungsten layer 30-1 is embedded between the further layer 5 with a higher thermal expansion coefficient than tungsten and the further layer 7 with a higher thermal expansion coefficient than tungsten, so that, for example, a sandwich layer stack 8 is created. In this way, the layer stack 8 can be deposited layer by layer onto the insulation layer 34 using a deposition method, for example the tungsten vapor deposition method. As already explained, the further layer 5, the further layer 7 or both further layers 5 and 7 can comprise titanium nitride (TiN), tungsten disulfide (WS 2 ), platinum (Pt), palladium (Pd), nickel (Ni), aluminum (Al) and / or aluminum oxide (Al 2 O 3 ).

[0070] In a layer stack 8 with the layer element 30-1 and a further adjacent layer 5 or a plurality of layers 5, 7, the layer element 30-1 can therefore, for example, comprise tungsten with an adjacent titanium nitride layer (as the further layer 5 or 7) or be arranged between titanium nitride layers (as the further layers 5 and 7). Furthermore, the layer stack 8 can also comprise niobium (as layer element 30-1) with an adjacent titanium nitride layer (as the further layer 5 or 7) or be arranged between titanium nitride layers (as the further layers 5 and 7) or tantalum (as layer element 30-1) with an adjacent titanium nitride layer (as the further layer 5 or 7) or be arranged between titanium nitride layers (as the further layers 5 and 7). For example, the further layer 5 or 7 orthe further layers 5 and 7 comprise, in addition to (= instead of) titanium nitride (TiN), tungsten disulfide (WS2), platinum (Pt), palladium (Pd), nickel (Ni), aluminum (Al) and / or aluminum oxide (Al2O3).

[0071] Fig. 4 illustrates a cryo-compatible quantum computing arrangement according to a further embodiment with two layer stacks 8 next to each other, which are directly connected to each other, for example. The quantum computing arrangement comprises, as already described in Fig. 5 shown a substrate structure 10, an insulation material 34 in the TSV 30, or between the substrate structure 10 and the further layer 5, and a layer element 30-1 (e.g. a tungsten layer etc.). In contrast to the in Fig. 3In contrast to the layer stacks 8 shown, embodiments further provide for the layer stacks 8 to be connected directly to one another. For example, the layer stack 8 can cover the wall area of ​​the feedthrough 30 such that the feedthrough is (e.g., completely) filled. As shown in Fig. 4 As shown, the further layer 7 in the TSV 30 can accordingly contain two layers. Additionally or alternatively, the material of layer 7 can have a correspondingly thick layer to form the filling element 30-2, or, for example, like the layer thicknesses of the further layer 5 and / or the layer element 30-1 (e.g., the tungsten layer), whereby this is only exemplary.

[0072] Furthermore, embodiments allow a quantum computing arrangement according to an embodiment to comprise only one further layer 7. In contrast to the representation in Fig. 4 shows the representation in Fig. 5a quantum computing arrangement with only a single additional layer 7 (corresponding, for example, to the filler element 30-2), which has a higher thermal expansion coefficient than tungsten. Furthermore, it is possible to deposit the respective layers 34, 5, 30-1, and 7 such that the tungsten layer 30-1 comprises the largest possible proportion of the material of the conductive feedthrough 30, for example, in the range of 50% to 99%, or 60% to 90%, or 70% to 80%. This allows the electrical properties of the electrical connection to be defined, for example, by dimensioning the tungsten layer 30-1 according to the quantum computing requirements.

[0073] The Fig. 5 The layers 5, 7, 30-1, 30-2, 34 etc. shown can also be used to Fig. 4The quantum computing arrangement allows for particularly simple fabrication of a three-dimensional structure for controlling ion-trap quibits in an ion-trap chip. This is because, on the one hand, the microelectronic components can be tested at cryogenic temperatures before use, and, on the other hand, a high integration density of the TSVs based on metal interdiffusion processes is achieved in order to control as many ion-trap qubits as possible.

[0074] Fig. 6shows a method 200 for manufacturing a cryogenically compatible device according to one embodiment. The method comprises providing 210 a microelectronic quantum computing component having a substrate structure, a plurality of first contact elements, and a plurality of conductive vias through the substrate structure, wherein the conductive vias each comprise a layer element comprising a first material that is superconducting at a quantum computer operating temperature and a fill element comprising a second material that is electrically conductive.The method further comprises forming 220 an electrical connection between the conductive feedthroughs on a first main surface region of the substrate structure and the associated first contact elements of the microelectronic quantum computing component, and providing 230 a further microelectronic component with a plurality of second contact elements. The method further comprises forming 240 a further electrical connection on a second main surface region of the substrate structure between the conductive feedthroughs with associated second contact elements and the further microelectronic component.

[0075] According to embodiments, the step 210 of providing the conductive feedthroughs comprises, for example, applying 250 the tungsten material of the layer element under compressive stress in feedthroughs in order to achieve the beta modification of the tungsten material and at least partially or completely filling 260 the feedthroughs with a tungsten material in order to obtain the conductive feedthroughs.

[0076] Furthermore, the method comprises, for example, arranging 270 a further layer with a material having a higher coefficient of thermal expansion than the tungsten material, adjacent to the layer element with the beta modification of the tungsten material.

[0077] Furthermore, the method comprises, for example, arranging 280 on both sides of a further layer with a material having a higher coefficient of thermal expansion than the tungsten material, adjacent to the layer element with the beta modification of the tungsten material.

[0078] The TSVs are completely filled using tungsten vapor deposition, e.g., tungsten hexafluoride and hydrogen gas. Completely filling the TSVs advantageously achieves greater conductivity than TiN-wetted TSVs at temperatures above the transition point of superconductivity. This significantly facilitates the testability of the integrated microelectronic components before they are deployed at application temperatures below superconductivity. This significantly simplifies the typically cost-intensive testing and thus significantly reduces the production costs of the integrated quantum chip system. Furthermore, the systems (quantum chips) can be tested at the wafer level (or die-on-wafer) without restriction of generality and constructed using the conventional known-good-die strategy, and then deployed functionally at the cryogenic temperatures of quantum computing applications.This advantageously eliminates the need for very cost-intensive testing in special cryogenic test systems at temperatures below superconductivity.

[0079] To achieve the highest possible critical temperature of the tungsten, it is advantageous if the deposited tungsten remains under compressive stress during the system's cooling process. This preserves the β-phase of tungsten, which has a higher critical temperature than other tungsten phases. For this purpose, it is advantageous if the tungsten layer is embedded between materials with a higher coefficient of thermal expansion than tungsten, for example, titanium nitride (TiN), tungsten disulfide (WS 2 ), platinum (Pt), palladium (Pd), nickel (Ni), aluminum (Al), and / or aluminum oxide (Al 2 O 3 ).

[0080] Although some aspects of the present disclosure have been described as features in the context of a device, it is clear that such a description may also be considered a description of corresponding method features. Although some aspects have been described as features in the context of a method, it is clear that such a description may also be considered a description of corresponding features of a device or the functionality of a device.

[0081] In the foregoing Detailed Description, various features have been grouped together in examples in order to streamline the disclosure. This manner of disclosure should not be interpreted as intending that the claimed examples include more features than are expressly recited in each claim. Rather, as the following claims reflect, the subject matter may lie in fewer than all of the features of a single disclosed example. Accordingly, the following claims are hereby incorporated into the Detailed Description, with each claim being capable of standing as its own separate example.While each claim may stand as its own separate example, it should be noted that although dependent claims in the claims refer to a specific combination with one or more other claims, other examples also include a combination of dependent claims with the subject matter of any other dependent claim or a combination of any feature with other dependent or independent claims. Such combinations are intended to be encompassed unless it is stated that a specific combination is not intended. Furthermore, it is intended to encompass a combination of features of a claim with any other independent claim, even if that claim is not directly dependent on the independent claim.Although specific embodiments have been shown and described herein, it will be apparent to one skilled in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and illustrated therein without departing from the scope of the present application. This application text is intended to cover all adaptations and variations of the specific embodiments described and discussed herein. Therefore, the scope of the present application is limited only by the language of the claims. References:

[0082] EP 2 876 435 B1 US 6,548,391 Tao et al., "3D Integration of CMOS-Compatible Surface Electrode Ion Trap and Silicon Photonics for Scalable Quantum Computing," 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2019, pp. 1735-1743, doi: 10.1109 / ECTC.2019.00266 Yost et al., "Solid-state qubits integrated with superconducting through-silicon vias", npj Quantum Information (2020) 59 K. Grigoras et al., "Superconducting TiN through-silicon-vias for quantum technology; IEEE 2019 21st Electronics Packaging Technology Conference" LITA et al.: Tuning of Tungsten Thin Film Superconducting Transition Temperature for Fabrication of Photon Number Resolving Detectors; IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 15, NO,.2, JUNE 2005

Claims

1. Cryo-compatible quantum computing arrangement (100), comprising: a microelectronic quantum computing component (110) with a substrate structure (10), a plurality of first contact elements (20-1), and a plurality of conductive feedthroughs (30) through the substrate structure (10), wherein the conductive feedthroughs (30) are electrically connected at a first main surface region (10-1) of the substrate structure (10) to associated first contact elements (20-1) of the microelectronic quantum computing component (110), and a further microelectronic component (120) with a plurality of second contact elements (20-2), wherein the conductive feedthroughs (30) are electrically connected at a second main surface region (10-2) of the substrate structure (10) to associated second contact elements (20-2) of the further microelectronic component (120), and characterized in that the conductive feedthroughs (30) each comprise, between the first contact element (20-1) and the second contact element (20-2), a layer element (30-1) with a first material with a beta-modification of tungsten, which is superconducting at a quantum computer operating temperature below the transition temperature for the superconductivity, and a filling element (30-2) with a second material, which is electrically conductive above the transition temperature for the superconductivity.

2. Arrangement according to claim 1, wherein the layer element (30-1) constitutes a part of the wall region or the entire wall region of the feedthrough (30), and wherein the filling element (30-2) fills at least 50% of the respective volume of the conductive feedthroughs (30) along the cross section between the first main surface region (10-1) and the second main surface region (10-2) of the substrate structure (10).

3. Arrangement according to claim 1 or 2, wherein the contact elements (20-1; 20-2) are formed as bond bumps or bond pillars.

4. Arrangement according to one of the preceding claims, wherein the contact connection between the contact elements (20-1) of the microelectronic quantum computing component (110) comprises a cryo-compatible connection manufactured by a metal interdiffusion method.

5. Arrangement according to one of the preceding claims, wherein the contact elements (20-1) at the first main surface region (10-1) of the substrate structure (10) comprise connections, manufactured by a metal interdiffusion method, to the contact elements (20-2) of the further microelectronic component (120).

6. Arrangement according to one of the preceding claims, wherein the contact elements (20-1) of the microelectronic quantum computing component (110) are connected to a plurality of conductive feedthroughs (30) in a parallel circuit.

7. Arrangement according to one of the preceding claims, wherein the plurality of conductive feedthroughs (30) are electrically insulated from the substrate structure (10) by means of an insulation material (34).

8. Arrangement according to one of the preceding claims, wherein the filling element (30-2) completely fills the conductive feedthroughs (30) in each case with a tungsten material.

9. Arrangement according to one of the preceding claims, wherein the filling element (30-2) comprises a tungsten material.

10. Arrangement according to claim 9, wherein, in order to maintain the beta-modification of the tungsten of the layer element (30-1), the tungsten is arranged as a layer in the conductive feedthroughs (30) of the substrate (10), wherein, adjacent to the layer element (30-1) with the beta-modification of the tungsten material, a further layer (5; 7) of a further material having a higher coefficient of thermal expansion than the tungsten material is arranged.

11. Arrangement according to claim 9 or 10, wherein, adjacent to the layer element (30-1) with the beta-modification of the tungsten material, a further layer (5; 7) with a further material having a higher coefficient of thermal expansion than the tungsten material is arranged.

12. Arrangement according to claim 11, wherein, adjacent to the layer element (30-1) with the beta-modification of the tungsten material, a further layer (5; 7) with a further material having a higher coefficient of thermal expansion than the tungsten material is arranged in each case on both sides.

13. Method (200) for providing a cryo-compatible quantum computing arrangement, the method comprising: providing (210) a microelectronic quantum computing component with a substrate structure, a plurality of first contact elements, and a plurality of conductive feedthroughs through the substrate structure, wherein the conductive feedthroughs each comprise a layer element with a first material with a beta-modification of tungsten, which is superconducting at a quantum computer operating temperature below the transition temperature of the superconductivity, and a filling element with a second material, which is electrically conductive above the transition temperature of the superconductivity, configuring (220) an electrical connection between the conductive feedthroughs at a first main surface region of the substrate structure and the associated first contact elements of the microelectronic quantum computing component, providing (230) a further microelectronic component with a plurality of second contact elements, and configuring (240) a further electrical connection at a second main surface region of the substrate structure between the conductive feedthroughs with associated second contact elements and the further microelectronic component.

14. Method according to claim 13, wherein the step (210) of providing the conductive feedthroughs comprises the following substeps: applying (250) the tungsten material of the layer element under compressive stress in feedthroughs in order to achieve the beta-modification of the tungsten material; and at least partially or completely filling (260) the feedthroughs with a tungsten material in order to obtain the conductive feedthroughs.

15. Method according to claim 14, further comprising: arranging (270), adjacent to the layer element with the beta-modification of the tungsten material, a further layer with a material having a higher coefficient of thermal expansion than the tungsten material.

16. Method according to claim 14 or 15, further comprising: arranging (280), adjacent to the layer element with the beta-modification of the tungsten material, a further layer with a material having a higher coefficient of thermal expansion than the tungsten material in each case on both sides.