Display substrate, display board and display device

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of the Chinese Patent Application No. 201721170305.2 filed on September 12, 2017.TECHNICAL FIELD

[0002] The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device.BACKGROUND

[0003] An array substrate generally includes a base substrate and a plurality of pixel units disposed on the base substrate and arranged in an array. Each of the pixel units includes a thin film transistor (TFT) and a pixel circuit electrically connected to the TFT.

[0004] The TFT generally includes an active layer, a drain electrode disposed above the active layer with respect to the base substrate, and an insulating layer between the active layer and the drain electrode. The drain electrode may be electrically connected to the active layer through a via in the insulating layer. In the case of a liquid crystal display, the pixel circuit includes a pixel electrode that forms one of the two electrodes of the liquid crystal capacitor. In the case of an organic light emitting diode (OLED) display, the pixel circuit also includes a pixel electrode (e.g., an anode electrode of an OLED device) on which a pixel defining layer is typically disposed. In either case, the pixel electrode can be electrically connected to the drain electrode of the TFT through the via

[0005] US2005263755A1 provides an organic light emitting display and method of fabricating the same. The organic light emitting display includes a substrate having formed thereon a thin film transistor including a gate electrode, a source electrode, and a drain electrode, a passivation layer formed on the substrate having a contact hole exposing the source or the drain electrode, a first insulating layer pattern formed on a portion of the passivation layer corresponding to an emission region and having a step portion that is higher than the passivation layer on the thin film transistor, a pixel electrode formed on a portion of the passivation layer and on a portion of the first insulating layer pattern that contacts the source or the drain electrode through the contact hole, and a second insulating layer pattern formed on portions of the passivation layer and the pixel electrode that defines the emission region.

[0006] US2016343784A1 provides an OLED display substrate and a manufacture method thereof. The OLED display substrate comprises a substrate, a TFT located on the substrate, a passivation layer located on the TFT, a flat layer located on the passivation layer, a connecting electrode being located on the flat layer and contacting the TFT, an anode being located on the flat layer and covering the connecting electrode, an organic emitting layer located on the anode and a cathode located on the organic emitting layer; the connecting electrode contacts the TFT via the contact hole penetrating the flat layer and the passivation layer; the anode is electrically connected to the TFT via the connecting electrode.

[0007] US2005110021A1 provides an organic light emitting display. The organic light emitting display includes a substrate having a pixel driving circuit region and an opening region. A thin film transistor having source / drain electrodes is positioned on the pixel driving circuit region of the substrate. A passivation insulating layer is positioned on the source / drain electrodes to have a via hole for exposing one of the source / drain electrodes. A pixel electrode is positioned on a bottom surface of the via hole and in contact with the exposed source / drain electrode, and extends onto the passivation insulating layer. A first photosensitive organic insulating layer is positioned within the via hole in which the pixel electrode is formed to fill the via hole and to expose a portion of the pixel electrode around the via hole. An organic emission layer is positioned on the exposed pixel electrode.

[0008] US2014117323A1 provides a thin film transistor array panel. The thin film transistor array panel includes a substrate, a semiconductor that is positioned on the substrate and that has a source area, a drain area, and a channel area, a gate insulating layer that is positioned on the semiconductor, a gate electrode that is positioned on the gate insulating layer and that overlaps the channel area, a first interlayer insulating layer that is positioned on the gate electrode and that has contact holes that expose the source area and the drain area, respectively, of which the source area and the drain area have a same plane pattern as that of the contact holes, and a source electrode and a drain electrode that are positioned on the first interlayer insulating layer and that are connected to the source area and the drain area, through the contact holes, respectively.SUMMARY

[0009] The invention is defined in independent claim 1. Preferred embodiments are defined in the dependent claims.

[0010] According to an aspect of the present disclosure, an array substrate is provided comprising: a base substrate comprising a plurality of pixel regions arranged in an array; a plurality of thin film transistors distributed within respective ones of the plurality of pixel regions, each of the thin film transistors comprising: an active layer located on the substrate; a gate electrode located on the base substrate, the active layer and the gate electrode being stacked on top of each other; a source electrode located above the gate electrode, the source electrode being electrically connected to the active layer through a first via; and a drain electrode located above the gate electrode, the drain electrode being electrically connected to the active layer through a second via, the drain electrode comprising a first portion located in the second via; a passivation layer located on the source electrodes and the drain electrodes, the passivation layer covering the first portions of the drain electrodes; and a plurality of pixel electrodes distributed within respective ones of the plurality of pixel regions and located on the passivation layer, each of the pixel electrodes being electrically connected to a respective one of the drain electrodes through a respective third via that extends through the passivation layer. The drain electrode further comprises a second portion outside the second via, and the pixel electrode is electrically connected to the second portion of the drain electrode through the third via. An orthographic projection of the third via onto the base substrate surrounds an orthographic projection of the second via onto the base substrate.

[0011] In some embodiments, the array substrate further comprises a planarizing layer located on the passivation layer. The planarizing layer is provided with a plurality of fourth vias, an orthographic projection of each of the fourth vias onto the base substrate completely covering an orthographic projection of a respective one of the third vias onto the base substrate. Each of the pixel electrodes comprises a first portion located in the respective third via, a second portion located in a respective one of the fourth vias, and a third portion located on the planarizing layer.

[0012] In some embodiments, the orthographic projection of each of the fourth vias onto the base substrate further completely covers an orthographic projection of a respective one of the second vias onto the base substrate.

[0013] In some embodiments, the orthographic projection of each of the fourth vias onto the base substrate has a shape selected from a group consisting of a circle and a square.

[0014] In some embodiments, a geometric center of the orthographic projection of each of the fourth vias onto the base substrate overlaps a geometric center of the orthographic projection of the respective third via onto the base substrate.

[0015] In some embodiments, the planarizing layer has a thickness of 1 to 4 µm.

[0016] According to the claimed invention, the orthographic projection of the third via onto the base substrate has an annular shape.

[0017] In some embodiments, a geometric center of the orthographic projection of the third via onto the base substrate overlaps a geometric center of the orthographic projection of the second via onto the base substrate.

[0018] In some embodiments, the orthographic projection of the third via onto the base substrate partially overlaps the orthographic projection of the second via onto the base substrate.

[0019] In some embodiments, the array substrate further comprises: a pixel defining layer located on the plurality of pixel electrodes and provided with a plurality of openings, each of the plurality of openings extending through the pixel defining layer to expose a region of a respective one of the plurality of pixel electrodes; a plurality of organic light emitting layers, each located in a respective one of the openings and covering the exposed region of the respective pixel electrode; and a complementary pixel electrode covering the plurality of organic light emitting layers and the pixel defining layer.

[0020] In some embodiments, the pixel defining layer has a thickness of 1 to 3 µm.

[0021] In some embodiments, the second via is tapered toward the base substrate.

[0022] In some embodiments, the second via has a minimum aperture that is greater than three times a depth of the second via.

[0023] In some embodiments, the array substrate further comprises a gate insulating layer sandwiched between the gate electrodes and the active layers.

[0024] In some embodiments, in each of the plurality of thin film transistors, the gate electrode is located farther from the base substrate than the active layer.

[0025] In some embodiments, in each of the plurality of thin film transistors, the gate electrode is located closer to the base substrate than the active layer.

[0026] According to another aspect of the present disclosure, a display panel is provided comprising the array substrate as described above.

[0027] According to yet another aspect of the present disclosure, a display device is provided comprising the display panel as described above.

[0028] These and other aspects of the present disclosure will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings in which: FIG. 1 is a schematic top plan view of a partial region of an array substrate in accordance with an embodiment of the present disclosure; FIG. 2 is a circuit schematic diagram of a partial region of the array substrate of FIG. 1; FIG. 3 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating an exemplary structure of a partial region of the array substrate of FIG. 1; FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating another exemplary structure of a partial region of the array substrate of FIG. 1; FIG. 5 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating yet another exemplary structure of a partial region of the array substrate of FIG. 1; FIG. 6 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating yet still another exemplary structure of a partial region of the array substrate of FIG. 1; and FIG. 7 is a schematic diagram of a display device in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0031] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. Terms such as "before" or "preceding" and "after" or "followed by" may be similarly used, for example, to indicate an order in which light extends through the elements. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It will be understood that when an element or layer is referred to as being "on", "connected to", "coupled to", or "adjacent to" another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to", "directly coupled to", or "immediately adjacent to" another element or layer, there are no intervening elements or layers present. In no event, however, should "on" or "directly on" be construed as requiring a layer to completely cover an underlying layer.

[0034] Embodiments of the disclosure are described herein with reference to schematic illustrations of idealized embodiments (and intermediate structures) of the disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the disclosure.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0036] Embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0037] FIG. 1 is a schematic top plan view of a partial region of an array substrate including an exemplary pixel unit in accordance with an embodiment of the present disclosure. It will be understood that although only a single pixel region is shown in FIG. 1 for convenience of illustration, the array substrate includes a plurality of such pixel regions arranged in an array.

[0038] Referring to FIG. 1, in the pixel region shown, a gate line 10 extends in a row direction, a data line 11 extends in a column direction, intersecting the gate line 10, and a power supply line 12 extends in parallel with the data line 11. The power line 12 includes a first electrode 120 that extends perpendicular to its length. A thin film transistor T 1 is disposed at the intersection of the gate line 10 and the data line 11, and includes a gate electrode G 1 connected to the gate line 10, a source electrode S 1 connected to the data line 11, and a drain electrode D 1 electrically connected to of a gate electrode G 2 of another thin film transistor T 2 through a fifth via V 5 that extends through an interlayer insulating layer 4 and a gate insulating layer 3. The gate electrode G 2 of the thin film transistor T 2 includes an extended portion forming a second electrode 130, wherein the second electrode 130 is disposed opposite to a first electrode 120 to form a storage capacitor. The thin film transistor T 2 further includes an active layer L 2 , a drain electrode D 2 electrically connected to the active layer L 2 through a second via V 2 , and a source electrode S 2 connected to the power supply line 12. The drain electrode D 2 is further electrically connected to a pixel electrode 2 through a third via V 3 .

[0039] FIG. 2 shows an equivalent circuit of the pixel region of FIG. 1, which is a pixel circuit including an organic light emitting diode (OLED). In this example, the pixel electrode 2 in FIG. 1 may be, for example, an anode electrode of the OLED. It will be understood that the pixel circuit of FIG. 2 is merely exemplary and that other embodiments are possible. It will also be understood that the concepts of the present disclosure are not limited to OLED array substrates, but may also be applied to liquid crystal display (LCD) array substrates.

[0040] Referring back to FIG. 1, the thin film transistors T 1 and T 2 may be amorphous silicon TFTs, polysilicon TFTs, or oxide semiconductor TFTs. In the thin film transistor T 1 , the gate electrode G 1 may also be a part of the gate line 10 (i.e., there is no separate gate pattern extending from the gate line 10), and the source electrode S 1 may also be a part of the data line 11 (i.e., there is no separate source electrode pattern extending from the data line 11). Embodiments of the present disclosure are not limited to TFTs of a particular kind and / or structure. By way of example and not limitation, the gate line 10, the gate electrodes G 1 and G 2 , the power supply line 12, the source electrodes S 1 and S 2 , the drain electrodes D 1 and D 2 , and the data line 11 may be made of a metal material such as Cu (copper), Al (aluminum), Mo (molybdenum), Ti (titanium), Cr (chromium), and W (tungsten) or an alloy thereof. In addition, they may be a single layer structure or a multilayer structure, such as a stacked structure of Mo\Al\Mo, Ti\Cu\Ti, and Mo\Ti\Cu.

[0041] FIG. 3 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating an exemplary structure of a partial region of the array substrate of FIG. 1.

[0042] As shown in FIG. 3, the array substrate includes a base substrate 1 on which the active layer L 2 of the thin film transistor T 2 and the gate insulating layer 3 are disposed. The gate insulating layer 3 is sandwiched between the gate electrode G 2 of the thin film transistor T 2 and the active layer L 2 . The active layer L 2 and the gate electrode G 2 are stacked on top of each other. In the example of FIG. 3, the thin film transistor T 2 is a top gate type transistor in which the gate electrode G 2 is located farther from the base substrate 1 than the active layer L 2 . Specifically, the gate insulating layer 3 covers the active layer L 2 , and the gate electrode G 2 is located on the gate insulating layer 3. The interlayer insulating layer 4 is disposed on the gate electrode G 2 . The source electrode S 2 and the drain electrode D 2 of the thin film transistor T 2 are located on the interlayer insulating layer 4. The source electrode S 2 is electrically connected to the active layer L 2 through the first via V 1 extending through the interlayer insulating layer 4 and the gate insulating layer 3, and the drain electrode D 2 is electrically connected to the active layer L 2 through the second via V 2 that extends through the interlayer insulating layer 4 and the gate insulating layer 3. The drain electrode D 2 includes a first portion D 2-1 located in the second via V 2 and a second portion D 2-2 located outside the second via V 2 . A passivation layer 5 is disposed on the source electrode S 2 and the drain electrode D 2 . The passivation layer 5 includes a portion 51 covering the first portion D 2-1 of the drain electrode D 2 . In this example, the portion 51 of the passivation layer 5 is directly on the first portion D 2-1 of the drain electrode D 2 . The pixel electrode 2 is located on the passivation layer 5, and is electrically connected to the drain electrode D 2 through the third via V 3 that extends through the passivation layer 5.

[0043] In this embodiment, the array substrate further includes a pixel defining layer 6 disposed on the pixel electrode 2. The pixel defining layer 6 is provided with an opening 61 extending through the pixel defining layer 6 to expose a region of the pixel electrode 2. An organic light-emitting layer 7 is disposed inside the opening 61 and covers the exposed region of the pixel electrode 2. The array substrate further includes a complementary pixel electrode 8 covering the organic light-emitting layer 7 and the pixel defining layer 6. The complementary pixel electrode 8, the organic light-emitting layer 7, and the pixel electrode 2 form an OLED device. For example, the pixel electrode 2 is the anode of the OLED device and the complementary pixel electrode 8 is the cathode of the OLED device. In some examples, the pixel defining layer 6 may have a thickness of, for example, 1 to 3 µm. This allows the organic light-emitting layer 7 to be provided with a deposition space having a sufficient depth.

[0044] The pixel defining layer 6 is generally prepared from an organic resin material. During the luminescence of the OLED device, residual gases in the resin material may escape from the pixel defining layer 6 due to heat generated by the luminescence.

[0045] In the absence of the passivation layer 5 (particularly the portion 51 of the passivation layer), the gas escaping from the pixel defining layer 6 may pass through a via structure between the pixel electrode 2 and the active layer L 2 (e.g., the second via V 2 and the third via V 3 ) and penetrate into the active layer L 2 . This will affect the stability of the active layer and change the electrical characteristics of the thin film transistor T 2 .

[0046] In contrast, due to the presence of the passivation layer 5 (particularly the portion 51 of the passivation layer 5) between the pixel defining layer 6 and the active layer L 2 , the gas penetration to the active layer L 2 can be blocked, thereby improving the electrical stability of thin film transistor T 2 . As mentioned earlier, this concept is equally applicable to LCD array substrates. Further, other insulating layers (e.g., the gate insulating layer 3 and the interlayer insulating layer 4) may also function to block the gas penetration to the active layer L2.

[0047] The orthographic projection of the third via V 3 onto the base substrate 1 may not overlap with the orthographic projection of the second via V 2 onto the base substrate 1. Given the fact that the pixel electrode 2 is electrically connected to the second portion D 2-2 of the drain electrode D 2 through the third via V 3 (i.e., a portion of the pixel electrode 2 is deposited in the third via V 3 and is in direct contact with the second portion D 2 -2 of the drain electrode D 2 ), in the example shown in FIGS. 1 and 3, the orthographic projection of the third via V 3 onto the base substrate 1 surrounds the orthographic projection of the second via V 2 on the substrate 1, thereby providing a large contact area between the pixel electrode 2 and the second portion D 2-2 of the drain electrode D 2 . This can facilitate the reliability of the electrical contact. In particular, in the example of FIG. 3, the orthographic projection of the third via V 3 onto the base substrate 1 is annular.

[0048] In this embodiment, the geometric center of the orthographic projection of the third via V 3 onto the base substrate 1 overlaps with the geometric center of the orthographic projection of the second via V 2 onto the base substrate 1. In the example of FIG. 3, since the orthographic projection of the third via V 3 onto the base substrate 1 is annular, the geometric center (or shape center) of the orthographic projection is the center of the two circles forming the annular shape (the centers of the two circles coinciding with each other).

[0049] FIG. 4 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating another exemplary structure of a partial region of the array substrate of FIG. 1. The same reference signs as in FIG. 3 denote the same elements.

[0050] As shown in FIG. 4, the orthographic projection of the third via V 3 onto the base substrate 1 overlaps with the orthographic projection of the second via V 2 onto the base substrate 1. Specifically, the orthographic projection of the third via V 3 onto the base substrate 1 may completely cover the orthographic projection of the second via V 2 onto the base substrate 1. This allows an increase in the contact area between the pixel electrode 2 and the second portion D 2-2 of the drain electrode D 2 , thereby improving the reliability of the electrical contact.

[0051] In this embodiment, the second via V 2 is tapered toward the base substrate 1. That is, the aperture of the second via V 2 gradually becomes smaller from top to bottom. In some examples, the minimum aperture of the second via V 2 is greater than three times the depth of the second via V 2 such that the drain electrode metal, when deposited at the second via V 2 , can follow the shape of the second via V 2 to form a recessed portion. Thus, the portion 51 of the passivation layer 5 that covers the drain electrode D 2 can be formed on the recessed portion of the drain electrode D 2 in the second via V 2 , providing a better blocking effect against the gas permeation to the active layer L 2 .

[0052] FIG. 5 is a schematic cross-sectional view taken along line A-A' of FIG. 1, illustrating still another exemplary structure of a partial region of the array substrate of FIG. 1. The same reference signs as in FIG. 3 denote the same elements.

[0053] Unlike the embodiments described above with respect to FIGS. 3 and 4, in the embodiment of FIG. 5, the gate insulating layer 3 is only located in the region of the active layer L 2 that corresponds to the gate electrode G 2 , that is, the gate insulating layer 3 is located only below the gate electrode G 2 . In this case, as shown in FIG. 5, the source electrode S 2 is connected to the active layer L 2 through the first via V 1 extending through the interlayer insulating layer 4, and the drain electrode D 2 is connected to the active layer L2 through the second via V 2 that extends through the interlayer insulating layer 4.

[0054] Other configurations of the array substrate are similar to the embodiment described above with respect to FIG. 3 and will not be described again herein.

[0055] FIG. 6 is a schematic cross-sectional view taken along line A-A' of FIG. 1 illustrating yet another exemplary structure of a partial region of the array substrate of FIG. 1. The same reference signs as in FIG. 3 denote the same elements.

[0056] As shown in FIG. 6, the array substrate further includes a planarizing layer 9 (having a thickness of, for example, 1 to 4 µm) provided on the passivation layer 5. The planarizing layer 9 is provided with a fourth via V 4 corresponding to the third via V 3 . Here, the fourth via V 4 corresponding to the third via V 3 means that the fourth via V 4 can expose the below third via V 3 after the fourth via V 4 is formed in the planarizing layer 9 and the pixel electrode 2 is not yet deposited.

[0057] The pixel electrode 2 is disposed on the planarizing layer 9. The pixel electrode 2 includes a first portion 21 located in the third via V 2 , a second portion 22 located in the fourth via V 4 , and a third portion 23 located on the planarizing layer 9. The first portion 21 of the pixel electrode 2 is in direct electrical contact with the drain electrode second portion D 2-2 . Since a portion of the pixel electrode 2 is deposited in the third via V 3 and the fourth via V 4 , a reliable connection between the first portion 21 of the pixel electrode 2 and the second portion D 2-2 of the drain electrode D 2 can be achieved.

[0058] The pixel defining layer 6 is disposed above the pixel electrode 2. The pixel defining layer 6 is provided with a plurality of openings 61 (only one of them is shown in FIG. 6). Each of the plurality of openings 61 extends through the pixel defining layer 6 to expose a region of a respective pixel electrode 2. In the pixel region shown in FIG. 6, the organic light-emitting layer 7 is disposed inside the opening 61 to cover the exposed region of the pixel electrode 2, and the complementary pixel electrode 8 is provided to cover the organic light-emitting layer 7 and the pixel defining layer 6. The complementary pixel electrode 8, the organic light-emitting layer 7, and the pixel electrode 2 form an OLED device.

[0059] In the example of FIG. 6, the orthographic projection of the fourth via V 4 onto the base substrate 1 completely covers the orthographic projection of the third via V 3 onto the base substrate 1. Further, the orthographic projection of the fourth via V 4 onto the base substrate 1 completely covers the orthographic projection of the second via V 2 onto the base substrate 1. The area of the fourth via V4 is large, providing a good electrical connection between the pixel electrode 2 and the drain electrode D 2 . Here, the orthographic projection of the fourth via V 4 onto the base substrate 1 may be circular or square. Moreover, the geometric center of the orthographic projection of the fourth via V 4 onto the base substrate 1 overlaps with the geometric center of the orthographic projection of the third via V 3 onto the base substrate 1.

[0060] In the embodiments described above, each of the gate insulating layer 3, the interlayer insulating layer 4, and the passivation layer 5 may be made of a silicon nitride or silicon oxide material. Each of them may be a single layer structure or a multilayer structure such as silicon oxide and silicon nitride in a stacked design. The planarizing layer 9 can be fabricated using an organic resin material. The pixel electrode 2 can be fabricated by using transparent metal oxide conductive materials such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-Doped Tin Oxide). In embodiments where the pixel electrode 2 is specifically an anode of the OLED device, the pixel electrode 2 can be fabricated using a transparent metal oxide conductive material. Alternatively, the pixel electrode 2 may also adopt a stacked structure of a transparent metal oxide conductive material and a metal material such as silver (Ag). For example, the pixel electrode 2 may be a three-layer structure of ITO\Ag\ITO. The complementary pixel electrode 8 may be made of a metal material such as aluminum (Al) and / or silver (Ag), and may be a single layer or a stacked structure. Other embodiments are also contemplated.

[0061] It will be understood that although the thin film transistors are shown and described as a top gate transistor in the above embodiments, each of them may be a bottom gate transistor in which the gate electrode is located closer to base substrate 1 than the active layer L 2 .

[0062] FIG. 7 is a block diagram showing a display device 70 in accordance with an embodiment of the present disclosure. By way of example and not limitation, the display device 70 can be any product or component having a display function, such as a cell phone, a tablet, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

[0063] Referring to FIG. 7, the display device 70 includes a display panel 100 for displaying images, a gate driver 200 for outputting gate scan signals to the display panel 100, a data driver 300 for outputting data voltages to the display panel 100, and a timing controller 400 for controlling the gate driver 200 and the data driver 300.

[0064] The display panel 100 includes an array substrate 101 and a counter substrate 102 opposite to the array substrate 101. In the case of a liquid crystal display device, the display panel 100 further includes a liquid crystal layer (not shown) sandwiched between the array substrate 101 and the counter substrate 102, and the counter substrate 102 may be a color filter substrate. In the case of an organic light emitting diode display device, the counter substrate 102 may be a cover plate.

[0065] The array substrate 101 includes a plurality of pixel regions PX arranged in an array. Each of the pixel regions PX is located at a respective intersection of the plurality of gate lines GL and the plurality of data lines DL. Each pixel region includes a pixel that includes a thin film transistor (not shown) and other associated components.

[0066] The gate driver 200 is electrically connected to first ends of the respective gate lines GL, thereby sequentially applying gate scan signals to the respective gate lines GL. In some exemplary embodiments, the gate driver 200 may be directly mounted (e.g., integrated) in the array substrate 101. Alternatively, the gate driver 200 may be connected to the display panel 100 through a Tape Carrier Package (TCP).

[0067] The data driver 300 is electrically connected to first ends of the respective data lines DL to output data voltages to the respective data lines DL. In some embodiments, data driver 300 can include a plurality of data driving chips operating in parallel.

[0068] The timing controller 400 controls the operation of each of the gate driver 200 and the data driver 300. Specifically, the timing controller 400 outputs data control signals and image data to control a driving operation of the data driver 300, and outputs gate control signals to control a driving operation of the gate driver 200. The data control signals and the image data are applied to the data driver 300. The gate control signals are applied to the gate driver 200.

[0069] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be regarded as illustrative and exemplary, rather than restrictive. The present disclosure is not limited to the embodiments disclosed. Variations to the disclosed embodiments can be understood and effected by those skilled in practicing the claimed subject matter, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that the measures cannot be used to advantage.

Claims

1. An array substrate, comprising: a base substrate (1) comprising a plurality of pixel regions arranged in an array; a plurality of thin film transistors (T2) distributed within respective ones of the plurality of pixel regions, each of the thin film transistors (T2) comprising: an active layer (L2) located on the substrate; a gate electrode (G2) located on the base substrate (1), the active layer (L2) and the gate electrode (G2) being stacked on top of each other; a source electrode (S2) located above the gate electrode (G2), the source electrode (S2) being electrically connected to the active layer (L2) through a first via (V1); and a drain electrode (D2) located above the gate electrode (G2), the drain electrode (D2) being electrically connected to the active layer (L2) through a second via (V2), the drain electrode (D2) comprising a first portion (D2-1) located in the second via (V2) and a second portion (D2-2) outside the second via (V2); a passivation layer (5) located on the source electrodes (S2) and the drain electrodes (D2), the passivation layer (5) covering the first portions (D2-1) of the drain electrodes (D2); and a plurality of pixel electrodes (2) distributed within respective ones of the plurality of pixel regions and located on the passivation layer (5), each of the pixel electrodes (2) being electrically connected to a respective one of the drain electrodes (D2) through a respective third via (V3) that extends through the passivation layer (5); wherein the pixel electrode (2) is electrically connected and is directly connected to the second portion (D2-2) of the drain electrode (D2) through the third via (V3); and wherein an orthographic projection of the third via (V3) onto the base substrate (1) surrounds an orthographic projection of the second via (V2) onto the base substrate (1), the orthographic projection of the third via (V3) onto the base substrate (1) is annular, and the orthographic projection of the third via (V3) onto the base substrate (1) does not overlap with the orthographic projection of the second via (V2) onto the base substrate (1).

2. The array substrate of claim 1, further comprising a planarizing layer (9) located on the passivation layer (5), wherein the planarizing layer (9) is provided with a plurality of fourth vias (V4), an orthographic projection of each of the fourth vias (V4) onto the base substrate (1) completely covering an orthographic projection of a respective one of the third vias (V3) onto the base substrate (1), and wherein each of the pixel electrodes (2) comprises a first portion (21) located in the respective third via (V3), a second portion (22) located in a respective one of the fourth vias (V4), and a third portion (23) located on the planarizing layer (9).

3. The array substrate of claim 2, wherein the orthographic projection of each of the fourth vias (V4) onto the base substrate (1) further completely covers an orthographic projection of a respective one of the second vias (V2) onto the base substrate (1).

4. The array substrate of claim 3, wherein the orthographic projection of each of the fourth vias (V4) onto the base substrate (1) has a shape selected from a group consisting of a circle and a square.

5. The array substrate of claim 2, wherein a geometric center of the orthographic projection of each of the fourth vias (V4) onto the base substrate (1) overlaps a geometric center of the orthographic projection of the respective third via (V3) onto the base substrate (1).

6. The array substrate of claim 1, wherein a geometric center of the orthographic projection of the third via (V3) onto the base substrate (1) overlaps a geometric center of the orthographic projection of the second via (V2) onto the base substrate (1).

7. The array substrate of claim 1, further comprising: a pixel defining layer (6) located on the plurality of pixel electrodes (2) and provided with a plurality of openings (61), each of the plurality of openings (61) extending through the pixel defining layer (6) to expose a region of a respective one of the plurality of pixel electrodes (2); a plurality of organic light emitting layers (7), each located in a respective one of the openings (61) and covering the exposed region of the respective pixel electrode (2); and a complementary pixel electrode (8) covering the plurality of organic light emitting layers (7) and the pixel defining layer (6).

8. The array substrate of claim 1, wherein the second via (V2) is tapered toward the base substrate (1).

9. The array substrate of claim 8, wherein the second via (V2) has a minimum aperture that is greater than three times a depth of the second via (V2).

10. The array substrate of claim 1, further comprising a gate insulating layer (3) sandwiched between the gate electrodes (G2) and the active layers (L2).

11. A display panel comprising the array substrate of any one of claims 1 to 10.

12. A display device comprising the display panel of claim 11.