Non-conductive etching stop structures for storage applications with large contact height differential
DE602019086448T2Active Publication Date: 2026-07-08INTEL NDTM US LLC
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Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- INTEL NDTM US LLC
- Filing Date
- 2019-05-09
- Publication Date
- 2026-07-08
AI Technical Summary
Technical Problem
The challenge in 3D NAND memory technology is the non-uniform etching of contact holes across a staircase structure, leading to potential short-circuits and latent defects due to varying contact hole depths, which traditional etch stops fail to address effectively.
Method used
A non-conductive etch stop, composed of high-k dielectric materials or multi-layer structures, is applied over the 3D NAND memory staircase structure to provide differential etch rates, ensuring uniform etching and preventing penetration of underlying wordlines.
Benefits of technology
The etch stop effectively protects wordline material from etching, eliminating non-uniform recess and short-circuits, thereby increasing yield and efficiency in forming contacts of varying depths.
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