Memory boot reset
Patent Information
- Application Number
- DE602020051864
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2019-12-20
- Filing Date
- 2020-12-14
- Publication Date
- 2025-05-21
- Estimated Expiration
- 2040-12-14
AI Technical Summary
Existing power-on-reset (POR) circuitries in memory sub-systems are limited by their inability to accurately monitor power supply voltage due to process-voltage-temperature (PVT) variations, leading to false indications of sufficient voltage levels for resetting, especially when the power supply voltage is low.
A POR component with multiple voltage generators, including a reference voltage generator and a power-up voltage generator, that are designed to be insensitive to PVT variations, ensuring a reliable measurement of the power supply voltage by generating a steady reference voltage and comparing it with the power-up voltage to provide a reset signal only when the power supply is sufficiently high.
This solution reduces instances of false voltage measurements due to PVT variations, ensuring proper reset of the memory sub-system by generating a reliable reset signal only when the power supply voltage is stable and sufficient, thereby enhancing the reliability of the memory sub-system's operation.