STORAGE DEVICE FOR PROVIDING DATA SECURITY

Description

Field of the Invention

[0001] The invention relates to memory devices, and in particular, to a memory device providing data security.Background of the Invention

[0002] Information security has become a great concern of electronic circuits as information technology and communication technology advance. Information security involves preventing unauthorized data access, use, modification, inspection and recording. It is important to maintain information security for memory devices.Summary of the Invention

[0003] The present disclosure aims at providing a memory device providing data security. This is achieved by a memory device according to claim 1. The dependent claims pertain to corresponding further developments and improvements.

[0004] As will be seen more clearly from the detailed description following below, the claimed memory device includes a physically unclonable function (PUF) unit, a controller and a memory array. The PUF unit is used to provide a random bit pool. The controller is coupled to the PUF unit and is used to extract a random bit sequence from the random bit pool. The controller includes a masking engine. The masking engine is used to perform a key derivation function to stretch the extracted random bit sequence and to mask an input signal. The memory array is coupled to the masking engine and is used to store according to the masked input signal.Brief Description of the Drawings

[0005] In the following, the invention is further illustrated by way of example, taking reference to the accompanying drawings. Thereof FIG. 1 is a block diagram of a cryptographic system according to an embodiment of the invention; FIG. 2 is a block diagram of a cryptographic system according to another embodiment of the invention; and FIG. 3 is a block diagram of a cryptographic system according to another embodiment of the invention. Detailed Description

[0006] As used herein, the term "true random" refer to a bit stream or a data sequence that is substantially 50% in a hamming weight and an inter-device (ID) hamming distance, and is substantially 1 in a minimum entropy (min-entropy).

[0007] FIG. 1 is a block diagram of a cryptographic system 1 according to an embodiment of the invention. The cryptographic system 1 may include a memory device 10 and a microprocessor (MCU) 12 coupled thereto. The cryptographic system 1 may be applicable in an internet of things (IoT) network. The MCU 12 may acquire data from an external device or access data from the memory device 10. The external device may be a sensor or a network. The memory device 10 may provide security functions including secure data storage, unique identity generation, true random number generation and secure key storage, thereby saving data processing resources of the MCU 12, protecting data from unauthorized access and enhancing data security.

[0008] The MCU 12 may include a crypto engine 120. The crypto engine 120 may be implemented by software code executable by the MCU 12. The memory device 10 may include a controller 100, a physically unclonable function (PUF) unit 105 and a memory array 106. The controller 100 may be coupled to the MCU 12, the PUF unit 105 and the memory array 106. The controller 100 may include a masking engine 101, a random number generator (RNG) 102 and a unique identifier (UID) unit 103. The masking engine 101, the random number generator 102 and the UID unit 103 may be coupled to the PUF unit 105. The masking engine 101 may be coupled to the memory array 106. The PUF unit 105, the memory array 106 and the controller 100 may form an integrated circuit.

[0009] The crypto engine 120 may perform an authentication process to provide assurance of the authenticity of data access, and hence, to control data access to the memory device 10. Upon verifying an authorized access, the crypto engine 120 may send a security command Cs to the memory device 10 to grant data access to the memory array 106. The memory device 10 may receive the security command Cs, and control the data access to the memory array 106 according to the security command Cs. The memory array 106 may be a NAND flash memory. The data access may be read access and / or write access.

[0010] The PUF unit 105 may store a random bit pool and generate a PUF response from the random bit pool in response to a PUF challenge. The OTP memory may be antifuse-based and the random bit pool may be programmed into the OTP memory during manufacturing setup. The random bit pool may include a plurality of PUF bits that are truly random. The PUF unit 105 may output the PUF response according to a predetermined selecting algorithm. In some embodiments, the PUF unit 105 may select the first 1K PUF bits as the PUF response. In other embodiments, the PUF unit 105 may select PUF bits from rows of memory cells in a predetermined row order, e.g. selecting PUF bits from odd rows in an ascending order, to serve as the PUF response. The PUF unit 105 may include a one-time programmable (OTP) memory. In some embodiments, the one-time programmable memory may be replaced with a non-volatile memory containing a plurality of true random bits. For example, the non-volatile memory may be 64-bit-by-64-bit flash memory cells, and each row, column or diagonal line of the memory cells may contain true random bits. In some embodiments, the plurality of true random bits may be updated regularly.

[0011] The controller 100 may operate the PUF unit 105 and the masking engine 101 to provide secure data storage. Upon receiving the security command Cs of granting data access, the controller 100 may extract a random bit sequence from the random bit pool in the PUF unit 105, the masking engine 101 may perform a key derivation function to stretch the extracted random bit sequence and to mask an input signal with the stretched random bit sequence, and the memory array 106 may store according to the masked input signal. The input signal may include an access address Addr or a data sequence Data. The masking of the input signal with the stretched random bit sequence may be data masking or address masking, and may involve performing an XOR operation on the stretched random bit sequence and the data sequence Data or the access address Addr in a bitwise manner. In data masking, the masking engine 101 may mask the access address Addr with the stretched random bit sequence to generate a derived key, and mask the data sequence Data with the derived key to generate a masked data sequence Datam, and the memory array 106 may store the masked data sequence Datam at the access address Addr. In some embodiments, the masking engine 101 may store the derived key in a local memory for recovering the masked data sequence Datam in a read operation. For example, in a read operation, the masking engine 101 may read the masked data sequence Datam at the access address Addr, mask the masked data sequence Datam with the derived key to recover the data sequence Data, and transmit the data sequence Data to the MCU 12. In address masking, the masking engine 101 may mask the data sequence Data with the stretched random bit sequence to generate a derived key, and mask the access address Addr with the derived key to generate a masked access address Addrm, and the memory array 106 may store the data sequence Data at the masked access address Addrm. In some embodiments, the masking engine 101 may store the derived key in the local memory for reproducing the masked access address Addrm in a read operation. For example, in a read operation, the masking engine 101 may receive the access address Addr from MCU 12, reproduce the masked access address Addrm by masking the access address Addr and the derived key, read the data sequence Data at the masked access address Addrm, and transmit the data sequence Data to the MCU 12. The data masking operation and the address masking operation enhance data security and protect data from unauthorized access.

[0012] The random number generator 102 may generate a true random number. In some embodiments, the crypto engine 120 may send a security command Cs including a request for a true random number to the controller 100, the controller 100 may extract a random bit sequence from the random bit pool in the PUF unit 105 in response to the request, and the random number generator 102 may generate a true random number TRN with the extracted random bit sequence, and transmit the true random number TRN to the crypto engine 120.

[0013] The UID unit 103 may generate a unique identifier. In some embodiments, the crypto engine 120 may send a security command Cs including a request for an unique identifier to the controller 100, the controller 100 may extract a random bit sequence from the random bit pool in the PUF unit 105 in response to the request, and the UID unit 103 may generate an unique identifier UID according to the extracted random bit sequence, and transmit the unique identifier UID to the crypto engine 120.

[0014] The PUF unit 105 may provide secure key storage. Specifically, a portion of the OTP memory in the PUF unit 105 may be reserved for storing secure keys. In some embodiments, the crypto engine 120 may send a security command Cs including a request for storing a secure key along with the secure key to the controller 100, and the PUF unit 105 may store secure key in the reserved portion of the OTP memory.

[0015] Since the masking engine 101 may perform data masking and / or address masking on the data sequences and / or access addresses, the memory device 10 may be used in an execute in place (XIP) method, in which programs are executed directly from the memory array 106 rather than copying the same into a volatile memory, thereby reducing the total amount of memory required.

[0016] The cryptographic system 1 employs the memory device 10 to provide security functions including secure data storage, unique identity generation, true random number generation and secure key storage, saving data processing resources of the MCU 12, enabling XIP operations while protecting data from unauthorized access and enhancing data security.

[0017] FIG. 2 is a block diagram of a cryptographic system 2 according to another embodiment of the invention. The cryptographic system 2 is different from the cryptographic system 1 in that an MCU 22 may include a non-volatile memory for storing authentication code 220, and a memory device 20 may further include a crypto engine 200. The crypto engine 200 may be implemented by a hardware circuit capable of loading the authentication code 220 from the MCU 12 upon power-up and executing the same. The following discussion will focus on the configurations and the operations of the authentication code 220 and the crypto engine 200. The crypto engine 200 may be coupled to the controller 100.

[0018] The crypto engine 200 may execute the authentication code 220 to perform an authentication process. The authentication process may include a sequence of authentication operations. The authentication code 220 may be firmware code for instructing the crypto engine 200 to perform the sequence of authentication operations. In some embodiments, the controller 100 may receive a sequence of security commands Cs from the MCU 22, the sequence of security commands Cs being used to execute the sequence of authentication operations. The controller 100 may instruct the crypto engine 200 to perform the sequence of authentication operations in response to the sequence of security commands Cs, and control the data access to the memory array 106 according to a result of the sequence of authentication operations. The controller 100 may grant the data access to the memory array 106 upon a successful authentication process, and may deny the data access to the memory array 106 upon a failed authentication process.

[0019] The crypto engine 200 may generate an entropy S by using the extracted random bit sequence and / or the true random number TRN. The MCU 22 may send a security command Cs including a request for an entropy to the controller 100. In one embodiment, in response to the request, the controller 100 may extract a random bit sequence from the random bit pool in the PUF unit 105 and instruct the random number generator 102 to generate the true random number TRN, and the crypto engine 200 may mask the true random number TRN with the extracted random bit sequence to generate the entropy S, and transmit the entropy S to the MCU 12. The true random number TRN, the extracted random bit sequence and the entropy S may be equal in length. In another embodiment, the crypto engine 200 may generate the entropy S by combining a plurality of bit in the true random number TRN in a predetermined period, e.g., 3 clock cycles, into an entropy bit, so as to generate the entropy S, and transmit the entropy S to the MCU 12. The entropy S may be shorter in length than that of the true random number TRN. In yet another embodiment, the crypto engine 200 may generate the entropy S by combining a plurality of bit in the extracted random bit sequence in a predetermined period into an entropy bit, so as to generate the entropy S, and transmit the entropy S to the MCU 12. The entropy S may be shorter in length than that of the extracted random bit sequence.

[0020] Since the crypto engine 200 is implemented by hardware, the authentication process may be performed in a quicker and more efficient manner. Further, since the crypto engine 200 is located in the memory device 20, all authentication data for use in the authentication process may be kept inside the memory device 20 without being exposed to external circuits, enhancing the security level. The cryptographic system 2 employs the crypto engine 200 and the authentication code 220 to increase operation speed and efficiency of the authentication process, reduce the risk of the authentication key from being exposed to external circuits, protect data from unauthorized access, and save data processing resources of the MCU 22.

[0021] FIG. 3 is a block diagram of a cryptographic system 3 according to another embodiment of the invention. The cryptographic system 3 is different from the cryptographic system 2 in that an MCU 32 may not have the authentication code 220, and a memory device 30 may further include a crypto processor 300. The following discussion will focus on the configurations and the operations of the crypto processor 300. The crypto processor 300 may be coupled to the crypto engine 200.

[0022] The crypto processor 300 may include a circuit instructing a sequence of authentication operations, thereby further increasing operation speed and efficiency of the authentication process. The controller 100 may receive a security command Cs to initiate an authentication process. The controller 100 may instruct the crypto processor 300 to initiate the authentication process in response to the security command Cs. In turn, the crypto processor 300 may instruct the crypto engine to perform the sequence of authentication operations. Subsequently, the crypto engine 200 may perform the sequence of authentication operations to generate an authentication result. The controller 100 may control the data access to the memory array 106 according to the authentication result. In particular, the controller 100 may grant the data access to the memory array 106 upon a successful authentication process, and may deny the data access to the memory array 106 upon a failed authentication process.

[0023] The crypto processor 300 may generate a key K by using the entropy S and the extracted random bit sequence. The MCU 32 may send a security command Cs including a request for a key to the controller 100. In response to the request, the controller 100 may extract a random bit sequence from the random bit pool in the PUF unit 105 and instruct the crypto engine 20 to generate the entropy S, and the crypto engine 200 may mask the entropy S with the extracted random bit sequence to generate the key K, and transmit the key K to the MCU 12. The entropy S, the extracted random bit sequence and the key K may be equal in length.

[0024] Since the crypto processor 300 and the crypto engine 200 are both implemented by hardware, the authentication process may be performed in a quicker and more efficient manner. Since the crypto processor 300 and the crypto engine 200 are both located in the memory device 30, all authentication data for use in the authentication process may be kept inside the memory device 30 without being exposed to external circuits, enhancing the security level. The cryptographic system 3 employs the crypto processor 300 to increase operation speed and efficiency of the authentication process, reduce the risk of the authentication key from being exposed to external circuits, protect data from unauthorized access, and save data processing resources of the MCU 32.

Claims

1. A memory device (10, 20, 30) comprising a memory array (106); a controller (100) coupled to a microprocessor (12, 22); a physically unclonable (PUF) unit (105); wherein the physically unclonable function (PUF) unit (105) is configured to provide a random bit pool; the controller (100) is coupled to the PUF unit (105) and is configured to, upon receiving from the microprocessor a security command to grant data access to the memory array, extract a random bit sequence from the random bit pool, and comprises: a masking engine (101) configured to perform a key derivation function to stretch the extracted random bit sequence, in a data masking operation, perform an XOR operation on the stretched random bit sequence and the access address (Addr) in a bitwise manner to mask the access address (Addr) with the stretched random bit sequence to generate a derived key, store the derived key in a local memory, and mask the data sequence (Data) with the derived key to generate a masked data sequence (Datam); and wherein the memory array (106) is coupled to the masking engine (101) and is configured to store the masked data sequence (Datam) at the access address; wherein the masking engine (101) is further configured to, in a read operation, read the masked data sequence from the memory array (106) at the access address, mask the masked data sequence with the derived key from the local memory to recover the data sequence, and transmit the data sequence to the microprocessor.

2. The memory device (10, 20, 30) of claim 1, characterised in that the controller (100) further comprises a unique identifier (UID) unit (103) configured to generate an unique identifier according to the extracted random bit sequence.

3. The memory device (10, 20, 30) of any of the preceding claims, characterised in that the controller (100) further comprises: a random number generator (102) coupled to the PUF unit (105) and configured to generate a true random number with the extracted random bit sequence.

4. The memory device (20, 30) of claim 3, characterised by further comprising: a crypto engine (200) coupled to the controller (100), and configured to generate an entropy (S) by using the extracted random bit sequence and / or the true random number.

5. The memory device (30) of claim 4, characterised by further comprising: a crypto processor (300) coupled to the crypto engine (200), and configured to generate keys (K) by using the entropy (S) and the extracted random bit sequence.

6. The memory device (10, 20, 30) of any of the preceding claims, characterised in that the PUF unit (105), the memory array (106) and the controller (100) are formed in an integrated circuit.

7. The memory device (10, 20, 30) of any of the preceding claims, characterised in that the PUF unit (105) comprises a one-time programmable memory.

8. The memory device (10, 20, 30) of any of the preceding claims, characterised in that the controller (100) is further configured to control data access to the memory array (106) according to the security command (Cs).

9. The memory device (20) of any of the preceding claims, wherein the microprocessor (12, 22) further comprises a crypto engine (120, 200) and wherein: the controller (100) further comprises a random number generator (102), and is further configured to receive a security command (Cs) including a request for an entropy (S) from the microprocessor (22), extract a second extracted random bit sequence from the random bit pool in response to the request, and instruct the random number generator (102) to generate a true random number (TRN); and the crypto engine (200) is configured to mask the true random number (TRN) with the second extracted random bit sequence to generate an entropy (S), and transmit the entropy (S) to the microprocessor (22).

10. The memory device (20) of any of claims 1 to 8, wherein the microprocessor (12, 22) further comprises a crypto engine (120, 200) and wherein: the controller (100) further comprises a random number generator (102), and is further configured to receive a security command (Cs) including a request for an entropy (S) from the microprocessor (22), and instruct the random number generator (102) to generate a true random number (TRN) in response to the request; and the crypto engine (200) is configured to combine a plurality of bits in the true random number (TRN) in a predetermined period to generate an entropy (S), and transmit the entropy (S) to the microprocessor (22).

11. The memory device (20) of any of claims 1 to 8, wherein the microprocessor (12, 22) further comprises a crypto engine (120, 200) and wherein: the controller (100) is further configured to receive a security command (Cs) including a request for an entropy (S) from the microprocessor (22), and extract a second extracted random bit sequence from the random bit pool in response to the request; and the crypto engine (200) is configured to combine a plurality of bits in the second extracted random bit sequence in a predetermined period to generate an entropy (S), and transmit the entropy (S) to the microprocessor (22).