SYSTOLIC ARRAY WITH FUSIONED MULTIPLICATION-ADDITION WITH EFFICIENT PRENORMALIZATION AND EXTENDED DYNAMICS RANGE
DE602020073190T2Active Publication Date: 2026-06-10AMAZON TECH INC
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- AMAZON TECH INC
- Filing Date
- 2020-11-25
- Publication Date
- 2026-06-10
AI Technical Summary
Technical Problem
Systolic arrays supporting both normal and denormal numbers result in significant increases in integrated circuit die cost, power consumption, and circuit complexity, particularly when used in neural networks requiring higher precision calculations.
Method used
Implementing a systolic array with a column of normalizers that normalize inputs and weights, using components like denormal detectors, exponent expanders, and shifters to convert inputs into a modified format, reducing the need for specialized circuitry for each data type.
Benefits of technology
Reduces dynamic power consumption and circuitry size while enabling the systolic array to handle both normal and denormal numbers efficiently, minimizing latency and cost.
✦ Generated by Eureka AI based on patent content.
Need to check novelty before this filing date? Find Prior Art
No text content released.