CHARACTERIZATION OF TRANSISTORS

Description

Domaine technique

[0001] This description relates generally to electronic devices and, more particularly, to methods for characterizing field effect transistors. Technique antérieure

[0002] To characterize a field-effect transistor, one can notably evaluate the effective mobility of the majority charge carriers (electrons or holes) in its conduction channel. The effective mobility values ​​obtained by standard characterization methods are, however, often erroneous, for example due to charge trapping during the measurement. This distorts the characterization of the transistor.

[0003] GB 2351156 describes a modeling of electrical characteristics of thin-film transistors. To this end, this document proposes a method for characterizing a field-effect transistor, including the measurement of a drain current vs. a gate voltage, as well as the measurement of a capacitance vs. the gate voltage. Summary of the invention

[0004] There is a need to improve devices and methods for characterizing transistors.

[0005] An embodiment overcomes all or part of the drawbacks of known transistor characterization devices and methods.

[0006] The invention, as defined by claim 1, provides a method of characterizing a field effect transistor, comprising: a step of applying, to the gate of the transistor, by a first pulse current-voltage characteristics measuring apparatus configured to subject the gate to voltage pulses and to measure a resulting electric current, a single gate voltage ramp; a step of measuring a drain current and a gate capacitance of the transistor during the application of the gate voltage ramp; and a step of interpreting both variations in the gate capacitance and variations in the drain current of the transistor.

[0007] According to one embodiment, the ramp is applied for a duration of between 1 µs and 20 µs, preferably between 1 µs and 5 µs.

[0008] According to one embodiment, the ramp is a straight line of substantially constant slope.

[0009] According to one embodiment, the slope of the ramp is comprised, in absolute value, between 0.1 V / µs and 10 V / µs, preferably between 0.5 V / µs and 1.5 V / µs.

[0010] According to one embodiment, the drain of the transistor is subjected, during the application of the ramp, to a drain voltage of between 1 mV and 500 mV, preferably between 50 mV and 150 mV, relative to the source of the transistor.

[0011] According to one embodiment, the source and a substrate of the transistor are, during the application of the ramp, brought to a reference potential, preferably ground.

[0012] According to one embodiment, variations in gate capacitance of the transistor are derived from variations in the displacement current in the transistor during application of the ramp.

[0013] According to one embodiment, an effective mobility value of the carriers in the transistor is calculated from: the transistor gate length; the transistor gate width; the transistor drain current; the transistor drain voltage; and the integral of the transistor gate capacitance with respect to the gate voltage during the application of the ramp.

[0014] According to one embodiment, a gate leakage current of the transistor is derived from a measurement of the source current and a measurement of the drain current during application of the ramp.

[0015] According to one embodiment, a threshold voltage shift of the transistor is evaluated during successive first phases of application of the gate voltage ramp, interspersed with second phases of application of a non-zero constant voltage on the gate of the transistor.

[0016] The invention, as defined by claim 11, provides an electronic device adapted to implement the method as described, the device comprising: a first pulse current-voltage characteristic measuring device that can be connected, preferably connected, to the gate of the transistor; a measurement acquisition system connected to the first pulse current-voltage characteristic measuring device; and a second pulse current-voltage characteristic measuring device that can be connected, preferably connected, to the drain of the transistor, wherein the first device is configured to apply: voltage pulses of increasing amplitude, in a case where the ramp has a positive slope; and voltage pulses of decreasing amplitude in a case where the ramp has a negative slope. Brève description des dessins

[0017] These and other features and advantages will be set forth in detail in the following description of particular embodiments and modes of implementation given without limitation in relation to the attached figures, among which: there figure 1 is a schematic and partial sectional view of an example of a transistor of the type to which the described embodiments and modes of implementation apply, by way of example; figure 2 is an electrical diagram of an example of an electronic device for characterizing transistors; the figure 3 is an example of a timing diagram associated with an example of a transistor characterization method; the figure 4 is a schematic and partial sectional view of the transistor of the figure 1 during a step of the process of the figure 3 ; there figure 5 is a schematic and partial sectional view of the transistor of the figure 1 during another stage of the process of the figure 3 ; there figure 6 is an example of a graph of the variation of source current and drain current of the transistor of the figure 1 when implementing the process of the figure 3 ; there figure 7 is an electrical diagram of an embodiment of an electronic device for characterizing transistors; the figure 8 is an example of a timing diagram associated with a mode of implementation of a transistor characterization method; the figure 9 is an electrical diagram of an embodiment of another electronic device for characterizing transistors; the figure 10 is a simplified, schematic and partial sectional view of an example of a transistor in one mode of operation; the figure 11 is a simplified, schematic and partial sectional view of the transistor of the figure 10 in another mode of operation; and the figure 12 is an example of a timing diagram associated with a mode of implementation of a method for evaluating a threshold voltage drift of a transistor. Description des modes de réalisation

[0018] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments and methods of implementation may have the same references and may have identical structural, dimensional and material properties.

[0019] For the sake of clarity, only the steps and elements useful for understanding the embodiments and implementation methods described have been represented and are detailed.

[0020] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0021] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0022] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0023] There figure 1 is a schematic and partial sectional view of an example of a transistor 100 of the type to which the described embodiments and modes of implementation apply, by way of example.

[0024] In the example shown, the transistor 100 is a field effect transistor. The transistor 100 is, for example, a metal-oxide-semiconductor field effect transistor, more commonly called a MOS transistor (from the English Metal-Oxide-Semiconductor). The transistor 100 is for example produced in and on a semiconductor substrate 102, for example a wafer or a piece of wafer made of silicon doped with a first type of conductivity.

[0025] As illustrated in figure 1 , the transistor 100 comprises a source region 104S and a drain region 104D. In the example shown, the source 104S and drain 104D regions are disjoint, and extend vertically from the upper surface of the substrate 102. The source 104S and drain 104D regions are for example each made of silicon doped with a second type of conductivity, different from the first type of conductivity.

[0026] The transistor 100 further comprises a gate region 104G. In the example shown, the gate region 104G is located on and in contact with the upper surface of the substrate 102. On the surface of the substrate 102, the gate region 104G extends horizontally above a portion of the substrate 102 bordered laterally by the source 104S and drain 104D regions. figure 1 , the gate region 104G extends above the source 104S and drain 104D regions. In the example shown, the gate region 104G partially coats the respective upper surfaces of the source region 104S and the drain region 104D. The region 104G is typically made of an electrically insulating material, for example an oxide.

[0027] In the example shown, a source electrode 106S, a gate electrode 106G and a drain electrode 106D are respectively formed on and in contact with the source region 104S, the gate region 104G and the drain region 104D of the transistor 100. Each of these electrodes 106S, 106G, 106D for example partially covers the free upper surface of the region 104S, 104G, 104D with which it is associated. For example, the electrodes 106S, 106G and 106D respectively constitute source, gate and drain terminals of the transistor 100. The source electrodes 106S, gate 106G and drain 106D are, for example, made of an electrically conductive material.

[0028] In a case where the substrate 102 is p-doped and the source 104S and drain 104D regions are each n-doped, the transistor 100 is referred to as an n-channel transistor, or nMOS transistor. The majority charge carriers in this case are electrons. If a voltage V GS greater than a threshold voltage V TH is applied between the gate 106G and source 106S electrodes of the transistor 100, electrons can flow within the n-channel formed between the source 104S and drain 104D regions.

[0029] In another case where the substrate 102 is n-doped and the source 104S and drain 104D regions are each p-doped, the transistor 100 is referred to as a p-channel transistor, or pMOS transistor. The majority charge carriers in this case are holes. If a voltage V GS lower than the threshold voltage V TH is applied between the gate 106G and source 106S electrodes of the transistor 100, holes can flow within the p-channel formed between the source 104S and drain 104D regions.

[0030] When one wishes to characterize a transistor, for example transistor 100, one can in particular evaluate the effective mobility, noted µ eff , of the majority charge carriers of its conduction channel. In other words, one can evaluate the effective mobility of the electrons, in the case of a transistor 100 of the nMOS type, or of the holes, in the case of a transistor 100 of the pMOS type. The effective mobility µ eff is for example representative of the electrical performances and the reliability of the transistor 100.

[0031] In order to evaluate the effective mobility µ eff of the carriers of a transistor such as transistor 100, it is possible, for example, to carry out, as a function of a variable potential VG imposed on its gate, measurements of drain current ID and measurements of gate capacitance C. These two categories of measurements are respectively designated by the terms “characteristics ID (VG )” and “characteristics C (VG )” in the remainder of the description.

[0032] There figure 2 is an electrical diagram of an example of an electronic device 200 for characterizing transistors. The device 200 can in particular make it possible to obtain the characteristics ID (VG ) and C (VG ) of a transistor, for example the transistor 100 of the figure 1 . In the example of the figure 2 , we consider that the transistor 100 is a pMOS type transistor whose substrate 102 is n-type doped and whose source 104S and drain 104D regions are each heavily p-type doped (p+).

[0033] In the example shown, the device 200 comprises a signal generator 202, for example a pulse generator. An output of the signal generator 202 is connected to the gate of the transistor 100, i.e. to the gate electrode 106G (not shown), by means of two cables 204-1 and 204-2 between which a connection tee 206 is interposed.

[0034] The output of the generator 202 is further connected or linked to an input (Ch1) of an electronic acquisition and / or recording device 208 (OSC), for example an oscilloscope, via the cable 204-1, the tee 206 and another cable 204-3. More precisely, in figure 2 , one end of cable 204-3 is connected to tee 206, the other end of cable 204-3 being connected to input Ch1 of oscilloscope 208.

[0035] In the example shown, the drain of the transistor 100, i.e. the drain electrode 106D (not shown), is connected to an inverting input (-) of an operational amplifier 210D via another cable 204-4. The non-inverting input (+) of the amplifier 210D is brought to a drain potential denoted VD . At the output of the amplifier 210D, a voltage V(ID ) is obtained which is the image of the drain current ID of the transistor 100, for example proportional to the current ID . In the example shown, the output of the amplifier 210D is connected to another input (Ch3) of the oscilloscope 208 via another cable 204-5. figure 2 , a resistor (R1) is connected between the inverting input and the output of the 210D amplifier.

[0036] In the example shown, the source of transistor 100, i.e. the source electrode 106S (not shown in figure 2 ), is connected to an inverting input (-) of another operational amplifier 210S via another cable 204-6. The non-inverting input (+) of the amplifier 210S is brought to a reference potential, for example ground. At the output of the amplifier 210S, a voltage V(I s ) is obtained, which is the image of a source current I s of the transistor 100, for example proportional to the current I s . In the example shown, the output of the amplifier 210S is connected to another input (Ch4) of the oscilloscope 208 via another cable 204-7. In figure 2 , another resistor (R2) is connected between the inverting input and the output of the 210S amplifier.

[0037] In figure 2 , the substrate 102 of the transistor 100 is brought to the reference potential. In the example shown, the face of the substrate 102 opposite the source 104S, gate 104G and drain 104D regions is grounded via another cable 204-8.

[0038] The cables 204-1, 204-2, 204-3, 204-4, 204-5, 204-6, 204-7 and 204-8 are for example coaxial cables, the sheath of which is grounded. In the example shown, the sheath of each cable 204-3, 204-5, 204-7 is connected to a ground terminal (GND) of the oscilloscope 208. For example, the signal generator 202 and the oscilloscope 208 of the circuit 200 may respectively have an output impedance and an input impedance equal to approximately 50 Ω.

[0039] The operation of the device 200 is explained in more detail in relation to the figures 3 à 6 below.

[0040] There figure 3 is an example of a timing diagram associated with an example of a transistor characterization process. The figure 3 illustrates for example the evolution, as a function of time (t), of the VG voltage imposed on the grid electrode 106G ( figure 1 ) of transistor 100 by generator 202 ( figure 2 ) of device 200.

[0041] In the example shown, the grid voltage VG first follows a first decreasing linear ramp 300-1, in other words a straight line with a negative direction coefficient. The voltage VG then follows a second increasing linear ramp 300-2, in other words another straight line with a positive direction coefficient. In the example shown in figure 3 , the gate voltage VG decreases from 0 V to -2 V between a time t0 and a time t1, after time t0. The gate voltage VG then increases from -2 V to 0 V between time t1 and a time t2, after time t1. In figure 3 , the instants t0 and t1 are separated by a duration D1, while the instants t1 and t2 are separated by another duration D2. For example, the durations D1 and D2 are each of the order of a few microseconds or tens of microseconds.

[0042] In practice, the transition between the negative slope ramp 300-1 and the positive slope ramp 300-2 can be achieved via a plateau. The gate voltage VG can, for example, be maintained at a constant value of approximately -2 V for a few tenths or hundredths of a microsecond between ramps 300-1 and 300-2.

[0043] For example, during ramps 300-1 and 300-2, the VD potential ( figure 2 ) of biasing the drain of transistor 100 is maintained at a substantially constant value. The potential VD is for example maintained equal to approximately minus one hundred millivolts (-100 mV) between times t0 and t2.

[0044] There figure 4 is a schematic and partial sectional view of the transistor 100 of the figure 1 during a step of the process of the figure 3 . There figure 4 symbolizes in particular electric currents which circulate in the transistor 100 during the application of the ramp 300-1 ( figure 3 ) decreasing grid voltage VG.

[0045] In the remainder of the description, we note ID ON< and IS ON< the currents respectively measured on the drain electrode 106D and on the source electrode 106S of the transistor 100 ( figure 1 ) during the negative slope ramp 300-1.

[0046] During the application of ramp 300-1, the drain current ID ON< is equal, in absolute value, to a channel current, denoted I ch , minus a drain-side gate leakage current, denoted I G_D , and minus a drain-side displacement current, denoted I dis_D . In other words, the current ID ON< satisfies the following relationship: I D ON = I ch − I G _ D − I dis _ D

[0047] Similarly, during the application of ramp 300-1, the source current IS ON< is equal, in absolute value, to the sum of a source-side gate leakage current, denoted I G_S , a source-side displacement current, denoted I dis_S , and the channel current I ch. In other words, the current IS ON< satisfies the following relationship: I S ON = I G _ S + I dis _ S + I ch

[0048] During ramp 300-1, the drain-side displacement current I dis_D is due to a charge of a capacitance between the gate electrode 106G and the drain electrode 106D of the transistor 100 ( figure 1 ). Similarly, during ramp 300-1, the source-side displacement current I dis_S is due to a charge of a capacitance between the gate electrode 106G and the source electrode 106S of the transistor 100 ( figure 1 ). During ramp 300-1, current I dis_D is directed from drain region 104D to gate region 104G, and current I dis_S is directed from source region 104S to gate region 104G.

[0049] The drain-side gate leakage current I G_D corresponds to an unwanted current flowing through the gate region 104G on the drain region 104D side. Similarly, the source-side gate leakage current I G_S corresponds to an unwanted current flowing through the gate region 104G on the source region 104S side. During ramp 300-1, the current I G_D is directed from the drain region 104D to the gate region 104G, and the current I G_S is directed from the source region 104S to the gate region 104G.

[0050] During ramp 300-1, the channel current I ch is directed from the source region 104S to the drain region 104D.

[0051] There figure 5 is a schematic and partial sectional view of the transistor 100 of the figure 1 during another stage of the process of the figure 3 . There figure 5 symbolizes in particular electric currents which circulate in the transistor 100 during the application of the ramp 300-2 ( figure 3 ) increasing grid voltage VG.

[0052] In the remainder of the description, we note ID OFF< and IS OFF< the currents respectively measured on the drain electrode 106D and on the source electrode 106S of the transistor 100 ( figure 1 ) during the 300-2 positive slope ramp.

[0053] During the application of ramp 300-2, the drain current ID OFF< is equal, in absolute value, to the sum of the drain-side displacement current I dis_D and the channel current I ch, minus the drain-side gate leakage current I G_D. In other words, the current ID OFF< satisfies the following relationship: I D OFF = I dis _ D + I ch − I G _ D

[0054] Similarly, during the application of ramp 300-2, the source current IS OFF< is equal, in absolute value, to the sum of the source-side gate leakage current I G_S and the channel current I ch, minus the source-side displacement current I dis_S. In other words, the current IS OFF< satisfies the following relationship: I S OFF = I G _ S − I dis _ S + I ch

[0055] During ramp 300-2, the drain-side displacement current I dis_D is due to a discharge of the capacitance between the gate electrode 106G and the drain electrode 106D of the transistor 100 ( figure 1 ). Similarly, during ramp 300-2, the source-side displacement current I dis_S is due to a discharge of the capacitance between the gate electrode 106G and the source electrode 106S of the transistor 100 ( figure 1 ). During ramp 300-2, current I dis_D is directed from gate region 104G to drain region 104D, and current I dis_S is directed from gate region 104G to source region 104S.

[0056] During ramp 300-2, the drain-side leakage current I G_D, the source-side leakage current I G_S and the channel current I ch are oriented in the same way as during ramp 300-1.

[0057] In the example of the process set out above in relation to the figures 3 à 5 , the currents ID ON< and IS ON< measured during ramp 300-1 and the currents ID OFF< and IS OFF< measured during ramp 300-2 allow the drain current ID to be obtained by applying the following formula: I D = I D ON + I D OFF + I S ON + I S OFF 4

[0058] From the previous formula, we can deduce the ID characteristic (VG ) of transistor 100.

[0059] Furthermore, in the example of the method set out above in relation to the figures 3 à 5 , the currents ID ON< and IS ON< measured during ramp 300-1 and the currents ID OFF< and IS OFF< measured during ramp 300-2 make it possible to obtain a grid leakage current, noted IG , by applying the following formula: I G = I S ON + I S OFF − I D ON − I D OFF 2

[0060] From equations [Math 1] to [Math 4] above, we can deduce an overall displacement current, denoted I dis . The current I dis verifies the following relation: I dis = I S ON − I S OFF + I D OFF − I D ON 2

[0061] Starting from the current I dis , we can deduce the characteristic C(VG ) of the transistor 100 by applying the following formula: C = I dis d V G d t

[0062] Assuming that transistor 100 has a gate length L and a gate width W, the effective mobility µ eff of transistor 100 can be calculated by applying the following relationship: μ eff = L W ⋅ I D Q i V D

[0063] In the relation [Math 9], Q i represents the density of mobile charges in the channel of transistor 100. The density Q i corresponds to the integral of the characteristic C(VG ): Q i = ∫ + ∞ V G C d V G

[0064] There figure 6 is an example of a graph of the variation of the source current I s (in microamperes) and the drain current ID (in microamperes) of transistor 100 of the figure 1 as a function of the gate potential VG (in volts) when implementing the process of the figure 3 . In particular, the figure 6 illustrates an example of the evolution of the ID ON< current (curve 600-1) and the IS ON< current (curve 600-2) during the 300-1 ramp, as well as the ID OFF< current (curve 600-3) and the IS OFF< current (curve 600-4) during the 300-2 ramp.

[0065] In the example shown, curves 600-1 and 600-4 are almost superimposed and curves 600-2 and 600-3 are almost superimposed. As illustrated in figure 6 , the displacement current I dis is in this case substantially equal, for a given grid potential VG, for example -2 V, to the difference between curves 600-2 and 600-4 or to the difference between curves 600-3 and 600-1. In other words, in the example shown where ID ON< ≈ IS OFF< and where ID OFF< ≈ IS ON< , the relationship [Math 7] can be simplified as follows: I dis ≈ I S ON − I S OFF ≈ I D OFF − I D ON

[0066] A disadvantage of the characterization method outlined above in relation to the figures 3 à 6 is due to the fact that, as in the example illustrated in figure 6 , curves 600-1 and 600-4 are often very close to curves 600-2 and 600-3. This generally does not allow the displacement current I to be estimated accurately, and the transistor characteristic C(VG) is distorted.

[0067] Another disadvantage of the characterization method outlined above in relation to the figures 3 à 6 is due to the fact that the estimation of the displacement current I dis requires the application of two ramps 300-1 and 300-2 with opposite slopes. The measurements carried out during ramp 300-2 are for example likely to be disturbed by trap states which may for example be activated during the application of ramp 300-1. This can distort the estimation of the current I dis and harm the accuracy of the characteristic C(VG ) obtained at the end of the two ramps 300-1 and 300-2.

[0068] What has been described above in relation to an example of a pMOS type transistor also applies to other field effect transistors, for example nMOS type transistors.

[0069] There figure 7 is an electrical diagram of an embodiment of an electronic device 700 for characterizing transistors, for example the transistor 100 of the figure 1 In the remainder of the description, it is considered that the transistor 100 is an nMOS type transistor whose substrate 102 is for example p-type doped and whose source 104S and drain 104D regions are for example each n-type doped.

[0070] The device 700 comprises a first device 702 (PIV1) for measuring current-voltage characteristics by pulses (in English Pulsed IV). For example, the device 702 is a measuring device known under the trade name “Model B1350” from the company KEYSIGHT. The device 702 is connected, preferably connected, to the gate electrode or terminal 106G of the transistor 100. In the example shown, the device 702 is further connected to a measurement acquisition system 704 (PC), for example a computer.

[0071] In operation, the apparatus 702 is configured to subject the electrode 106G to LV voltage pulses and to measure the resulting electrical current. This current corresponds to the global displacement current I dis as previously discussed in relation to the figure 5 The voltage pulses applied to the gate of the transistor 100 by the device 702 each have, for example, a duration of the order of ten or even a hundred nanoseconds.

[0072] In the example shown, the source electrode 106S of the transistor 100 is brought to a reference potential, preferably ground (VS = 0 V). Similarly, the drain electrode 106D of the transistor 100 is brought to the reference potential, preferably ground (VD = 0 V). In other words, both the source and the drain of the transistor 100 are grounded.

[0073] The device 700 makes it possible in particular to obtain the characteristic C(VG) of a transistor by applying, to the gate electrode 106G, a single voltage ramp VG of positive or negative slope. In practice, the apparatus 702 of the device 700 is for example configured to apply, to the gate electrode 106G of the transistor 100, voltage pulses VG of increasing amplitude in the case of a positive slope ramp.

[0074] There figure 8 is an example of a timing diagram associated with a method of implementing a transistor characterization method. The figure 8 corresponds, for example, to a timing diagram of a mode of implementation of a method for characterizing the transistor 100 using the device 700 of the figure 7 .

[0075] In the example shown, the gate voltage VG applied to the gate electrode 106G of the transistor 100 ( figure 7 ) follows a ramp 800 with a positive slope between an instant t0 and an instant t1, subsequent to the instant t0. The ramp 800 is for example a straight line with a substantially constant slope. During the ramp 800, the displacement current I dis is measured on the gate electrode 106G. This allows for example to deduce the characteristic C(VG ) of the transistor 100 by applying the formula [Math 8].

[0076] The ramp 800 is applied for a duration (t1 - t0) of between 1 µs and 20 µs, preferably between 1 µs and 5 µs, for example equal to approximately 3 µs.

[0077] In the example shown, the ramp 800 has a slope dV G / dt of between 0.1 V / µs and 10 V / µs, preferably between 0.5 V / µs and 1.5 V / µs. The ramp 800 has, for example, a slope dV G / dt equal to approximately 1 V / µs. The faster the ramp 800, the higher the displacement current I dis. An advantage of using a ramp 800 having a slope of the order of one volt per microsecond is that this allows, for example, access to a measurement precision greater than that which would be obtained using the method described in relation to the figure 6 .

[0078] The step of measuring the current I dis on the gate of the transistor 100 may in practice be preceded by a calibration step. The calibration step is carried out, for example, in a configuration where measurement tips of the device 702 ( figure 7 ) are not brought into contact with the transistor 100. This makes it possible, for example, to obtain a value of parasitic displacement current coming from an intrinsic capacitance of the device 702. This value can then be subtracted from the displacement current measurement I dis carried out by placing the measuring tips of the device 702 in contact with the transistor 100 and applying the gate voltage ramp 800 VG.

[0079] It has been described in relation to the figure 8 an implementation mode in which the transistor is of the pMOS type and where the ramp 800 has a positive slope. This is not, however, limiting. The person skilled in the art is capable of adapting the implementation mode described to other types of field effect transistors, in particular to a transistor of the nMOS type. Furthermore, the person skilled in the art is capable of transposing the implementation mode described to a characterization method in which the voltage ramp VG is a straight line with a negative slope and of a value equal, apart from the sign, to the value of the slope 800.

[0080] There figure 9 is an electrical diagram of an embodiment of another electronic device 900 for characterizing transistors, for example the transistor 100. The device 900 of the figure 9 includes common elements with the 700 device of the figure 7 These common elements will not be described again below.

[0081] Device 900 of the figure 9 differs from the 700 device of the figure 7 mainly in that, in the case of the device 900, the drain electrode 106D of the transistor 100 is connected, preferably connected, to a second device 902 (PIV2) for measuring current-voltage characteristics by pulses. The device 902 is for example analogous to the device 702. In the example shown, the device 902 is connected to the computer 704 (PC).

[0082] In operation, the apparatus 902 is configured to subject the drain electrode 106D of the transistor 100 to a voltage VD of between 1 mV and 500 mV, preferably between 50 mV and 150 mV. The apparatus 902 is for example configured to apply a voltage equal to approximately 100 mV to the drain of the transistor 100. In operation, the apparatus 902 is further configured to measure the drain current ID on the drain electrode 106D of the transistor 100.

[0083] By applying a single 800 ramp to the 106G electrode ( figure 8 ) of voltage VG and by imposing on the electrode 106S a substantially constant voltage VS, it is possible to measure both variations in displacement current I dis and drain current ID . In other words, it is possible, from a single ramp, to interpret both variations in gate capacitance C and drain current ID of the transistor 100. This makes it possible, for example, to obtain in a single ramp 800 the characteristic C(VG ) and the characteristic ID (VG ) of the transistor 100. From the characteristic C(VG ), it is possible in particular to deduce the mobility µ eff of the carriers in the channel of the transistor 100, for example by applying the relation [Math 9].

[0084] It might be thought that the measurement of the characteristic C(VG ) would be disturbed by the application of a non-zero drain voltage VD, for example due to a change in the potential difference between the source 106S and drain 106D electrodes. In practice, the inventors have however found that the application of a voltage VD lower than 500 mV has a negligible influence on the characteristics C(VG ) obtained. This is in particular the case for transistors whose gate capacitance C is greater than approximately 10 pF, for example for transistors whose gate has a thickness of the order of 30 nm and a surface area of ​​the order of 8,000 µm 2< and is subjected to a slope ramp equal to approximately 1 V / µs.

[0085] In the mode of implementation set out in relation to the figure 9 , for simplicity, it is considered that the source-side gate leakage current I G_S and the drain-side gate leakage current I G_D of the transistor 100 are both negligible. This can for example be justified by the fact that the gate region 104G of the transistor 100 has a thickness of the order of a few tens of nanometers. For example, the gate region 104G consists of a layer of alumina (Al 2 O 3 ) having a thickness of 30 nm.

[0086] Alternatively, for example in cases where the currents I G_S and I G_D are not negligible, a third apparatus (not shown) for measuring pulsed current-voltage characteristics may be connected, preferably connected, to the source electrode 106S of the transistor 100. For example, the third apparatus may be configured to apply a zero source voltage VS and to measure the source current IS during the ramp 800 ( figure 8 ) of voltage VG. Considering for simplicity that the leakage current of the substrate 102 ( figure 1 ) is negligible, the grid leakage current IG in this case verifies the following relation: I G = I D − I S

[0087] Although described above in relation to the figures 7 à 9 modes of implementing transistor characterization methods applied to a case where the transistor 100 is of the nMOS type, the person skilled in the art is able to transpose what has been previously explained to other types of field effect transistors, in particular to a case where the transistor 100 is of the pMOS type.

[0088] There figure 10 is a simplified, schematic, and partial sectional view of an example of a transistor 1000 in one operating mode. The figure 10 more particularly symbolizes an accumulation of electrical charges in the vicinity of an interface between a substrate 1002, in and on which the transistor 1000 is formed, and a gate oxide region 1004G.

[0089] In the example shown, the gate oxide region 1004G has, when viewed in cross-section, a “U” shape. The region 1004G extends vertically from the upper surface of the substrate 1002. For example, a gate electrode 1006G is formed on and in contact with the gate oxide region 1004G.

[0090] In figure 10 , region 1004G separates two portions of a passivation layer 1008 partially coating the upper surface of substrate 1002. figure 10 , the portions of passivation layer 1008 are symbolized by hatched areas.

[0091] For example: the substrate 1002 is made of gallium nitride (GaN); the gate oxide region 1004G is made of alumina (Al 2 O 3 ); and the passivation layer 1008 is made of aluminum-gallium nitride (AlGaN).

[0092] There figure 10 illustrates in particular a situation in which a gate potential VG greater than a threshold voltage V TH of the transistor 1000 is applied to the gate electrode 1006G. In this situation, charges 1010 forming part of an electron channel 1012 formed between two parts of a two-dimensional electron gas (2DEG) are subjected to an electric field symbolized by arrows 1014 directed towards the gate electrode 1006G. This results in the trapping, in the gate oxide layer 1004G, of charges 1016 coming from the electron channel 1012. The operating mode illustrated in figure 10 is called the "accumulation regime" because charges, in this case electrons, are accumulated in the 1004G gate oxide layer.

[0093] There figure 11 is a simplified, schematic and partial sectional view of the transistor 1000 of the figure 10 in another mode of operation. The figure 11 more particularly symbolizes the influence of the electric charges 1016 trapped in the gate oxide region 1004G of the transistor 1000.

[0094] There figure 11 illustrates in particular a situation subsequent to the application, on the gate electrode 1006G of the transistor 1000, of a gate potential VG greater than the threshold voltage V TH for a duration for example of the order of several seconds. In this situation, the charges 1016 trapped in the gate oxide layer 1004G each produce an electric field symbolized by arrows 1100. The electric field 1100 produced by each charge 1016 tends to oppose the electric field 1014 of the charges 1010 of the electron channel 1012.

[0095] The presence of the 1016 charges in the 1004G layer is the cause of a phenomenon called bias temperature instability (BTI). This phenomenon notably leads to a progressive degradation of the electrical performance of the transistor 1000. For example, this phenomenon may be responsible for a shift or drift ΔV TH of the threshold voltage V TH of the transistor 1000 as a function of time.

[0096] There figure 12 is an example of a timing diagram associated with a mode of implementation of a method for evaluating a drift ΔV TH of threshold voltage of a transistor, for example transistor 1000 ( figure 10 ).

[0097] In the example shown, a substantially constant grid voltage VG, denoted V stress, is applied between an instant t0 (t0a, t0b, t0c) and an instant t1 (t1a, t1b, t1c) to the electrode 1006G ( figure 10 ). Between consecutive times t1 and t0, the voltage V stress is stopped to evaluate the characteristics C(VG ) and ID (VG ) of the transistor 1000. For this, gate voltage ramps VG are applied, for example analogous to the ramp 800 described in relation to the figure 8 . For example, the voltage V stress is of the order of several volts, for example equal to approximately 4 V. The duration of application of the voltage V stress between two consecutive instants t0 and t1 is, for example, of the order of several seconds.

[0098] The methods for evaluating the characteristics C(VG ) and ID (VG ) set out above in relation to the figures 7 à 9 advantageously make it possible to limit the duration separating each instant t1 from the following instant t0. This limits, for example, the appearance of a phenomenon known as overlap, during which the charges 1016 ( figure 10 ) trapped in the gate oxide layer 1004G tend to return to the channel 1012 formed in the substrate 1002. The overlap phenomenon in fact distorts the estimation of the characteristic C(VG ), because it is the origin of an attenuation of the electric field 1100.

[0099] An advantage of the characterization methods set out above in relation to the figures 7 à 12 is due to the fact that they are likely to provide an estimate of the displacement current I dis and a characteristic C(VG ) of the transistor more precise than those which would be obtained by current characterization methods.

[0100] Another advantage of the characterization methods set out above in relation to the figures 7 à 12is due to the fact that the estimation of the displacement current I dis is carried out by applying a single ramp 800. The measurements carried out during the ramp 800 are in particular unlikely to be disturbed by trap states. This improves the accuracy of the estimation of the current I dis and of the characteristic C(VG ) obtained at the end of a single ramp 800.

[0101] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, what is described above in relation to an implementation in which the voltage ramp 800 has a positive slope can be transposed by those skilled in the art to a case where the voltage ramp applied to the gate of the transistor has a negative slope.

[0102] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the practical implementation of the devices 702 and 902 for measuring current-voltage characteristics by pulses is within the reach of the person skilled in the art.

Claims

1. Method of characterizing a field-effect transistor (100; 1000), comprising: a step of application, to the gate (106G; 1006G) of the transistor, by a first pulsed current-vs.-voltage characteristic measurement system (702) configured to submit the gate to voltage pulses and to measure a resulting electric current (Idis), of a single ramp (800) of the gate voltage (VG); a step of measurement of a drain current (ID) and of a gate capacitance (C) of the transistor (100; 1000) during the application of the ramp (800) of the gate voltage (VG); and a step of interpretation both of variations of the gate capacitance (C) and of variations of the drain current (ID) of the transistor.

2. Method according to claim 1, wherein the ramp (800) is applied for a time period in the range from 1 µs to 20 µs, preferably from 1 µs to 5 µs.

3. Method according to claim 1 or 2, wherein the ramp (800) is a straight line having a substantially constant slope.

4. Method according to claim 3, wherein the slope of the ramp (800) is in the range, in absolute value, from 0.1 V / µs to 10 V / µs, preferably from 0.5 V / µs to 1.5 V / µs.

5. Method according to any one of claims 1 to 4, wherein the drain (106D) of the transistor (100; 1000) is submitted, during the application of the ramp (800), to a drain voltage (VD) in the range from 1 mV to 500 mV, preferably from 50 mV to 150 mV, with respect to the source (106S) of the transistor.

6. Method according to any one of claims 1 to 5, wherein the source (106S) and a substrate (102; 1002) of the transistor are, during the application of the ramp (800), taken to a reference potential, preferably the ground.

7. Method according to any one of claims 1 to 6, wherein the variations of the gate capacitance (C) of the transistor (100; 1000) are deduced from variations of the displacement current (Idis) in the transistor during the application of the ramp (800).

8. Method according to any one of claims 1 to 7, wherein an effective mobility value (µeff) of the carriers in the transistor (100; 1000) is calculated based on: the gate length (L) of the transistor; the gate width (W) of the transistor; the drain current (ID) of the transistor; a drain voltage (VD) of the transistor; and the integral of the gate capacitance (C) of the transistor with respect to the gate voltage (VG) during the application of the ramp (800).

9. Method according to any one of claims 1 to 8, wherein a gate leakage current (IG) of the transistor (100; 1000) is deduced from a measurement of the source current (IS) and from a measurement of the drain current (ID) during the application of the ramp (800).

10. Method according to any one of claims 1 to 9, wherein an offset (ΔVTH) of the threshold voltage (VTH) of the transistor (100; 1000) is estimated during first successive phases of application of the ramp (800) of the gate voltage (VG), separated by second phases of application of a non-zero constant voltage (Vstress) to the gate (106G; 1006G) of the transistor.

11. Electronic device adapted to implementing the method according to any one of claims 1 to 10, the device comprising: the first pulsed current-vs.-voltage characteristic measurement system (702) which may be coupled, preferably connected, to the gate (106G; 1006G) of the transistor (100; 1000); a measurement acquisition system (704) coupled to the first pulsed current-vs.-voltage characteristic measurement system (702); and a second pulsed current-vs.-voltage characteristic measurement system (902) which may be coupled, preferably connected, to the drain (106D) of the transistor wherein the first system applies: - voltage pulses having an increasing amplitude, in a case where the ramp (800) has a positive slope; and - voltage pulses having a decreasing amplitude, in a case where the ramp has a negative slope.