ELECTRONIC COMPONENT WITH HETERO TRANSITION, FEATURING A FIELD PLATE AND A P-DOTED FLOATTING AREA

Description

DOMAINE TECHNIQUE DE L'INVENTION

[0001] The present invention relates to heterojunction-based power electronic components, such as high electron mobility transistors (or HEMTs) and gallium nitride (GaN) Schottky lateral diodes. ARRIERE-PLAN TECHNOLOGIQUE DE L'INVENTION

[0002] A heterojunction is formed by the junction of two semiconductor materials with different band gaps. For example, an AlGaN / GaN heterojunction consists of a gallium nitride (GaN) layer topped by an aluminum gallium nitride (AlGaN) layer. A two-dimensional electron gas (or 2DEG) forms at the interface between the AlGaN and GaN layers due to spontaneous and piezoelectric polarization. This two-dimensional electron gas serves as a conduction channel within heterojunction electronic components, such as HEMT transistors and Schottky side diodes.

[0003] Heterojunction electronic components can withstand high current densities in the on-state due to the high density of charge carriers (electrons) and their high mobility within the two-dimensional electron gas. For certain applications, such as high-voltage switching, it is important that these electronic components also exhibit good voltage resistance in the off-state, i.e., a high breakdown voltage.

[0004] The document [“RESURF AlGaN / GaN HEMT for high voltage power switching”, IEEE Electron Device Letters, Vol. 22, No. 8, p. 373-375, 2001] describes an AlGaN / GaN HEMT transistor having a high breakdown voltage, greater than 1 kV.

[0005] With reference to the figure 1 This transistor comprises a substrate 10, a p-doped GaN buffer layer 11 (p-GaN) disposed on the substrate 10, an n-doped GaN channel layer 12 (n-GaN) disposed on the buffer layer 11, an n-doped AlGaN barrier layer 13 (n-AlGaN) disposed on the channel layer 12, and a passivation layer 14 disposed on the barrier layer 13. The n-GaN channel layer 12 and the n-AlGaN barrier layer 13 form a heterojunction 20. A two-dimensional electron gas 21 is intrinsically formed at the interface between the channel layer 12 and the barrier layer 13. This two-dimensional electron gas 21 is shown in dashed lines on the figure 1 .

[0006] The transistor further comprises a gate electrode 15, extending through the passivation layer 14 to be in contact with the barrier layer 13, drain and source electrodes 16-17 connected together by the two-dimensional electron gas 21 and two field plates 18a-18b arranged on the passivation layer 14, forming respectively extensions of the gate electrode 15 and the drain electrode 16.

[0007] The p-GaN buffer layer 11 and the n-GaN channel layer 12 together form a PN junction under the heterojunction, which improves the confinement of the two-dimensional electron gas by creating a buried potential barrier (“back-barrier”).

[0008] The PN junction and the field plates 18a-18b redistribute the electric field more uniformly in the component, which has the effect of increasing the breakdown voltage of the transistor (i.e. the maximum permissible voltage between the drain and the source in the blocked state).

[0009] However, the PN junction also has the effect of partially depleting the two-dimensional electron gas 21, which leads to an increase in the on-state resistance of the component, of about 14% compared to a structure without a PN junction.

[0010] US2015 / 270355 describes another AlGaN / GaN heterojunction transistor, comprising a GaN channel layer, an AlGaN barrier layer disposed on the channel layer, a source electrode, a drain electrode, a gate electrode, and a fieldplate forming an extension of the source electrode. The transistor further includes a p-doped AlGaN floating layer disposed on the barrier layer between the gate and drain electrodes, directly above one flank of the fieldplate. This p-doped AlGaN floating layer, called the RESURF (for "Reduced Surface Field") layer, reduces the electric field in the passivation layer separating the fieldplate and gate electrode, specifically the field peaks at the end of the fieldplate and the end of the gate electrode. This electric field reduction effect, however, remains limited to the passivation layer. RESUME DE L'INVENTION

[0011] The invention aims to increase the breakdown voltage of a heterojunction electronic component while limiting the increase in its electrical resistance in the on-state.

[0012] According to the invention, this objective is achieved by providing a heterojunction electronic component comprising: a substrate; a heterojunction comprising a channel layer disposed on the substrate and a barrier layer disposed on the channel layer; a passivation layer disposed on the barrier layer; a field plate separated from the barrier layer by a portion of the passivation layer; and a floating region of a p-type doped semiconductor material located in the barrier layer above a flank of the field plate, the floating region having a thickness less than that of the barrier layer.

[0013] The p-doped floating region located in the barrier layer reduces the electric field in both the passivation and barrier layers, resulting in an increase in the component's breakdown voltage. Furthermore, this floating region confines the two-dimensional electron gas of the heterojunction less effectively than a confinement layer located beneath the channel layer. Therefore, the increase in breakdown voltage does not come at the expense of a significant degradation of the component's other electrical characteristics, particularly its on-state resistance.

[0014] In the transistor described in US2015 / 270355, the floating region is located on the barrier layer, not within its boundaries. The (lateral) electric field in the barrier layer is not reduced but rather shifted and concentrated at the distal end of the floating region. This results in a risk of component breakdown at this point of shift. Furthermore, the electric field is also increased in the two-dimensional electron gas (forming part of the transistor's conduction channel), which can lead to the formation of hot carriers during transistor switching.

[0015] Preferably, the component further comprises a first electrode and a second electrode separated from the first electrode by at least part of the passivation layer.

[0016] In one embodiment, the component is of the diode type, the first electrode is an anode and the second electrode is a cathode.

[0017] In one embodiment, the component is of the transistor type, the first electrode is a gate electrode and the second electrode is a drain electrode.

[0018] In an embodiment compatible with the two preceding ones, the component comprises a plurality of field plates and a plurality of floating regions of p-type doped semiconductor material, each floating region being located in the barrier layer above a flank of one of the field plates.

[0019] In addition to the characteristics mentioned in the preceding paragraphs, the component according to the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: the floating region has a concentration of p-type doping impurities between 1.10 18< cm -3< and 2.10 19< cm -3< ; the floating region is centered with respect to the flank of the field plate; the floating region has a width less than twice the width of the field plate; the field plate forms an extension of the first electrode; the barrier layer is made of the unintentionally doped semiconductor material; and the floating region is in direct contact with the passivation layer.

[0020] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BREVE DESCRIPTION DES FIGURES

[0021] Other features and advantages of the invention will become clear from the description given below, which is by way of example and not limitation, with reference to the accompanying figures, including: [ Fig. 1 ], previously described, schematically represents a heterojunction transistor according to the prior art; [ Fig. 2 ] represents a first embodiment of a heterojunction electronic component according to the invention; [ Fig. 3 ] shows the forward-looking characteristic IV of a Schottky side-diode equipped with a p-doped floating region, according to one aspect of the invention, and the forward-looking characteristic IV of a Schottky side-diode lacking a p-doped floating region; [ Fig. 4 ] shows the inverse IV characteristic of a Schottky side diode equipped with a p-doped floating region, according to one aspect of the invention, and the inverse IV characteristic of a Schottky side diode lacking a p-doped floating region; [ Fig. 5 ] represents a second embodiment of a heterojunction electronic component according to the invention; [ Fig. 6 ] represents a third embodiment of a heterojunction electronic component according to the invention; [ Fig. 7 ] represents the absolute value of the electric field in the barrier layer of an example component according to the invention and, for comparison, that of a transistor according to document US2015 / 270355 and that of a transistor without a floating region; and [ Fig. 8 ] represents the electric field in absolute value under the heterojunction of an example of a component according to the invention and, for comparison, that of a transistor according to document US2015 / 270355 and that of a transistor without a floating region.

[0022] For clarity, identical or similar elements are identified by identical reference symbols across all figures. DESCRIPTION DETAILLEE

[0023] There figure 2 This schematic cross-sectional view represents a first embodiment of a heterojunction electronic component 1. This type of component finds advantageous applications in power electronics, for example as a power switch. Component 1 can thus switch reversibly between a first state called the "conducting state" (or "ON state") and a second state called the "blocking state" (or "OFF state").

[0024] Component 1 comprises a substrate 10 and a heterojunction 20 disposed on the substrate 10. The heterojunction 20 comprises a first semiconductor layer 12, commonly called the "channel layer" and disposed on the substrate 10, and a second semiconductor layer 13, commonly called the "barrier layer" and disposed on the channel layer 12. A two-dimensional electron gas 21 (or 2DEG) is formed intrinsically (by heterojunction) at the interface between the channel layer 12 and the barrier layer 13. On the figure 2 , it is symbolized by dotted lines in channel layer 16 along the interface between channel layer 16 and barrier layer 17.

[0025] The substrate 10 is, for example, made of silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or sapphire (Al₂O₃). The channel layer 12 and the barrier layer 13 are formed of semiconductor materials having different band gaps. Preferably, the channel layer 12 and the barrier layer 13 are made of III-V semiconductor material, for example, GaN-based (GaN or GaN alloys such as AlGaN, InGaN, etc.).

[0026] The heterojunction 20 is, for example, of the GaN / AlGaN type. The channel layer 12 is then made of gallium nitride, preferably unintentionally doped (UID GaN), while the barrier layer 13 is made of aluminum gallium nitride, preferably unintentionally doped (UID AlGaN). A semiconductor material is considered unintentionally doped when its donor and acceptor dopant concentrations are less than 1016 cm-3 (NA < 1016 cm-3 and ND < 1016 cm-3). Preferably, the channel layer 12 has a thickness between 20 nm and 500 nm, while the barrier layer 13 has a thickness between 2 nm and 30 nm. The thickness of a layer is measured in a direction perpendicular to the substrate 10.

[0027] Alternatively, the channel layer 12 and the barrier layer 13 can be respectively in GaAs and Al x Ga 1-x As (x<0.25), or in Ga y In 1-y As (y-0.8) and Al x Ga 1-x As (x<0.25).

[0028] The heterojunction 20 may also include an intermediate layer (not shown in the figure), interposed between the channel layer 12 and the barrier layer 13, to increase the density and mobility of electrons in the two-dimensional electron gas 21. Such an intermediate layer is typically extremely thin (e.g. 1 nm thick) and may be made of aluminium nitride (AIN), this material being particularly suitable for the interface between a GaN channel layer 12 and an AlGaN barrier layer 13.

[0029] Still referring to the figure 2 The component 1 advantageously comprises a semi-insulating buffer layer 11, disposed between the substrate 10 and the channel layer 12. This buffer layer 11 limits lateral and vertical leakage currents in the component 1 and improves its (lateral) voltage withstand in the blocked state, in other words, its ability to withstand high reverse voltages. The buffer layer 11 preferably comprises a semiconductor material, such as GaN or AlGaN. This semiconductor material may be doped with impurities, such as carbon atoms. The buffer layer 11 may, in particular, be formed by a single layer of GaN:C or by a GaN:C / Al x Ga 1-x N bilayer, with x between approximately 4% and 8%. The thickness of the buffer layer 11 is chosen according to the desired breakdown voltage for the component 1. For example, it is between 1 µm and 15 µm.

[0030] In the case of a substrate 10 made of a material other than GaN (e.g. Si, SiC or sapphire), component 1 may further include a transition layer (not shown in the figures) disposed between the substrate 10 and the channel layer 12, and more particularly between the substrate 10 and the buffer layer 11. This transition layer allows the crystal lattice parameter to be adapted and the mechanical stresses to be managed between the substrate 10 and the layers of the heterojunction 20. It may include a nucleation sublayer (for example a 100 nm thick AIN layer), in contact with the substrate 10, and several adaptation sublayers stacked on the nucleation sublayer.The adaptation sublayers include, for example, AlGaN whose aluminum content varies from one layer to another (for example, several layers of AlGaN with a mole fraction of AIN that decreases with distance from the substrate 10, or a super-network comprising several Al x Ga 1-x N / GaN bilayers).

[0031] Component 1 also includes a passivation layer 14 disposed on the barrier layer 13, a first electrode 15 and a second electrode 16 separated (laterally) from the first electrode 15 by at least a portion of the passivation layer 14. The first electrode 15 and the second electrode 16 rest, for example, on a lower portion of the channel layer 12. An upper portion of the channel layer 12, the barrier layer 13 and at least a portion of the passivation layer 14 extend between the first electrode 15 and the second electrode 16.

[0032] The passivation layer 14 can be made of a single electrically insulating material, for example, silicon dioxide (SiO₂), silicon nitride (Si₃N₄), aluminum nitride (Al₂O₃), or alumina (Al₂O₃). Alternatively, the passivation layer can consist of several stacked sublayers made of different insulating materials, typically alternating oxide (e.g., SiO₂) and nitride (e.g., SiN) sublayers. These different sublayers serve as a support for one or more field plates, described below.

[0033] Each of the first and second electrodes 15-16 can be made of a metallic material, preferably chosen from aluminum (Al), copper (Cu), gold (Au), titanium (Ti), titanium nitride (TiN), and nickel (Ni), or of several stacked metallic materials. The material(s) used to form the first electrode 15 may be different from the material(s) used to form the second electrode 16. For example, the first electrode 15 is made of nickel (a low-temperature annealed barrier metal compound) and the second electrode 16 is made of an Al / Ti stack.

[0034] In this first embodiment, component 1 is a Schottky lateral diode. The first electrode 15 is an anode, in Schottky contact with the two-dimensional electron gas 21, and the second electrode 16 is a cathode, in ohmic contact with the two-dimensional electron gas 21. The anode and cathode are located at opposite ends of the two-dimensional electron gas 21. They are connected by the two-dimensional electron gas 21.

[0035] Component 1 further comprises a first field plate 18a, associated with the first electrode 15 and separated from the barrier layer 13 by a first portion 14a (typically a sub-layer) of the passivation layer 14. The first field plate 18a may form an extension of the first electrode 15, preferably extending parallel to the barrier layer 13 in the direction of the second electrode 16. In other words, it may be formed by a projecting portion of the first electrode 15. The first field plate 18a may be made of the same metallic material(s) as the first electrode 15 or of a different metallic material(s). The first portion 14a of the passivation layer 14 preferably has a constant thickness.

[0036] Optionally, component 1 includes a second field plate 18b, associated with the second electrode 16 and separated from the barrier layer 13 by a second portion 14b of the passivation layer 14 (preferably of constant thickness). The second field plate 18b can form an extension of the second electrode 16, which preferably extends parallel to the barrier layer 13 in the direction of the first electrode 15.

[0037] The 18a-18b field plates reduce electric field peaks due to abrupt discontinuities between the different materials of component 1. They distribute the electric field more uniformly within component 1 and improve its voltage resistance.

[0038] Finally, component 1 includes a floating region 19 located in the barrier layer 13 directly above one flank of the first field plate 18a. A floating region is defined as a region subjected to no external electrical polarization (i.e., no electrical potential is applied to this region), unlike the first and second electrodes 15-16. Thus, the floating region 19 is electrically isolated from the electrodes of component 1. A first portion of the barrier layer 13 separates the floating region 19 from the first electrode 15, and a second portion of the barrier layer 13 separates the floating region 19 from the second electrode 16.

[0039] The flank of the first field plate 18a, under which the floating region 19 is located, is the one furthest from the first electrode 15. In other words, the floating region 19 is located directly above a distal end of the first field plate 18a (relative to the first electrode 15).

[0040] The floating region 19 is made of a p-type doped semiconductor material. This semiconductor material is advantageously the same as that forming the barrier layer 13, in this example AlGaN. Thus, the fabrication of component 1 is simplified. The floating region 19 can, in particular, be formed by doping a portion of the barrier layer 13 with p-type doping impurities (for example, magnesium ions).

[0041] The floating region 19 has a thickness less than that of the barrier layer 13, so as not to interrupt the two-dimensional electron gas 21 between the first electrode 15 and the second electrode 16. The floating region 19 is advantageously in direct contact with the passivation layer 14, as shown in the figure 2 . Floating region 19 can therefore be implemented more easily and at a lower cost.

[0042] The floating region 19 has, in a plane parallel to the substrate 10, at least one dimension smaller than that of the barrier layer 13. In other words, the floating region 19 occupies only a portion of the barrier layer 13 in a plane parallel to the substrate 10. More precisely, in the cross-sectional plane of the figure 2 , the floating region 19 has a width L FZ less than the width L BL of the barrier layer 13, i.e. the distance between the first and second electrodes 15-16.

[0043] The floating region 19 reduces (at a given reverse voltage) the electric field in the portion of the passivation layer 14 located above the floating region 19 and in the portion of the barrier layer 13 separating the floating region 19 from the channel layer 12, and more particularly vertically along the flank of the first field plate 18a. These two areas of the component are usually limiting in terms of voltage withstand, because the electric field is very strong there.

[0044] The reduction of the electric field in the passivation layer 14 and in the barrier layer 13 is the result of greater ionization of donor-type doping impurities (thanks to free charge carriers - holes - brought by the floating region 19) at the interface between the passivation layer 14 and the barrier layer 13. The increase in the density of ionized donors at the interface locally lowers the conduction band in the floating region 19 and in the passivation layer 14, which compensates for the raising of the conduction band due to the presence of the p-doped region.

[0045] By locally reducing the electric field within the component, it can withstand a higher reverse voltage. The component's breakdown voltage is therefore increased.

[0046] There figure 3 represents the forward current density IF of a Schottky lateral diode according to the figure 2 as a function of the forward bias voltage VF and, for comparison, the forward current density IF of a Schottky side diode lacking a floating region 19 in the barrier layer 13.

[0047] The two curves are almost superimposed. This means that the floating region 19 has virtually no impact on the forward performance of the diode, particularly on the threshold voltage and on-state resistance.

[0048] There figure 4 represents the reverse current density IR as a function of the reverse bias voltage VR for these same two lateral Schottky diodes. Again, the curves overlap. The floating region 19 therefore has no influence on the reverse leakage current of the diode. Note that the figure 4 does not represent the diode breakdown voltage.

[0049] Other characterizations (CV in particular) showed that the capacity of the component was not substantially modified by the insertion of the floating region 19 into the barrier layer 13.

[0050] Thus, compared to a p-doped confinement layer disposed under the channel layer 12 and extending over the entire length of the two-dimensional electron gas 21, the floating region 19 disposed in the barrier layer 13 has a limited negative impact on the performance of component 1, and in particular its on-state resistance.

[0051] The floating region 19 is advantageously centered (i.e. arranged symmetrically) with respect to the flank of the first field plate 18a, in order to minimize the electric field in the barrier layer 13 and the passivation layer 14. It can also be slightly offset, towards the first electrode 15 or the second electrode 16, as long as it is crossed by the vertical projection of the flank of the first field plate 18a.

[0052] The width L FZ of the floating region 19 (measured parallel to the substrate 10 in the cross-section plane of the figure 2 ) is preferably less than twice the width L FP of the first field plate 18a. Thus, when the floating region 19 is centered with respect to the (outer) side of the first field plate 18a, it does not come into contact with the first electrode 15.

[0053] The concentration of p-type doping impurities (activated) in the floating region 19 is advantageously between 1.10 18< cm -3< and 2.10 19< cm -3< , in order to obtain a significant reduction in the electric field without excessively decreasing the electron density in the two-dimensional electron gas 21. Depending on the concentration of doping impurities in the floating region 19, the thickness of the floating region 19 can be between 10% and 90% of the barrier layer thickness 13.

[0054] In a second embodiment illustrated by the figure 5 , component 1 comprises several field plates 18a associated with the first electrode 15 and several p-doped floating regions 19, as described previously.

[0055] The field plates 18a preferably form extensions of the first electrode 15 (or projections of the first electrode 15 into the passivation layer 14). They can be separated in pairs by a portion (typically a sublayer) of the passivation layer 14 or, as shown in the figure 5 , in contact with each other, for example in the form of stair steps.

[0056] Each of the floating regions 19 is located in the barrier layer 13 vertically above at least one field plate flank (forming, for some, a transition between two successive field plates), and preferably vertically above one flank of a single field plate. Each floating region 19 reduces the electric field locally, that is, in the portions of the passivation layer 14 and the barrier layer 13 arranged opposite each other. A field plate 19 located below one flank of a (single) field plate 18a has no effect on the electric field below the flank of the adjacent field plate 18a.

[0057] Providing several distinct floating regions 19, each associated with a single field plate 18a, rather than a single floating region extending along several field plates, significantly reduces the electric field while limiting the confinement of the two-dimensional electron gas 21.

[0058] Advantageously, each field plate 18a is associated with a single floating region 19.

[0059] Three field plates 18a and three floating regions 19 were shown as examples on the figure 5 . More generally, component 1 can comprise N field plates 18a associated with the first electrode 15 and M floating regions 19, N and M being natural integers greater than or equal to 2 and M being less than or equal to N.

[0060] In a third embodiment illustrated by the figure 6 Component 1 is a heterojunction transistor, also called a high electron mobility transistor (HEMT). The first electrode is a gate electrode, isolated from the heterojunction 20 by a dielectric layer 22, typically made of an oxide called "gate oxide," and the second electrode 16 is a drain electrode. Besides the first electrode 15, the second electrode 16 and all the other elements described previously in relation to the figure 2 , the transistor includes a third electrode 17 forming a source electrode.

[0061] The gate electrode 15 of the transistor is arranged between the drain and source electrodes 16-17. It can split the two-dimensional electron gas 21 in two by extending through the barrier layer 13 and part of the channel layer 12, as illustrated in the figure 6 , or on the contrary leave it whole and stop at barrier layer 13.

[0062] The drain electrode 16 and the source electrode 17 are located at opposite ends of the two-dimensional electron gas 21. When the transistor is in the on state, they are electrically connected by the two-dimensional electron gas 21 and a conduction channel, formed by an inversion layer that accumulates electrons along the gate oxide layer.

[0063] The heterojunction transistor may comprise a single field plate 18a on the gate side and a single floating region 19, as described in relation to the figure 2 , or several (N) grid-side field plates 18a and several (M≤N) floating regions 19, as described in relation to the figure 5 . The field plates 18a and the floating regions 19 are located between the grid electrode 15 and the drain electrode 16 (where the electric field is strongest).

[0064] There figure 7 The figure represents the absolute value of the electric field in the barrier layer 13 of a heterojunction transistor according to an embodiment of the invention (solid line) and, for comparison, that of a transistor according to US2015 / 270355 (dashed line) and that of a transistor without a floating region (dashed line). The transistor according to the invention (shown at the bottom of the figure) comprises a field plate 18a extending from the gate 15 and a single floating region 19. The electric field is simulated at 1 nm under the interface between the barrier layer 13 and the passivation layer 14 (or between the barrier layer 13 and the floating region 19 in the case of US2015 / 270355).

[0065] There figure 7 This shows that when the floating region 19 is introduced into the barrier layer 13, the electric field is reduced in the barrier layer 13, particularly under the flank of the field plate 18a (solid line vs. dashed line). When the floating region 19 is located on the barrier layer 13 (document US2015 / 270355), the electric field, on the contrary, remains unchanged under the flank of the field plate 18a. Worse, it increases sharply at the distal end of the floating region 19, forming a field peak 70 (dashed line).

[0066] There figure 8This figure represents, for these same transistors, the absolute electric field at 1 nm below the heterojunction, in other words, in the so-called "channel" region where the two-dimensional electron gas is formed (however, in the blocked state, the two-dimensional electron gas is depleted). This figure shows that another field peak 80 appears in the channel region, directly above the distal end of the floating region 19, when the latter is located on the barrier layer 13. A high field in the channel region can create hot carriers during transistor switching and lead to its destruction.

[0067] The manufacturing of the heterojunction electronic component 1 may involve the following steps: form successively on the substrate 10, for example by epitaxy, the nucleation layer, the adaptation layers and / or the buffer layer 11 (if applicable), the channel layer 12 and the barrier layer 13; form the p-doped floating region 19 in the barrier layer 13; form the passivation layer 14 on the barrier layer 13; form the first and second electrodes 15-16, by etching the passivation layer 14 and part of the heterojunction 20 and then deposition of one or more metallic materials; form the first field plate 18a and (if applicable) the second field plate 18b, by etching the passivation layer 14 and then deposition of one or more metallic materials, in such a way that the floating region 19 is located above one flank of the first field plate 18a.

[0068] The first and second electrodes 15-16 and the first and second field plates 18a-18b are preferably formed simultaneously.

[0069] Several techniques can be implemented to form the p19 doped floating region in the barrier layer 13.

[0070] The floating region 19 can in particular be formed by implanting p-type doping impurities (such as magnesium ions) into a portion of the barrier layer 13, preferably through a thin passivation layer (thickness between 3 nm and 20 nm to avoid channeling of the implanted ions) disposed on the barrier layer 13 and the opening of a mask disposed on this passivation layer.

[0071] The barrier layer 13 and the floating region 19 can also be formed by successively growing on the channel layer 12 a first sublayer of unintentionally doped semiconductor material (e.g. UID AlGaN) and a second sublayer of p-doped semiconductor material (e.g. AlGaN), then by implanting in regions of the second sublayer (arranged on either side of the floating region 19 to be formed) n-type doping impurities to compensate for the p-doping or hydrogen ions to neutralize the p-type doping impurities.

[0072] Alternatively, the same regions of the second sublayer in p-doped semiconductor material can be etched through openings in a mask, after etching the thin passivation layer, to delimit the floating region 19, then the barrier layer 13 is finalized (i.e. completed) by growing unintentionally doped semiconductor material epitaxially outside the floating region 19. The thin passivation layer prevents the growth of unintentionally doped semiconductor material above the floating region 19.

[0073] Finally, a last technique for forming the floating region 19 involves etching a portion of the barrier layer 13 through the opening of a mask, after etching the thin passivation layer, and then growing the p-doped semiconductor material by epitaxy in the etched area. The thin passivation layer prevents the growth of the p-doped semiconductor material outside the etched area.

Claims

1. Heterojunction electronic component (1) comprising: - a substrate (10); - a heterojunction (20) comprising a channel layer (12) arranged on the substrate (10) and a barrier layer (13) arranged on the channel layer (12); - a passivation layer (14) arranged on the barrier layer (13); - a field plate (18a) separated from the barrier layer (13) by a portion (14a) of the passivation layer (14); - a floating region (19) made from a p-doped semiconductor material in vertical alignment with a flank of the field plate (18a); characterised in that the floating region (19) is located in the barrier layer (13) and has a thickness less than that of the barrier layer (13).

2. Component (1) according to claim 1, wherein the floating region (19) has a concentration in p type doping impurities comprised between 1.1018 cm-3 and 2.1019 cm-3.

3. Component (1) according to one of claims 1 and 2, wherein the floating region (19) is centred with respect to the flank of the field plate (18a).

4. Component (1) according to any of claims 1 to 3, wherein the floating region (19) has a width (LFZ) less than twice the width (LFP) of the field plate (18a).

5. Component (1) according to any of claims 1 to 4, comprising a plurality of field plates (18a) and a plurality of floating regions (19) made from a p-doped semiconductor material, each floating region (19) being located in the barrier layer (13) in vertical alignment with a flank of one of the field plates (18a).

6. Component (1) according to any of claims 1 to 5, further comprising a first electrode (15) and a second electrode (16) separated from the first electrode (15) by at least a portion of the passivation layer (14).

7. Component (1) according to claim 6, wherein the field plate (18a) forms an extension of the first electrode (15).

8. Component (1) according to one of claims 6 and 7, of the diode type, wherein the first electrode (15) is an anode and the second electrode (16) is a cathode.

9. Component (1) according to one of claims 6 and 7, of the transistor type, wherein the first electrode (15) is a gate electrode and the second electrode is a drain electrode (16).

10. Component (1) according to any of claims 1 to 9, wherein the barrier layer (13) is comprised of an unintentionally doped semiconductor material.

11. Component (1) according to any of claims 1 to 10, wherein the floating region (19) is in direct contact with the passivation layer (14).