LDO power supply circuit and power amplifier

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a technical field of radio frequency communications, and in particular to a low dropout regulator (LDO) power supply circuit and a power amplifier.BACKGROUND

[0002] At present, power control methods of a power amplifier includes a current control method and a voltage control method.

[0003] A current control technology, also known as a base electrode control technology, is a closed-loop control. By detecting a current output from an output end of the power amplifier, the current output from the output end of the power amplifier is input to a feedback end of a low dropout regulator (LDO) power supply circuit, and is combined with a control voltage Vramp, then a power control of the power amplifier is realized by adjusting a bias current of the power amplifier.

[0004] A voltage control technology is also known as a collector electrode control technology. The control voltage Vramp controls a voltage of the LDO power supply circuit. The LDO power supply circuit provides power for the power amplifier.

[0005] In the prior art, when the power amplifier is controlled by the control voltage Vramp, regardless of whether the voltage control method or the current control method is used, a switching spectrum of the power amplifier is greatly affected by a rising slope of the control voltage Vramp and a falling slope of the control voltage Vramp, so a slope of the control voltage Vramp needs to be controlled to obtain a good switching spectrum performance of the power amplifier.

[0006] Therefore, it is necessary to provide an LDO power supply circuit and a new power amplifier to solve the above problems in the prior art. US2013 / 002220A1 discloses a semiconductor integrated circuit for regulator including: a control transistor; a voltage divider circuit generating a feedback voltage proportional to an output voltage; a control circuit controlling the control transistor based on difference between the feedback voltage and a reference voltage; and a terminal through which an output voltage switching control signal is received, and being configured to switch the output voltage into a first voltage or into a second voltage lower than the first voltage, by varying division ratio in the voltage divider circuit in response to the signal. The semiconductor integrated circuit further includes: a discharging transistor between the output terminal and the ground; and a circuit outputting a signal for keeping the discharging transistor turned on over a period from change of the signal to fall of the output voltage from the first voltage down to the second voltage. WO2019 / 161655A1 discloses a feedback control circuit for a power amplifier. The circuit comprises a feedback acquisition circuit, a VLDO control circuit, a radio frequency signal amplifying circuit, a choke inductor, and a matching circuit; the feedback acquisition circuit is used for acquiring a voltage signal by means of an acquisition tube, and converting the voltage signal into an output current signal and sending the output current signal to the VLDO control circuit; the VLDO control circuit is used for receiving the output current signal, which controls output of a VLDO voltage signal together with a Vramp voltage; the radio frequency signal amplifying circuit is used for receiving the VLDO voltage signal, and adjusting the voltage and the power of the output voltage signal together with the choke inductor and the matching circuit. US2018 / 120881A1 discloses apparatus and methods for programmable low dropout regulators for radio frequency electronics. In certain configurations, an LDO regulator for generating a programmable output voltage includes a regulation field-effect transistor having a drain electrically connected to the LDO regulator's output, an error amplifier that controls a gate of the regulation FET, a feedback circuit that provides a feedback signal to an inverting input of the error amplifier, an output capacitor electrically connected to the LDO regulator's output, and an alternative discharge circuit. When the output voltage of the LDO regulator is programmed from a high voltage level to a low voltage level, the alternative discharge circuit activates to discharge the output capacitor to improve the LDO regulator's transient response.SUMMARY

[0007] In view of the above technical problems in the prior art, the present disclosure provides a low dropout regulator (LDO) power supply circuit and a power amplifier with a good switching spectrum performance.

[0008] In order to solve the above technical problems in the prior art, in a first aspect, embodiments of the present disclosure provide the LDO power supply circuit including an operational amplifier, a first transistor, and a resistance feedback network.

[0009] A negative electrode input end of the operational amplifier is configured to be connected to a control voltage. A positive electrode input end of the operational amplifier is an input end of the LDO power supply circuit. An output end of the operational amplifier is connected to a gate electrode of the first transistor.

[0010] A source electrode of the first transistor is configured to be connected to a power supply voltage. A drain electrode of the first transistor is an output end of the LDO power supply circuit.

[0011] The resistance feedback network is connected between the drain electrode of the first transistor and the positive electrode input end of the operational amplifier. The resistance feedback network comprises a first resistance, a second resistance, a third resistance, and a second transistor; a first end of the first resistance is connected to the drain electrode of the first transistor; a second end of the first resistance is connected to the positive electrode input end of the operational amplifier; a first end of the second resistance is connected to the second end of the first resistance; a second end of the second resistance is grounded; a first end of the third resistance is connected to the second end of the first resistance; a second end of the third resistance is connected to a drain electrode of the second transistor; a source electrode of the second transistor is grounded; and the first resistance and the second resistance jointly form a first feedback coefficient; the first resistance, the third resistance, and the second transistor jointly form a second feedback coefficient, and the first feedback coefficient is different from the second feedback coefficient. A gate electrode of the second transistor is configured to be connected to the control voltage and controlled by the control voltage to turn on.

[0012] Optionally, the first transistor is a positive channel metal oxide semiconductor (PMOS) transistor, and the second transistor is an N-Metal-Oxide-Semiconductor (NMOS) transistor.

[0013] Optionally, the LDO power supply circuit further includes a voltage stabilizing capacitor. A first end of the voltage stabilizing capacitor is connected to the drain electrode of the first transistor. A second end of the voltage stabilizing capacitor is grounded.

[0014] In a second aspect, the embodiments of the present disclosure further provide a power amplifier including a bias circuit, an input end of the power amplifier, an input matching circuit, a power amplifier unit, an output matching circuit, and an output end of the power amplifier. The input end of the power amplifier, the input matching circuit, the power amplifier unit, the output matching circuit, and the output end of the power amplifier are connected in sequence. An output end of the bias circuit is connected to an input end of the power amplifier unit. The power amplifier further includes the LDO power supply circuit provided by the present disclosure. The input end of the LDO power supply circuit is connected to the input end of the power amplifier unit. The output end of the LDO power supply circuit is connected to an input end of the bias circuit to form a current feedback control of the power amplifier unit.

[0015] Optionally, the power amplifier further includes a choke inductor. A first end of the choke inductor is connected to the power supply voltage. A second end of the choke inductor is connected to an output end of the power amplifier unit.

[0016] In a third aspect, the embodiments of the present disclosure further provide a power amplifier including a bias circuit, an input end of the power amplifier, an input matching circuit, a power amplifier unit, an output matching circuit, and an output end of the power amplifier. The input end of the power amplifier, the input matching circuit, the power amplifier unit, the output matching circuit, and the output end of the power amplifier are connected in sequence. The output end of the bias circuit is connected to the input end of the power amplifier unit. The input end of the bias circuit is connected to the power supply voltage. The power amplifier further includes the LDO power supply circuit provided by the present disclosure. The output end of the LDO power supply circuit is connected to the output end of the power amplifier unit to form a voltage feedback control of the power amplifier unit.

[0017] Optionally, the power amplifier further includes the choke inductor. The output end of the LDO power supply circuit is connected in series with the choke inductor, the output end of the LDO power supply circuit is connected to the output end of the power amplifier unit.

[0018] Optionally, a plurality of N-Metal-Oxide-Semiconductor (NMOS) transistors are connected in series to form the power amplifier unit.

[0019] Optionally, the power amplifier unit is an N-type power amplifier triode.

[0020] Compared with the prior art, the present disclosure provides the LDO power supply circuit and the power amplifier, in which the resistance feedback network is connected between the drain electrode of the first transistor and the positive electrode input end of the operational amplifier in the LDO power supply circuit. The resistance feedback network forms the first feedback coefficient and the second feedback coefficient. By adopting a combination of two different feedback coefficients, a rising slope of an output voltage V LDO of the LDO power supply circuit is improved, thereby effectively improving the switching spectrum performance of the power amplifier applying the LDO power supply circuit.BRIEF DESCRIPTION OF DRAWINGS

[0021] The present disclosure will be described in detail below with reference to the accompanying drawings. The above or other aspects of the present disclosure will be more clearly and more readily understood by reference to following detailed description of the accompanying drawings. In the drawings: FIG. 1 is a circuit diagram of a low dropout regulator (LDO) power supply circuit according to one embodiment of the present disclosure. FIG. 2 is a circuit diagram of a power amplifier according to a first embodiment of the present disclosure. FIG. 3 is another circuit diagram of the power amplifier according to the first embodiment of the present disclosure. FIG. 4 is a power output simulation diagram of the power amplifier according to the first embodiment of the present disclosure. FIG. 5 is a circuit diagram of the power amplifier according to a second embodiment of the present disclosure. FIG. 6 is another circuit diagram of the power amplifier according to the second embodiment of the present disclosure. DETAILED DESCRIPTION OF EMBODIMENTS

[0022] The embodiments of the present disclosure are further described below with reference to the accompanying drawings.

[0023] Specific embodiments described herein are the specific embodiments of the present disclosure, which are used to illustrate concepts of the present disclosure and are explanatory and exemplary, and should not be construed as being limited to the embodiments of the present disclosure and protection scope of the present disclosure set forth herein. Except for the embodiments described herein, a person of ordinary skill in the art may also adopt other obvious technical solutions based on contents of claims and specification disclosed in the present disclosure, the technical solutions include any obvious replacement and modification technical solutions adopting the embodiments described herein, which are all within the protection scope of the present disclosure.

[0024] Following description of the embodiments is provided with reference to the accompanying drawings, and is used to illustrate specific embodiments that can be implemented by the present disclosure. Directional terms mentioned in the present disclosure, for example, up, down, front, rear, left, right, inside, outside, and side surfaces, etc., are merely directions referring to the accompanying drawings. Therefore, the directional terms used herein are used to illustrate and understand the present disclosure, but are not intended to limit the present disclosure.

[0025] Please refer to FIG. 1, which is a circuit diagram of a low dropout regulator (LDO) power supply circuit according to one embodiment of the present disclosure, the present disclosure provides the LDO power supply circuit 100 including an operational amplifier OP, a first transistor P1, and a resistance feedback network 10.

[0026] A negative electrode input end of the operational amplifier OP is configured to be connected to a control voltage Vramp. A positive electrode input end of the operational amplifier OP is an input end of the LDO power supply circuit 100. An output end of the operational amplifier OP is connected to a gate electrode of the first transistor P1.

[0027] A source electrode of the first transistor P1 is configured to be connected to a power supply voltage VBAT. A drain electrode of the first transistor P1 is an output end of the LDO power supply circuit 100 configured to generate an output voltage V LDO of the LDO power supply circuit 100.

[0028] The resistance feedback network 10 is connected between the drain electrode of the first transistor P1 and the positive electrode input end of the operational amplifier OP. The resistance feedback network 10 forms a first feedback coefficient and a second feedback coefficient. The first feedback coefficient is different from the second feedback coefficient. By adopting a design of a circuit structure described above and a combination of two different feedback coefficients, a rising slope of the output voltage V LDO of the LDO power supply circuit 100 is improved, thereby effectively improving a switching spectrum performance of the power amplifier applying the LDO power supply circuit 100.

[0029] The resistance feedback network 10 includes a first resistance R4, a second resistance R5, a third resistance R6, and a second transistor N0.

[0030] A first end of the first resistance R4 is connected to the drain electrode of the first transistor P1. A second end of the first resistance R4 is connected to the positive electrode input end of the operational amplifier OP.

[0031] A first end of the second resistance R5 is connected to the second end of the first resistance R4. A second end of the second resistance R5 is grounded.

[0032] A first end of the third resistance R6 is connected to the second end of the first resistance R4. A second end of the third resistance R6 is connected to a drain electrode of the second transistor N0.

[0033] A gate electrode of the second transistor N0 is configured to be connected to the control voltage Vramp and controlled by the control voltage Vramp. A source electrode of the second transistor N0 is grounded.

[0034] The first resistance R4 and the second resistance R5 jointly form the first feedback coefficient. The first resistance R4, the third resistance R6, and the second transistor N0 jointly form the second feedback coefficient.

[0035] In the embodiment, the first transistor P1 is a positive channel metal oxide semiconductor (PMOS) transistor, and the second transistor N0 is an N-Metal-Oxide-Semiconductor (NMOS) transistor.

[0036] Optionally, the LDO power supply circuit 100 further includes a voltage stabilizing capacitor C3. A first end of the voltage stabilizing capacitor C3 is connected to the drain electrode of the first transistor P1. A second end of the voltage stabilizing capacitor C3 is grounded. The voltage stabilizing capacitor C3 is a voltage stabilizing capacitor for the output voltage V LDO of the LDO power supply circuit 100 output from the output end of the LDO power supply circuit 100.

[0037] Some embodiments of the power amplifier applying the LDO power supply circuit 100 mentioned above are provided below for detailed explanation:Embodiment 1

[0038] Please refer to FIG. 2, which is a circuit diagram of a power amplifier according to a first embodiment of the present disclosure, the present disclosure provides the power amplifier 200 including a bias circuit 201, an input end RF_IN of the power amplifier 200, an input matching circuit 202, a power amplifier unit 203, an output matching circuit 204, an output end RF_OUT of the power amplifier 200, and the LDO power supply circuit 100 provided by the present disclosure. The input end RF_IN of the power amplifier 200, the input matching circuit 202, the power amplifier unit 203, the output matching circuit 204, and the output end RF_OUT of the power amplifier 200 are connected in sequence. The power amplifier 200 further includes a driver amplifier unit 205, and the driver amplifier unit 205 is connected between the input end RF_IN of the power amplifier 200 and the input matching circuit 202. The input port RF_IN of the power amplifier 200, the driver amplifier unit 205, and the input matching circuit 202 are connected in series.

[0039] An output end of the bias circuit 201 is connected to an input end of the power amplifier unit 203. The input end of the LDO power supply circuit 100 is connected to the input end of the power amplifier unit 203. The output end of the LDO power supply circuit 100 is connected to an input end of the bias circuit 201 to control a feedback current of the power amplifier unit 203.

[0040] Specifically, in the embodiment of the present disclosure, the input matching circuit 202 is a second capacitor C4.

[0041] A plurality of N-Metal-Oxide-Semiconductor (NMOS) transistors are connected in series to form the power amplifier unit 203. Specifically, the plurality of the NMOS transistors include a third transistor N2, a fourth transistor N3, and a fifth transistor N4, which are connected in sequence. A gate electrode of the third transistor N2 is the input end of the power amplifier unit 203. A source electrode of the third transistor N2 is grounded. A drain electrode of the third transistor N2 is connected to a source electrode of the fourth transistor N3. A gate electrode of the fourth transistor N3 is connected to a first stabilized voltage supply VG3. A drain electrode of the fourth transistor N3 is connected to a source electrode of the fifth transistor N4. A gate electrode of the fifth transistor N4 is connected to a second stabilized voltage supply VG4. A drain electrode of the fifth transistor N4 is an output end of the power amplifier unit 203.

[0042] The driver amplifier unit 205 includes a first drive amplifier AMP 1 and a second drive amplifier AMP2. The first drive amplifier AMP1 and the second drive amplifier AMP2 are connected in sequence.

[0043] Optionally, the power amplifier 200 further includes a choke inductor L1. A first end of the choke inductor L1 is connected to the power supply voltage VBAT. A second end of the choke inductor L1 is connected to the output end of the power amplifier unit 203.

[0044] When the control voltage Vramp is low, a proportional relationship between the output voltage V LDO of the LDO power supply circuit 100 and the control voltage Vramp is: V LDO = 1 + R 4 / R 5 × Vramp − R 4 × I fb

[0045] I fb is a feedback current that outputs to the output end of the LDO power supply circuit 100.

[0046] When the control voltage Vramp rises to turn on the second transistor N0, a feedback ratio of the output voltage V LDO of the LDO power supply circuit 100 is: V LDO = 1 + R 4 / R 6 + R n / / R 5 × Vramp − R 4 × I fb

[0047] Generally, the resistances satisfy R 5 > R 6 + R n , where R n is the resistance of the second transistor N0, and the above formula may be simplified to be: V LDO ≈ 1 + R 4 / R 6 + R n × Vramp − R 4 × I fb

[0048] When the control voltage Vramp rises to be greater, more than 1V and the resistance of the second transistor N0 is small, and R n can be ignored. The feedback ratio of the output voltage V LDO of the LDO power supply circuit 100 is: V LDO ≈ 1 + R 4 / R 6 × Vramp − R 4 × I fb

[0049] The resistances satisfy R 5 > R 6 + R n > R 6 . Therefore,as the control voltage Vramp rises from low to high, the feedback ratio of the output voltage V LDO of the LDO power supply circuit 100 is gradually increased. A principle of optimizing the switching spectrum of the power amplifier is as follows: when the control voltage Vramp is low, an internal circuit is in a low voltage state, and a voltage value and the slope of the output voltage V LDO of the LDO power supply circuit 100 must be small to obtain a good switching spectrum performance of the power amplifier.

[0050] In the embodiment of the present disclosure, the power amplifier unit of the power amplifier is an N-type power amplifier triode Q2. As shown in FIG. 3, which is another circuit diagram of the power amplifier according to the first embodiment of the present disclosure, and the power amplifier shown in FIG. 3 is basically same as the power amplifier shown in FIG. 2, except that a structure of the power amplification unit described above is different, and the principle thereof is same, and details are not described herein again.

[0051] As shown in FIG. 4, FIG. 4 is a power output simulation diagram of the power amplifier according to the first embodiment of the present disclosure. Through simulation, it should be noted that, the power amplifier in the prior art only uses a single feedback coefficient, i.e., the power amplifier does not use a circuit of the second transistor N0 and the third resistor R6, and a power output waveform of the power amplifier is as shown in a curve of a waveform 1, and the output voltage V LDO of the LDO power supply circuit 100 reaches up to 1.6 V.

[0052] However, the power amplifier of the present disclosure adopts the combination of two different feedback coefficients, i.e., after the power amplifier uses the circuit of the second transistor N0 and the third resistor R6, the power output waveform of the power amplifier is shown as a curve of a waveform 2, and the output voltage V LDO of the LDO power supply circuit 100 reaches up to 2.2 V. A higher output voltage V LDO of the LDO power supply circuit 100 means that the power amplifier can provide a higher power output.

[0053] When the control voltage Vramp is low, the curve of the waveform 1 and the curve of the waveform 2 basically coincide and reach a same slope. Therefore, the curve of the waveform 2 has a slow rise when the control voltage Vramp is low, thereby ensuring the good switching spectrum performance of the power amplifier. When the control voltage Vramp is relatively high, the output voltage V LDO of the LDO power supply circuit 100 is high, thereby ensuring a high output power of the power amplifier.

[0054] Compared with the prior art, the power amplifier of the present disclosure adopts the combination of two different feedback coefficients, i.e., the power amplifier uses the circuit of the second transistor N0 and the third resistor R6, the high output power of the power amplifier can be obtained under a condition of ensuring a certain switching spectrum performance of the power amplifier.Embodiment 2

[0055] Please refer to FIG. 5, which is a circuit diagram of the power amplifier according to a second embodiment of the present disclosure. In the embodiment of the present disclosure, a circuit structure of the power amplifier is basically same as the circuit structure of the power amplifier of the first embodiment, and a difference between the first embodiment and the second embodiment lies in a control method of the LDO power supply circuit 100, i.e., a connection method of the LDO power supply circuit 100 connected to the power amplifier in first embodiment is different from the connection method of the LDO power supply circuit 100 connected to the power amplifier in second embodiment, which is specifically as follows:

[0056] The power amplifier 400 includes a bias circuit 401, the input end RF_IN of the power amplifier 400, an input matching circuit 402, a power amplifier unit 403, an output matching circuit 404, the output end RF_OUT of the power amplifier 400, and the LDO power supply circuit 100 provided by the present disclosure. The input end RF_IN of the power amplifier 400, the input matching circuit 402, the power amplifier unit 403, the output matching circuit 404, and the output end RF_OUT of the power amplifier 400 are connected in sequence. The power amplifier 400 further includes a driver amplifier unit 405, and the driver amplifier unit 405 is connected between the input end RF_IN of the power amplifier and the input matching circuit 402. The input end RF_IN of the power amplifier 400, the driver amplifier unit 405, and the input matching circuit 402 are connected in series.

[0057] The output end of the bias circuit 401 is connected to the input end of the power amplifier unit 403. The input end of the bias circuit 401 is connected to the power supply voltage VBAT. The output end of the LDO power supply circuit 100 is connected to the output end of the power amplifier unit 403 to control form a voltage feedback control of the power amplifier unit 403.

[0058] In the embodiment of the present disclosure, the power amplifier 400 further includes the choke inductor L1. The output end of the LDO power supply circuit 100 is connected in series with the choke inductor L1, and the output end of the LDO power supply circuit 100 is connected to the output end of the power amplifier unit 403.

[0059] The principle of optimizing the switching spectrum of the power amplifier is as follows: when the control voltage Vramp is low, the internal circuit is in the low voltage state, and the voltage value of the output voltage V LDO of the LDO power supply circuit 100 and the slope of the output voltage V LDO of the LDO power supply circuit 100 must be small to obtain a good switching spectrum performance of the power amplifier. When the control voltage Vramp is high, the output voltage V LDO rises to provide power to the power amplifier 400, so that the power amplifier 400 reaches a required output power. When the control voltage Vramp is high, if a relatively low feedback ratio of the output voltage V LDO of the LDO power supply circuit 100 is still used, the low output voltage V LDO of the LDO power supply circuit 100 is low, resulting in a low output power of the power amplifier 400 that cannot meet requirements of the output power of the power amplifier 400. However, in the embodiment of the present disclosure, a high, a medium or a low feedback ratio of the output voltage V LDO of the LDO power supply circuit 100 satisfies requirements for the output power of the power amplifier and the switching spectrum of the power amplifier.

[0060] In addition to the differences mentioned above, and other features in the second embodiment are same as that in the first embodiment, and details are not described herein again.

[0061] In the embodiment of the present disclosure, the power amplifier unit 403 of the power amplifier 400 is an N-type power amplifier triode Q2. As shown in FIG. 6, which is a second circuit diagram of the power amplifier according to second embodiment of the present disclosure, and the power amplifier shown in FIG. 6 is basically same as the power amplifier shown in FIG. 7, except that the structure of the power amplification unit described above is different, but the principle of optimizing the switching spectrum of the power amplifier is same, and details are not described herein again.

[0062] Compared with the prior art, the present disclosure provides the LDO power supply circuit 100 and the power amplifier, in which the resistance feedback network is connected between the drain electrode of the first transistor and the positive electrode input end of the operational amplifier in the LDO power supply circuit 100. The resistance feedback network forms the first feedback coefficient and the second feedback coefficient. The first feedback coefficient is different from the second feedback coefficient. By adopting a combination of two different feedback coefficients, a rising slope of an output voltage V LDO of the LDO power supply circuit 100 is improved, thereby effectively improving the switching spectrum performance of the power amplifier applying the LDO power supply circuit 100.

Claims

1. A low dropout regulator LDO, power supply circuit (100), comprising: an operational amplifier (OP); a first transistor (P1); and a resistance feedback network (10); wherein a negative electrode input end of the operational amplifier (OP) is configured to be connected to a control voltage (Vramp); an output end of the operational amplifier (OP) is connected to a gate electrode of the first transistor (P1); a source electrode of the first transistor (P1) is configured to be connected to a power supply voltage (VBAT); a drain electrode of the first transistor (P1) is an output end of the LDO power supply circuit (100); and the resistance feedback network (10) is connected between the drain electrode of the first transistor (P1) and the positive electrode input end of the operational amplifier (OP); the resistance feedback network (10) comprises a first resistance (R4), a second resistance (R5), a third resistance (R6), and a second transistor (N0); wherein: a first end of the first resistance (R4) is connected to the drain electrode of the first transistor (P1); a second end of the first resistance (R4) is connected to the positive electrode input end of the operational amplifier (OP); a first end of the second resistance (R5) is connected to the second end of the first resistance (R4); a second end of the second resistance (R5) is grounded; a first end of the third resistance (R6) is connected to the second end of the first resistance (R4); a second end of the third resistance (R6) is connected to a drain electrode of the second transistor (N0); a source electrode of the second transistor (N0) is grounded; and the first resistance (R4) and the second resistance (R5) jointly form a first feedback coefficient; the first resistance (R4), the third resistance (R6), and the second transistor (N0) jointly form a second feedback coefficient; the first feedback coefficient is different from the second feedback coefficient; characterized in that a positive electrode input end of the operational amplifier (OP) is an input end of the LDO power supply circuit (100); a gate electrode of the second transistor (N0) is configured to be connected to the control voltage (Vramp) and the second transistor (N0) is controlled by the control voltage (Vramp) to turn on.

2. The LDO power supply circuit (100) according to claim 1, wherein the first transistor (P1) is a positive channel metal oxide semiconductor (PMOS) transistor; the second transistor (N0) is an N-Metal-Oxide-Semiconductor (NMOS) transistor.

3. The LDO power supply circuit (100) according to claim 1, wherein the LDO power supply circuit (100) further comprises a voltage stabilizing capacitor (C3); a first end of the voltage stabilizing capacitor (C3) is connected to the drain electrode of the first transistor (P1); a second end of the voltage stabilizing capacitor (C3) is grounded.

4. A power amplifier (200), comprising: a bias circuit (201); an input end (RF_IN) of the power amplifier (200); an input matching circuit (202); a power amplifier unit (203); an output matching circuit (204); and an output end (RF_OUT) of the power amplifier (200); wherein the input end (RF _IN) of the power amplifier (200), the input matching circuit (202), the power amplifier unit (203), the output matching circuit (204), and the output end (RF_OUT) of the power amplifier (200) are connected in sequence; an output end of the bias circuit (201) is connected to an input end of the power amplifier unit (203); and the power amplifier (200) further comprises the LDO power supply circuit (100) according to any one of claims 1-3; the input end of the LDO power supply circuit (100) is connected to the input end of the power amplifier unit (203); the output end of the LDO power supply circuit (100) is connected to an input end of the bias circuit (201) to form a current feedback control of the power amplifier unit (203).

5. The power amplifier (200) according to claim 4, wherein the power amplifier (200) further comprises a choke inductor (L1); a first end of the choke inductor (L1) is connected to the power supply voltage (VBAT); a second end of the choke inductor (L1) is connected to an output end of the power amplifier unit (203).

6. A power amplifier (400), comprising: a bias circuit (401); an input end (RF _IN) of the power amplifier (400); an input matching circuit (402); a power amplifier unit (403); an output matching circuit (404); and an output end (RF_OUT) of the power amplifier (400); wherein the input end (RF _IN) of the power amplifier (400), the input matching circuit (402), the power amplifier unit (403), the output matching circuit (404), and the output end (RF_OUT) of the power amplifier (400) are connected in sequence; an output end of the bias circuit (401) is connected to the input end of the power amplifier unit (403); the power amplifier (400) further comprises the LDO power supply circuit (100) according to any one of claims 1-3; an input end of the bias circuit (401) is connected to the power supply voltage (VBAT); the output end of the LDO power supply circuit (100) is connected to the output end of the power amplifier unit (403) to form a voltage feedback control of the power amplifier unit (403).

7. The power amplifier (400) according to claim 6, wherein the power amplifier (400) further comprises the choke inductor (L1); the output end of the LDO power supply circuit (100) is connected in series with the choke inductor (L1), and the output end of the LDO power supply circuit (100) is connected to the output end of the power amplifier unit (403).

8. The power amplifier (200, 400) according to any one of claims 4-7, wherein a plurality of NMOS transistors are connected in series to form the power amplifier unit (203, 403).

9. The power amplifier (200, 400) according to any one of claims 4-7, wherein the power amplifier unit (203, 403) is an N-type power amplifier triode.