INTERACTIVE DISPLAY DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE

Description

Domaine technique

[0001] This description relates generally to the field of image display devices, and more specifically to an interactive image display device combining a light emission function and an electromechanical transduction function, for example, a haptic feedback function. This description also relates to a method for manufacturing such a device. Technique antérieure

[0002] Various applications can benefit from an interactive image display device that combines a light emission function with an electromechanical transduction function. Such a device can, for example, be used to create large-format interactive displays, such as computer screens, television screens, tablet screens, etc.

[0003] US document 2019 / 197284 describes ultrasonic transducers incorporated into an organic light-emitting diode panel and display devices containing such transducers.

[0004] US document 2019 / 187748 describes a light-emitting audio device, an audio-emitting device, and a display device.

[0005] US document 2017 / 110504 describes a pixel with an integrated piezoelectric micromechanical ultrasonic transducer and an array of such transducers. Summary of the invention

[0006] An object of an embodiment is to overcome all or part of the disadvantages of known solutions for creating an interactive image display device combining a light emission function and an electromechanical transduction function.

[0007] For this purpose, the invention provides an optoelectronic device comprising at least one electromechanical transducer located directly above at least one light-emitting diode, said at least one electromechanical transducer and said at least one light-emitting diode being connected to conductive tracks of the same carrier substrate.

[0008] According to one embodiment, said at least one electromechanical transducer and said at least one light-emitting diode are located on the same side of the substrate.

[0009] According to one embodiment, said at least one electromechanical transducer is located on the side of a first face of the transfer substrate and said at least one light-emitting diode is located on the side of a second face of the transfer substrate, opposite to the first face.

[0010] According to one embodiment, the device comprises a plurality of electromechanical transducers forming a first matrix and a plurality of light-emitting diodes forming a second matrix, the first matrix having a pitch greater than the second matrix.

[0011] According to one embodiment, the device includes a planarization layer extending laterally between the light-emitting diodes, and a transparent protective cover covering the light-emitting diodes and the planarization layer.

[0012] According to one embodiment, the device further comprises pillars passing through the planarization layer and mechanically connecting the transducers to the transparent protective cover.

[0013] According to one embodiment, said at least one electromechanical transducer has lateral dimensions greater than said at least one light-emitting diode.

[0014] According to one embodiment, the conductive tracks form an interconnection network configured to control said at least one electromechanical transducer and said at least one light-emitting diode.

[0015] According to one embodiment, the device further comprises, for each electromechanical transducer, a selection transistor connected to said electromechanical transducer.

[0016] According to one embodiment, the selection transistor comprises a first conduction terminal connected to an electrode of said electromechanical transducer, a second conduction terminal connected to one of the conductive tracks of the carrier substrate and a control terminal connected to another track among the conductive tracks of the carrier substrate.

[0017] According to one embodiment, said at least one electromechanical transducer comprises an active layer based on lead zirconate titanoate or aluminium nitride.

[0018] According to an embodiment not part of the invention as claimed, each light-emitting diode comprises a single elementary diode adapted to emit light in a range of wavelengths.

[0019] According to the invention, each light-emitting diode comprises an elementary chip having several elementary diodes adapted respectively to emit light in different wavelength ranges and an elementary circuit for controlling the elementary diodes.

[0020] According to one embodiment, said at least one electromechanical transducer is a piezoelectric transducer.

[0021] According to one embodiment, said at least one electromechanical transducer is a PMUT or CMUT transducer.

[0022] The invention provides a method for manufacturing an optoelectronic device comprising the following successive steps: a) to mount at least one electromechanical transducer on a substrate; and b) to mount at least one light-emitting diode on the substrate, directly above said at least one electromechanical transducer, said at least one electromechanical transducer and said at least one light-emitting diode being connected to conductive tracks of the reporting substrate. Brève description des dessins

[0023] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: THE figures 1A, 1B, 1C, 1D et 1E are cross-sectional views illustrating successive stages of an example of a manufacturing process for an optoelectronic device according to a given embodiment; the figure 2 is a cross-sectional view illustrating a variant of the optoelectronic device of the 1E ; THE figures 3A, 3B, 3C, 3D, 3E , 3F, 3G, 3H et 3I are cross-sectional views illustrating successive stages of an example of a manufacturing process for an optoelectronic device according to a given embodiment; the figure 4 is a schematic and partial top view illustrating an example of an interconnection network for an optoelectronic device; the figure 5 is an electrical diagram equivalent to the interconnection network of the figure 4 ; there figure 6 is a cross-sectional view schematically and partially illustrating a variant embodiment of the optoelectronic device of the figure 1E ; and the figure 7 is a cross-sectional view schematically and partially illustrating a variant embodiment of the optoelectronic device of the figure 6 . Description des modes de réalisation

[0024] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, the implementation of the electromechanical transducers, light-emitting diodes (LEDs), and integrated circuits for controlling the described devices has not been detailed, as the detailed implementation of these components is within the grasp of a person skilled in the art based on the information provided in this description. Furthermore, the various applications of the described devices have not been detailed, as the described embodiments are compatible with all or most applications that could benefit from a device combining a light emission function and an electromechanical transduction function.

[0026] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements.

[0027] The "transmittance of a layer" is defined as the ratio of the intensity of radiation exiting the layer to the intensity of radiation entering the layer. In the following description, a layer or film is said to be opaque to radiation when the transmittance of the radiation through the layer or film is less than 10%. In the following description, a layer or film is said to be transparent to radiation when the transmittance of the radiation through the layer or film is greater than 10%.

[0028] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0029] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0030] According to one aspect of an embodiment, an optoelectronic device combining a light emission function and an electromechanical transduction function, for example a haptic feedback function, is made by implementing a process comprising the steps of forming at least one electromechanical transducer on one face of a transfer substrate, and then transferring at least one light-emitting diode (LED) onto the transfer substrate, directly above the electromechanical transducer.

[0031] The f igures 1A à 1E These are cross-sectional views illustrating successive stages of a non-limiting example of implementing such a process. igures 1A à 1E illustrate more precisely successive manufacturing steps of an optoelectronic device 100 comprising electromechanical transducers T, for example electroacoustic transducers, for example ultrasonic transducers, and light-emitting diodes D located on the same side of face 101T of a transfer substrate 101. Various variants are within the reach of a person skilled in the art from the indications in this description.

[0032] For the sake of simplicity, the igures 1A à 1E illustrate the realization of an example of an optoelectronic device comprising two electromechanical transducers and six light-emitting diodes. This example is not limiting, however; the described process can of course be adapted to realize optoelectronic devices comprising different numbers of electromechanical transducers and light-emitting diodes than those shown, for example, several thousand electromechanical transducers and light-emitting diodes.

[0033] There figure 1A is a cross-sectional view illustrating a structure obtained at the end of a formation step, on face 101T of the transfer substrate 101 (the upper face of the transfer substrate 101, in the orientation of the figure 1A ), of an electrically conductive layer 103.

[0034] The 101 substrate can have a monolithic structure or can be a layer covering a support made of another material. For example, the 101 substrate can be made of a transparent material, such as glass or a transparent polymer. Generally, the 101 substrate can be made of any type of material suitable for receiving the electromechanical transducers T.

[0035] The electrically conductive layer 103 covers the upper face 101T of the substrate 101 and is intended to form one or more electrodes of the electromechanical transducers T. More precisely, in the example shown, the layer 103 extends continuously over and in contact with the upper face 101T of the substrate 101 and is intended to form an electrode (the lower electrode, in the orientation of the figure 1A common to the electromechanical transducers T of the device 100. Alternatively, layer 103 can, for example, be etched, e.g., by photolithography followed by etching, or deposited by a screen-printing process so as to form disjointed parts of layer 103, each defining a lower electrode of one or more of the electromechanical transducers T. Connection tracks, not shown, can also be formed in layer 103. The electrically conductive layer 103 is, for example, made of a metal, e.g., gold, silver, platinum, molybdenum, ruthenium, titanium, etc., or of a metal alloy. As an example, layer 103 has a thickness of approximately 300 nm.

[0036] There figure 1B is a cross-sectional view illustrating a structure obtained at the end of a subsequent realization step, on the side of the upper face 101T of the substrate 101, of the electromechanical transducers T.

[0037] In the example shown, each electromechanical transducer T is of the piezoelectric type and has a piezoelectric active layer 105 interposed between the lower electrode 103 and another electrode 107 (the upper electrode, in the orientation of the figure 1B The piezoelectric layer 105 is, for example, made of lead zirconate titanate (PZT) or aluminum nitride (AlN). The upper electrode 107 is, for example, made of a metal, for example, chosen from the list of metals indicated previously for layer 103, or of a metal alloy. The upper electrode 107 is, for example, made of the same material as the lower electrode 103. As an example, the upper electrode 107 has a thickness between 100 and 500 nm, for example, on the order of 200 nm. Alternatively, electrodes 103 and 107 are each made of a transparent conductive material, for example, a transparent conductive oxide (TCO), for example, indium tin oxide (ITO). This makes it possible to create a transparent device.

[0038] For example, a discontinuous layer of conductive adhesive, such as silver paste, is screen-printed onto layer 103, the adhesive layer material being deposited only in locations where the electromechanical transducers T are to be made. A stack comprising the piezoelectric layer 105 and the upper electrode 107 is then transferred, for each piezoelectric transducer T, to the upper face 101T of the substrate 101. A pick-and-place device can be used to position each stack comprising layer 105 and electrode 107 onto the conductive layer 103. Alternatively, only the piezoelectric layer 105 may be transferred onto layer 103 first, with the upper electrodes 107 being formed subsequently, for example, by spraying a metallic layer through a stencil.

[0039] Alternatively, the piezoelectric layer material 105 of each electromechanical transducer T can be deposited as a thin film completely covering the upper surface of the layer 103, for example by a sol-gel process (e.g., in the case of PZT) or a sputtering process (e.g., in the case of AlN). Disjointed portions of the piezoelectric thin film can then be formed by photolithography and etching, so as to individualize the layer 105 of each transducer T. The upper electrodes 107 can then be formed, for example, by a step of depositing a conductive layer on the upper surface 101T of the substrate 101, followed by photolithography and etching steps to individualize the electrodes 107 for each transducer T.

[0040] There figure 1C is a cross-sectional view illustrating a structure obtained at the end of a subsequent deposition step, on the upper face 101T of the transfer substrate 101, of a layer 109 of passivation of the transducers T.

[0041] In the example shown, layer 109 covers the lateral walls of the piezoelectric layers 105, as well as the lateral walls and upper surface of the upper electrodes 107 of the T transducers. In this example, layer 109 completely fills the spaces extending laterally between the piezoelectric T transducers. Layer 109 plays a role, for example, in passivating or encapsulating the T transducers. Layer 109 aims, for example, to protect the T transducers from external damage due to humidity. Layer 109 also performs a planarization function on the upper surface of the structure.

[0042] The layer 109 is, for example, deposited as a full plate on the side of face 101T, and then a planarization step, for example chemical polishing, is carried out to obtain a substantially flat top surface. In this case, the layer 109 is, for example, made of silicon dioxide (SiO2). Alternatively, the layer 109 can be formed by depositing or laminating a polymer, for example benzocyclobutene (BCB), on the side of face 101T.

[0043] Furthermore, during this step, through-openings 111 are formed in the layer 109 directly above the upper electrodes 107 of the piezoelectric transducers T. In the example shown, part of the upper face of each electrode 107 is exposed at the bottom of each trench 111. The openings 111 of the layer 109 are, for example, formed by photolithography and then etching.

[0044] There figure 1D is a cross-sectional view illustrating a structure obtained at the end of a subsequent step of formation of contact resumption elements 113 inside the openings 111.

[0045] In the example shown, the contact elements 113 completely fill the openings 111 and are flush with the upper surface of the passivation layer 109. The contact elements 113 are, for example, formed by full-plate deposition of an electrically conductive layer on the side facing 101T, followed by etching the layer. For example, the contact elements 113 are made of a metal, for example, selected from the list of metals indicated previously for layer 103, or of a metal alloy. The contact elements 113 are, for example, made of the same material as the electrodes 107. Alternatively, the contact elements 113 are formed by screen printing an electrically conductive material such as silver paste. For example, the contact elements have a thickness of approximately 300 nm.

[0046] Furthermore, during this step, an interconnection network 115 is created on the upper face 101T side of the transfer substrate 101. The interconnection network is more precisely, in the example illustrated in figure 1D , located on and in contact with the passivation and planarization layer 109. Although this was not detailed in figure 1D The interconnection network 115 includes, for example, metallization levels, such as two metallization levels separated from each other by dielectric layers. Each metallization level comprises, for example, several disjoint portions, electrically insulated from each other, of the same metallic layer. In addition, conductive vias not shown in figure 1D can be carried out in the interconnection network 115 in order, for example, to interconnect several portions of metallic layers that are part of distinct metallization levels.

[0047] Each contact re-establishment element 113 allows, for example, the upper electrode 107 of one of the piezoelectric transducers T to be connected to one of the metallization levels (not shown in figure 1D ) of the interconnection network 115.

[0048] Furthermore, during this step, metallic pads 117 are formed on and in contact with the upper face of the interconnection network 115. In this example, the pads 117 are located directly above the piezoelectric transducers T. The pads 117 are, for example, connected to another level of metallization of the interconnection network 115.

[0049] There figure 1E is a cross-sectional view illustrating a structure obtained at the end of a subsequent step of transferring the light-emitting diodes D onto the substrate 101.

[0050] In the example shown, the LEDs D are more precisely located on the upper face 101T of the substrate 101, directly above the piezoelectric transducers T. In this example, the LEDs D and the piezoelectric transducers T are superimposed. Each LED D includes, for example, as in the example illustrated in figure 1E , metal pads 119 placed in contact with metal pads 117 so as to connect the light-emitting diodes D to the interconnection network 115. As an alternative, the light-emitting diodes D can for example be connected to the metal pads 117 using under bump metallization (UBM) structures, microtube, etc.

[0051] The process described in relation to the figures 1A à 1E can be used to create large-scale display devices, such as television, computer, smartphone, and tablet screens, combining an image display function with an electromechanical transduction function, for example, to create an interactive screen adapted to implement haptic feedback, sound emission, and finger detection (based on a process comprising an emission phase followed by a reception phase), etc. Such a device can comprise a plurality of monolithic elementary electronic chips arranged, for example, in a matrix arrangement, on the same substrate. In the case of device 100 illustrated in figure 1E The elementary electronic chips can correspond to the rectangles symbolizing the light-emitting diodes D. The elementary chips are mounted securely to the substrate 101 and connected to electrical connection elements of the substrate 101, including, for example, the interconnection network 115, for their control. According to the invention, each chip comprises several LEDs and a control circuit for said LEDs. By way of example, each chip comprises three individually controllable LEDs, each by means of its respective control circuit, defining three emission pixels adapted to emit red, green, and blue light, respectively. Each elementary chip corresponds, for example, to one display pixel of the device 100.

[0052] According to an alternative embodiment not forming part of the invention as claimed, each chip comprises a single individual LED and lacks an integrated control circuit. An external control circuit, for example implemented using TFT (Thin Film Transistor) technology, can then be formed on the substrate.

[0053] There figure 2 is a cross-sectional view illustrating a variant of the optoelectronic device 100 of the figure 1E . There figure 2 represents more precisely an optoelectronic device 200 comprising piezoelectric transducers T and light-emitting diodes D located respectively on the side of two opposite faces of the same carrier substrate.

[0054] The 200 device of the figure 2 includes common elements with device 100 of the figure 1E These common elements will not be detailed again below. Device 200 of the figure 2 differs from device 100 of the figure 1E principally in that, in device 200, the electromechanical transducers T are made on the side of a second face 101B of the transfer substrate 101 (the lower face of the transfer substrate 101, in the orientation of the figure 2 ) opposite the first face 101T. In the example shown, the common electrode 103 of the transducers T covers the lower face 101B of the substrate 101. In addition, in this example, the interconnection network 115 is located on and in contact with the upper face 101T of the substrate 101.

[0055] Device 200, for example, is produced by a process analogous to the manufacturing process of device 100 previously described in relation to the figures 1A à 1E For example, the piezoelectric transducers are first fabricated on the side of face 101B, then the substrate 101 is glued onto a temporary support substrate, or handle, on the side of face 101B. The interconnection network 115 is then fabricated on the side of face 101T of the transfer substrate 101, and then the light-emitting diodes D are transferred onto the connection pads 117 above the interconnection network 115. The temporary support substrate can then be separated from the rest of the structure.

[0056] We represented in figure 2 An example in which the piezoelectric transducers T are without a passivation layer. However, it would be possible to deposit a passivation layer, for example a layer similar to layer 109 of device 100, on the underside 101B of substrate 101 after fabrication or transfer of the piezoelectric transducers T.

[0057] THE figures 3A à 3I are cross-sectional views illustrating steps in a manufacturing and transfer process of the light-emitting diodes D of the device 100, 200 in the case where each light-emitting diode D corresponds to an elementary pixel chip of the display device 100, 200.

[0058] There figure 3A includes a view (a) schematically representing a control structure comprising a first substrate 301 in and on which a plurality of elementary control integrated circuits 303 have been formed, for example identical or similar, corresponding respectively to the control integrated circuits of the future elementary pixel chips of the device 100, 200.

[0059] The 301 substrate may have a monolithic structure, or it may be a layer covering a support made of another material. The 301 substrate is, for example, a semiconductor material, such as silicon. As an example, the 301 substrate is a wafer or a piece of wafer made of monocrystalline silicon, the top face of the 301 substrate having, for example, a crystalline orientation <111> . The 301 substrate may have a multilayer silicon-on-insulator structure, also called SOI (from the English "Semiconductor On Insulator"), comprising a semiconductor support substrate, for example silicon, an insulating layer, for example silicon oxide, disposed on and in contact with the top face of the support substrate, and a top semiconductor layer, for example monocrystalline silicon, disposed on and in contact with the top face of the insulating layer.

[0060] In the case where the substrate 301 is of the SOI type, the control elementary circuits 303 are formed, for example, in and on the upper semiconductor layer of the substrate 301. Each control elementary circuit 303 comprises, for example, a plurality of MOS transistors (not detailed in the figures 3A à 3I The 303 elementary control circuits are, for example, made using CMOS technology (Complementary Metal Oxide Semiconductor). Each 303 elementary control circuit can include a circuit adapted to control the light emission by the LED(s) of the future pixel chip element of the device 100, 200.

[0061] In this example, each elementary control circuit 303 includes, on its upper face, one or more metallic connection pads 305a, 305b. For example, the pads 305a, 305b are flush with the upper face of an upper insulating layer, for example of silicon oxide, of an interconnect stack (not detailed in the figures) covering the upper face of the upper semiconductor layer of the substrate 301. Thus, in this example, the upper surface of the control structure of view (a) is a flat surface having an alternation of metallic regions (the pads 305a, 305b) and insulating regions.

[0062] For example, each control circuit element 303 includes a specific metal contact 305a for each LED of the future pixel chip of the device, intended to be connected to an anode region of the LED and allowing individual control of the light emission by said LED. Each control circuit element 303 may further include a metal contact 305b intended to be connected to a cathode region of each LED of the future pixel chip of the device. In the case where the chip contains several LEDs, the cathode contact may be common to all the LEDs on the chip. Thus, the control circuit element 303 may include a single metal contact 305b.

[0063] As an example, each pixel chip in the device comprises three individually controllable LEDs adapted to emit blue, green, and red light, respectively. In this case, each control circuit 303 may comprise three separate metal pads 305a for connection to the anode regions of the three LEDs, and a single metal pad 305b for collective connection to the cathode regions of the three LEDs. In the cross-sectional view of the figure 3A , only two 305a metal pads and one 305b metal pad per electronic circuit were shown.

[0064] In the illustrated example, the upper surface of the control structure (a) is coated with a metallic layer 307. In this example, the layer 307 extends continuously and with a substantially uniform thickness over the entire upper surface of the interconnecting stack of the control structure. Thus, the layer 307 connects all the metallic studs 305a, 305b of the control structure to one another.

[0065] There figure 3A It further includes a view (b) schematically representing a structure comprising a second substrate 311, on the upper surface of which rests an active stack of LEDs 313. The active stack of LEDs 313 is, for example, a stack of inorganic LEDs, for example based on one or more III-V semiconductor materials, for example based on gallium nitride. The substrate 311 is, for example, made of sapphire or silicon.

[0066] The active stack of LEDs 313 includes, for example, in order from the top face of the substrate 311, an N-type doped semiconductor layer 315 forming a cathode layer, an active layer 317, and a P-type doped semiconductor layer 319 forming an anode layer. The active layer 317, for example, comprises alternating layers of quantum wells in a first semiconductor material and barrier layers in a second semiconductor material, defining a stack of multiple quantum wells. Although this has not been detailed in figure 3A , the active stack of 313 LEDs may also include one or more other layers, for example chosen from charge injection, transport or blocking layers (electrons or holes).

[0067] The active stack 313 can be formed by epitaxy on the upper face of the substrate 311. As an alternative, the active stack 313 is formed by epitaxy on a growth substrate, not shown, and then transferred to the upper face of the substrate 311.

[0068] At this stage, the 313 stack is not yet structured into individual LEDs. In other words, the layers of the 313 stack extend continuously and with a substantially uniform thickness across the entire upper surface of the 311 substrate.

[0069] In the illustrated example, the upper surface of the view structure (b) is coated with a metallic layer 321 on and in contact with the upper face of the active LED stack 313. The metallic layer 321 may be a single layer or a stack of several metallic layers. Preferably, the metallic layer 321 comprises, on its upper face, a layer of the same material as layer 307.

[0070] There figure 3B illustrates the structure obtained after a subsequent step of transferring and fixing the active stack of LEDs 313 and the metal layer 321 onto the structure of view (a) of the figure 3A .

[0071] During this step, the structure of view (b) of the figure 3A is reported on the upper face of the structure of view (a) of the figure 3A using substrate 311 as a handle. The underside (in the orientation of the figure 3B , corresponding to the upper face in the orientation of the figure 3A ) of the metallic layer 321 is fixed to the upper face of the metallic layer 307. The fixing is obtained for example by direct bonding or molecular bonding of the lower face of the layer 321 to the upper face of the layer 307, that is to say without the addition of material between the two layers.

[0072] The substrate 311 is then removed, for example by grinding and / or chemical etching, so as to free access to the top face of the active LED stack 313, i.e., in this example, the top face of the cathode semiconductor layer 315 of the active LED stack 313.

[0073] There figure 3C Figure 3 illustrates a trench formation step 323 extending vertically into the active LED stack 313 from its top face and laterally delimiting, within the stack 313, a plurality of islands 325 corresponding to the individual LEDs of the future elementary chips of the device. The trenches 323 are formed, for example, by plasma etching. In top view (not shown), the trenches 323 form a grid laterally separating the elementary diodes 325 from one another.

[0074] There figure 3C This further illustrates a subsequent step of vertically extending the trenches 323 through the metallic layers 321 and 307, for example using the same etching mask (not shown) as that used in the previous step. At the end of this step, the trenches 323 emerge onto the upper face of the interconnect stack covering the upper face of the substrate 301.

[0075] The portion of the stack of layers 321 and 307 remaining beneath each LED 325 after this step constitutes an anode electrode for the LED. This anode electrode is in contact, via its lower face, with the upper face of a metal connection pad 305a of the underlying control circuit element 303. Thus, each LED has its anode electrode individually connected to a metal connection pad 305a of a control circuit element 303.

[0076] In this example, a trench 323 is further formed opposite each metal connecting block 305b so as to free access to the upper face of the blocks 305b.

[0077] There figure 3C This further illustrates a subsequent step of passivating the sides of the LEDs 325. For this purpose, a layer 327 of an electrically insulating material, for example silicon oxide or silicon nitride, is deposited by a conformal deposition method on the upper surface of the structure. The layer 327 then coats the upper surface and sides of the LEDs 325, as well as the sides of the portions of the metal layers 307 and 321 located beneath the LEDs 325, and, at the bottom of the trenches 323, the upper surface of the interconnect stack coating the substrate 301. A vertical anisotropic etching step is then implemented to remove the horizontal portions of the layer 327, retaining only the vertical portions of this layer, which coat the sides of the LEDs 325 and the sides of the portions of the metal layers 307 and 321 located beneath the LEDs 325.

[0078] There figure 3D illustrates a subsequent step of filling the trenches 323 with metal 329. As an example, the metal 329 is initially deposited over the entire upper surface of the structure with a thickness greater than the depth of the trenches 323, so as to completely fill the trenches 323. A planarization step, for example by chemical polishing, is then carried out to provide access to the upper face of the LEDs 325. This results in a substantially flat upper surface on which the cathode semiconductor regions 315 of the LEDs 325, the vertical insulation regions 327 of the LEDs, and the metallic regions 329 filling the trenches 323 are flush. In top view (not shown), the metallic regions 329 form a conductive grid separating the LEDs 325 laterally from each other.The metallic regions 329 are electrically connected to the metallic pads 305b at the bottom of the trenches 323, and define a common cathode contact metallization for all the LEDs 325 in the structure.

[0079] There figure 3D This further illustrates a subsequent step of depositing a conductive layer 331, transparent to the emission wavelengths of the LEDs in the display device, onto the upper surface of the structure. The layer 331 extends, for example, continuously and with a substantially uniform thickness over the entire upper surface of the structure. The layer 331 is, for example, a transparent conductive oxide, such as indium tin oxide (ITO). Alternatively, the layer 331 can be a metallic layer thin enough to be transparent, for example, a silver layer less than 80 nm thick.

[0080] Layer 331 is in contact, via its lower face, with the upper face of the cathode semiconductor regions 315 of the LEDs 325, and defines a common cathode electrode of the LEDs 325. Layer 331 is also in contact, via its lower face, with the upper face of the metallic region 329. Thus, layer 331 electrically connects the cathode semiconductor region 315 of each LED 325 to the common cathode contact metallization 329 of the structure.

[0081] There figure 3E is a cross-sectional view illustrating in a very schematic way a structure of the type obtained at the end of the steps previously described in relation to the figure 3D In the example shown, the structure more precisely comprises the substrate 301, in and on which the elementary control integrated circuits 303 have been formed, surmounted by an emission stage 351. The emission stage 351 comprises a plurality of LEDs (for example, the LEDs 325 of the figure 3D , not detailed on the figures 3E à 3I ) individually controllable by the circuits 303. In order not to clutter the drawing, only the pads 305a and 305b of the control integrated circuits 303, located on the upper face of the substrate 301, have been detailed on the figures 3E à 3I .

[0082] There figure 3F illustrates a step in gluing the structure of the figure 3E on a temporary support substrate 353, for example silicon. The structure of the figure 3E is fixed to the support substrate 353 by its face opposite the control integrated circuits 303, i.e. by its lower face in the orientation of the figure 3F , corresponding to its upper face in the orientation of the figure 3E .

[0083] There figure 3F It further illustrates an optional step of thinning the semiconductor substrate 301, on its face opposite the stage 351. In the case where the control integrated circuits 303 are initially formed in and on a SOI-type substrate, the thinning step of the figure 3F may consist of removing the support substrate from the SOI substrate, so as to retain only the single-crystal silicon layer and the insulating layer of the SOI substrate.

[0084] Alternatively, in a case where the integrated circuits 303 are formed in and on a solid silicon substrate, the thinning step can consist of reducing the thickness of the substrate 301, for example by grinding, from its top face (in the orientation of the figure 3F ). An insulating passivation layer (not detailed in the figure) can then be deposited on the upper face of the thinned substrate 301.

[0085] There figure 3G illustrates a formation stage, on the upper face side of substrate 301 (in the orientation of the figure 3G ), of metal connection pads 355 connected to connection pads 305a and 305b and / or to connection terminals of electronic components, for example MOS transistors, integrated circuits 303, via conductive vias not detailed in the figure, passing through the semiconductor substrate 301 of the integrated circuits 303. Since the pads 355 are essentially connected to connection terminals inside the circuit, their number is in practice greater than the number of pads 355.

[0086] There figure 3G This further illustrates a step in forming trenches 357 from the upper surface of the substrate 301, vertically traversing the integrated circuits 303 and the emission stage 351 and opening onto the upper surface of the temporary support substrate 353. The trenches 357 laterally delimit a plurality of semiconductor chips 359 corresponding to the elementary pixel chips of the display device. The trenches 357 can be formed by plasma etching, sawing, or any other suitable cutting method.

[0087] THE figures 3H et 3I illustrate a step of fixing elementary chips 359 onto the upper face of the same transfer substrate 361 of the display device. The transfer substrate 361 comprises, on its upper face, a plurality of metal connection pads 363, intended to be fixed and connected electrically and mechanically to corresponding metal connection pads 355 of the elementary chips 359.

[0088] The structure of the figure 3G is returned ( figure 3H ) so as to place the metal connection pads 355 of elementary chips 359 opposite corresponding metal connection pads 363 of the transfer substrate 361. The opposite pads 355 and 363 are then fixed and electrically connected, for example by direct gluing, by welding, by means of microtubes, or by any other suitable method.

[0089] Once fixed to the transfer substrate 361, the elementary chips 359 are detached from the temporary support substrate 353, and the latter is removed ( figure 3I For example, the detachment of the chips 359 is achieved by mechanical peeling or by peeling using a laser beam. This results in a simultaneous collective transfer of a plurality of elementary chips 359 from the temporary support substrate 353 to the transfer substrate 361.

[0090] The pitch (center-to-center distance in front view) of the elementary chips 359 on the transfer substrate 361 is, for example, a multiple of the pitch of the elementary chips 359 on the substrate 353. Thus, only a portion of the elementary chips 359 (one out of two, in the example shown) is transferred simultaneously from the temporary support substrate 353 to the transfer substrate 361. The other chips remain attached to the temporary support substrate 353 and can be transferred later to another portion of the transfer substrate 361 or to another transfer substrate.

[0091] In a case where the process of figures 3A à 3I is implemented to manufacture and then transfer elementary chips to the side of face 101T of the transfer substrate 101 of device 100 or 200, substrate 361 corresponds for example to the transfer substrate 101 surmounted by the interconnection network 115. The pads 361 located on the surface of substrate 361 then correspond to the pads 117 carried by the interconnection network 115, and the pads 355 of the chips 359 correspond to the pads 119 of the light-emitting diodes D.

[0092] An example embodiment has been described above in which each elementary chip comprises a stack of a control integrated circuit, for example a CMOS circuit, and one or more inorganic LEDs. As an alternative, each elementary chip may comprise a stack of a control integrated circuit, for example a CMOS circuit, and one or more organic LEDs arranged on one face of the control circuit.

[0093] There figure 4 is a schematic and partial top view illustrating an example of the implementation of the interconnection network 115 of the optoelectronic device 100 of the figure 1E . There figure 4 illustrates more precisely an example of the realization of network 115 in the case where the light-emitting diodes D of device 100 correspond to elementary chips each comprising several individually controllable LEDs, for example three individually controllable LEDs adapted to emit blue light, green light and red light respectively.

[0094] For the sake of simplicity, only a portion of the interconnection network 115 located directly above a piezoelectric transducer T surmounted by nine light-emitting diodes D of the optoelectronic device 100 has been shown in figure 4 .

[0095] The interconnection network 115 includes electrical connection elements, and in particular conductive tracks and conductive pads, formed on the upper face of the planarization layer 109. These electrical connection elements are formed, for example, by printing a succession of conductive and insulating levels on the upper face of the layer 109. The electrical connection elements are formed, for example, by a deposition or printing process such as inkjet printing, screen printing, rotogravure, vacuum deposition, or any other suitable method.

[0096] In the example shown, the interconnection network 115 comprises two superimposed conductive metallic layers M1 and M2 separated by an insulating layer (not visible in figure 4 ), and metallic vias V connecting the two metallic levels M1 and M2 through the insulating level. In this example, the interconnection network 115 further includes metallic connection pads (not visible in figure 4 ) formed on the upper metallic level M2, intended to be connected to the connection pads 117.

[0097] In the example shown, the fabrication of the interconnection network 115 includes the following three successive deposition steps.

[0098] In a first deposition step, a plurality of conductive tracks are formed on the upper face of layer 109, substantially parallel to the direction of the columns of the display device (vertical direction in the orientation of the figure 4 More specifically, in this example, during the first deposition step, two conductive tracks, C1 and C2, are formed for each column of the display device, extending along approximately the entire length of the display's columns. Track C1 is used to carry a DATA_D signal that adjusts the brightness emitted by the LEDs of the column's individual chips. Track C2 is used to distribute a high VDD supply voltage to the individual pixel chips.

[0099] In this example, during the first deposition step, a conductive track C3 is also formed for each column of piezoelectric transducers T, extending along substantially the entire length of the display device's columns. The track C3 is designed to carry a DATA_T signal, which can, for example, control the intensity of haptic feedback, in a case where the piezoelectric transducers T are adapted to produce haptic feedback, or display an image of the distance of a user's finger from the device 100, in a case where the piezoelectric transducers T are adapted to detect the presence of a finger.

[0100] In the example shown, during the first deposition step, a connection area 401 is also formed for each piezoelectric transducer T. This area is located on and in contact with the upper end of the contact element 113 of the transducer. In this example, the area 401 is further connected to one conduction terminal (source or drain) of a transistor 403, the other conduction terminal of transistor 403 being connected to the conductive track C3.

[0101] The conductive elements formed during this first deposition stage define the first conductive level M1 of the transfer substrate.

[0102] In a second deposition step, the first conductor is covered with an insulating material (not visible in the figure), so as to allow the subsequent deposition of conductive tracks extending above tracks C1, C2 and C3, without creating a short circuit with tracks C1, C2 and C3.

[0103] In a third deposition step, a plurality of conductive tracks, substantially parallel to the direction of the display line, are formed on the upper surface of layer 109. More specifically, in this example, during the third deposition step, two conductive tracks, L1 and L2, extending along substantially the entire length of the display line, are printed for each line of the display. The L1 tracks are intended to carry a SELECT_D signal for selecting the corresponding pixel line. The L2 tracks are intended to distribute a low supply voltage, VK, for example, lower than the VDD voltage, to the various individual pixel chips.

[0104] In the example shown, during the third deposition step, a conductive track L3 is also formed for each row of piezoelectric transducers, extending along substantially the entire length of the display unit's columns. Track L3 is designed to carry a SELECT_T signal that selects the corresponding row of piezoelectric transducers T. In this example, track L3 is connected to each control electrode (gate) of transistor 403 for each piezoelectric transducer T in device 100. Transistor 403 is, for example, a selection transistor adapted to select the associated piezoelectric transducer T based on the SELECT_T signal applied to its control electrode by track L3.

[0105] The conductive elements printed during this third deposition stage define the second conductive level M2 of the interconnection network 115.

[0106] After the third deposition step, for each pixel, four conductive pads 117 are formed on conductive areas of the metallic layer M2 (not shown). These pads are designed to receive four separate connection pads 119 of the pixel's elementary chip. The pads 117 allow, for example, sequential addressing of the three LEDs on the chip.

[0107] There figure 5 is an electrical diagram equivalent to the interconnection network of the figure 4 Unlike the figure 4 illustrating a portion of the interconnection network 115 comprising a single piezoelectric transducer T, the figure 5 illustrates a portion of the 115 interconnection network comprising nine piezoelectric transducers T. In figure 5 Each piezoelectric transducer T is symbolized by its upper electrode 107. The lower electrode 103 (not visible in figure 4) is for example common to all T transducers and brought to a reference potential, for example ground.

[0108] The 115 interconnection network of the figure 5 for example, it is part of an active control matrix for the light-emitting diodes D and the piezoelectric transducers T of the device 100. Alternatively, the device 100 may include a passive control matrix for the light-emitting diodes D and the piezoelectric transducers T. In this case, the tracks L3 and the transistors 403 are omitted, for example, and the tracks C3 are connected to the upper electrodes 107 of the piezoelectric transducers T by the contact resumption elements 113. In the case of a passive matrix, the lower electrode 103 of each piezoelectric transducer T is, for example, separate from the lower electrode 103 of the other piezoelectric transducers T of the device. The lower electrodes 103 of the T transducers of the same column are for example connected to the same vertical track analogous to the C3 track but made for example in the metallic layer where the electrodes 103 are formed.

[0109] Alternatively, and according to the invention, it is planned to control the piezoelectric transducers T of the device 100 using transistors located in the control circuits 303 of the elementary chips 359 previously described in relation to the figures 3G à 3I .

[0110] One advantage of the embodiments described above in relation to the figures 1A à 1E and with the figure 2 This is due to the fact that the piezoelectric transducers T and the light-emitting diodes D of devices 100 and 200 form first and second matrices, respectively, which can have different pitches. The pitch of the piezoelectric transducer matrix T is preferably larger than the pitch of the light-emitting diode matrix D. This makes it possible, in particular, to create transducers T with lateral dimensions greater than those of the light-emitting diodes D. The transducers T can thus advantageously produce a more intense haptic feedback than that which would be obtained, for example, with coplanar matrices of piezoelectric transducers T and light-emitting diodes D having approximately equal pitches.

[0111] There figure 6 is a cross-sectional view schematically and partially illustrating a variant embodiment of the optoelectronic device of the figure 1E .

[0112] The device of the figure 6 includes the same elements as the device of the figure 1E arranged in roughly the same way.

[0113] In the example of the figure 6 The device further includes a planarization layer 601, for example made of a polymer material, filling the space between the elementary chips D. As an example, the planarization layer 601 is flush with the top surface of the elementary chips D. As an alternative (not shown), the planarization layer covers the top surface of the elementary chips D. In this case, the planarization layer 601 is made of a material transparent to the light emitted by the LEDs of the elementary chips D.

[0114] The device of the figure 6 further includes a transparent protective layer or cover 603, for example of glass, extending continuously over the entire surface of the device, above the planarization layer 601 and the elementary chips D.

[0115] The 601 planarization layer is made of a material suitable for transmitting acoustic vibrations emitted and received by the T transducers.

[0116] Optionally, the planarization layer 601 can provide a bonding function for the protective cover 603.

[0117] The 603 cover protects the device and can form a haptic action surface for the device.

[0118] There figure 7 is a cross-sectional view schematically and partially illustrating a variant embodiment of the optoelectronic device of the figure 6 .

[0119] The device of the figure 7 includes the same elements as the device of the figure 6 arranged substantially in the same way, and further includes pillars 701 of a material more rigid than the material of the planarization layer 601, vertically traversing the planarization layer 601 through its entire thickness.

[0120] In the example shown, the pillars 701 extend from the lower face of the hood 603 to the upper face of the interconnection network 115. As an alternative, not shown, the pillars 701 may vertically traverse the interconnection network 115 and emerge onto the upper face of the transducers T or the passivation layer 109 of the transducers T.

[0121] The 701 pillars ensure better transmission of acoustic vibrations emitted and received by the T transducers.

[0122] As an example, the 701 pillars are formed in engraved openings after the deposition of the planarization layer 601 and before the deposition of the hood 603.

[0123] The 701 pillars, for example, are made of metal or any other material rigid enough to transmit acoustic vibrations.

[0124] It should be noted that the variants of figures 6 et 7 can be combined with the variant of the figure 2 .

[0125] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to them. In particular, the embodiment, for device 200 of the figure 2 , of an active control matrix for the piezoelectric transducers T and the light-emitting diodes D, analogous to the active and passive matrices described in relation to the figures 4 et 5 is within the reach of a person in the profession based on the above instructions.

[0126] Furthermore, although embodiments have been described in which the piezoelectric transducers T are rectangular or square and arranged in a matrix, other shapes and arrangements are within the grasp of those skilled in the art. For example, one could provide piezoelectric transducers T each in a horizontal or vertical band shape, with the transducers T in the device then being, for instance, substantially parallel to each other.

[0127] Furthermore, the embodiments described are not limited to the examples of materials and / or dimensions mentioned in this description.

[0128] Finally, the practical implementation of the described embodiments and variations is within the reach of a person skilled in the art, based on the functional guidelines provided above. In particular, adapting the implementation of the described process in relation to the figures 1A à 1E to obtain a structure of the type described in relation to the figure 2 is within the reach of a person in the trade based on the indications in this description.

[0129] Furthermore, the practical realization of the 403 selection transistors is within the reach of a person skilled in the art, based on the above indications.

[0130] Furthermore, the embodiments described are not limited to the electromechanical transducer examples detailed above. As an alternative, the transducers in the examples described above can be replaced by any other type of electromechanical transducer, for example, electroacoustic transducers, ultrasonic transducers, or diaphragm ultrasonic transducers. For example, the electromechanical transducers could be capacitive diaphragm transducers, for example, of the CMUT type (Capacitive Micromachined Ultrasonic Transducer). Alternatively, the electromechanical transducers could be piezoelectric diaphragm transducers, for example, of the PMUT type (Piezoelectric Micromachined Ultrasonic Transducer).

Claims

1. Optoelectronic device (100; 200) comprising at least one electromechanical transducer (T) located vertically in line with at least one light-emitting diode (D), said at least one electromechanical transducer and said at least one light-emitting diode being connected to conductive tracks (L1, L2, L3, C1, C2, C3) of a same transfer substrate (101), characterized in that: - each light-emitting diode (D) comprises an elementary chip (359) comprising a plurality of elementary diodes (325) respectively adapted to emitting light in different wavelength ranges and an elementary control circuit (303) of the elementary diodes; and - each electromechanical transducer (T) is controlled by the or one of the elementary control circuit(s) (303) of the elementary diodes.

2. Device (100) according to claim 1, wherein said at least one electromechanical transducer (T) and said at least one light-emitting diode (D) are located on the side of a same surface (101T) of the transfer substrate (101).

3. Device (200) according to claim 1, wherein said at least one electromechanical transducer (T) is located on the side of a first surface (101B) of the transfer substrate (101) and said at least one light-emitting diode (D) is located on the side of a second surface (101T) of the transfer substrate, opposite to the first surface.

4. Device according to any one of claims 1 to 3, comprising a plurality of electromechanical transducers (T) forming a first array and a plurality of light-emitting diodes (D) forming a second array, the first array having a greater pitch than the second array.

5. Device according to claim 4, comprising a planarization layer (601) extending laterally between the light-emitting diodes (D), and a transparent protection cover (603) covering the light-emitting diodes (D) and the planarization layer (601).

6. Device according to claim 5, further comprising pillars (701) crossing the planarization layer (601) and mechanically coupling the transducers (T) to the transparent protection cover (603).

7. Device according to any one of claims 1 to 5, wherein said at least one electromechanical transducer (T) has greater lateral dimensions than said at least one light-emitting diode (D).

8. Device according to any one of claims 1 to 7, wherein the conductive tracks (L1, L2, L3, C1, C2, C3) form an interconnection array (115) configured to control said at least one electromechanical transducer (T) and said at least one light-emitting diode (D).

9. Device according to any one of claims 1 to 8, further comprising, for each electromechanical transducer (T), a selection transistor (403) connected to said electromechanical transducer.

10. Device according to claim 9, wherein the selection transistor (403) comprises a first conduction terminal connected to an electrode (107) of said electromechanical transducer (T), a second conduction terminal connected to one of the conductive tracks (L1, L2, L3, C1, C2, C3) of the transfer substrate (101) and a control terminal connected to another track among the conductive tracks of the transfer substrate.

11. Device according to any one of claims 1 to 10, wherein said at least one electromechanical transducer (T) comprises an active layer (105) based on lead zirconate titanate or on aluminum nitride.

12. Device according to any one of claims 1 to 11, wherein said at least one electromechanical transducer (T) is a piezoelectric transducer.

13. Device according to any one of claims 1 to 11, wherein said at least one electromechanical transducer (T) is a piezoelectric micromachined ultrasonic transducer, PMUT, or a capacitive micromachined ultrasonic transducer, CMUT.

14. Method of manufacturing an optoelectronic device (100; 200), comprising the following successive steps: a) forming at least one electromechanical transducer (T) on a transfer substrate (101); and b) transferring at least one light-emitting diode (D) onto the transfer substrate, vertically in line with said at least one electromechanical transducer, said at least one electromechanical transducer and said at least one light-emitting diode being connected to conductive tracks (L1, L2, L3, C1, C2, C3) of the transfer substrate and characterized in that: - each light-emitting diode (D) comprises an elementary chip (359) comprising a plurality of elementary diodes (325) respectively adapted to emitting light in different wavelength ranges and an elementary circuit (303) for controlling the elementary diodes; and - each electromechanical transducer (T) is controlled by the or one of the elementary control circuit(s) (303) of the elementary diodes.