VOLTAGE REFERENCE CIRCUIT

Description

DOMAINE TECHNIQUE

[0001] The invention relates to the field of voltage reference circuits used in integrated circuits.

[0002] The invention relates in particular to a voltage reference circuit having a more compact structure and making it possible to provide a constant voltage reference even when the power source, temperature or component parameters vary. ETAT DE LA TECHNIQUE

[0003] Typically, voltage reference circuits are circuits that provide a stable and constant reference voltage over time. The goal is to obtain a reference voltage that is insensitive to variations in certain parameters.

[0004] For example, these parameters include supply voltage, temperature, manufacturing variations, and component aging.

[0005] In particular, transistors are often found in voltage reference circuits. However, the parameters of a given transistor can vary greatly depending on its manufacturing process. Moreover, two transistors resulting from the same manufacturing process can be significantly different depending on their positioning on the semiconductor wafer used in their fabrication.

[0006] One of these parameters is the threshold voltage value at which a channel forms between the drain and source of a given transistor. This minimum value is the one that must be applied between the gate and source in order to conduct an electric current between the drain and source of that particular transistor. This parameter can vary by up to 50% from one transistor to another, which can lead to a loss of stability in the circuit's voltage reference.

[0007] A voltage reference circuit typically includes two types of transistors: depletion transistors and enhancement transistors.

[0008] As illustrated on the figure 1 from prior art, a depletion-mode transistor 2005 is commonly symbolized with a continuous line connecting the drain, source, and base. An enhancement-mode transistor 2025 is commonly symbolized with a dashed line connecting the drain, the source, and the base.

[0009] For example, as illustrated in the figure 1 extracted from US document 9,647,476 B2, a voltage reference circuit 2000 typically includes a depletion-mode transistor 2005 whose drain is connected to a voltage source V+ and whose source is connected with eight enhancement transistors 2025 in series. Each enhancement-mode transistor 2025has its gate connected to its drain, and the last enhancement-mode transistor in the series has its source connected to ground. The gate of the depletion-mode transistor 2005 is also connected to ground. The reference voltage Vref is measured between a point located between a capacitor 2015 and the source of an enhancement-mode transistor 2055 whose gate is connected between the sixth and seventh depletion transistors in the series.

[0010] In this configuration, the voltage reference circuit 2000 This allows for low current consumption, typically less than 1µA. However, such a circuit cannot achieve high reference voltage values. Furthermore, this type of circuit is sensitive to variations in transistor parameters, and in particular, the reference voltage exhibits instabilities.

[0011] According to another example, the publication "A 23.6ppm / °C Monolithically Integrated GaN Reference Voltage Design with Temperature Range from -50°C to 200°C and Supply Voltage Range from 3.9 to 24V" by Cheng-Hsing Liao et al. describes several embodiments of voltage reference circuits.

[0012] There figure 2 illustrates one of these embodiments, in which the voltage reference circuit includes a first branch comprising a depletion transistor QD1 whose drain is connected to a voltage source VDD, whose source is connected to a first terminal of a resistor R1 and whose grid is connected to the second terminal of the resistor R1.

[0013] The second terminal of the resistance R1 is also connected to the drain of an enhancement transistor QE2, whose source is connected to ground.

[0014] The voltage reference circuit of the figure 2 also includes a second branch comprising a first enhancement transistor QE4 whose drain is connected to the voltage source VDD and whose source is connected to a first terminal of a resistor R2.

[0015] The second terminal of the resistance R2 is connected to the drain of a second enhancement transistor QE3, whose grid is connected to its drain and whose source is connected to ground.

[0016] The first and second branches are interconnected so that the gate of the depletion transistor QD1 The first branch is connected to the gate of the first enhancement transistor. QE4 of the second branch. Furthermore, the gate of the enhancement transistor QE2 from the first branch and connect to the enriched transient grid QE3 of the second branch, so as to form a current mirror.

[0017] The reference voltage Vref is taken at the source of the enhancement transistor QE4.

[0018] There figure 3 illustrates a second embodiment described in the publication by Cheng-Hsing Liao et al. cited above. The circuit has the same architecture as that described in the figure 2 However, the circuit includes additional components. The first branch contains an additional enhancement-mode transistor. QE5, whose drain is connected to the source of the enhancement transistor QE2 and whose source is connected to ground.

[0019] The second branch has an additional resistance R2 connected between the resistance R2 and the drain of the enhancement-mode transistor QE2 and an additional enhancement transistor QE6, whose drain is connected to the source of the enhancement transistor QE3 and whose source is connected to ground.

[0020] The transistor grid QE6 is connected on one side to the transistor gate QE5 and on the other hand to the transistor drain QE3.

[0021] There figure 4 illustrates another voltage reference circuit described in the publication by Cheng-Hsing Liao et al. cited above, in which the voltage reference circuit includes a first branch comprising a first depletion transistor QSG,D1 whose drain is connected to a voltage source VDD, whose source is connected to a first terminal of a first resistor RSG1 and whose grid is connected to the second terminal of the first resistor RSG1. The first branch also includes a second depletion-mode transistor QSG,D3, whose drain is connected to the second terminal of the first resistor RSG1, whose source is connected to a first terminal of a second resistor RSG2 and whose grid is connected to the second terminal of the resistor RSG2.

[0022] The drain of the second depletion-mode transistor QSG,D3 is also connected to the drain of an enhancement transistor QSG,E1, whose source is connected to ground.

[0023] The circuit of the figure 4 also includes a second branch comprising a first depletion transistor QSG,D2 whose drain is connected to the voltage source VDD. The first depletion-mode transistor QSG,D2 is connected, via its source, to the drain of a second depletion-mode transistor QSG,D4. The source of the second depletion transistor QSG,D4 is connected to the first terminal of a third resistor RREF, whose second terminal is connected to the drain of an enhancement transistor QSG,E2. The source of the enhancement transistor QSG,E2 is connected to ground, while the gate of the enhancement transistor QSG,E2 is connected to its drain.

[0024] The first and second branches are connected to each other at the level of the depletion transistors. QSG,D1 And QSG,D2, whose gates are connected. Similarly, depletion-mode transistors QSG,D3 And QSG,D4 have their gates connected. Finally, the gates of the enhancement-mode transistors QSG,E1 And QSG,E2 are also connected to each other.

[0025] The reference voltage Vref is taken at the source of the depletion transistor QSG,D4.

[0026] Although they are more stable than the circuit of the figure 1 the circuits described in figures 2 à 4 include resistors R1, RSG1, RSG2 These resistors are used to regulate the current. This method is usually very efficient due to the linear behavior of the resistor. However, to limit power consumption, these resistors must be quite large, which means they also occupy a large area of ​​semiconductor material. Therefore, it is difficult to incorporate such resistors into integrated circuits, especially when minimizing their surface area is a priority.

[0027] Publications EP 0 183 185 A2, US 2020 / 257325 A1 and US 4 727 309 A disclose voltage reference circuits that are part of the prior art.

[0028] The problem that the invention aims to solve is to obtain a stable voltage reference circuit, particularly with respect to variations in the manufacturing process of the transistors, while limiting the power consumption of the circuit, as well as the space it occupies. EXPOSE DE L'INVENTION

[0029] To solve this problem, the Applicant has developed a voltage reference circuit comprising: a first branch comprising: a first depletion-mode head transistor whose drain is connected to a voltage source, a first enhancement-mode foot transistor whose source is connected to ground, whose drain is connected, on the one hand, to the gate of the head transistor, and on the other hand to the gate of said foot transistor, and a dipole whose first terminal is connected to the source of the head transistor and whose second terminal is connected to the drain of the foot transistor, and a second branch comprising: a second depletion-mode head transistor whose drain is connected to the voltage source, whose source is connected to the drain of a third depletion-mode transistor and whose gate is connected to the source of said third depletion-mode transistor, and a second enhancement-mode foot transistor whose source is connected to ground and whose drain is connected to the source of the third depletion-mode transistor, the source of the first head transistor of the first branch being connected to the gate of the third depletion transistor of the second branch, the gates of the first foot transistor of the first branch and the second foot transistor of the second branch being connected so as to form a current mirror, the reference voltage being supplied at the source of the second head transistor of the second branch.

[0030] Such a circuit has very few components compared to the prior art circuit of the figure 1 Compared to the circuits of figures 2 à 4 The circuit of the invention comprises substantially the same number of components and, in one embodiment, may advantageously contain no resistors. It thus occupies less surface area compared to the prior art and is easier to integrate into compact circuits. Furthermore, less noise, related to the interactions between components, appears on the voltage reference signal due to the limited number of components. In addition to being more compact, the circuit of the invention exhibits improved performance compared to prior art circuits, particularly in terms of temperature stability.

[0031] According to a first embodiment, the dipole is an enhancement transistor whose drain is connected, on the one hand, to the gate of said enhancement transistor, and on the other hand, to the first terminal of the dipole, and whose source is connected to the second terminal of the dipole.

[0032] A transistor whose gate is connected to its drain behaves almost like a diode. The transistor's size generally doesn't significantly affect the voltage reference value. However, the size can be adjusted to limit the power consumption of the voltage reference circuit.

[0033] This embodiment is the simplest. The circuit comprises only three depletion-mode transistors and four enhancement-mode transistors, for a total of seven components. Such a circuit is therefore particularly easy to implement in small integrated circuits.

[0034] According to a second embodiment, the dipole comprises n enhancement transistors, each of said enhancement transistors having its gate connected to its drain, said enhancement transistors being connected in series, two consecutive transistors being connected by the source of one and the drain of the other and, the drain of the first transistor forming the first terminal of the dipole and the source of the last transistor forming the second terminal of the second dipole.

[0035] The number of enhancement-mode transistors (EMTs) in diode configuration within the circuit is chosen to achieve a compromise between energy consumption and surface area. Indeed, a greater number of EMTs in diode configuration results in lower energy consumption for the circuit, but conversely, the circuit occupies more space.

[0036] According to a preferred embodiment, the dipole comprises three enhancement transistors.

[0037] This embodiment represents an attractive compromise between energy consumption and footprint. In this embodiment, the voltage reference circuit has a ratio of approximately two depletion-mode transistors to enhancement-mode transistors, which compensates for variations in the previously defined threshold value. Indeed, for N-channel transistors, depletion-mode transistors have a negative threshold value, while enhancement-mode transistors have a positive threshold value. Furthermore, the absolute value of the threshold value of an enhancement-mode transistor is approximately twice that of a depletion-mode transistor. Thus, one enhancement-mode transistor can compensate for a pair of depletion-mode transistors. The threshold values ​​cancel each other out, or even cancel each other out, which limits the detrimental effects on the reference voltage.

[0038] In practice, the invention finds a particularly advantageous application for transistors for which no complementary transistor exists, that is, when only one polarity exists, such as the N-type in GaN, with the dual possibility of enhancement and depletion devices, such as GaN-type transistors or NMOS transistors. However, the invention is also valid for complementary transistor technologies such as NPN or PNP bipolar transistors and N- or P-type CMOS transistors. DESCRIPTION DES FIGURES

[0039] The method of implementing the invention, as well as the resulting advantages, will become clear from the description of the embodiments that follow, supported by the attached figures in which: [ Fig 1 ] There figure 1 is an early electrical diagram of a prior art voltage reference circuit, [ Fig 2 ] There figure 2 is a second electrical diagram of a prior art voltage reference circuit, [ Fig 3 ] There figure 3 is a third electrical diagram of a prior art voltage reference circuit, [ Fig 4 ] There figure 4 is a fourth electrical diagram of a prior art voltage reference circuit, [ Fig 5 ] There figure 5 is an electrical diagram of the voltage reference circuit according to a first embodiment of the invention, [ Fig 6 ] There figure 6 is an electrical diagram of the voltage reference circuit according to a second embodiment of the invention, [ Fig 7 ] There figure 7 is an electrical diagram of the voltage reference circuit according to a third embodiment of the invention, [ Fig 8 ] There figure 8 is a comparative table of the performance of reference circuits from the state of the art of figures 2 à 4 and the circuit of the invention illustrated in the figure 5 . [ Fig 9 ] There figure 9 is a comparative graph of the evolution of the reference voltage as a function of temperature for the circuit of the invention illustrated in the figure 5 and for the state-of-the-art circuit of the figure 4 , And [ Fig 10 ] There figure 10 is a comparative graph of the evolution of the reference voltage as a function of the supply voltage for theoretically identical transistors whose intrinsic parameters differ due to manufacturing tolerances, for the circuit of the invention illustrated in the figure 5 and for the state-of-the-art circuit of the figure 4 . DESCRIPTION DETAILLEE DES MODES DE REALISATION

[0040] As illustrated on the figures 5 à 7 The voltage reference circuit of the invention comprises two branches 101, 102.

[0041] The first branch 101 includes a first depletion-mode head transistor M1whose drain is connected to a voltage source Vcc. The voltage source Vcc preferably provides a DC voltage that can vary depending on the current supplied or depending on the time, and for example between 4 and 12 V.

[0042] The first branch 101 also includes a first step transistor with enhancement M3 whose source is connected to ground.

[0043] The first two lead transistors M1 and on foot M3 are connected to each other via a dipole D1, D11, D21 exhibiting advantageous resistive behavior, linear or non-linear. For example, the dipole D1, D11, D21 is either a resistor, a diode, or a transistor configured as a diode, having two terminals Q1, Q11, Q21 And Q2, Q12, Q22. The dipole D1, D11, D21 allows the head transistor to be biased M1.

[0044] Thus, the first head transistorM1 is connected, via its source, to the first terminal Q1, Q11, Q21 of the dipole D1, D11, D21, while the first foot transistor M3 is connected, via its drain, to the second terminal Q2, Q12, Q22 of the dipole D1, D11, D21.

[0045] Furthermore, the drain of the first foot transistor M3 is also connected, on the one hand, to the gate of the first head transistor M1 , and on the other hand, to its own grid.

[0046] In the implementation of the figure 5 the dipole D1 corresponds to an enhancement transistor M2, configured as a diode, meaning its gate is connected to its drain. Thus, the drain of the enhancement-mode transistor M2 corresponds to the first boundary Q1 of the dipole D1 and the source of the enhancement transistor M2 corresponds to the second boundary Q2 of the dipole D1.

[0047] In the implementation of the figure 6 the dipole D11 corresponds to three enhancement transistors M21, M22, M23 connected in series. The three transistors M21, M22, M23 are mounted in diode mode. Thus, the drain of the enhancement transistor M21 corresponds to the first boundary Q11 of the dipole D11. The source of the enhancement transistor M21 is connected to the drain of the enhancement transistor M22 and the source of the enhancement transistor M22 is connected to the drain of the enhancement transistor M23. Finally, the source of the enhancement transistor M23 corresponds to the second boundary Q12 of the dipole D11.

[0048] In the implementation of the figure 7 the dipole D21 corresponds to n enhancement transistors M31-M3n connected in series. Each enhancement transistor M31-M3n is connected in diode mode. Thus, the drain of the enhancement transistor M31 corresponds to the first boundary Q21 of the dipole D21 and the source of the enhancement transistor M3n corresponds to the second boundary Q22 of the dipole D21. Two consecutive transistors are connected by the source of one and the drain of the other.

[0049] The second branch 102 includes a second depletion-mode head transistor M4, whose drain is connected to the voltage source Vcc.

[0050] The second branch 102 also includes a second enhancement-mode transistor M7, whose source is connected to ground.

[0051] The second head transistors M4 and on foot M7 are connected to each other via a third depletion-mode transistor M5.

[0052] Thus, the third depletion-mode transistor M5 is connected, via its drain, to the source of the second head transistor M4, and through its source, to the drain of the second foot transistor M7.

[0053] The first and second branches 101, 102 are interconnected at two locations.

[0054] Indeed, the source of the first head transistor M1, of the first branch 101 is connected to the gate of the third depletion transistor M5 of the second branch 102.

[0055] Similarly, the grids of the first and second foot transistors M3 And M7 are connected to each other, forming a current mirror. Thus, the current flowing through the first foot transistor M3 is copied into the second foot transistor M7.

[0056] The reference voltage value Vref is measured at the source of the second head transistor M4 and in relation to mass.

[0057] Transistors can belong to the category of N-type GaN or MOS transistors. These transistor categories can have a negative threshold value, which allows for compensation of manufacturing process variations, also known as "cornering" in the Anglo-Saxon literature.

[0058] There figure 8 illustrates a comparative table of the performance of the voltage reference circuits of figures 2 à 4 and the circuit of the invention of the figure 5 .

[0059] Thus, it is initially observed that the surface area occupied by prior art circuits is approximately 20 times greater than that occupied by the circuit of the invention. The circuit of the invention is therefore very compact, offering comparable, and even improved, performance in certain respects. Indeed, the circuit of the invention consumes a lower maximum current than prior art circuits, typically equal to 1 µA.

[0060] Furthermore, the circuit of the invention exhibits less temperature variation compared to prior art circuits. Measurements were carried out by the Applicant to compare the performance obtained between the circuit of the invention and a prior art circuit.

[0061] As illustrated on the figure 9 between 25 and 150°C, the reference voltage of the invention 91 varies by approximately 1%, while the reference voltage 92of the prior art circuit of the figure 4 varies by approximately 11.9%. The temperature sensitivity of the circuit of the invention is therefore reduced by a factor of 12 and the circuit is more robust.

[0062] The resulting voltage reference circuit is also relatively insensitive to fluctuations in supply voltage, temperature, and variations in the transistor manufacturing process.

[0063] There figure 10 compares the variations in the reference voltage Vref for transistors that are theoretically identical, but whose intrinsic parameters differ due to manufacturing tolerances.

[0064] For the state-of-the-art circuit 93-95 illustrated at figure 4 We note that for a supply voltage greater than 4V, the reference voltage Vref measured for transistors varies from 12.4%, while for the circuit of the invention 96-98 illustrated at figure 5, it varies by 5.4%, more than half as much.

[0065] In conclusion, the invention makes it possible to obtain a stable voltage reference circuit, particularly with respect to variations in the manufacturing process of the transistors and the temperature, while limiting the power consumption of the circuit, as well as the space it occupies.

Claims

1. Voltage reference circuit (1000, 1001, 1002) comprising: - a first branch (101) comprising: • a first depletion-mode top transistor (M1), the drain of which is connected to a voltage source (Vcc), • a first enhancement-mode bottom transistor (M3), the source of which is connected to the ground, the drain of which is connected, on the one hand, to the gate of the top transistor (M1), and on the other hand, the gate of said bottom transistor (M3), and • a dipole (D1, D11, D21), a first terminal (Q1, Q11) of which is connected to the source of the top transistor (M1) and the second terminal (Q2, 21) of which is connected to the drain of the first bottom transistor (M3), and - a second branch (102) comprising: • a second depletion-mode top transistor (M4), the drain of which is connected to the voltage source (Vcc), the source of which is connected to the drain of a third depletion-mode transistor (M5), and the gate of which is connected to the source of said third depletion-mode transistor (M5), and • a second enhancement-mode bottom transistor (M7), the source of which is connected to the ground, and the drain of which is connected to the source of the third depletion-mode transistor (M5), the source of the first top transistor (M1) of the first branch (101) being connected to the gate of the third depletion-mode transistor (M5) of the second branch (102), the gates of the first bottom transistor (M3) of the first branch (101) and of the second bottom transistor (M7) of the second branch (102) being connected so as to form a current mirror, the reference voltage (Vref) being provided to the source of the second top transistor (M4) of the second branch (102).

2. Voltage reference circuit according to claim 1, characterised in that the dipole (D1) is a depletion-mode transistor (M2), the drain of which is connected, on the one hand, to the gate of said enhancement-mode transistor (M2), and on the other hand, to the first terminal (Q1) of the dipole (D1), and the source of which is connected to the second terminal (Q2) of the dipole (D1).

3. Voltage reference circuit according to claim 1, characterised in that the dipole (D21) comprises n enhancement-mode transistors (M31, M3n), each of said enhancement-mode transistors (M31-M3n) having its gate connected to its drain, said enhancement-mode transistors (M31-M3n) being connected in series, two consecutive transistors (M31-M3n) being connected by the source of one and the drain of the other and, the drain of the first transistor (M31) forming the first terminal (Q21) of the dipole (D21) and the source of the last transistor (M3n) forming the second terminal (Q22) of the second dipole (D21).

4. Voltage reference circuit according to claim 4, characterised in that the dipole (D11) comprises three enhancement-mode transistors (M21, M22, M23).

5. Voltage reference circuit according to claim 1, characterised in that the transistors are GaN transistors.