MONITORING THE CONDITION OF A CAPACITOR IN A POWER CONVERTER

Description

FIELD

[0001] The present disclosure relates to a method for monitoring a health of a capacitor of a power converter.BACKGROUND

[0002] Electrical devices, such as, power converters are used in a multitude of applications where an efficient management and transformation of electrical energy is required. The power converters may be employed where an alternating current is the primary mode of power delivery, such as in renewable energy integration, vehicular propulsion, and various industrial processes. Despite their role, the power converters may also be susceptible to operational disruptions due to component degradation, which can lead to significant downtime and maintenance costs. The component degradation often stems from thermal and electrical stress.

[0003] One of the weakest components in a power converter system may be capacitors. Failures of the capacitors may be prevented by employing a suitable capacitor condition monitoring system to identify and predict capacitor degradation to estimate a remaining useful life of the capacitors.

[0004] Efforts to enhance reliability in the power converters have led to development of diagnostic tools aimed at assessing the health of the capacitors. However, current methods require additional hardware or modification in the existing hardware. Therefore, the current methods may not be suitable for commercial off-the-shelf power converters and may limit adaptability across different technologies prevalent in the field.

[0005] A method capable of estimating a condition of the capacitors without any additional hardware or modifications to existing hardware may offer substantial advantages in applications where safety and reliability are of high importance.

[0006] For capacitors, equivalent series resistance (ESR) and capacitance are the widely used degradation indicators where ESR is most commonly used for aluminium electrolytic, and capacitance is used for both aluminium electrolytic, film and ceramic types. Most of the existing methods focuses on only one of these two parameters. A background art is given by Sundararajan Prasanth et al., "Condition Monitoring of DC-Link Capacitors Using Goertzel Algorithm for Failure Precursor Parameter and Temperature Estimation", IEEE TRANSACTIONS ON POWER ELECTRONICS, INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, USA, vol. 35, no. 6, June 2020, pages 6386-6396.

[0007] Therefore, the industry recognizes the importance of a versatile and integrated approach to health monitoring of the capacitors of the power converters that can operate with existing system configurations and provide comprehensive diagnostics.

[0008] There is a need to provide a method for monitoring a health of a capacitor of a power converter that addresses the aforementioned shortcomings or at least provides a useful alternative to known such methods.SUMMARY

[0009] In accordance with a first aspect of the present disclosure, a method for monitoring a health of a capacitor of a power converter is disclosed. The method comprises acquiring a DC link capacitor voltage V dc , an input current I in , phase currents I a , I b , I c , and switching pulses SP1, SP2, SP3 of the power converter. The method further comprises calculating a DC link current I dc based on the switching pulses SP1, SP2, SP3 and the phase currents I a , I b , I c . The method further comprises calculating a capacitor current I cap based on the DC link current I dc and the input current I in . The method further comprises applying Goertzel algorithm to determine a first z-domain equation H(z)I cap of the capacitor current I cap and a second z-domain equation H(z)V dc of the DC link capacitor voltage V dc . The method further comprises determining an estimated equivalent series resistance (ESR) and an estimated capacitance of the capacitor based on the first z-domain equation H(z)I cap of the capacitor current I cap and the second z-domain equation H(z)V dc of the DC link capacitor voltage V dc . The method further comprises retrieving an initial ESR and an initial capacitance of the capacitor. The method further comprises comparing the estimated ESR with the initial ESR and / or the estimated capacitance with the initial capacitance to determine if the capacitor is degraded, short-circuited, or open-circuited.

[0010] The method according to the present disclosure may enable equipment health monitoring (EHM) and remaining useful life estimation of the capacitor in the power converter. The method may be applied to existing power converters just by accessing terminals that are usually available for a user by acquiring the DC link capacitor voltage V dc , the input current I in , the phase currents I a , I b , I c , and the switching pulses SP1, SP2, SP3 of the power converter. These parameters may be easy to obtain using available data and using inexpensive sensors and may not require any customized circuits to extract any signature. Therefore, the method may be easily applied to any commercial off-the-shelf as well as in-house power converter systems. The method may further provide an early detection of degradation, short-circuits, or open-circuits, which further may enable to prevent the power converter failures. The method may therefore reduce maintenance costs. Further, the method uses the estimated capacitance and the estimated ESR and therefore may be applied to dominant capacitor technologies.

[0011] Further developments of the method can be found in the dependent claims and show particularly advantageous possibilities to realize above-described concept in light of the object of the disclosure and regarding further advantages.

[0012] In a further development, the method comprises pausing an operation of the power converter upon determining that the capacitor is degraded, short-circuited, or open-circuited.

[0013] Pausing the operation of the power converter upon determining that the capacitor is degraded, short-circuit, or open-circuit may prevent any occurrence of damage to the power converter and / or a load electrically connected to the power converter.

[0014] In a further development, the DC link capacitor voltage is acquired from a voltage sensor. The voltage sensor used to acquire the DC link capacitor voltage may be an inexpensive voltage sensor.

[0015] In a further development, the input current is acquired from an input current sensor. The input current sensor used to acquire the input current may be an inexpensive current sensor.

[0016] In a further development, the phase currents are acquired from corresponding phase current sensors. The phase current sensors used to acquire the phase currents may be inexpensive current sensors.

[0017] In a further development, the switching pulses are acquired from a controller of the power converter. The switching pulses may be readily and easily acquired from the controller of the power converter.

[0018] In a further development, the DC link current is calculated from the equation: I dc = SP 1 ∗ I a + SP 2 ∗ I b + SP 3 ∗ I c

[0019] Therefore, the DC link current may be simply calculated using the switching pulses and the phase currents which may be acquired using inexpensive current sensors.

[0020] In a further development, the capacitor current is calculated by subtracting the DC link current from the input current.

[0021] Therefore, the capacitor current may be easily determined in a simplified manner without any additional components or modifications by employing inexpensive current and voltage sensors.

[0022] In a further development, the first z-domain equation of the capacitor current is: H z Icap = 1 − w kx NxZ − 1 1 − 2 cos 2 πkx Nx Z − 1 + Z − 2 ∗ Icap

[0023] Where, Nx is a number of samples and Kx is: Kx = Nx 1 Nx ∗ Ts where, Ts is a sampling time.

[0024] The first z-domain equation may provide efficient evaluation of the capacitor current.

[0025] In a further development, the second z-domain equation of the DC link capacitor voltage is: H z Vdc = 1 − w kx NxZ − 1 1 − 2 cos 2 πkx Nx Z − 1 + Z − 2 ∗ Vdc where, Nx is the number of samples and kx is, Kx = Nx 1 Nx ∗ Ts where, Ts is the sampling time.

[0026] The second z-domain equation may provide efficient evaluation of the capacitor voltage.

[0027] In a further development, the estimated ESR of the capacitor is estimated from the equation: estimated ESR = Real H z Vdc H z Icap

[0028] The estimated ESR may be simply and accurately estimated using the first and second z-domain equations from the above equation.

[0029] In a further development, the method comprises identifying a dominant frequency component based on the DC link capacitor voltage.

[0030] The dominant frequency component may be used to estimate the estimated capacitance of the capacitor.

[0031] In a further development, the estimated capacitance of the capacitor is estimated from the equation: estimated capacitance = Imag H z Vdc H z Icap ∗ abs 1 / 2 ∗ pi ∗ fd

[0032] The estimated capacitance may be simply and accurately estimated using the first and second z-domain equations from the above equation.

[0033] In a further development, the method comprises indicating that the capacitor is degraded if the estimated ESR is greater than the initial ESR by at least 10% of the initial ESR.

[0034] Upon receiving an indication that the capacitor is degraded, a user or a controller may decide the subsequent steps (e.g., to pause or stop an operation of the power converter) accordingly.

[0035] In a further development, the method comprises indicating that the capacitor is short-circuited if the estimated ESR is less than the initial ESR by at least 100% of the initial ESR.

[0036] Upon receiving an indication that the capacitor is short-circuited, the user or the controller may decide the subsequent steps (e.g., to pause or stop the operation of the power converter) accordingly.

[0037] In a further development, the method comprises indicating that the capacitor is degraded if the estimated capacitance is less than the initial capacitance by at least 5% of the initial capacitance and at most 50% of the initial capacitance.

[0038] Upon receiving an indication that the capacitor is degraded, the user or the controller may decide the subsequent steps (e.g., to pause or stop the operation of the power converter) accordingly.

[0039] In a further development, the method comprises indicating that the capacitor is open-circuited if the estimated capacitance is less than the initial capacitance by at least 50% of the initial capacitance.

[0040] Upon receiving an indication that the capacitor is open-circuited, the user or the controller may decide the subsequent steps (e.g., to pause or stop the operation of the power converter) accordingly.

[0041] According to a second aspect, a system is disclosed. The system comprises a processor and a memory having stored therein a plurality of instructions that when executed by the processor causes the system to perform the method of the first aspect.

[0042] It shall be understood that the method for monitoring the health of the capacitor of the power converter according to the first aspect of the disclosure and the system according to the second aspect of the disclosure may comprise identical or similar developments, in particular as described in the dependent claims. Therefore, a development of one aspect of the disclosure is also applicable to another aspect of the disclosure.

[0043] These and other aspects of the method of the present disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. The embodiments of the method are described in the following on the basis of the drawings. The latter is not necessarily intended to represent the embodiments to scale. Drawings are, where useful for explanation, shown in schematized and / or slightly distorted form. With regard to additions to the teachings immediately recognizable from the drawings, reference is made to the relevant state-of-the-art. It should be borne in mind that numerous modifications and changes can be made to the form and detail of an embodiment without deviating from the general idea of the disclosure. The features of the method of the present disclosure in the description, in the drawings and in the claims may be essential for a further development of the method either individually or in any combination.

[0044] In addition, all combinations of at least two of the features disclosed in the description, drawings and / or claims fall within the scope of the disclosure. The general idea of the disclosure is not limited to the exact form or detail of the preferred embodiment shown and described below, or to an object which would be limited in comparison to the object claimed in the claims. For specified design ranges, values within the specified limits are also disclosed as limit values and thus arbitrarily applicable and claimable.BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Further advantages, features and details of the present disclosure result from the following description of the preferred embodiments as well as from the drawings, which show in: FIG. 1a schematic circuit diagram of a power converter, according to an embodiment of the present disclosure; FIG. 2a schematic block diagram of a system, according to an embodiment of the present disclosure; FIG. 3a flow chart for a method for monitoring a health of a capacitor of the power converter, according to an embodiment of the present disclosure; FIG. 4an exemplary graphical representation of current phases; FIG. 5an exemplary graphical representation of an input current, a DC link current and a DC link current; FIG. 6an exemplary graph depicting an amplitude versus a frequency of a DC link capacitor voltage; FIG. 7a flow chart of a method for determining an estimated equivalent series resistance (ESR) of the capacitor, according to an embodiment of the present disclosure; and FIG. 8a flow chart of a method for determining an estimated capacitance of the capacitor, according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] Aspects and embodiments of the present disclosure will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art.

[0047] FIG. 1 shows a schematic circuit diagram of a power converter 300, according to an embodiment of the present disclosure. In the illustrated embodiment of FIG. 1, the power converter 300 is a three-phase inverter. Further, the power converter 300 may be a commercial off-the-shelf power converter.

[0048] The power converter 300 comprises a plurality of switches S1, S2, S3, S4, S5, S6. In the illustrated example of FIG. 1, the power converter 300 comprises six switches. However, in some other embodiments, the power converter 300 may comprise any number of switches based on desired application attributes. The power converter 300 further comprises a capacitor 302 electrically connected in parallel with the plurality of switches S1, S2, S3, S4, S5, S6. In some embodiments, the capacitor 302 is a DC link capacitor. In some embodiments, the capacitor 302 may provide energy for one switching cycle of the power converter 300.

[0049] In the illustrated example of FIG. 1, the power converter 300 is electrically connected to a DC source 320. The DC source 320 is configured to provide a DC power to the power converter 300. In some embodiments, the DC source 320 may be a rectifier. In some embodiments, the DC source 320 may be a battery. Further, the power converter 300 is electrically connected to a load 330. In some embodiments, the load 330 may be a three-phase motor.

[0050] In some cases, the DC source 320 may introduce parasitic inductance in the power converter 300. When the DC source 320 is the rectifier, the DC source 320 may introduce its own harmonics into the power converter 300. In such cases, the capacitor 302 may be used to eliminate the harmonics and provide a fundamental component to the power converter 300. Hence, the capacitor 302 may play an important role in the operation of the power converter 300.

[0051] As shown in FIG. 1, the DC source 320 provides an input current I in to the power converter 300. Further, an electrical voltage across the capacitor 302 is a DC link capacitor voltage V dc . Furthermore, each phase of the power converter 300 receives a corresponding phase current I a , I b , I c . Specifically, the phase of the power converter 300 comprising the switches S1, S4 receives the phase current I a , the phase of the power converter 300 comprising the switches S3, S6 receives the phase current I b , and the phase of the power converter 300 comprising the switches S5, S2 receives the phase current I c . Furthermore, each phase of the power converter 300 receives a corresponding switching pulse SP1, SP2, SP3. Specifically, the phase of the power converter 300 comprising the switches S1, S4 receives the switching pulse SP1, the phase of the power converter 300 comprising the switches S3, S6 receives the switching pulse SP2, and the phase of the power converter 300 comprising the switches S5, S2 receives the switching pulse SP3. In some embodiments, the switching pulses SP1, SP2, SP3 may be provided by a controller 340. In some embodiments, the controller 340 may be a component of the power converter 300. In some embodiments, the power converter 300 may operate using a typical pulse width modulation (PWM) technique. Switching of the power converter 300 may produce a current which has a fundamental component and many harmonics. Both the fundamental and harmonic currents are drawn from the capacitor 302.

[0052] In some embodiments, the DC link capacitor voltage V dc is acquired from a voltage sensor 304. Further, in some embodiments, the input current I in is acquired from an input current sensor 306. In some embodiments, the phase currents I a , I b , I c are acquired from corresponding phase current sensors 308. In some embodiments, the switching pulses SP1, SP2, SP3 are acquired from the controller 340 of the power converter 300.

[0053] FIG. 2 shows a schematic block diagram of a system 100, according to an embodiment of the present disclosure. The system 100 comprises a processor 102 and a memory 104 having stored therein a plurality of instructions that when executed by the processor 102 causes the system 100 to perform operations described herein.

[0054] Referring to FIGS. 1 and 2, in some embodiments, the processor 102 is communicably connected to the input current sensor 306, the voltage sensor 304, and the phase current sensors 308. The processor 102 may monitor the health of the capacitor 302 of the power converter 300 by performing the operations described herein.

[0055] FIG. 3 shows a flow chart for a method 200 for monitoring the health of the capacitor 302 of the power converter 300 shown in FIG. 1, according to an embodiment of the present disclosure. The method 200 is described with further reference to FIGS. 1 and 2. In some embodiments, the processor 102 causes the system 100 to perform the method 200.

[0056] At step 202, the method 200 comprises acquiring the DC link capacitor voltage V dc , the input current I in , the phase currents I a , I b , I c , and the switching pulses SP1, SP2, SP3 of the power converter 300.

[0057] As discussed above, in some embodiments, the DC link capacitor voltage V dc is acquired from the voltage sensor 304, the input current I in is acquired from the input current sensor 306, the phase currents I a , I b , I c are acquired from the corresponding phase current sensors 308, and the switching pulses SP1, SP2, SP3 are acquired from the controller 340 of the power converter 300.

[0058] At step 204, the method 200 comprises calculating a DC link current I d , based on the switching pulses SP1, SP2, SP3 and the phase currents I a , I b , I c . In some embodiments, the DC link current I d , is calculated from the equation: I dc = SP 1 ∗ I a + SP 2 ∗ I b + SP 3 ∗ I c .

[0059] At step 206, the method 200 comprises calculating a capacitor current I cap based on the DC link current I dc and the input current I in . In some embodiments, the capacitor current I cap is calculated by subtracting the DC link current I dc from the input current I in , i.e., I cap = I in - I dc . The capacitor current I cap may produce a variation in the DC link voltage V dc .

[0060] Therefore, the capacitor current I cap may be easily determined using the method 200 by employing the input current sensor 306 and the phase current sensors 308. The input current sensor 306 and the phase current sensors 308 may be less expensive compared to high-bandwidth current sensors that may be required for capacitor current sensing applications.

[0061] At step 208, the method 200 comprises applying Goertzel algorithm to determine a first z-domain equation H(z)I cap of the capacitor current I cap and a second z-domain equation H(z)V dc of the DC link capacitor voltage V dc .

[0062] In some embodiments, the first z-domain equation H (z)I cap of the capacitor current I cap is: H z Icap = 1 − w kx NxZ − 1 1 − 2 cos 2 πkx Nx Z − 1 + Z − 2 ∗ Icap where, Nx is a number of samples and Kx is: Kx = Nx 1 Nx ∗ Ts where, Ts is a sampling time.

[0063] In some embodiments, the number of samples Nx and the sampling time Ts may be based on a switching frequency of the power converter 300.

[0064] Further, in some embodiments, the second z-domain equation H(z)V dc of the DC link capacitor voltage V dc is: H z Vdc = 1 − w kx NxZ − 1 1 − 2 cos 2 πkx Nx Z − 1 + Z − 2 ∗ Vdc

[0065] At step 210, the method 200 comprises determining an estimated equivalent series resistance (ESR) and an estimated capacitance of the capacitor 302 based on the first z-domain equation H(z)I cap of the capacitor current I cap and the second z-domain equation H(z)V dc of the DC link capacitor voltage V dc .

[0066] In some embodiments, the estimated ESR of the capacitor 302 is estimated from the equation: estimated ESR = Real H z Vdc H z Icap

[0067] Furthermore, in some embodiments, the estimated capacitance of the capacitor 302 is estimated from the equation: estimated capacitance = Imag H z Vdc H z Icap ∗ abs 1 / 2 2 ∗ pi ∗ fd where, fd is a dominant frequency component (shown in FIG. 5).

[0068] In some embodiments, the method 200 further comprises identifying the dominant frequency component fd based on the DC link capacitor voltage V dc . In some embodiments, the dominant frequency component fd is about ±5% of the switching frequency of the power converter 300.

[0069] Therefore, the method 200 may rely on measuring the switching current harmonics to estimate the estimate capacitance and the estimate ESR.

[0070] At step 212, the method 200 comprises retrieving an initial ESR and an initial capacitance of the capacitor 302. In some embodiments, the initial ESR and the initial capacitance of the capacitor 302 may be retrieved from the memory 104 communicably coupled to the processor 102. In some other embodiments, the initial ESR and the initial capacitance of the capacitor 302 may be retrieved from an external database (not shown) communicably coupled to the processor 102.

[0071] At step 214, the method 200 comprises comparing the estimated ESR with the initial ESR and / or the estimated capacitance with the initial capacitance to determine if the capacitor 302 is degraded, short-circuited, or open-circuited. In some embodiments, the method 200 comprises pausing an operation of the power converter 300 upon determining that the capacitor 302 is degraded, short-circuited, or open-circuited. In some embodiments, the method 200 comprises stopping the operation of the power converter 300 upon determining that the capacitor 302 is degraded, short-circuited, or open-circuited.

[0072] In some embodiments, the method 200 further comprises indicating that the capacitor 302 is degraded if the estimated ESR is greater than the initial ESR by at least 10% of the initial ESR.

[0073] In some embodiments, the method 200 further comprises indicating that the capacitor 302 is degraded if the estimated capacitance is less than the initial capacitance by at least 5% of the initial capacitance and at most 50% of the initial capacitance. In other words, the method 200 comprises indicating that the capacitor 302 is degraded if the estimated capacitance is less than the initial capacitance between 5% and 50% of the initial capacitance.

[0074] In some embodiments, the method 200 further comprises indicating that the capacitor 302 is short-circuited if the estimated ESR is less than the initial ESR by at least 100% of the initial ESR.

[0075] In some embodiments, the method 200 comprises indicating that the capacitor 302 is open-circuited if the estimated capacitance is less than the initial capacitance by at least 50% of the initial capacitance.

[0076] FIG. 4 shows an exemplary graphical representation of the current phases I a , I b , I c . FIG. 4 further shows the DC link current I dc calculated based on the switching pulses SP1, SP2, SP3 (shown in FIG. 1) and the phase currents I a , I b , I c .

[0077] FIG. 5 shows an exemplary graphical representation of the input current I in and the DC link current I dc (also shown in FIG. 4). FIG. 5 further shows the capacitor current I cap calculated based on the DC link current I dc and the input current I in .

[0078] FIG. 6 shows an exemplary graph depicting an amplitude versus a frequency of the DC link capacitor voltage V dc shown in FIG. 1. FIG. 6 further shows the dominant frequency component fd of the DC link capacitor voltage V dc .

[0079] FIG. 7 shows a flow chart of a method 600 for determining the estimated ESR of the capacitor 302 shown in FIG. 1, according to an embodiment of the present disclosure. FIG. 7 is described with further reference to FIGS. 1-6.

[0080] The method 600 comprises a step 602 equivalent to the step 202 of the method 200. Specifically, at step 602, the method 600 comprises acquiring the DC link capacitor voltage V dc , the input current I in , the phase currents I a , I b , I c , and the switching pulses SP1, SP2, SP3 of the power converter 300.

[0081] The method 600 further comprises a step 604 equivalent to the step 208 of the method 200. Specifically, at step 604, the method 600 comprises applying the Goertzel algorithm to determine the first z-domain equation H(z)I cap of the capacitor current I cap and the second z-domain equation H(z)V dc of the DC link capacitor voltage V dc .

[0082] The method 600 further comprises a step 606 comprising determining the estimated ESR based on the first z-domain equation H(z)I cap of the capacitor current I cap and the second z-domain equation H(z)V dc of the DC link capacitor voltage V dc .

[0083] The method 600 further comprises a step 608A comprising determining if the estimated ESR is greater than the initial ESR by at least 10% of the initial ESR. The method 600 proceeds to a step 610 comprising indicating that the capacitor 302 is degraded when the estimated ESR is greater than the initial ESR by at least 10% of the initial ESR, otherwise the method 600 proceeds to the step 604.

[0084] The method 600 further comprises a step 608B comprising determining if the estimated ESR is less than the initial ESR by at least 100% of the initial ESR. The method 600 proceeds to a step 612 comprising indicating that the capacitor 302 is short-circuited if the estimated ESR is less than the initial ESR by at least 100% of the initial ESR, otherwise the method 600 proceeds to the step 604.

[0085] FIG. 8 shows a flow chart of a method 700 for determining the estimated capacitance of the capacitor 302 shown in FIG. 1, according to an embodiment of the present disclosure. FIG. 8 is described with further reference to FIGS. 1-6.

[0086] The method 700 comprises a step 702 equivalent to the step 202 of the method 200. Specifically, at step 702, the method 700 comprises acquiring the DC link capacitor voltage V dc , the input current I in , the phase currents I a , I b , I c , and the switching pulses SP1, SP2, SP3 of the power converter 300.

[0087] The method 700 further comprises a step 704 equivalent to the step 208 of the method 200. Specifically, at step 704, the method 700 comprises applying the Goertzel algorithm to determine the first z-domain equation H(z)I cap of the capacitor current I cap and the second z-domain equation H(z)V dc of the DC link capacitor voltage V dc .

[0088] The method 700 further comprises a step 706 comprising determining the estimated ESR based on the first z-domain equation H(z)I cap of the capacitor current I cap and the second z-domain equation H(z)V dc of the DC link capacitor voltage V dc .

[0089] The method 700 further comprises a step 708A comprising determining if the estimated capacitance is less than the initial capacitance by at least 5% of the initial capacitance and at most 50% of the initial capacitance. The method 700 proceeds to a step 710 comprising indicating that the capacitor 302 is degraded when the estimated capacitance is less than the initial capacitance by at least 5% of the initial capacitance and at most 50% of the initial capacitance, otherwise the method 700 proceeds to the step 704.

[0090] The method 700 further comprises a step 708B comprising determining if the estimated capacitance is less than the initial capacitance by at least 50% of the initial capacitance. The method 700 proceeds to a step 712 comprising indicating that the capacitor 302 is open-circuited if the estimated capacitance is less than the initial capacitance by at least 50% of the initial capacitance, otherwise the method 700 proceeds to the step 704.

[0091] Referring to FIGS. 1 to 8, the method 200 may enable equipment health monitoring (EHM) and remaining useful life estimation of the capacitor 302 in the power converter 300. The method 200 may be applied to existing power converters just by accessing terminals that are usually available for a user by acquiring the DC link capacitor voltage V dc , the input current I in , the phase currents I a , I b , I c , and the switching pulses SP1, SP2, SP3 of the power converter 300. These parameters may be easy to obtain using available data and using inexpensive sensors and may not require any customized circuits to extract any signature. Therefore, the method 200 may be easily applied to any commercial off-the-shelf as well as in-house power converter systems. The method 200 may further provide an early detection of degradation, short-circuits, or open-circuits, which further may enable to prevent the power converter failures. The method 200 may therefore reduce maintenance costs. Further, the method 200 uses the estimated capacitance and the estimated ESR and therefore may be applied to dominant capacitor technologies.List of reference signs (part of the description)

[0092] 100System 102Processor 104Memory 200Method 202Step 204Step 206Step 208Step 210Step 212Step 214Step 300Power Converter 302Capacitor 304Voltage Sensor 306Input Current Sensor 308Phase Current Sensors 320DC source 330Load 340Controller 600Method 602Step 604Step 606Step 608AStep 608BStep 610Step 612Step 700Method 702Step 704Step 706Step 708AStep 708BStep 710Step 712Step fdDominant Frequency Component V dc DC Link Capacitor Voltage I dc DC Link Current I cap Capacitor Current I in Input Current I a Phase Current I b Phase Current I c Phase Current S1Switch S2Switch S3Switch S4Switch S5Switch S6Switch SP1Switching Pulses SP2Switching Pulses SP3Switching Pulses

Claims

1. A method (200) for monitoring a health of a capacitor (302) of a power converter (300), the method (200) comprising the steps of: acquiring a DC link capacitor voltage (Vdc), wherein the method is characterised by comprising further the steps of acquiring an input current (Iin), phase currents (Ia, Ib, Ic), and switching pulses (SP1, SP2, SP3) of the power converter (300); calculating a DC link current (Idc) based on the switching pulses (SP1, SP2, SP3) and the phase currents (Ia, Ib, Ic); calculating a capacitor current (Icap) based on the DC link current (Idc) and the input current (Iin); applying Goertzel algorithm to determine a first z-domain equation (H(z)lcap) of the capacitor current (Icap) and a second z-domain equation (H(z)Vdc) of the DC link capacitor voltage (Vdc); determining an estimated Equivalent Series Resistance (ESR) and an estimated capacitance of the capacitor (302) based on the first z-domain equation (H(z)Icap) of the capacitor current (Icap) and the second z-domain equation (H(z)Vdc) of the DC link capacitor voltage (Vdc); retrieving an initial ESR and an initial capacitance of the capacitor (302); and comparing the estimated ESR with the initial ESR and / or the estimated capacitance with the initial capacitance to determine if the capacitor (302) is degraded, short-circuited, or open-circuited.

2. The method (200) of claim 1, comprising pausing an operation of the power converter (300) upon determining that the capacitor (302) is degraded, short-circuited, or open-circuited.

3. The method (200) of claim 1 or 2, wherein the DC link capacitor voltage (Vdc) is acquired from a voltage sensor (304), and / or the input current (Iin) is acquired from an input current sensor (306).

4. The method (200) of any preceding claim, wherein the phase currents (Ia, Ib, Ic) are acquired from corresponding phase current sensors (308).

5. The method (200) of any preceding claim, wherein the switching pulses (SP1, SP2. SP3) are acquired from a controller (340) of the power converter (300).

6. The method (200) of any preceding claim, wherein the DC link current (Idc) is calculated from the equation: I dc = SP 1 ∗ I a + SP 2 ∗ I b + SP 3 ∗ I c 7. The method (200) of any preceding claim, wherein the capacitor current (Icap) is calculated by subtracting the DC link current (Idc) from the input current (Iin).

8. The method (200) of any preceding claim, wherein the first z-domain equation (H(z)Icap) of the capacitor current (Icap) is: H z Icap = 1 − w kx NxZ − 1 1 − 2 cos 2 πkx Nx Z − 1 + Z − 2 ∗ Icap where, Nx is a number of samples and Kx is: Kx = Nx 1 Nx ∗ Ts where, Ts is a sampling time.

9. The method (200) of any preceding claim, wherein the second z-domain equation (H(z)Vdc) of the DC link capacitor voltage (Vdc) is: H z Vdc = 1 − w kx NxZ − 1 1 − 2 cos 2 πkx Nx Z − 1 + Z − 2 ∗ Vdc where, Nx is the number of samples and kx is, Kx = Nx 1 Nx ∗ Ts where, Ts is the sampling time.

10. The method (200) of any preceding claim, wherein the estimated ESR of the capacitor (302) is estimated from the equation: estimated ESR = Real H z Vdc H z Icap 11. The method (200) of any preceding claim, comprising identifying a dominant frequency component (fd) based on the DC link capacitor voltage (Vdc).

12. The method (200) of claim 11, wherein the estimated capacitance of the capacitor (302) is estimated from the equation: estimated capacitance = Imag H z Vdc H z Icap ∗ abs 1 / 2 ∗ pi ∗ fd 13. The method (200) of any preceding claim, further comprising indicating that the capacitor (302) is degraded if the estimated ESR is greater than the initial ESR by at least 10% of the initial ESR, and / or further comprising indicating that the capacitor (302) is short-circuited if the estimated ESR is less than the initial ESR by at least 100% of the initial ESR.

14. The method (200) of any preceding claim, further comprising indicating that the capacitor (302) is degraded if the estimated capacitance is less than the initial capacitance by at least 5% of the initial capacitance and at most 50% of the initial capacitance, and / or further comprising indicating that the capacitor (302) is open-circuited if the estimated capacitance is less than the initial capacitance by at least 50% of the initial capacitance.

15. A system (100) including a processor (102) and a memory (104) having stored therein a plurality of instructions that when executed by the processor (102) causes the system (100) to perform the method (200) of any of the preceding claims.