Switching circuit for a cam

Abstract

The invention relates to a switching circuit with a CMOS inverter and a changeable resistor (Rfb), wherein the changeable resistor (Rfb) electrically connects the input (Vin) of the CMOS inverter to the output (Vout) of the CMOS inverter. The invention also relates to a CAM having such a switching circuit. As a result, a switching circuit can be produced which can operate like an analogue CAM and a digital CAM.

Description

[0001] Circuit for a CAM

[0002] Description

[0003] The invention relates to a circuit for a CAM, in particular an analog Content Addressable Memory (aCAM).

[0004] CAM is an abbreviation for "Content-Addressable Memory." Unlike conventional memory types such as RAM (Random Access Memory), where data is accessed via the memory address, a CAM allows data to be accessed based on its content. This means that you can search for specific data in a CAM without knowing the exact memory address. This is often referred to as "associative memory." It is possible to apply an input signal to a CAM. The input signal can be a voltage applied to the CAM, and thus an analog signal. The CAM can then output whether the input signal is stored or not. This can be done, for example, by outputting a "0" or a "1," i.e., by outputting a digital value. For example, a CAM can output the value "0" if the entered memory value is not stored in the associative memory.A CAM can output the value “1” if the entered memory value is stored in the CAM.

[0005] The publications "Can Li et al. “Analog content-addressable memories with memristors”. In: Nature Communications 11.1 (Apr. 2020). DOI: 10.1038 / s41467-020-15254-4" and "Jinane Bazzi et al. Efficient Analog CAM Design. 2022. DOI: 10.48550 / ARXIV.2203.02500. URL: https: / / arxiv.org / abs / 2203.02500" each describe an "analog CAM" (aCAM), in which input signals and stored data can be continuous analog values ​​rather than binary numbers. This aCAM outputs a "1" if an input signal matches the stored data. Otherwise, a "0" is output.

[0006] A "differentiable analog CAM" (dCAM) is known from the paper "Giacomo Pedretti et al. "Differentiable Content Addressable Memory with Memristors", Advanced Electronic Materials 8.8 (Mar. 2022), p. 2101198. DOI: 10.1002 / aelm" that can also output values ​​between 0 and 1 to find partial matches and enable traceability within an aCAM system. A CAM can include a CMOS inverter. CMOS is a term for semiconductor devices that use both p-channel and n-channel MOSFETs on a common substrate. A CMOS inverter is an electronic component that can convert one signal format to another. There are CMOS inverters that can convert an input voltage to a different output voltage and thus amplify it. For example, such a CMOS inverter can convert a low input voltage into a higher output voltage, i.e. multiply it by a factor.

[0007] The aim of the present invention is to provide a circuit for a CAM that can improve the flexibility of a CAM. In particular, the circuit should be able to create a CAM that can have the properties of an aCAM and a dCAM. Such a CAM can, for example, optionally output binary values ​​or analog values ​​in response to an applied analog input signal. Analog values ​​can indicate a measure of a distance or a degree of agreement. A distance can express how far an applied input signal is from a value stored in the CAM or how closely an applied input signal agrees with a stored value. The CAM can then, for example, optionally output the values ​​"0" and "1", but also values ​​that lie between "0" and "1", such as the value "0.6" or "0.5".

[0008] To achieve this goal, a circuit is provided. The circuit may comprise a CMOS inverter. The circuit may comprise a resistor. The resistor may be arranged in such a way that the circuit's output signal no longer changes abruptly depending on the input signal, as is the case with a conventional CMOS inverter, and in this sense can only output a "0" or "1". Instead, the output signal may change gradually once the input signal has exceeded a threshold. This can be achieved by electrically connecting the input of the CMOS inverter to the output of the CMOS inverter via the resistor. The circuit may further be configured so that the resistance can be changed. The resistance can be changed, for example, by switching the resistor back and forth between an initial value and a very high-impedance final value.The resistance can be changed, for example, by a switch that can be opened and closed. The high-impedance final value can be such that the CMOS inverter behaves like a conventional CMOS inverter. The switch can be such that the CMOS inverter behaves like a conventional CMOS inverter when the switch is open. The output value can be such that the CMOS inverter behaves as described above. The output value can be, for example, at least 1 MQ (megaohm), or at least 50 MQ, or at least 100 MQ, or at least 200 MQ. The output value can be, for example, less than 500 MQ or less than 300 MQ. The final value can be, for example, at least 1 GQ (gigaohm), or at least 50 GQ, or at least 100 GQ.

[0009] The circuit can therefore include a CMOS inverter with a resistive feedback path to modify the conversion of an input signal into an output signal. For example, the CMOS inverter can reduce gain. The circuit makes it possible to create a CAM with greater flexibility. The circuit can support both high-resolution analog CAMs (aCAM) with sharp selection and differentiable CAMs (dCAM) with flat selection function margins for improved intra-cell distance metrics for gradient descent.

[0010] Amplification by the CMOS inverter also depends on the potential V applied to the CMOS inverter ss and Vdd. The voltage applied to the CMOS inverter is the difference between the potentials V ss and Vdd can be used to determine the maximum amplification of an input signal by the circuit. The potential V sscan be permanently 0 volts. The potential Vdd can be permanently 1 volt.

[0011] For example, if a potential V ss= 0 volts and a potential Vdd = 1 volt is applied, then an input signal can only be output in inverted form. If the input signal is 0 volts, then 1 volt can be output. If the input signal is 1 volt, then 0 volt can be output. The gain can be modulated around the value 0.5 volts. If the input signal is 0.5 volts, then 0.5 volts can be output. It may be that the input signal is 0.4 volts in order to output 0.6 volts. It may be that the input signal is 0.3 volts in order to output 0.7 volts. This modulation can, however, be limited to the range around a certain value, such as 0.5 volts. It may therefore be that an input voltage of 0.2 volts is too low to produce an output signal of less than 1 volt.It is therefore possible that an input voltage of 0.2 volts results in an output voltage of 1 volt.

[0012] The modulation depends on the size of the resistor. The higher the resistance, the less abruptly an output signal can change from "0" to "1". If the resistor has a very high resistance, the circuit behaves like a conventional CMOS inverter, which can abruptly convert one input voltage into another output voltage. The input of the CMOS inverter can be electrically connected to a memristor. The memristor can be designed to store information. The circuit can therefore be set up and operated in such a way that a voltage can be applied to the memristor, which can be used to adjust the conductance of the memristor. Such a voltage is also called a write voltage. In this case, programming of the memristor is possible. For example, the memristor can be programmed using a digital signal, which can be converted into an analog voltage by a digital-to-analog converter.Using the analog converted voltage, the conductance of the memristor can be programmed.

[0013] The circuit can be configured and operated in such a way that a voltage can be applied to the memristor, allowing the memristor's conductance to be read. Such a voltage is also called the read voltage.

[0014] The input of the CMOS inverter can be electrically connected to a transistor. The transistor can serve as a voltage divider, for example, to read the conductance of the memristor. The transistor can be part of a voltage divider.

[0015] The memristor can be electrically connected in series with the transistor.

[0016] The transistor can be an NMOS transistor.

[0017] The electrical connection provided by the variable resistor can be interrupted by a switch to change the electrical resistance. In a technically simple embodiment, the switch can be a transistor. Such a change can create a circuit that can operate both as an analog CAM and as a digital CAM.

[0018] The variable resistor can be configured so that it can be switched between a very high-impedance conductance and a comparatively low-impedance conductance. This also allows a circuit to be created that can be operated both as an analog CAM and as a digital CAM. The high-impedance conductance can be more than 1 MΩ. The low-impedance conductance can be less than 500 MΩ.

[0019] The circuit can be part of a CAM. In other words, a CAM comprises at least one circuit as described above. A CAM can comprise two circuits as described above. There can be exactly two such circuits. Three or more such circuits are then excluded. Each circuit can comprise an identical layout to minimize the technical complexity of manufacturing.

[0020] The CAM can include two CMOS inverters, two memristors and four additional transistors.

[0021] The cam may comprise two sections, each of which may contain a circuit as previously described. Each section may have its own input for an input voltage. Each section may have its own output for an output voltage.

[0022] The input of one section can be connected to the input of the other section via an inverter.

[0023] The outputs of both sections can be connected to a shared line. This shared line can be used to indicate a hit. This means that an analog voltage corresponding to a "0" or a "1" signal can be output via the shared line. A voltage corresponding to a signal between "0" and "1" can also be output.

[0024] A CAM according to the invention can be part of a neural network to enable training of the neural network. Using the CAM according to the invention, information can be obtained about how well a neural network is performing.

[0025] The properties and behavior of a neural network should resemble those of a biological neural network. A neural network should be able to recognize patterns using adaptive algorithms. A neural network, like the human brain, should not have to start from scratch for every task or problem. It should be able to draw on previously acquired knowledge and experiences.

[0026] A neural network with memristors is known from document CN 208922326 U. A circuit serving as a synapse of a neural network made of semiconductor materials with an electrically charged carrier gas is described in document EP 0 529 565 B1. An integrated circuit for providing a synapse is known from document US 2019164597 A1. A neural network can be implemented using conventional CMOS technology with a large number of transistors. A neural network can comprise ferroelectric field-effect transistors (FeFETs). The circuit according to the invention can be part of one of these neural networks. The invention is explained in more detail below with reference to figures. They show:

[0027] Figure 1 : Circuit with a CMOS inverter and a variable resistor;

[0028] Figure 2: CMOS inverter;

[0029] Figure 3: Design of the circuit from Figure 1;

[0030] Figure 4: Behavior of the output voltage compared to the input voltage of the

[0031] circuit from Figure 3;

[0032] Figure 5: Implementation of a variable resistor;

[0033] Figure 6: further implementation of a variable resistor;

[0034] Figure 7: Circuit for computer simulation;

[0035] Figure 8: Result of the computer simulation;

[0036] Figure 9: state-of-the-art analog CAM;

[0037] Figure 10: Current-voltage characteristic curve of the CAM from Figure 9;

[0038] Figure 11 : analog CAM;

[0039] Figure 12: analog and digital CAM;

[0040] Figure 13: Current-voltage characteristic of the CAM from Figure 12.

[0041] Figure 1 shows a circuit 1 with a CMOS inverter with an input j n and an output V out. The CMOS inverter comprises, as shown by circuit symbols in Figure 1, a p-channel MOSFET and an n-channel MOSFET. A potential Vss can be applied to the drain terminal D of the n-channel MOSFET of the CMOS inverter. A potential Vdd can be applied to the drain terminal D of the p-channel MOSFET of the CMOS inverter. The maximum possible gain by the CMOS inverter is determined by the potential difference between the potentials Vss and Vdd. In addition to the CMOS inverter, there is a variable resistor Rfb that connects the input Vj. n of the CMOS inverter with the output V ou t of the CMOS inverter. G denotes the gate terminals of the two MOSFETs in Figure 1. S denotes the source terminals of the two MOSFETs in Figure 1.

[0042] The resistor Rfb is variable because its conductance can be changed. There can be at least a first electrical conductance and a second electrical conductance. The resistor Rfb can then be switched so that it can optionally have the first electrical conductance or the second electrical conductance. It can be switched back and forth between the two conductances. One of the two conductances can correspond to the case in which there is no electrically conductive connection, i.e. it is a conventional CMOS inverter, as shown in Figure 2. Figure 3 shows a further embodiment of a circuit with the help of which a particularly flexible CAM can be created. In addition to the circuit 1 shown only schematically, this circuit has a transistor 2 and a memristor 3. The transistor 2 can be a MOSFET. A conductance can be set for the memristor 3.Transistor 2 and memristor 3 can be connected in series, as shown in Figure 3. Memristor 3 can be connected to the drain terminal of transistor 2, as shown in Figure 3. If a voltage VDL is applied to the gate terminal of transistor 2, transistor 2 acts as a voltage divider. The applied voltage VDL can be chosen so that after the application of voltage DL, a read voltage is applied to transistor 2. The read voltage can be less than 0.7 V. Memristor 3 then acts like a fixed resistor. The voltage thus applied at input Vj. n The voltage applied to circuit 1 depends on the conductance of memristor 3. Circuit 1 then outputs V ou t outputs a voltage that depends on the set conductance of the resistor Rfb. If the conductance Rfb is very high, for example, in the GQ range, then V out generally outputs a minimum voltage of, for example, 0 volts or a maximum voltage of, for example, 1 volt. This corresponds to a "0" or a "1" as information. If the conductance Rfb is not very high-impedance and amounts to, for example, a few 100 MΩ, a voltage can be output that lies between the minimum and maximum of the voltages available at the output V ou t can be output. This allows a measurement to be output as information that lies between "0" and "1" and can thus be viewed as analog information. It is therefore possible to use this circuit to create a CAM that can operate both as an aCAM and as a dCAM.

[0043] Figure 4 shows the behavior of the voltage at the output V ou t as a function of the voltage applied to the input VDL. If the resistance Rfb is very high, then the voltage applied to the output V ouThe output voltage changes from a minimum voltage value according to curve 4 to a maximum voltage value, thus outputting purely digital information as soon as the voltage applied to the VDL input exceeds a limit value VoL_bound. If the resistance Rfb is not very high, then medium voltage values ​​according to curve 5 are possible, thus outputting analog information at the Vout output of the CMOS inverter.

[0044] Figure 5 shows an implementation of a variable resistor Rfb that can be changed. The variable resistor Rfb comprises an ohmic resistor 6, which can have a conductance of several hundred megaohms. Using a transistor 7, the current flow through the ohmic resistor 6 can be enabled or interrupted. It can thus be switched between two different states. Figure 6 shows another implementation of a variable resistor. It is a circuit for implementing a controllable, high-ohmic MOS impedance. The operation of this high-ohmic CMOS circuit is explained in more detail in the paper "Armin Tajalli, Yusuf Leblebici, and Elizabeth Brauer. “Implementing Ultra-high-Value Floating Tunable CMOS Resistors”, Electronics Letters 44 (Feb. 2008). DOI: 10.1049 / el:20082538". By applying potentials V ssand Vdd, the resistor is switched. The resistance can be set such that it can be switched between a conductance in the range of, for example, 100 MQ to 500 MQ and a conductance of, for example, more than 1 GQ. These conductances occur between contacts 1 and 2. Contacts 1 and 2 are the terminals and “+”, which are shown in Figure 2 of the cited document.

[0045] The influence of the resistance Rfb was tested using a computer simulation. Figure 7 shows the circuit used for the computer simulation. The ohmic resistor R1 simulates memristor 3. The ohmic resistor R2 simulates the variable resistor Rfb. Figure 8 shows the result of the computer simulation. Two different values ​​for R1 were simulated for the conductance of memristor 3. The simulation showed that changing the conductance of memristor 3 shifts the family of curves along the Vdl axis from approximately 0.6 V to approximately 0.8 V. By adjusting the conductance of memristor 3, the limit value VDL-bound can be set, which determines when a jump from the information "0" to the information "1" is possible.

[0046] Four different conductances were simulated for the resistor Rfb: 5MQ, 10MQ, 23MQ, and 50MQ. The higher the conductance for Rfb, the more the curve resembled the curve of a conventional CMOS inverter with a sudden increase in the voltage at the output V ou t is output as soon as the applied voltage Vdl exceeds a limit. The conductance of the resistor Rfb can therefore be used to adjust how steep a jump from the information "0" to the information "1" is.

[0047] The conductance of memristor 3 shown in Figure 3 can be changed as follows. First, a high voltage can be applied to terminal VSL+AE of the memristor, which is selected to be high enough to reset the memristor. After resetting memristor 3, a voltage high enough to write to the memristor using a voltage applied to terminal VDL can be applied to transistor 2. Memristor 3 can be used to store information. The conductance of memristor 3 can be programmed. A programmed conductance of memristor 3 encodes a voltage and thereby stores information. Using a circuit according to the invention, it can be checked whether an applied voltage VDL corresponds to the encoded voltage. The mode of operation is described in the publication "Can Li et al. “Analog content-addressable memories with memristors” In: Nature Communications 11.1 (Apr. 2020). DOI: 10.1038 / s41467-020-15254-4". The resulting circuit is shown in Figure 9 of this document. This circuit is formed from six transistors and two memristors. The circuit shown in Figure 9 of this document compares an analog input signal with a stored range defined by an upper and a lower limit. The upper limit is determined by the conductance of one memristor. The lower limit is determined by the conductance of the other memristor. The circuit outputs whether or not a match has been found with the range. Figure 10 of this document shows an example result as a function of an applied input voltage VDL. A match, and thus a "1", is output when the current IML jumps from the value 0.34 pA to the value 0 pA.The fact that the falling edge deviates significantly from a vertical line makes it difficult to clearly distinguish between a match and a mismatch. This has a negative impact on storage density. The lack of symmetry between the rising and falling edges is also disadvantageous. To obtain a more favorable current-voltage characteristic curve, the paper "Jinane Bazzi et al. Efficient Analog CAM Design. 2022. DOI: 10.48550 / ARXIV.2203.02500. URL: https: / / arxiv.org / abs / 2203.02500" proposes a circuit that includes additional inverter stages. This circuit comprises ten transistors and two memristors. In this case, both the falling and rising edges are very steep. This enables high storage density.However, there is still an asymmetric relationship between the rising and falling edges.

[0048] Figure 11 shows a circuit with a further improved current-voltage characteristic. This circuit is an aCam and is an independent invention. The circuit comprises two memristors (8 and 9), two CMOS inverters (10 and 11), and four additional transistors (12, 13, 14, 15). The circuit thus comprises two memristors and eight transistors.

[0049] Section 17 of the circuit includes memristor 8, CMOS inverter 10, and the two transistors 12 and 13. This section 17 is identical to section 18, which includes memristor 9, CMOS inverter 11, and the two transistors 14 and 15. The circuit is further configured such that a voltage VDL LB can be applied as an input signal to section 17, and a voltage VDL HB to section 18.

[0050] The circuit may include an inverter 16 that inverts an applied input voltage VDL. A voltage VDL that is identical to the voltage DL LB may thus be applied to the first section 17. An inverted voltage V DL which is identical to the voltage VDL HB.

[0051] The inversion ensures that the second section 18 refers to the rising edge. The first section 17 refers to the falling edge. In Figure 11, this is expressed by the designations VDL LB and VDL HB, where "LB" denotes a "low bound" and HB an upper bound ("high bound"). The inversion also ensures that sections 17 and 18 can be identical. This not only simplifies the layout but also ensures that the rising and falling edges are symmetrical.

[0052] Inverter 16 may comprise a digital inverter. Inverter 16 may comprise an analog-to-digital converter that digitizes a voltage VDL. The digital signal may be inverted by the digital inverter. The inverted digital signal is then converted into an analog voltage by a digital-to-analog converter. Inverter 16 may be an analog inverter, such as an operational amplifier.

[0053] The provision of an inverter 16 is not absolutely necessary. It only matters that a voltage VDL LB can be applied to the first section 17 and a suitably inverted voltage VDL HB to the second section 18. For example, it is possible to control the circuit digitally as follows. A voltage VDL LB can be applied to the first section 17 using a digital signal. The digital signal can be used to control an analog-to-digital converter so that the analog-to-digital converter applies the voltage VDL LB to the first section 17. A voltage VDL HB can be applied to the second section 18 using a digital signal. The digital signal can be used to control an analog-to-digital converter so that the analog-to-digital converter applies the voltage VDL HB to the second section 18.It can be achieved that the voltage VDL HB SO is inverted compared to the voltage VDL LB, so that the first section 17 refers to the falling edge and the second section 18 to the rising edge.

[0054] The conductance of the first memristor 8 thus defines a lower limit for a stored range. The conductance of the second memristor 9 defines an upper limit for a stored range. The circuit can include a conductor ML ("match line"), via which the results of sections 17 and 18 can be output. Potentials VSL+OE and VSL+AE can be applied to sections 17 and 18 together via corresponding conductors for operation.

[0055] This independent invention makes it possible to achieve edges as steep as those achieved with the aCam described above, with its two memristors and ten transistors. However, the edges are now advantageously symmetrical. This could offer further advantages in applications. For example, it could lead to improved results in machine learning.

[0056] The circuit shown in Figure 11 is not a CAM, which can be operated not only as an aCAM, but also as a dCAM. To achieve this, the circuit shown in Figure 1 can be integrated into the circuit shown in Figure 11, for example. A circuit created in this way is shown in Figure 12.

[0057] Figure 13 shows current-voltage characteristics that can be achieved with the circuit shown in Figure 12, as a function of the resistance Rfß. It can be seen that symmetrical current-voltage characteristics can be obtained. The falling edge is symmetrical to the rising edge. With such current-voltage characteristics, the behavior of a dCAM can be achieved. If the resistance Rfß is sufficiently large, the circuit shown in Figure 12 behaves like the circuit shown in Figure 11, i.e., like an aCAM.

[0058] For example, the variable resistor RFB in the circuit shown in Figure 12 can be 800 Ω to allow the CAM to operate like an analog CAM. The variable resistor RFB can be 10 Ω or more to allow the CAM to operate like a digital CAM.

Claims

Claims 1. Circuit comprising a CMOS inverter (10, 11) and a variable resistor (Rfb), wherein the variable resistor (Rfb) controls the input (Vj n ) of the CMOS inverter (10, 11) with the output (V ou t) of the CMOS inverter (10, 11).

2. Circuit according to the preceding claim, characterized in that the input (Vj n ) of the CMOS inverter (10, 11) is electrically connected to a memristor (3, 8, 9).

3. Circuit according to one of the preceding claims, characterized in that the input (Vj n ) of the CMOS inverter (10, 11) is electrically connected to a transistor (2, 12, 14).

4. Circuit according to the two preceding claims, characterized in that the memristor (3, 8, 9) is electrically connected in series with the transistor (2, 12, 14).

5. Circuit according to one of the three preceding claims, characterized in that the transistor (2, 12, 14) is an NMOS transistor.

6. Circuit according to one of the preceding claims, characterized in that the electrical connection provided by the variable resistor (Rfb) can be interrupted by a switch.

7. Circuit according to the preceding claim, characterized in that the switch is a transistor (7).

8. Circuit according to one of the preceding claims, characterized in that the variable resistor (Rfb) is arranged so that it can be switched back and forth between a very high-impedance conductance and a comparatively low-impedance conductance.

9. Circuit according to the preceding claim, characterized in that the high-resistance conductance is more than 1 GQ or at least 10 GQ and the low-resistance conductance is less than 1 GQ or less than 500 MQ.

10. Circuit according to one of the preceding claims, characterized in that the circuit is part of a neural network. 11 . Circuit according to one of the preceding claims, characterized in that the circuit is part of a CAM.

12. Circuit according to the preceding claim, characterized in that the CAM comprises two CMOS inverters (12, 14), two memristors (8, 9) and four further transistors (12, 13, 14, 15).

13. Circuit according to one of the two preceding claims, characterized in that the cam comprises two identical sections (17, 18), each section comprising a circuit with the features of claim 4 and each section having its own input for an input voltage (VDL LB, VDL HB).

14. Circuit according to the preceding claim, characterized in that the input of one section (17) is connected to the input of the other section (18) via an inverter (16).

15. Circuit according to one of the two preceding claims, characterized in that the outputs of the two sections (17, 18) are connected to a common line (ML).

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