Method for operating a flying capacitor multilevel converter

Abstract

The invention relates to a method for operating a flying capacitor multilevel converter (1), comprising at least one half-bridge (HB1 to HB3), comprising an upper branch having multiple series-connected semiconductor switches (H1, H2, H(N-2), H(N-1)) and a lower branch having multiple series-connected semiconductor switches (L1, L2, L(N-2), L(N-1)), wherein the upper branch and the lower branch are connected to one another at a connecting point (VP) for the connection of a phase (P1, P2, P3), wherein pairs of one semiconductor switch (H1, H2, H(N-2), H(N-1), L1, L2, L(N-2), L(N-1)) from each of the upper and lower branch are bypassed by a respective capacitor (CFC1, CFC2, CFC(N- 2), CDC) or by a respective series circuit of capacitors (CFC1, CFC2, CFC(N-2), CDC) at the same distance from the connecting point (VP) at the terminals thereof that are turned away from the connecting point (VP), wherein the semiconductor switches (H1, H2, H(N-2), H(N-1), L1, L2, L(N-2), L(N-1)) are actuated using pulse-width-modulated signals at a switching frequency (f sw )), wherein the switching frequency (f sw ) is briefly increased in the event of overload.

Description

[0001]202302624 Fair copy 1 Description Method for operating a flying capacitor multilevel converter The invention relates to a method for operating a flying capacitor multilevel converter. Flying capacitor multilevel converters are known in the art. These have so-called flying capacitors, the required capacitance of which influences the power density and the cost of the converter. If the capacitance is selected to be too low, the voltage ripple across these capacitors increases, which also increases the voltage load on the semiconductor switches. Therefore, the reliability of the converter suffers from a capacitance that is selected to be too low and, consequently, an excessively high voltage ripple on a respective capacitor voltage across the flying capacitors.To dimension a reliable flying-capacitor multilevel converter, the capacitor capacitance must be designed so that their capacitor voltage varies only slightly during operation, i.e., exhibits a low voltage ripple. If this voltage ripple becomes too large, the reliability of the semiconductor switches suffers due to increased voltage stress. For this purpose, previously known solutions design a minimum required capacitor capacitance for the maximum possible current. KHAN WAQAR A ET AL: "An Optimized Phase Shifted PWM for Flying Capacitor Multilevel Converter", 2019 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), IEEE, September 29, 2019 (2019-09-29), pages 5104-5108, XP033666348, DOI: 10.1109 / ECCE.2019.8912530 describes a novel modulation method for reducing the voltage ripple of the flying capacitors (FC) in a flying capacitor multilevel converter (FCML).The method is based on the 202302624 clean copy 2 modification of the conventional phase-shifted PWM method (PSPWM). The proposed method reduces the required capacitance compared to conventional PSPWM while maintaining the same voltage ripple limitation. A phase-shifted PWM with variable frequency (VF-PSPWM) is proposed that varies the frequency of the carrier signal based on the magnitude of the load current. The reduced voltage ripple reduces the capacitance requirements in the design, thereby achieving designs with higher power density. The invention is based on the object of specifying a novel method for operating a flying capacitor multilevel converter. This object is achieved according to the invention by a method having the features of claim 1. Advantageous embodiments of the invention are the subject of the dependent claims.A flying capacitor multilevel converter has at least one half-bridge, comprising an upper branch with several semiconductor switches connected in series and a lower branch with several semiconductor switches connected in series, wherein the upper branch and the lower branch are connected to one another at a connection point for connecting a phase, wherein pairs of one semiconductor switch each from the upper and lower branches are bridged at the same distance from the connection point at their connections pointing away from the connection point with a capacitor each or with a series connection of capacitors each. In a method according to the invention for operating the flying capacitor multilevel converter, the semiconductor switches are controlled with pulse-width modulated signals at a switching frequency, wherein the switching frequency is briefly increased in the event of an overload.The duration of a short-term overload depends on the overload profile. Typical overload profiles range from milliseconds to seconds. By using the solution according to the invention, even high overload profiles can be implemented without having to oversize the converter. A significant advantage of the solution according to the invention is the possibility of reducing the required capacitor capacitance.This results in the following advantages, for example, when doubling the switching frequency for double overload: • halving the required capacitance, • halving the volume of the capacitors (if scalable, for example with MLCCs), • halving the cost of the capacitors, • halving the space requirement and therefore increasing the power density and lower probability of failure due to fewer components, • simple implementation (linear increase in the switching frequency with the power or with the actual value of the phase current from the normal operating point, for example nominal load), • if very short but high overload is required, this enables simple implementation without oversizing the converter, and • enabling very short but high overload profiles without oversizing the converter.According to the invention, a nominal switching frequency is used at a normal operating point, and in the event of an overload, the switching frequency is increased starting from the normal operating point, for example, linearly, since the switching frequency is included linearly in the calculation of the required capacitance of the flying capacitors. 202302624 Clean copy 4 In one embodiment, the normal operating point is or will be set to a nominal power, but could also be shifted to another location. According to the invention, the switching frequency remains or is maintained constant below the normal operating point.In one embodiment, all pairs of semiconductor switches from the upper and lower branches are bridged at the same distance from the connection point by a capacitor or a series connection of capacitors at their terminals pointing away from the connection point, wherein the two outermost semiconductor switches of all half-bridges are each connected at their terminals pointing away from the connection point to a DC link capacitor connected to ground or to a series connection of DC link capacitors connected to ground and are connected to a DC supply voltage. In one embodiment, the flying capacitor multilevel converter has at least three half-bridges for supplying three phases. According to the invention, the phases are each connected to an inductor and a filter module to ensure electromagnetic compatibility.In one embodiment, the semiconductor switches are designed as IGBTs or field-effect transistors, in particular MOSFETs or GaN HEMTs. The above-described properties, features, and advantages of this invention, as well as the manner in which they are achieved, will become clearer and more readily understood in connection with the following description of exemplary embodiments, which are explained in more detail in conjunction with the drawings.6 shows a schematic diagram of an exemplary power profile of a chassis. Corresponding parts are provided with the same reference numerals in the figures. Figure 1 is a schematic view of a typical design of a three-phase flying capacitor multilevel converter. The converter 1 has three half-bridges HB1, HB2, HB3, each of which supplies a phase P1, P2, P3 with an alternating voltage U.N,1 , U N,2 , U N,3 Each of the half-bridges HB1, HB2, HB3 has an upper branch and a lower branch, between which the respective phases P1, P2, P3 are connected. The phases P1, P2, P3 can each be supplied with an inductance L DM1 , L DM2 , L DM3 and a filter module F1, F2, F3 to ensure electromagnetic compatibility (EMC). 202302624 Clean copy 6 The upper branch has a number of series-connected upper semiconductor switches H1, H2, H (N-2) , H (N-1) and the lower branch has an equal number of series-connected lower semiconductor switches L1, L2, L (N-2) , L (N-1) The number shown in Figure 1 is merely an example. In other embodiments, a different number of semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1)The semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) are designed, for example, as IGBTs or field-effect transistors, in particular MOSFETs or GaN HEMTs. In the context of the present application, the term "inner terminal" refers to the terminal of a semiconductor switch H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) which faces a connection point VP of the respective half-bridge HB1, HB2, HB3, to which the respective phase P1, P2, P3 is connected. Accordingly, the term external terminal is used for the terminal of a semiconductor switch H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1)which is facing away from the connection point VP of the respective half-bridge HB1, HB2, HB3. The two innermost semiconductor switches H1, L1, i.e. those semiconductor switches H1, L1 of the upper branch and the lower branch, which are directly connected to each other and to the respective phase P1, P2, P3 with their inner terminals at the connection point VP, are connected to a capacitor C at their outer terminals. FC1 , a so-called flying capacitor. The two semiconductor switches H2, L2 of the upper branch and the lower branch, which are closest to the outside, i.e. away from the connection point VP, are also connected to a capacitor C at their outer terminals. FC2 , a so-called flying capacitor. Likewise, with the exception of the two outermost semiconductor switches H (N-1) , L (N-1)all pairs of semiconductor switches H located one step further out (N-2) , L (N-2) at their outer terminals also with a respective capacitor C FC(N-2) , a so-called flying capacitor. The two outermost semiconductor switches H (N-1) , L (N-1) All half-bridges HB1, HB2, HB3 are connected together at their outer terminals to a DC link capacitor C DC connected. The two DC link capacitors C DC are therefore connected in series and connected to a DC supply voltage U DC connected. The required capacity of the capacitors C FC1 , C FC2 , C FC(N-2)(Flying Capacitors) of the converter 1 defines the power density and the costs of the converter 1. If the capacity is chosen too low, the voltage ripple (also called voltage ripple) on these capacitors C FC1 , C FC2 , C FC(N-2) which also increases the voltage load on the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) increases. Therefore, the reliability of the converter 1 suffers from an insufficiently selected capacitance and consequently an excessively high voltage ripple on a respective capacitor voltage U FC1 , U FC2 , U FC(N-2) over the flying capacitors C FC1 , C FC2 , C FC(N-2) . In order to dimension a reliable flying capacitor multilevel converter 1, the capacitance of the capacitors C FC1 , C FC2 , C FC(N-2) be designed so that their capacitor voltage U FC1 , U FC2 , UFC(N-2) only slightly varies during operation, i.e. a low voltage ripple ∆ ^^ ி^,^^௫ If this voltage ripple ∆ ^^ ி^,^^௫ too large, the reliability of the semiconductor switches H1, H2, H (N-2) , H (N- 1) , L1, L2, L (N-2) , L (N-1) due to an increased voltage load. Previously known solutions require a minimum required capacity ^^ ி^,^^^ of the capacitor C FC1 , C FC2 , C FC(N-2) designed for the maximum possible current. This corresponds to the peak value in industrial applications. ^^ ^^,^^ an overload current according to equation (1). ^^ ி^ is in equation (1) a number of voltage levels and ^^ ௌ^a set switching frequency. According to the present invention, in order to reduce this capacitance (and to correspondingly reduce costs, number of components and volume), the switching frequency ^^ ௌ^ This results in increased losses at the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) However, since these losses only occur briefly, the advantage of reduced capacitance outweighs the disadvantages. However, the increased losses should be taken into account when dimensioning a heat sink for the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) be taken into account. Since the switching frequency ^^ ௌ^ linear in the calculation of the required capacity, it is advantageous to use the switching frequency ^^ ௌ^ linear from a selected normal operating point BP nThis is shown as an example in Figure 2. Figure 2 is a schematic diagram of the switching frequency ^^ ௌ^ depending on a standardized power P / Pn. The normal operating point BP n , from which the switching frequency ^^ ௌ^ is increased, in this example it is set to a nominal power Pn, but could also be moved to another location. Below the normal operating point BP n should the switching frequency ^^ ௌ^ cannot be further reduced due to the filter design, which is why the switching frequency ^^ ௌ^ in the example shown remains constant from this point onwards. 202302624 Fair copy 9 This does not necessarily result in a doubling of the losses at the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) Figure 3 shows an example of a loss distribution of the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L(N-2) , L (N-1) The losses V are shown as a function of the standardized power P / Pn. Curve K1 shows conduction losses, curve K2 shows switching losses, and curve K3 shows total losses at the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) . It can be seen that the switching losses normally increase linearly with the power P, while the conduction losses increase quadratically with the power P. If the switching frequency ^^ ௌ^ increases linearly, the switching losses also increase quadratically. This comparison of the changed switching losses SV is shown schematically in Figure 4. The switching losses SV are shown as a function of the standardized power P / Pn. Curve K4 shows the switching losses SV of the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1)without switching frequency adjustment. Curve K5 shows the switching losses SV of the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) with the switching frequency adjustment according to the invention, i.e. the linearly increasing switching frequency ^^ ௌ^ However, this increase is small for the total losses. Figure 5 is a schematic diagram of the total losses GV of the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) depending on the standardized power P / Pn. Curve K6 shows the total losses GV of the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) without switching frequency adjustment. Curve K7 shows the total losses GV of the semiconductor switches H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) with the switching frequency adjustment according to the invention, i.e. the linearly increasing switching frequency ^^ ௌ^As shown in the example, with a triple overload, the total losses GV will only increase by about 30%, whereby the capacitances of the capacitors 202302624 Clean copy 10 C FC1 , C FC2 , C FC(N-2) can be designed to be smaller by a factor of 3. Consequently, for this example, the cost and space requirements of the capacitors C FC1 , C FC2 , C FC(N-2) by a factor of 3. Such a solution is particularly advantageous because very short-term but very high overloads often occur in typical power profiles of positioning applications. Figure 6 is a schematic diagram of an exemplary power profile of a chassis, where the power P is plotted against time t. If the solution according to the invention is not used, the capacitors C FC1 , C FC2 , C FC(N-2)According to the prior art, they are always dimensioned for these high overload currents. By using the solution according to the invention, even very short overload profiles with a high overload can be realized without having to significantly oversize the converter 1. Although the invention has been illustrated and described in detail using preferred exemplary embodiments, the invention is not limited by the disclosed examples, and other variations can be derived therefrom by a person skilled in the art without departing from the scope of the invention. Regardless of the grammatical gender of a particular term, persons with male, female, or other gender identities are also included.

Claims

202302624 Fair copy 11 claims 1. Method for operating a flying capacitor multilevel converter (1), comprising at least one half-bridge (HB1 to HB3), comprising an upper branch with several series-connected semiconductor switches (H1, H2, H (N-2) , H (N-1) ) and a lower branch with several series-connected semiconductor switches (L1, L2, L (N-2) , L (N-1) ), wherein the upper branch and the lower branch are connected to each other at a connection point (VP) for connecting a phase (P1, P2, P3), wherein pairs each comprise a semiconductor switch (H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) ) from the upper and lower branches at the same distance from the connection point (VP) at their terminals pointing away from the connection point (VP) with a capacitor (C FC1 , C FC2 , C FC(N-2) , C DC ) or with a series connection of capacitors (C FC1 , CFC2 , C FC(N-2) , C DC ) are bridged, whereby the semiconductor switches (H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) ) with pulse width modulated signals with a switching frequency ( ^^ ௌ^ ), whereby the switching frequency ( ^^ ௌ^ ) is briefly increased in the event of an overload, whereby the phases (P1, P2, P3) are each connected to an inductance (L DM1 , L DM2 , L DM3 ), characterized in that the phases (P1, P2, P3) are each connected to a filter module (F1, F2, F3) to ensure electromagnetic compatibility, wherein at a normal operating point (BP n ) a nominal switching frequency ( ^^ ௌ^ ) is used and the switching frequency ( ^^ ௌ^ ) in case of overload starting from the normal operating point (BP n ) is increased, whereby the normal operating point (BP n) is or will be set to a rated power (Pn), whereby the switching frequency ( ^^ ௌ^ ) below the normal operating point (BP n ) remains constant or is maintained.

2. Method according to claim 1, wherein the normal operating point (BP n ) is or will be set to a nominal power (Pn).

3. Method according to one of the preceding claims, wherein all pairs each consist of a semiconductor switch (H1, H2, H (N-2) , 202302624 Fair copy 12 H (N-1) , L1, L2, L (N-2) , L (N-1) ) from the upper and lower branches at the same distance from the connection point (VP) at their terminals pointing away from the connection point (VP) with a capacitor (C FC1 , C FC2 , C FC(N-2) , C DC ) or with a series connection of capacitors (C FC1 , C FC2 , C FC(N-2) , C DC ) are bridged, with the two outermost semiconductor switches (H (N-1) , L(N-1) ) of all half-bridges (HB1, HB2, HB3) together at their terminals pointing away from the connection point (VP) with a DC link capacitor (C DC ) or a series connection of DC link capacitors (C DC ) and connected to a DC supply voltage (U DC ) are connected.

4. Method according to one of the preceding claims, wherein the flying capacitor multilevel converter (1) has at least three half-bridges (HB1, HB2, HB3) for supplying three phases (P1, P2, P3).

5. Method according to one of the preceding claims, wherein the semiconductor switches (H1, H2, H (N-2) , H (N-1) , L1, L2, L (N-2) , L (N-1) ) are designed as IGBTs or field-effect transistors, in particular MOSFETs.

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