Multistage analogue-to-digital converter

Abstract

The invention relates to an electronic device having a first memory (1, 7) for storing an analogue signal and a second memory (2, 8) for storing another analogue signal, and having an ADC that can digitize the one and the other analogue signal in alternating fashion. The invention furthermore relates to a method for digitizing an input signal by way of an electronic device, wherein a first input signal is digitized by a first ADC of the electronic device and at the same time a second input signal is digitized by a second ADC of the electronic device. The invention enables a high sampling rate.

Description

[0001] Multi-stage analog-to-digital converter

[0002] The invention relates to a multi-stage analog-to-digital converter. An analog-to-digital converter can convert an analog input signal into a digital output signal. An analog-to-digital converter is also called an analog-to-digital converter. ADC is used as an abbreviation for an analog-to-digital converter.

[0003] A multi-stage analog-to-digital converter converts an analog input signal into a digital output signal in several stages. In a first stage, the analog output signal is roughly quantized. Following the coarse quantization, a further quantization takes place in a second step, which improves the accuracy of the result of the first coarse quantization. To improve accuracy, the analog input signal must be available for comparison purposes during the second step. To ensure that the analog input signal is available during a second step, a sample-and-hold circuit or a track-and-hold circuit can be provided. A sample-and-hold circuit can briefly hold analog voltage values ​​at a defined value. A sample-and-hold circuit has a control input, a signal input, and a signal output.The control input switches between sample and hold phases. This determines whether the output signal follows the input signal (sample phase) or is held (hold phase). Alternatively, a track-and-hold circuit can be provided, which can also temporarily hold analog voltage values ​​at a defined value.

[0004] A multi-stage analog-to-digital converter may include more than two stages for digitization to improve accuracy and thus resolution.

[0005] A multi-stage analog-to-digital converter first roughly converts an analog input signal into a digital signal and then refines the result using at least one further stage to achieve higher resolution and accuracy.

[0006] If a time-dependent analog signal is to be digitized by a multi-stage analog-to-digital converter, it may be necessary to sample the time-dependent analog signal at specified intervals. A first sampled signal can be fed to the multi-stage analog-to-digital converter and digitized. Following the digitization of the first sampled signal, a second sampled signal can be fed to the multi-stage analog-to-digital converter and digitized. The time required by the multi-stage analog-to-digital converter for digitization limits the sampling rate.

[0007] The aim of the present invention is to be able to digitize a time-dependent analog signal using a multi-stage analog-to-digital converter with a high sampling rate.

[0008] This object can be achieved by an electronic device comprising the features of the first claim. A method comprises the features of the independent claim. The dependent claims relate to advantageous embodiments.

[0009] The electronic device may comprise a multi-stage analog-to-digital converter. The electronic device may comprise a first memory for a first sampled signal. The electronic device may comprise a second memory for a second sampled signal. The first sampled signal at a first time may be stored in the first memory. A later sampled second signal at a later second time may be stored in the second memory. The electronic device may be configured to quantize the second sampled signal by a first stage, while the accuracy of the result of the second sampled signal is improved by a second stage. Because two memories may be present, the first sampled signal for the first stage and the second sampled signal for the second stage can be held simultaneously.A second stage for a first sampled signal can therefore be performed in parallel with a first stage for a first sampled signal. Since the first and second stages can be performed in parallel, a high sampling rate is possible.

[0010] The multi-stage analog-to-digital converter may comprise a first converter with which an input voltage applied to the multi-stage analog-to-digital converter can be quantized. The analog-to-digital converter can form a residual value from the applied input voltage and the result of the quantization. The multi-stage analog-to-digital converter may comprise a second converter with which the residual value can be quantized. The multi-stage analog-to-digital converter can generate a binary result from the results of the two quantizations. The multi-stage analog-to-digital converter may be able to output a binary number as the result. The first converter and / or the second converter may be a flash ADC. A flash ADC may comprise several resistors connected in series as a voltage divider. A reference voltage can be applied to the series-connected resistors.

[0011] A first comparator can be connected to a first resistor of the series-connected resistors such that a first portion of the reference voltage, and thus a first comparison voltage, is applied to the first comparator. A second comparator can be connected to a second resistor such that a second portion of the reference voltage, and thus a second comparison voltage, is applied to the second comparator. In this way, a comparison voltage can be applied to each comparator of the flash ADC, with the comparison voltages being different.

[0012] If a permissible input voltage is applied to the flash ADC, each comparator compares this input voltage with the applied reference voltage. The first comparator compares the input voltage with the first reference voltage. The second comparator compares the input voltage with the second reference voltage, and so on.

[0013] If the input voltage is greater than a reference voltage, the corresponding comparator outputs a "high" signal, thus the digital value "1." If the input voltage is less than an applied reference voltage, the comparator outputs a "low" signal, thus the digital value "0."

[0014] A flash ADC can digitize an analog input signal very quickly. However, many comparators are required for high resolution. For example, a 3-bit ADC requires seven comparators. A 3-bit ADC can output a three-digit binary number as a result, and thus 2 3 or eight possible states. While a flash ADC can therefore digitize very quickly, the resolution of a flash ADC is limited to a few bits in practice due to the considerable technical complexity.

[0015] The first converter and / or the second converter can be a SAR-ADC. A SAR-ADC can compare a first reference voltage with an input voltage. For example, a maximum voltage Vmax of 10 volts can be applied to a SAR-ADC as an input signal. To determine the value for the highest bit, the so-called "most significant bit" (MSB), the first reference voltage within the SAR-ADC can be set to, for example, half the value of Vmax, i.e., 5 volts. A comparator of the SAR-ADC can then compare the first reference voltage of Vmax / 2, i.e., 5 volts, with the voltage to be digitized, which has therefore been applied to the SAR analog-to-digital converter as the input voltage.

[0016] If the comparator determines that the voltage or input voltage is higher than the first reference voltage, i.e., more than 5 volts in the example, a 1 is assigned to the highest bit, i.e., the MSB. A second reference voltage is also set, which can then be Vmax / 2 + Vmax / 4, i.e., 7.5 volts.

[0017] If the comparator detects that the voltage or input voltage is less than 5 volts, the MSB is set to 0. A second reference voltage is also set, which can be Vmax / 2 - Vmax / 4, i.e., 2.5 volts.

[0018] The input voltage is then compared with the second reference voltage by the comparator. The comparator outputs a value for the second bit based on the comparison: a "0" if the input voltage is lower than the second reference voltage, and a "1" if the input voltage is higher than the second reference voltage.

[0019] A third reference voltage can then be specified. For example, Vmax / 8 can be added to the second reference voltage if the comparator outputs a "1" as the second bit. The third reference voltage can then be equal to the second reference voltage + Vmax / 8. If the comparator outputs a "0" as the second bit, the third reference voltage can be equal to the second reference voltage - Vmax / 8.

[0020] The input voltage can then be compared with the third reference voltage by the comparator. Depending on the comparison, the comparator can output a value for a third bit: a "0" if the input voltage is lower than the third reference voltage, and a "1" if the input voltage is higher than the third reference voltage.

[0021] This can be continued until the value for the LSB, the lowest bit, has been determined. In the case of a 4-bit SAR ADC, four reference voltages can be determined in this way, and a "0" or "1" can be successively assigned to the total of four bits. This could result in a 1111 if 10 volts were applied to the ADC as the input voltage. This could result in a 0000 if 0 volts were applied to the ADC as the input voltage.

[0022] The SAR analog-to-digital converter can include a DAC, i.e. a digital-to-analog converter, which generates the required reference voltages.

[0023] Each ADC in a multi-stage analog-to-digital converter can have a low resolution. However, high resolution can still be achieved through multi-stage digitization.

[0024] A first ADC of a multi-stage analog-to-digital converter can quantify an input voltage applied to the multi-stage analog-to-digital converter with low resolution. For example, the input voltage can be 7.5 volts. Using the first ADC, a first digital result can be determined which corresponds to 5 volts, for example. The first digital result of the first ADC can be converted into an analog voltage by a first digital-to-analog converter, i.e. 5 volts in the example case. The voltage obtained by the first digital-to-analog converter can be subtracted from the then buffered input voltage in order to obtain a first residual value. In the example case, the first residual value is 7.5 volts - 5 volts and therefore 2.5 volts. The first residual value can be amplified in order to avoid disadvantages due to noise. The first residual value or the possible...The amplified first residual value can be quantified again with low resolution by a second ADC. Using the second ADC, a second digital result can be determined, corresponding, for example, to 3 volts. If this second digital result is added to the first digital result, the resulting value in this example is 8 volts. 8 volts can then be output, for example, in the form of a binary number.

[0025] A multi-stage analog-to-digital converter can include a third ADC to further improve resolution. The second digital result of the second ADC can then be converted into an analog voltage, in this example 3 volts, by a second digital-to-analog converter or by the first digital-to-analog converter. The voltage obtained by the second digital-to-analog converter can be subtracted from the first residual to obtain a second residual. In this example, the second residual is 2.5 volts minus 3 volts, or -0.5 volts. The second residual can optionally be amplified to avoid disadvantages due to noise. The possibly amplified second residual can be quantified again with low resolution by a third ADC. Using the third ADC, a third digital result can be determined, corresponding to, for example, -0.4 volts.If a sum of the digitized results is formed, the result in the example case is a value of 7.6 volts or a corresponding binary number.

[0026] With little construction effort, a high resolution can be achieved using such a multi-stage analog-to-digital converter.

[0027] The first and second memories can alternately transmit a stored analog input signal to a second ADC for digitizing a residual signal, wherein the residual signal is formed from the transmitted analog input signal and the result of the digitized signal.

[0028] The memories for storing analog signals may include one or more damping capacitors.

[0029] Capacitors of different capacitances may be present. Damping capacitors, which are used to store analog input signals, may have the largest capacitance.

[0030] Each memory for storing an analog signal can be electrically connected to an input terminal for an input signal via two switches.

[0031] A second ADC may be present. Each memory for storing an analog signal can be electrically connected to each ADC via a switch.

[0032] An ADC may be present which includes bit capacitors and a comparator (13).

[0033] There can be at least one bit capacitor that has half the capacitance of another bit capacitor.

[0034] There may be at least one bit capacitor with the same capacitance as a damping capacitor used to store an analog signal. There may be an ADC comprising a voltage divider with resistors and comparators.

[0035] Each ADC may include a reference voltage terminal for a reference voltage.

[0036] There can be two input terminals for an input signal and for an inverted input signal.

[0037] There may be a common-mode voltage terminal that is electrically connectable via switches to the first memory for storing an analog signal and to the second memory for storing another analog signal and / or via switches to bit capacitors of an ADC.

[0038] There may be a ground connection that can be electrically connected to bit capacitors of an ADC via switches.

[0039] An ADC may include a capacitor for binary weighting.

[0040] A capacitor for binary weighting can be connected to a comparator and to a common-mode voltage terminal.

[0041] The invention relates to a method for digitizing an input signal with an electronic device, wherein a first input signal is digitized by a first ADC and simultaneously a second input signal is digitized by a second ADC.

[0042] An input signal can be applied to one input terminal of the electronic device and an inverted input signal can be applied to another input terminal of the electronic device in order to digitize a signal.

[0043] The invention is explained in more detail below with reference to figures.

[0044] Figure 1 : SAR-ADC with integrated sample-and-hold circuit;

[0045] Figure 2: Flash ADC.

[0046] Figure 1 illustrates an embodiment of the invention, which may include capacitors 1 to 12, a comparator 13, and switches 14 to 33. Each capacitor 1 to 12 has two terminals. Comparator 13 has a first + terminal and a second - terminal as input. Comparator 13 has an output via which a comparison result can be output. Switches 14 to 33 can be implemented as transistors. Figure 1 shows a SAR-ADC with an integrated sample-and-hold circuit and a capacitive DAC. The sample-and-hold circuit is configured to alternately store and output input voltages.

[0047] An input voltage can be applied to the input with terminals V in ,p, V in , nbe applied or be applied. Capacitors are charged by closing the two input switches 23 and 26. The comparator 13 then determines bits in stages by comparing the applied input voltage or residual voltage with an associated, respectively determined reference voltage.

[0048] A first connection V in,p is electrically connected to the first input switch 23. Capacitor 1 is electrically connected to the first input switch 23 via a switch 24. The switch 24 is open. Therefore, capacitor 1 is not charged when the first input switch 23 is closed. Capacitor 2 is electrically connected to the first input switch 23 via a switch 25. The switch 25 is closed. Therefore, capacitor 2 is charged when the first input switch 23 is closed. Capacitors 3, 4, 5 are connected to the first input switch 23. Therefore, capacitors 3, 4, 5 are charged when the first input switch 23 is closed.

[0049] The two capacitors 1 and 2 serve to temporarily store applied input voltages, which are therefore called damping capacitors. Therefore, the capacitance of the two damping capacitors 1 and 2 is maximally large and amounts to, for example, 4C. Each damping capacitor 1, 2 is connected via a switch 15, 16 to a first terminal R es , P an output. Using the first terminal R es , P At the output, an input voltage temporarily stored in the damping capacitor 1, 2 can be alternately applied to another ADC. The additional ADC can be, for example, a flash ADC, a second SAR ADC, or a delta-sigma ADC.

[0050] In the case of Figure 1, switch 15 is closed. Therefore, a stored input voltage can be applied to another ADC using the first damping capacitor 1. In the case of Figure 1, switch 16 is open. Therefore, a stored input voltage cannot be applied to another ADC using the second damping capacitor 2. Capacitors 3, 4, and 5 are required to determine bits incrementally. Capacitors 3, 4, and 5 are therefore called bit capacitors. Each bit capacitor 3, 4, and 5 is electrically connected to one of the + terminals of comparator 13.

[0051] The electrical connections are implemented via conductive tracks. A first conductive track may be provided, as shown in Figure 1, connecting the input switch 23 to one positive terminal of the comparator 13. A first terminal of each damping capacitor 1, 2 may be electrically connected to the first conductive track via a switch 24, 25, as shown in Figure 1. A first terminal of each bit capacitor 3, 4, 5 may be electrically connected to the first conductive track, as shown in Figure 1.

[0052] A first bit capacitor 3 can also have the maximum capacitance 4C in order to be able to determine the MSB, i.e. the most significant bit. A second bit capacitor 4 can have a lower capacitance in order to be able to determine a second bit. The capacitance of this second bit capacitor 4 is expediently half the capacitance of the first bit capacitor 3 and can therefore be 2C. If a third bit is to be determined, a third bit capacitor 5 with a further reduced capacitance is present. The capacitance of this third bit capacitor 5 is expediently half the capacitance of the second bit capacitor 4 and can therefore be 1C. If higher resolution is required, a further bit capacitor with a further reduced capacitance can be present for each additional bit.

[0053] For the second connection V in , nof the input, there can be a parallel setup. Parallel to the damping capacitors 1 and 2, there can be two further damping capacitors 7 and 8, which are connected to the input terminal V in , n via switches 27, 28 and a shared second input switch 26. The additional damping capacitors 7 and 8 can have the same capacitance of, for example, 4C as the damping capacitors 1 and 2. If an input voltage is applied and the second input switch 26 is closed, then in the case of Figure 1, only the second damping capacitor 8 is charged because the switch 28 is closed and the switch 27 is open. The additional damping capacitors 7 and 8 can also be connected in the same way as previously described to a second terminal R es,n of the output in order to be able to alternately pass a stored input signal to the aforementioned further ADC. In addition, there can be further bit capacitors 9, 10, 11 in parallel with the bit capacitors 3, 4, 5, which can be charged by closing the input switch 26. The further bit capacitors 9, 10, 11 can also be connected by their respective first terminal to the other terminal of the comparator 13. The capacitance of further bit capacitors 9, 10, 11 can match the capacitance of the previously mentioned bit capacitors 3, 4, 5. The capacitance of the bit capacitor 9 responsible for determining the MSB can be, for example, 4C, in line with bit capacitor 3. The capacitance of the bit capacitor 10 responsible for determining the second bit can be, for example, 2C, in line with bit capacitor 4.The capacitance of a bit capacitor 11 responsible for determining a third bit can be, for example, in accordance with the bit capacitor 5 1C.

[0054] A pair of capacitors can therefore be used to determine one bit. The capacitance of a pair can decrease further for each additional bit, for example, by halving it.

[0055] A second terminal of each bit capacitor 3, 4, 5, 9, 10, 11 can be optionally connected to a reference voltage terminal V via an associated switch 18, 19, 20, 31, 32, 33 re f for a reference voltage, a common mode voltage terminal V cm for a common-mode voltage or a GND terminal for ground. The terminals of each damping capacitor 1 , 2, 7, 8 can be connected to common-mode voltage terminals V via switches 21 , 22, 14, 17, 29, 30, 34, 37 cmfor the common-mode voltage. The common-mode voltage can be smaller than the reference voltage. For example, the common-mode voltage can be half the reference voltage. For example, if the reference voltage is 5 V, the common-mode voltage can be 2.5 V.

[0056] For example, a maximum possible input voltage can be twice the reference voltage. This is especially true in a differential approach with an inverted input signal. If the reference voltage is 5 V, for example, the maximum possible input voltage can be 10 V. A maximum possible input voltage can, for example, be as large as the reference voltage. This is especially true in a non-differential approach without an inverted input signal.

[0057] There may be a capacitor 6 which is connected on the one hand via its first terminal to a first common-mode voltage terminal Vcm and on the other hand, is connected via its second terminal to the first + terminal of the comparator 13. In parallel, a capacitor 12 may be present, which is connected via its first terminal to a second common-mode voltage terminal V cm and, on the other hand, is connected via its second terminal to the second terminal of comparator 13. The capacitance of the two capacitors 6 and 12 can be small. The capacitance of the two capacitors 6 and 12 can match the capacitance of capacitors 5 and 11, which are used to determine the LSB. The capacitance of the two capacitors 6 and 12 can be, for example, 1 C.

[0058] The parallel configuration described in Figure 1 advantageously allows for working with voltages ranging from a negative value to a positive value. This allows a signal of, for example, 10 V to be applied in inverted form to improve the digitization result. At the input terminal V in ,p can then be applied with 10 V. At the input terminal V in , n -10 V can then be applied. An input voltage twice the signal voltage is then processed. This allows, among other things, interference to be better avoided. Detection is also improved.

[0059] In such a parallel setup, the common-mode voltage serves as a virtual ground.

[0060] The parallel configuration described in Figure 1 serves only to improve results. Therefore, the parallel configuration is not necessary to implement a SAR ADC with a sample-and-hold circuit that can alternately store and output input voltages. In a non-parallel configuration, a common-mode voltage is of no use and is therefore not provided.

[0061] A first signal can be detected as follows: Starting from the state of switches 14 to 33 shown in Figure 1, the voltage of the signal in the amount of x volts is applied to the input terminal V in ,p. The signal is also inverted. The inverted voltage is applied to the input terminal V in , napplied, i.e., -x volts. Input switches 23 and 26 are closed. The system waits until the corresponding capacitors 2 to 5 or 2 to 6 and 8 to 11 or 8 to 12 have charged. Once capacitors 2 to 5 or 6 and 8 to 11 or 12 have charged, input switches 23 and 26 are opened.

[0062] After opening, the applied input voltage is processed. In a first step, a direct check is carried out to determine whether the voltage, V in ,p, which is applied to the + terminal of the comparator 13, is greater than the voltage, V in , n, which is present at the - terminal of comparator 13. Assuming this is the case, the comparator outputs the signal "high." The first bit, i.e., the MSB, is therefore a "1." If the voltage then present at the + terminal of comparator 13 is lower than the voltage present at the - terminal of comparator 13, the comparator outputs the signal "low." The first bit, i.e., the MSB, is then a "0."

[0063] If the first bit is a "1", then switch 18, which is assigned to one capacitor 3 with, for example, a capacitance of 4C, is connected to ground, i.e., to the GND terminal. Switch 31, which is assigned to the other capacitor 9, is connected to the reference voltage terminal V re f and thus to the reference voltage. If the first bit is "0", then switch 18 is connected to the reference voltage terminal V ref. Switch 31 is connected to ground. After the second bit is detected, switches 18 and 31 remain in their respective assumed positions until the end of the conversion.

[0064] If another pair of capacitors 4, 10 is present, the process continues accordingly. If the second bit is a "1," then switch 19, which is assigned to one capacitor 4 with, for example, half the capacitance 2C, is connected to ground, i.e., to the GND terminal. Switch 32, which is assigned to the other capacitor 10, is connected to the reference voltage terminal V re f and thus to the reference voltage. If the second bit is "0", then switch 19 is connected to the reference voltage terminal V ref. Switch 32 is connected to ground. The third bit is then determined. After the third bit is determined, switches 19 and 32 remain in their respective assumed positions until the end of the conversion.

[0065] If another pair of capacitors 5, 11 is present, the process continues accordingly. If the second bit is a "1", then switch 20, which is assigned to one capacitor 5 with, for example, a further halved capacitance of 1 C, is connected to ground, i.e., to the GND terminal for ground. Switch 33, which is assigned to the other capacitor 11, is connected to the reference voltage terminal Vref and thus to the reference voltage. If the third bit is a "0", then switch 20 is connected to the reference voltage terminal V ref. Switch 33 is connected to ground. The fourth bit is then determined. After the third bit is determined, switches 19 and 32 remain in their respective assumed positions until the end of the conversion.

[0066] After the end of the conversion, the switches 18,19, 20, 31, 32, 33 are returned to their initial position, i.e. electrically connected to the common mode voltage terminal V cm , brought.

[0067] The two capacitors 6 and 12 may be present for binary weighting purposes. If the sum of the capacitances of the upper bit capacitors 3, 4, and 5 is 7C, then the upper capacitor 6 expediently has a capacitance of 1C to achieve a total capacitance of 8C. The test range can then be halved from bit capacitor to bit capacitor.

[0068] If the next signal is to be digitized, the switches for the damping capacitors 1, 2, 7, 8 are switched so that the first pair, i.e. the damping capacitors 1, 7, can now be charged. The switches 14, 16, 22, 24, 27, 30, 34 and 36 are closed. The switches 15, 17, 21, 25, 28, 29, 35 and 37 are opened. Following this, the already digitized signal, which is stored by the damping capacitors 2 and 8, can be improved by another ADC, since the second terminals of the two second damping capacitors 2 and 8 are connected to the terminals R by closing the switches 16, 36. es , P and R es ,n are electrically connected and the second terminals of the first two damping capacitors 1 and 7 are separated from the terminals R by opening the switches 15, 35 es , P and R es,n have been electrically separated. If the input switches (23, 26) are now closed, a next signal can be digitized without having to wait for the complete digitization by, for example, the multi-stage analog-to-digital converter of the previous first signal.

[0069] An example of another ADC is shown in Figure 2. It is a flash ADC. The flash ADC includes a voltage divider formed by resistors 38. The voltage divider divides a voltage applied to a reference voltage terminal V re f applied reference voltage. Comparators 39 compare the voltage of an input signal V in with the voltages provided by the voltage divider to digitize the input signal.

Claims

Claims 1. Electronic device comprising a first memory (1, 7) for storing an analog signal and a second memory (2, 8) for storing another analog signal and an ADC capable of alternately digitizing one and the other analog signal.

2. Electronic device according to the preceding claim, characterized in that the first and the second memory (1, 7; 2, 8) can alternately transmit a stored analog input signal to a second ADC for the digitization of a residual signal, wherein the residual signal is formed from the transmitted analog input signal and the result of the digitized signal.

3. Electronic device according to one of the preceding claims, characterized in that the memories for storing analog signals comprise one or more damping capacitors (1, 2, 7, 8).

4. Electronic device according to the preceding claim, characterized in that capacitors (1 to 12) with different capacitances (4C, 2C, 1C) are present and the damping capacitors (1, 2, 7, 8) have the largest capacitance (4C).

5. Electronic device according to one of the preceding claims, characterized in that each memory (1, 7; 2, 8) for storing an analog signal via two switches (23, 24, 25, 27, 28) with an input terminal (V in , p , V in , n ) for an input signal.

6. Electronic device according to one of the preceding claims, characterized in that a second ADC is present and each memory (1, 7; 2, 8) for storing an analog signal is electrically connectable to each ADC via a switch (15, 16, 24, 25, 27, 28, 35, 36).

7. Electronic device according to one of the preceding claims, characterized in that an ADC is present which comprises bit capacitors (3, 4, 5, 9, 10, 11) and a comparator (13).

8. Electronic device according to the preceding claim, characterized in that there is at least one bit capacitor (4, 10) which has half the capacitance of another bit capacitor (3, 9).

9. Electronic device according to one of the two preceding claims, characterized in that there is at least one bit capacitor (3, 9) which has the same capacitance as a damping capacitor (1, 2, 7, 8) provided for storing an analog signal.

10. Electronic device according to one of the preceding claims, characterized in that an ADC is present which comprises a voltage divider with resistors (38) and comparators (39). 11 . Electronic device according to one of the preceding claims, characterized in that each ADC has a reference voltage terminal (V re f) for a reference voltage.

12. Electronic device according to one of the preceding claims, characterized in that two input terminals (V in ,p, V in , n ) for an input signal and for an inverted input signal.

13. Electronic device according to one of the preceding claims, characterized in that a common-mode voltage terminal (V cm ) is present, which can be electrically connected via switches (14, 17, 21, 22, 29, 30, 34, 37) to the first memory (1, 7) for storing an analog signal and to the second memory (2, 8) for storing another analog signal and / or via switches (18, 19, 20, 31, 32, 33) to bit capacitors (4, 5, 6, 9, 10, 11) of an ADC.

14. Electronic device according to one of the preceding claims, characterized in that a connection (GND) for earth is provided, which can be electrically connected via switches (18, 19, 20, 31, 32, 33) to bit capacitors (4, 5, 6, 9, 10, 11) of an ADC.

15. Electronic device according to one of the preceding claims, characterized in that an ADC comprises a capacitor (6, 12) for binary weighting.

16. Electronic device according to the preceding claim, characterized in that the capacitor (6, 12) for binary weighting is connected on the one hand to a comparator (13) and on the other hand to a common-mode voltage terminal (V cm ) is connected.

17. Method for digitizing an input signal with an electronic Device according to one of the preceding claims, characterized in that a first input signal is digitized by a first ADC and at the same time a second input signal is digitized by a second ADC.

18. Method according to the preceding claim, characterized in that an input terminal (V in , p ) an input signal and to another input terminal (V in ,n) the inverted input signal is applied.

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