Method and electronic device having operating phases of different length

Abstract

The invention relates to a method for operating an electronic device having operating phases of different length, characterized in that the shorter operating phase is stopped and the longer operating phase is started in a manner controlled by a clock frequency, and in that the end of the longer operating phase is detected and the shorter operating phase is started when the end of the longer operating phase has been detected. The invention relates to an electronic device for carrying out the method. Very rapid operation can thus be achieved by simple technical means.

Description

[0001] Process and electronic device with different operating phases

[0002] The invention relates to a method for operating an electronic device with operating phases of varying lengths. The invention relates to an electronic device for implementing the method.

[0003] An electronic device's electronic circuit may require a reference clock for its operation. For high-precision circuits, the reference clock, whose signal is a square wave, must be generated from a sine wave, as only a sine wave source meets the high requirements. However, this also means that the edges of the square wave are evenly spaced.

[0004] There are electronic devices with such circuits that go through operating phases of varying lengths during operation. If the operating phases of a circuit are to be started by a reference clock, uniform intervals with a reference clock result in time losses that could be avoided with better-adapted clocking. Such a circuit is referred to below as a circuit with operating phases of varying lengths. An electronic device with such a circuit is therefore an electronic device with operating phases of varying lengths.

[0005] An example of a circuit with operating phases of varying lengths is an analog-to-digital converter, which, in a first operating phase, loads an analog signal to be analyzed into a buffer for further processing and, in a second operating phase, converts the analog signal into a digital signal. The second operating phase—i.e., converting an analog signal into a digital signal—can take longer than the first operating phase—i.e., loading the signal into a buffer. If the two operating phases are started one after the other with a reference clock in which the time interval between two signals corresponds to the time length of the second operating phase, then an unnecessarily long time is spent on the first operating phase.

[0006] The invention is intended to enable an electronic device with operating phases of varying lengths to be operated quickly.

[0007] The problem can be solved by a method for operating an electronic device with operating phases of varying lengths. A clock frequency is used to stop the shorter operating phase and start the longer operating phase. The end of the longer operating phase is detected. The shorter operating phase is started when the end of the longer operating phase has been detected.

[0008] The problem can be solved by an electronic device with a circuit having operating phases of different lengths. A first operating phase therefore lasts shorter than a second operating phase. The electronic device can comprise a reference clock circuit with which a reference clock can be generated. The circuit can comprise at least one switch with which an operating phase of the circuit can be started and / or stopped. The electronic device can be set up such that an operating phase can be stopped by a phase switch under control of the clock frequency. The electronic device can be set up such that the shorter operating phase can be stopped by a phase switch under control of the clock frequency. The shorter operating phase is then stopped by the phase switch in cycles, i.e. at predetermined time intervals.The electronic device can be set up so that an operating phase can be started by a phase switch under control of the clock frequency. The electronic device can be set up so that the longer operating phase can be started by a phase switch under control of the clock frequency. The longer operating phase is then started in cycles by a phase switch. The electronic device can be set up so that the end of an operating phase can be detected. The electronic device can be set up so that the end of the longer operating phase can be detected. This can be the operating phase that can be started by a phase switch under control of the reference clock. The electronic device can be set up so that an operating phase is started by a phase switch when the end of the other operating phase is detected.The electronic device can be configured so that a phase switch starts an operating phase when the end of another operating phase is detected. The electronic device can be configured so that a phase switch starts the shorter operating phase when the end of the longer operating phase is detected.

[0009] This allows one operating phase to be started immediately, independent of a clock signal, as soon as another operating phase has ended. This allows one operating phase, for example a longer one, to be started immediately as soon as the other, for example a shorter one, has ended. Delays that can occur with operating phases of different lengths for the reasons mentioned above can be avoided with little technical effort.

[0010] In one embodiment of the invention, a time interval between two signals of the reference clock is shorter than the duration of the longer operating phase. If the longer operating phase lasts 2 ms, for example, then the time interval between two signals of the reference signal is less than 2 ms. This makes it possible to achieve an improved time saving. A time interval between two signals can be the time interval between two rising edges of two consecutive signals. It is therefore possible to determine how large the time interval is between two consecutive rising edges in order to determine the time interval. However, it is also possible for the time interval between two signals to be a rising edge followed by a falling edge. One signal is then a rising edge and the other signal is the falling edge.

[0011] In one embodiment of the invention, the time interval between two signals of the reference clock is longer than the duration of the shorter operating phase. For example, if the shorter operating phase lasts 1 ms, the time interval between two signals of the reference signal is greater than 1 ms. This allows for improved time savings.

[0012] In one embodiment of the invention, the electronic device comprises a first circuit with which an analog voltage can be sampled and a sampled analog voltage can be held.

[0013] The first circuit may have a signal input to which an analog voltage can be applied. An analog voltage applied to the signal input is called an input voltage. The first circuit may sample an input voltage during a sampling phase. Following the sampling phase, the first circuit may hold the sampled input voltage during a holding phase, i.e., store it for at least a short time. The circuit may have a signal output. A voltage that can be output via the signal output is called an output voltage. A sampled input voltage held by the first circuit can be read out via the signal output. The first circuit may include a capacitor by which a sampled analog voltage can be held. The circuit may include more than one capacitor by which a sampled analog voltage can be held.The capacitance of two capacitors used to hold a sampled analog voltage can differ. The capacitance of one capacitor can be half that of the other. The signal input can be connected to a switch to initiate a sampling phase. The switch can be a transistor.

[0014] The sampling and hold phases are fundamentally different. Typically, the hold phase is longer than the sampling phase.

[0015] The first circuit may have a control input that can be used to switch between the sampling phase and the holding phase. The first circuit may have an electronic switch that can be used to switch between the sampling phase and the holding phase. The electronic switch may be a transistor. A gate terminal or a base terminal of a transistor may then be the control input.

[0016] The first circuit may include a capacitor for storing an input voltage. The capacitor may be charged by the input voltage. The sampling phase may end as soon as the capacitor has been charged to the desired level by the input voltage. The sampling phase may end as soon as the input voltage is equal to the output voltage.

[0017] The first circuit can be configured to maintain the value of the input voltage at the moment of switching from the sampling phase to the holding phase during the hold phase. The first circuit can be configured to maintain the arithmetic mean of the input voltage during the measurement interval, thus storing it for a short time.

[0018] The first circuit may include an impedance converter through which the capacitor can be charged. The impedance converter can prevent excessive loading of a voltage source and thus a falsified measurement result.

[0019] The first circuit may include a voltage follower, which may be connected downstream of the capacitor. The downstream voltage follower may help maintain a held voltage at the signal output for as long as possible. The first circuit may be configured such that the output voltage follows the input voltage with a time delay during the sampling phase. During the holding phase, the output voltage may correspond to the value of the input voltage at the end of the sampling phase.

[0020] The first circuit can be designed as a sample-and-hold circuit or as a track-and-hold circuit or can comprise such a circuit. In both designs, there can be a reference clock circuit which generates a reference clock during operation. The sampling and / or holding can be controlled by the reference clock. If the first circuit is designed as a track-and-hold circuit, for example, then a rising edge of the reference clock signal can be used to switch from the hold phase to the sampling phase, or vice versa. A falling edge can be used to switch from the sampling phase to the hold phase, or vice versa. Switching can also only occur on a rising or only on a falling edge. For example, switching from the sampling phase to the hold phase is only possible on a rising edge. The switching can, for example, end the sampling phase and start the hold phase.

[0021] The sampling phase can be the first operating phase. The sampling phase can then be started by a phase switch when the end of the second operating phase is detected. The phase switch can be an electronic switch of the first circuit.

[0022] In one embodiment, the first circuit comprises a device for converting a held input signal into a digital signal. The device for converting a held input signal into a digital signal may comprise a comparator that can compare a voltage with a reference voltage and output a result of the comparison. This operating phase, during which a held voltage is converted into a digital signal, is called a conversion phase. Such a conversion phase may be an operating phase. Such a conversion phase may be the longer operating phase.

[0023] The electronic device may include an analog-to-digital converter (ADC for short). The analog-to-digital converter may include an ADC input. The analog-to-digital converter may include an ADC output. The analog-to-digital converter may convert an input signal applied to its ADC input into a digital output signal. The digital output signal may be output via its ADC output. The time required by the analog-to-digital converter for conversion is called the conversion phase. The conversion phase may be the second phase of operation. Controlled by a clock frequency, the conversion phase is then started by a phase switch. As soon as all bits of the digital output signal have been output via the ADC output, the first phase of operation is started.

[0024] The analog-to-digital converter can be a SAR ADC or a delta-sigma ADC.

[0025] The input signal for the analog-to-digital converter can be an output signal of the first circuit.

[0026] The circuit may include a flip-flop. The flip-flop may be a clock-edge-triggered D flip-flop.

[0027] A flip-flop is an electronic circuit with inputs and outputs for input signals and output signals. The state of an output signal depends on the input signals. Furthermore, the state of an output signal can depend on the state of a previous output signal. For example, an RS flip-flop has two inputs called "R" and "S." "R" stands for "reset," and "S" for "set." The RS flip-flop also has two outputs called "Q" and "Q."

[0028] If a "high" signal is applied to the set input S and a "low" signal is applied to the reset input R of an RS flip-flop, the Q output is set and thus assumes the "set" state. If a "low" signal is applied to the set input S and a "high" signal to the reset input R, the Q output is reset. If a "low" signal is applied to both inputs, the state of the Q output remains unchanged. Applying a "high" signal to both inputs is prohibited.

[0029] The output Q is an inverted output to the output Q, which assumes the opposite state of the output Q.

[0030] Signals in an RS flip-flop can be pulse-shaped. This means that the state of an output does not change when a pulse-shaped signal ends. The state of an output in an RS flip-flop can therefore only be changed by applying another signal. There are flip-flops that are controlled by a reference clock. Such a flip-flop can comprise an RS flip-flop in which the input S is connected to the input R via an inverter to provide a data input D. The inverter prevents the inputs S and R from being at the same logic level. This means that the same "low" or "high" signal cannot be present at both inputs R and S at the same time.

[0031] Such a flip-flop includes a second reference clock input, called "C." "D" stands for "data." "C" stands for "clock."

[0032] A flip-flop controlled by a reference clock can respond either only to the rising edge of an applied reference clock or only to the falling edge. If a reference clock is applied to the reference clock input C for operation, the state of an output Q only changes when either a rising edge of an applied reference clock or a falling edge occurs at input C. If such a flip-flop responds, for example, to a rising edge of a reference clock, the state of the output Q is set upon the occurrence of a rising edge if the signal "high" is present at the data input D, and thus a "high" at the set input R and a "low" at the reset input. The state of the output Q can no longer change until the next rising edge occurs.If the next rising edge occurs and a "low" signal is then present at the data input D, the output state is reset because the "low" signal is then present at the set input and the "high" signal is present at the reset input R. Otherwise, the state of the output Q remains set. Such a flip-flop is also called a clock-edge-triggered D flip-flop.

[0033] By using such a flip-flop, it is possible to ensure that an analog-to-digital converter controlled by a clock signal only responds to an edge of the clock signal. This is preferably used to start the hold phase. During the hold phase, the held analog signal is converted to a digital signal.

[0034] Following the conversion, an analog-to-digital converter can independently generate a signal that marks the completion of the conversion. The independently generated signal can then start the sampling phase. This allows the analog-to-digital converter to independently adjust the ratio of the edges locally. The invention is explained in more detail below with reference to the figures. They show:

[0035] Figure 1 : Electronic device;

[0036] Fig. 2: Circuit.

[0037] Figure 1 outlines the principle of the invention using the example of an analog-to-digital converter with an integrated track-and-hold circuit. A reference clock circuit is connected to an input of a flip-flop 2. The flip-flop is connected to a switch 4 via a line 3. The switch 4 can connect a signal generator 5 to an analog-to-digital converter 6. The analog-to-digital converter 6 comprises a memory 7 and a converter 8. The flip-flop is connected via a line 9 to an interface of the analog-to-digital converter 6, which interface starts a conversion of an analog signal stored in the memory 7 in the analog-to-digital converter. An output of the analog-to-digital converter 6 is connected via a line 10 to a reset interface of the flip-flop 2, via which the flip-flop 2 can be reset.

[0038] Flip-flop 2 only changes its state at the output on a rising edge. If the flip-flop changes its output state due to a rising edge of the reference clock generated by the reference clock circuit, the flip-flop outputs a signal via its output that opens switch 4 and starts the conversion of the analog signal stored in memory 7 into a digital signal by converter 8. Once the conversion is complete and a digital number with bits 0 to n has been output, analog-to-digital converter 6 also outputs a signal via line 10 to the reset interface of flip-flop 2, which resets flip-flop 2. Resetting closes switch 4 and stores a new analog signal in memory 7. Storing stops as soon as a rising edge of the reference clock restarts the described cycle.

[0039] The reference clock circuit can include a crystal oscillator to generate a reference clock. A crystal oscillator is an electronic circuit for generating oscillations that contains a quartz crystal as the frequency-determining component. The reference clock circuit can be a PLL-based oscillator. PLL stands for Phase-Locked Loop. The reference clock circuit can be configured to generate a square wave signal. The reference clock circuit can be configured to allow the frequency of the reference clock to be adjusted. With integrated clock synthesizer technology, PLL-based oscillators, such as PLL-based crystal oscillators, can be programmed to generate different frequencies.

[0040] Flip-flop 2 can be a D flip-flop.

[0041] Suitable reference clock circuits and flip-flops are commercially available.

[0042] Figure 2 shows an embodiment with a SAR-ADC 6 capable of 6-bit resolution. The SAR-ADC 6 comprises a capacitive digital-to-analog converter 11 (CDAC), a comparator 12, and a counter 13. An input signal and an inverted input signal can be applied to the SAR-ADC 6 via a block 14 comprising a T / H buffer and switch 4. A reference buffer 15 for a common-mode voltage V is also provided. cmpresent. The CDAC 11 comprises a plurality of capacitors. A first pair of capacitors has a capacity of 16C. A subsequent pair of capacitors has a capacity of 8C, i.e., half the capacity of the first pair of capacitors with a capacity of 16C. The next pair of capacitors has a further halved capacity of 4C. The next pair of capacitors has a further halved capacity of 2C. The next pair of capacitors has a further halved capacity of C. The aforementioned capacitors of the CDAC 11 can be connected via switches to ground GND, to a common-mode voltage V cm or with a reference voltage V ref can be connected. There may be additional pairs of these capacitors to improve resolution. There may be fewer pairs of these capacitors if a lower resolution is sufficient. In addition, for reasons of binary weighting, as shown in Figure 2, there may be another pair of capacitors with capacitance C that are permanently connected to the common-mode voltage V cm are connected. A first capacitor of each pair can be connected to one input of comparator 12. A second capacitor of each pair can be connected to the other input of comparator 12. Comparator 12 compares the respective applied voltages to determine a digital value for each bit. Counter 13 switches the switches accordingly and can finally reset flip-flop 2 after determining the last bit.

[0043] The electronic device may include a second analog-to-digital converter capable of digitizing a residual value. The residual value may be a difference between the value obtained by digitization and a held voltage. It may thus be digitized with improved resolution. The second analog-to-digital converter may be, for example, a SAR ADC, a sigma-delta ADC, or a flash ADC.

Claims

Claims 1. A method for operating an electronic device with operating phases of different lengths, characterized in that the shorter operating phase is stopped and the longer operating phase is started under the control of a clock frequency, and that the end of the longer operating phase is detected and that the shorter operating phase is started when the end of the longer operating phase has been detected.

2. Electronic device for carrying out the method according to the preceding claim, comprising a circuit with operating phases of different lengths, comprising a reference clock circuit (1) with which a reference clock can be generated, characterized in that the electronic device is set up in such a way that, controlled by the clock frequency, the shorter operating phase is stopped and the longer operating phase is started, and the end of the longer operating phase is detected, and the shorter operating phase is started when the end of the longer operating phase is detected.

3. Electronic device according to the preceding claim, characterized in that the time interval between two signals of the reference clock is shorter than the time duration of the longer operating phase.

4. Electronic device according to one of the preceding claims, characterized in that the time interval between two signals of the reference clock is longer than the duration of the shorter operating phase.

5. Electronic device according to one of the preceding claims, characterized in that the shorter operating phase is a sampling phase for sampling an analog voltage.

6. Electronic device according to one of the preceding claims, characterized in that the longer operating phase is a conversion phase for converting an analog voltage into a digital signal.

7. Electronic device according to one of the preceding claims, characterized in that it comprises an analog-digital converter (6).

8. Electronic device according to the preceding claim, characterized in that the analog-to-digital converter (6) is a SAR analog-to-digital converter.

9. Electronic device according to one of the preceding claims, characterized in that it comprises a clock edge-triggered D flip-flop (2).

10. Electronic device according to one of the preceding claims, characterized in that the reference clock circuit (1) comprises a quartz oscillator.

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