A photodetector and a method for fabricating the same

Abstract

The disclosure relates to a method for fabricating a photodetector, the method comprising: depositing a first layer on a substrate; creating a first array of first throughgoing holes in the first layer, exposing a conductive surface of the substrate; depositing a second layer on top of the first layer; etching the second layer through the second throughgoing holes in a mask layer thereby exposing the conductive surface of the substrate and forming an array of cavities; selectively growing a respective crystal from the respective conductive surface such that each respective crystal fills up each respective cavity of the array of cavities; wherein the first layer is of a material different from a material of the second layer, and wherein the materials of the first and second layers are selected such that for given crystal growth conditions a probability for crystal nucleation is lower than on the conductive surface.

Description

[0001]A PHOTODETECTOR AND A METHOD FOR FABRICATING THE SAME Field of invention The present disclosure relates to photodetectors, and fabrication thereof, for example an infrared photodetector. Technical Background Focal plane arrays, FPAs, are arrays of photodetectors that may be used for imaging purposes, or non-imaging purposes such as spectrometry, LIDAR, and wave- front sensing. Infrared FPAs are used in industrial processes to spot thermal and chemical gas leakage, as well as for night vision in both civil and military contexts, such as missile or related weapons guidance sensors, infrared astronomy, thermal imaging for firefighting, medical imaging, and infrared phenomenology. Available FPAs depend on flip-chip bonding which limits the pixel sensor resolution. In addition, since the flip-chip bonding process is performed after chip dicing, each chip must be processed serially, which limits the throughput and increases the cost for large scale manufacturing. Hence, there is a need for reducing the complexity and cost of production of FPAs, while at the same time facilitating efficient integration and increasing the throughput of the process. Summary of invention It is an object to mitigate, alleviate or eliminate one or more of the above- identified deficiencies in the art and disadvantages singly or in any combination and at least partly solve the above-mentioned problem and further problems mentioned below. According to a first aspect, there is provided a method for fabricating a photodetector, the method comprising: depositing a first layer on a substrate, and creating a first array of first throughgoing holes in the first layer, exposing a conductive surface of the substrate, wherein the first throughgoing holes have a first width. The method further comprises depositing a second layer on top of the first layer, and arranging a mask layer on top of the second layer, the mask layer comprising a second array of second throughgoing holes, wherein the second throughgoing holes have a second width being larger than the first width. The method further comprises etching the second layer through the second throughgoing holes in the mask layer thereby exposing the conductive surface of the substrate and forming an array of cavities, and selectively growing a respective crystal from the respective conductive surface such that each respective crystal fills up each respective cavity of the array of cavities, wherein the first layer is of a material different from a material of the second layer, and wherein the materials of the first and second layers are selected such that for given crystal growth conditions a probability for crystal nucleation is lower than on the conductive surface. The conductive surface may comprise a metallic material. The conductive surface may comprise a semiconducting material. Elemental materials are referred to herein by their element symbol or abbreviation. For example, indium arsenide may typically be referred to as InAs and silicon dioxide may be referred to as SiO2. In general, layers or structures said to comprise a specific material or element, may be understood as at least partially comprising or substantially consisting of the specific material or element. The layers of the semiconductor structure may be understood as ordered in a bottom up order. In this context the term “on” refers to arranging layers or structures above or onto other layers or structures. The term “vertical” refers to the direction in which layers are arranged on each other. The vertical direction is considered perpendicular or normal to the top surface of the substrate, wherein the top surface may be considered to be substantially planar. The term “laterally” refers to any direction being perpendicular to the vertical direction. The etching of the second layer may be an anisotropic dry etch in which the second layer below the opening of the etch mask in the vertical direction is removed. In an anisotropic dry etching process, the second array of second throughgoing holes will be directly transferred to the second layer, resulting in vertical cavity walls and a pixel size with the same shape as the second throughgoing holes in the mask layer. Alternatively, the etching of the second layer may be an isotropic wet chemical etch, in which the etching leads to under-etching of the second throughgoing holes in the mask layer and an expansion of the pixel size laterally, at least to a distance in either direction corresponding to the thickness of the second layer. The resulting cavities may then obtain a bowl-like shape, with cavity dimensions or diameters that are smaller at the bottom than the top. The etching may comprise the use of hydrogen fluoride, HF. The crystal may be grown via for example metal organic vapor phase epitaxy, MOVPE, or metal organic chemical vapor deposition, MOCVD. The crystal may comprise a III-V semiconductor, for example InAs, InSb, GaSb, InP, InAs1-xSbx, InxGa1-xAs or InAs1-xPx, or any III-V semiconductor that can be grown by MOVPE at low enough temperature to avoid degradation of a possibly underlying readout integrated circuit, ROIC. The mask layer may be an organic photoresist, a carbon layer, a metal layer, or an inorganic dielectric layer. Hence, the second layer may be selectively etched relative the mask layer. The first and second layers may be passive in the sense that the surface of the materials of the first and second layers is such that for given crystal growth conditions the probability for crystal nucleation is lower than on the metallic surface. The material of the second layer may be selected such that is may be selectively etched relative the mask layer. The first layer may comprise Si3N4, ZrO2 and / or HfO2 and the second layer may comprise SiO2, Si2N3 and / or Al2O3. The first width of the first throughgoing holes defines the exposed area of the conductive surface of the substrate. The first width of the first throughgoing holes may be smaller than 100 nm. The exposed area of the metallic surface may be smaller than 10000 nm2. Preferably, the exposed area may be smaller than the average diffusion length of adsorbed crystal growth precursor species or its derivates. Hence, a single nucleation event is facilitated during initialization of the selective growing of the respective crystals. After the single nucleation event, all precursor material that arrives in the vicinity of the surface will contribute to the growth of this first crystal nucleus, and the probability for further nucleation on the metal surface is suppressed. The second width to first width ratio may be at least 3:1. Preferably, the ratio may be at least 30:1. The method may further comprise extending the conductive surface of the substrate through the first throughgoing holes by depositing a metallic material in the first throughgoing holes. The step of extending the conductive surface may be performed after exposing the conductive surface of the substrate through the first throughgoing holes, and before the step of depositing a second layer. The conductive surface may be extended to the same thickness as the first layer or lower. The metallic material may be planarized after deposition to ensure that the thickness is the same or lower as the first layer. The metallic material may be or comprise for example tungsten. The metallic material may comprise other electrically conductive material such as Ti, Al, Cu, Ni, and / or Au. The conductive surface may have a higher nucleation rate compared to the first and second layer, such that for given crystal growth conditions the probability for crystal nucleation is higher on the conductive surface. The method may further comprise removing material of each respective crystal protruding from each respective cavity after selectively growing the respective crystals. Hence, it may be ensured that the thickness of the grown crystal is the same as the height of the second layer. The step of removing material may comprise polishing, chemical etching, or chemical mechanical polishing, CMP. The method may further comprise p- or n-doping a lower portion of the crystal abutting the conductive surface of the substrate and n- or p-doping an upper portion of each crystal such that the upper portion has opposite doping with respect to the lower portion. The n- or p-doping may be introduced in the initial stages of crystal growth realizing a n- or p-region in the lower portion and turned off during the following part of the growth to realize an intrinsic i-region in a middle portion. The opposite doping may be introduced in the later stages of crystal growth realizing a p- or n-region in the upper portion of each crystal. By this, a p-i-n structure may be realized. Alternatively, the step of p- or n-doping of the upper portion of each crystal may comprise extending each crystal with a p- or n-doped region. This may be done by regrowing a thin doped region after the step of selectively growing the respective crystal or after the step of removing material of each respective crystal protruding from each respective cavity. The upper portion may be thinner than 100 nm. The lower, middle and upper portion may be of the same material or different materials having similar crystal lattice constants. The method may further comprise depositing a contact on each respective crystal. The contact may be arranged at a circumference of an upper portion of the respective crystal. Alternatively, or in combination the contact may be transparent contact, e.g., made of Indium Tin Oxide. A transparent contact may cover the whole top surface of each respective crystal. The first and second arrays of throughgoing holes may be overlapping. By the first and second arrays of throughgoing holes overlapping is meant that each hole in the second array of throughgoing holes is overlapping one of the holes in the first array of throughgoing holes. Hence, the first and second array are arranged in register with each other. A shape of the second throughgoing holes may be circular, hexagonal or square. The method may further comprise providing a substrate comprising a readout integrated circuit, ROIC, wherein the provided substrate is the substrate onto which the first layer is deposited. Hence, reading out generated charge in the crystal is allowed in the ROIC located below. The ROIC may comprise a complementary metal oxide semiconductor, CMOS, chip. By growing the crystal directly on top of a ROIC chip, it eliminates the need for flip-chip bonding. In flip-chip bonding, the ROIC chip and the crystal would be joined by flipping the crystal and carefully aligning it with the chip. Such an alignment process requires a high level of precision and can only be carried out serially, which limits the throughput and increases the cost for large scale manufacturing. The method according to embodiments of the present inventive concept allows for efficient integration without the need for complex and costly alignment processes. The method further allows for separate design of ROIC and the crystal, while at the same time facilitating efficient integration and increasing the throughput of the process. According to a second aspect, there is provided a photodetection device produced by the method according to the present inventive concept. According to a third aspect, there is provided photodetection device, comprising from the bottom and up: a substrate having a plurality of a conductive elements constituting contact to a readout integrated circuit comprised in the substrate; a first layer comprising an array of throughgoing holes overlapping the plurality of conductive elements, wherein the throughgoing holes have a first width; a second layer comprising an array of cavities, each cavity having a second width being larger than the first width and each cavity comprising a crystal, wherein each crystal has a thickness that is at least equal to a thickness of the second layer and each crystal (300) is in conductive contact with a respective conductive element; and a contact on each respective crystal. Wherein the first layer is of a material different from a material of the second layer. By the plurality of throughgoing holes overlapping the plurality of conductive elements is meant that each of the plurality of throughgoing holes is overlapping one of the conductive elements. Hence, the plurality of throughgoing holes and the plurality of conductive elements are arranged in register with each other. The photodetection device may further comprise an array of conductive protrusions arranged in the array of throughgoing holes of the first layer such that each throughgoing hole is filled by a conductive protrusion, wherein the conductive protrusions have the first width. The conductive protrusions may be made of a metal. The metal may comprise one or more of W, Ti, Al, Cu, Ni, and / or Au. The first width may be smaller than 100 nm. A second width to first width ratio may be at least 10:1. The crystal may comprise a III-V semiconductor, such as InAs, InSb, GaSb, InP, InAs1-xSbx, InxGa1-xAs or InAs1-xPx. The first layer may comprise Si3N4, ZrO2 and / or HfO2. The second layer may comprise SiO2, Si2N3 and / or Al2O3. The throughgoing holes and the cavities may be overlapping. By the throughgoing holes overlapping the cavities is meant that each of the throughgoing holes is overlapping one of the cavities. Hence, the throughgoing holes and the cavities are arranged in register with each other. The above-mentioned features in connection with the photodetection device, when applicable, apply to this third aspect as well. In order to avoid undue repetition, reference is therefore made to the above. The material of the crystal may be selected with regard to the optimal detection wavelength for the photodetector. The material of the crystal may comprise InAs, InSb, GaSb, InP, InAs1-xSbx, InxGa1-xAs or InAs1-xPx, allowing coverage of the IR spectrum from 0.840 µm (InP) to 14 µm (InAs0.37Sb0.63). The photodetection device may be suitable for medium wavelength infrared, MWIR, 6-7µm wavelength. A further scope of applicability of the present invention will become apparent from the detailed description given below. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the scope of the invention will become apparent to those skilled in the art from this detailed description. Hence, it is to be understood that this invention is not limited to the particular component parts of the device described or acts of the methods described as such device and method may vary. It is also to be understood that the terminology used herein is for purpose of describing particular embodiments only and is not intended to be limiting. It must be noted that, as used in the specification and the appended claim, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements unless the context clearly dictates otherwise. Thus, for example, reference to "a device" or "the device" may include several devices, and the like. Furthermore, the words "comprising", “including”, “containing” and similar wordings does not exclude other elements or steps. Brief description of the drawings The above and other aspects of the present invention will now be described in more detail, with reference to appended figures. The figures should not be considered limiting; instead, they are used for explaining and understanding. Like reference numerals refer to like elements throughout. Fig.1 is a flow chart disclosing a method for fabricating a photodetector. Fig.2a-f discloses a photodetection device during fabrication in a cross- sectional view. Fig.3 discloses a photodetection device in perspective view. Fig.4 illustrates an alternative layout of a top contact for a photodetection device. Fig.5 illustrates an alternative layout of a bottom contact for a photodetection device. Fig.6 is a diagram wherein the yield of single grain crystals is indicated for different metallic surface diameters. Detailed description The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which currently preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided for thoroughness and completeness, and to fully convey the scope of the invention to the skilled person. In connection with figure 1, a method for fabricating a photodetector is disclosed as a flow chart. The method comprises the step of depositing S10 a first layer 110 on a substrate 200. Depositing S10 may comprise processes such as chemical vapor deposition, CVD, physical vapor deposition, PVD, or atomic layer deposition, ALD. The thickness of the first layer may be 10-100 nm. Preferably, the thickness of the first layer is 40 nm. If not explicitly stated otherwise, thickness will henceforth refer to vertical thickness. The method further comprises creating S20 a first array of first throughgoing holes 111 in the first layer 110, exposing a conductive surface 210 of the substrate 200, wherein the first throughgoing holes 111 have a first width w1. The first throughgoing holes 111 may be defined using lithography. Preferably, the first width w1 is smaller than 100 nm, and the surface area of the exposed conductive surface is less than 10000 nm2. The resulting device from this step is illustrated in figure 2a. The conductive surface 210 is electrically conducting. The conductive surface 210 may be made from a metal, such as W, Ti, Al, Cu, Ni, and / or Au or and / or from a semiconducting material. Prior to the step of depositing S10 a first layer, the method may comprise a step of providing S01 a substrate 200 comprising a readout integrated circuit, wherein the provided substrate is the substrate 200 onto which the first layer 110 is deposited. After the step of creating S20 a first array of first throughgoing holes 111, the method may further comprise extending S21 the conductive surface 210 of the substrate 200 through the first throughgoing holes 111 by depositing a conductive material in the first throughgoing holes 111. The deposited conductive material may be a metallic material, e.g., W, Ti, Al, Cu, Ni, and / or Au. Preferably, the metallic material comprises W. The deposited conductive material may hence be said to form a conductive plug. A diameter of the conductive plug may be larger than 10 nm. A convenient diameter is smaller than 100 nm. A surface area of the conductive plug may be 1000 – 10000 nm^2. The length of the conductive plug should not be larger than the thickness of the first layer, so that the conductive plug does not protrude above the first layer. The length of the conductive plug should be sufficiently small so that the resistance of the plug is small. The thickness of the first layer should be sufficiently large for resulting in a sufficient insulation. The electric field over the first layer should not exceed a break- down electric field of the material. Such break-down electric field may be about 6 - 7 MV / cm, for example for Si3N4. The aspect ratio between the widths w1 of the first throughgoing holes 111 and the thickness of the first layer determines the electrical resistance of the conductive plug. The electrical resistance of the conductive plug can be a serious series resistance. This is the reason for why one wants to keep the thickness of the first layer reasonably thin compared to widths w1 of the first throughgoing holes 111. A reasonable lower bound for w1 is 10 nm, which is already very challenging to make in practice. Preferably, the conductive surface has a higher nucleation rate compared to the first and second layer, such that for given crystal growth conditions the probability for crystal nucleation is higher on the conductive surface. A conductive material, e.g., a metallic material, may be deposited over the whole surface of the first layer 110 and then being planarized such that the only remaining conductive material is comprised in the first array of the first throughgoing holes 111. The planarization may be performed through polishing, chemical etching, or chemical mechanical polishing, CMP. The conductive material of the conductive plug may be extended to the same thickness as the first layer or a lower thickness. The resulting device from this step is illustrated in figure 2b. Before the conductive material is deposited in the first throughgoing holes 111, the surface of the substrate below the holes may be treated to improve electric contact between the deposited conductive material and the surface of the substrate. This can be done by using a strong acid or ammonia, which removes any oxidized surface layers or other substance. Then, the acid or ammonia may be removed by rinsing, to remove the acid or ammonia and products of the reaction. The same procedure may be used on the upper surface of the plug, wherein the crystal is to be grown. A major and unique benefit of the present integration approach is that the crystal is directly grown on a metal that without further processing could potentially be used as a contact in an electronic device. It is therefore interesting to evaluate the electrical characteristics of the interface contact. The current-voltage characteristics of the interface are ohmic, with no indication of Schottky-like behavior. Indeed, the absence of a significant energy barrier has been confirmed by measuring the current-voltage characteristics at various temperatures down to 13K, which result in similar ohmic characteristics with ohmic connection to the bottom metal electrode without need for further processing. The conductive material for a conductive plug 210b can be deposited for example by a sputtering or evaporation method (physical vapor deposition PVD), as well as a chemical vapor deposition method (CVD). The method further comprises depositing S30 a second layer 120 on top of the first layer 110. The thickness of the second layer may be 1-10 µm. Preferably, the thickness of the second layer is 3µm. The method further comprises arranging S40 a mask layer 130 on top of the second layer 120, the mask layer 130 comprising a second array of second throughgoing holes 131, wherein the second throughgoing holes 131 have a second width w2 being larger than the first width w1. The mask layer 130 may comprise an organic photoresist, a carbon layer, a metal layer, or an inorganic dielectric layer. The second array of second throughgoing holes 131 may be defined through photolithography. The second width w2 of the second throughgoing holes 131 may be larger than the first width by a ratio of at least 3:1 such as 10:1, preferably 30:1. The second width w2 may be 30 µm. The first and second arrays of throughgoing holes 111, 131 may be overlapping. The resulting device from this step is illustrated in figure 2c. The method further comprises etching S50 the second layer 120 through the second throughgoing holes 131 in the mask layer 130 thereby exposing the conductive surface 210 of the substrate 200 or the conductive plug 210b and forming an array of cavities 121. The material of the second layer 120 may be selected such that it can be selectively etched relative to the material of the mask layer 130. The second width w2 of the second throughgoing holes 131 may be selected with regard to the desired size of the cavities 121. The shape of the second throughgoing holes 131 may be circular, hexagonal or square, or any other shape. The etching S50 of the second layer 120 may be an isotropic wet chemical etch using an etchant that selectively etches the material of the second layer 120 and no other material. The etchant may be for instance hydrogen fluoride, HF. The resulting cavities 121 may then obtain a bowl-like shape, with a dimension or diameter which is smaller at the bottom than the top, as is illustrated in figure 2d. The largest diameter is indicated by w3. The etching S50 of the second layer 120 may comprise other processes, such as anisotropic dry etch processes. The mask layer may be removed after the step of etching S50 the second layer 120. The mask layer can be removed in different ways depending on the type of mask. If an organic material, then exposing it to a solvent or an oxygen plasma will selectively remove it without damage to the rest of the structure. The method further comprises selectively growing S60 a respective crystal 300 from the respective metallic surface 210 such that each respective crystal 300 fills up each respective cavity 121 of the array of cavities. The growth of the crystal 300 may be initiated via for example metal organic vapor phase epitaxy MOVPE. For step S60, typical parameters are as follows: Carrier gas is usually H2 or N2 at a total pressure of 100 mbar. The partial pressure of growth precursors is 10-6 to 10-4 mbar, usually with a ratio of V / III precursor of 10-100. The temperature should be high enough so that the precursor species can react to form the crystal, which is typically above 300°C or 400°C. The upper limit is set by the requirement to avoid degradation of the substrate. For ROICs this typically sets a limitation of at most 550°C. A preferred temperature is 450°C. The crystal 300 may comprise a III-V semiconductor, for example InAs, InSb, GaSb, InP, InAs1-xSbx, InxGa1-xAs or InAs1-xPx. The growth of the crystal 300 is initiated on the metallic surface 210, and after a single nucleation event all precursor material that arrives in the vicinity of the surface will contribute to the growth of this first crystal nucleus, and the probability for further nucleation on the metal surface 210 is suppressed. This is because of the smaller size of the exposed area of the metallic surface 210 than the average diffusion length of adsorbed crystal growth precursor species or its derivatives. The precise size of the first width w1, and thereby the exposed area of the metallic surface 210, may be selected with regards to growth conditions, such as the selected temperature and total and partial pressure of the precursor gases and carrier gas. After the initial nucleation phase, continued exposure to the precursors species at the growth conditions may result in growth of the crystal 300 to fill up each cavity 121 in the array of cavities in the second layer 120. In this process, the crystal orientation may not necessarily be controlled, as crystal lattices of the metallic surface and the crystal may be too distinct for allowing for epitaxial growth. The growth of the crystal from a single nucleation event results in a crystal having no or few lattice errors. To achieve single crystalline crystal growth it is required that there is only a single nucleation event on the exposed metal and that this nucleus grows to fill up the full cross sectional area before another nucleation event occurs. This requires the nucleation probability on the metal surface to be sufficiently high compared to the surrounding surfaces. However, the nucleation probability on the metal cannot be too high, as this may lead to nucleation of multiple distinct crystallites that would converge into a polycrystal. The diameter of the metallic surface 210 is of importance for obtaining a single grain crystal. Fig.6 is a diagram wherein the yield of single grain crystals is indicated for different metallic surface diameters. As appears from the diagram, a diameter of 120 nm will yield slightly more than 40 % single grain crystals, while a diameter of 75 nm will yield approximately 70 % single grain crystals. Consequently, a diameter of about 100 nm or smaller will yield more than about 50 % single grain crystals, which is desirable. A diameter of 40 nm would result in more than 90 % single grain crystals. Although not shown in the diagram, smaller diameters will work as well, down to about 10 nm. The growth of the crystal 300 may be performed such that the crystal reaches the top surface of the cavity. Alternatively, the growth of the crystal may continue such that the crystal protrudes above each cavity 121. Removing S70 material of each respective crystal 300 protruding from each respective cavity 121 may then be performed, for instance by a chemical- mechanical polishing process, CMP, which may be selective to the crystal 300 and not the material of the second layer 120, ensuring a natural stop of the CMP at the top of the cavity 121. The size of the cavity 121 depends on the targeted detection wavelength. For widths and thicknesses greater than roughly 2 x the wavelength of the light, the pixel will behave according to geometrical optics and light transmitted into the crystal will be absorbed efficiently. However, for pixels smaller than this limit, wave optics come into play, giving substantial diffraction and interference effects. The crystal will then act as a kind of antenna, and the precise shape of the pixel will determine the strength of the electric field of the light inside the crystal and engineering a crystal shape or surface texturing that maximizes this antenna effect can substantially improve absorption efficiency for crystals smaller than approximately 2 times the wavelength. Plasmonic nanoantenna’s can also be structured on the top of the crystal to focus the electromagnetic field into the crystal. A suitable diameter or dimension of the cavity may be ½ - 10 times the wavelength, with a maximum of 10 µm to be competitive compared to other methods. For example, for 7 µm target wavelength (InSb crystal) one would use a diameter in the range 3.5-10 µm. For the smallest structures some clever choice of patterning like described above should be made to maximize light absorption. The first layer 110 is of a material different from a material of the second layer 120, and the materials of the first and second layers 110, 120 are selected such that for given crystal growth conditions a probability for crystal nucleation is lower than on the metallic surface 210. The first layer 110 may comprise Si3N4, ZrO2 and / or HfO2, and the second layer 120 may comprise SiO2, Si2N3 and / or Al2O3. The resulting device from this step is illustrated in figure 2e. The method may further comprise p- or n-doping S61 a lower portion of the crystal 310 abutting the metallic surface 210 of the substrate 200 and n-or p-doping S62 an upper portion 320 of each crystal 320 such that the upper portion 320 has opposite doping with respect to the lower portion 310. The p- or n-doping S61 may be introduced in the initial stages of crystal growth realizing a p- or n-region in the lower portion 310 and turned off during the following part of the growth to realize an intrinsic i-region in a middle portion 300. The opposite doping may be introduced in the later stages of crystal growth realizing a n- or p-region in the upper portion 320 of each crystal. By this, a p-i-n structure may be realized, illustrated in figure 2e by dotted lines. Additionally, or alternatively, the method may comprise n- or p-doping S62 an upper portion of each crystal 320 comprises extending each crystal 300 with an n- or p-doped region, as illustrated in figure 2f. This may be done by regrowing a doped upper region 320 after the step of selectively growing S60 the respective crystal and doping S62 the lower portion as illustrated in figure 1, or after the step of removing material S70 of each respective crystal protruding from each respective cavity (not illustrated). The upper portion may be thinner than 100 nm. The lower, middle and upper portion may be of the same material or different materials having similar crystal lattice constants. The method may further comprise depositing S80 a contact 400 on each respective crystal 300, wherein the contact 400 may be arranged at a circumference of an upper portion of the respective crystal 320. The contact 400 may comprise any adequate electrically conducting material. Alternatively, or on combination, the top contact may be a transparent conducting electrode for example consisting of Indium Tin Oxide (ITO). Such a transparent conducting electrode may cover the whole top surface of each respective crystal. According to another example, the top contact may be a conducting electrode going across the center of the pixel top surface. Such a conducting electrode may be made from a metal. An alternative to use a top contact according to any of the examples above may be to cover parts of the inside of the cavity walls with a conducting electrode material before step S60, given that there is sufficient selectivity in crystal nucleation. For example, a TiN metal may be used as a passive template wall and after growth be used as an electrode contact, this is illustrated in Fig.4 wherein a conducting electrode material is deposited forming an imbedded top electrode 450. As illustrated in Fig.5, a further embodiment comprises an extended bottom electrode 500 of a material which has a lower probability of nucleation compared to the conductive plug 210b. The extended bottom electrode 500 may have an overlap with the conductive plug 210b, which defines the boundaries of the nucleation area. The effective w1 is then defined as the gap in the layer of the added extended bottom electrode 500 above the conductive plug 210b. The benefits of these approaches are that one may optimize the distance that generated charge carriers need to travel to reach a contact, improving detectivity of the device. Turning now to figure 3, a photodetection device 100 produced by the method illustrated in figure 1 is shown. The photodetection device 100 comprises from the bottom and up: a substrate 200 having a plurality of a conductive elements 210a constituting contact to a readout integrated circuit comprised in the substrate 200; an array of conductive protrusions 210b, wherein the conductive protrusions 210b have a first width w1; a first layer 110 comprising an array of throughgoing holes 111 corresponding to the array of conductive protrusions 210b, such that each throughgoing hole 111 is filled, potentially filled up, by each conductive protrusion 210b; a second layer 120 comprising an array of crystals 300, wherein each crystal 300 has a thickness that is at least equal to a thickness of the second layer 120, a contact 400 on each respective crystal 300; wherein the first layer 110 is of a material different from a material of the second layer 120. As has been discussed above, the conductive protrusions 210b are preferably made from metallic material. Each crystal 300 in the array of crystals may be considered a pixel in the photodetection device 100. The lateral and vertical extent of each pixel will be defined by the cavities 121 in the second layer 120. The inter-pixel separation will be defined by the walls of the cavities 121, i.e. the material of the second layer 120 that remains after the step of etching S50 the second layer 120. The inter-pixel separation may be below 500 nm, or even below 100 nm as it is limited only by the etching process S50 that defined them. The shape of the second throughgoing holes 131, and the anisotropic or isotropic etching process S50 may be selected with regard to the desired final shape of the crystals 300 or pixels. For instance, a circular shape of the second throughgoing holes 131 and an isotropic etch S50 may result in a bowl-like shaped pixel, a square shape of the second throughgoing holes 131 and an anisotropic etch S50 may result in a cubical pixel, etc. The photodetection device 100 shown in Fig.3 has a rectangular or square configuration, but triangular or hexagonal configurations may also be considered. There are a number of other embodiments partly dependent on the construction of the read out integrated circuit, ROIC. The substrate 200 may already have a conductive surface which is about 10 - 100 nm in diameter, which forms the interface between the ROIC and the photodetection device 100. The substrate may from the start have the configuration shown in Fig.2b. The conductive surface may be a sensing contact such as a gate contact in a MOSFET arranged in the ROIC. In this case, the step of depositing a first layer 110 is no longer required and the process can start with the second layer. A method for fabricating a photodetector having an array of pixels will now be discussed. The method comprising the following steps. Providing a substrate having a conducting surface for each pixel in the array of pixels, the conducting surface being electrically connected to a pixel read-out circuit. For each pixel in the array of pixels, defining a crystal growth surface on or in electric contact with the conducting surface. For each pixel in the array of pixels, depositing a cavity forming material on the substrate. For each pixel in the array of pixels, generating a cavity through the cavity forming material extending to the crystal growth surface, wherein a top dimension (w2) of the cavity is larger than a corresponding dimension (w1) of the crystal growth surface. For each pixel in the array of pixels, growing a crystal starting from the crystal growth surface and filling up the cavity, wherein the cavity forming material has a lower probability of crystal nucleation than the crystal growth surface material. The conducting surface of the substrate may form the crystal growth surface. The conducting surface of the substrate may be a metallic material compatible with crystal growth. In another embodiment, the substrate 200 may have a metallic surface larger than 100 nm. In this case, a first layer is needed for reducing the dimension or diameter of the nucleation position to below 100 nm. However, no conductive plug may be required, since the crystal can grow directly on the metallic surface. The method may comprise depositing a delimiting layer on said conducting surface delimiting a partial area on the conducting surface for forming the crystal growth surface, wherein the conducting surface of the substrate is of a metallic material compatible with crystal growth. In this case, the extended bottom electrode 500 (of for example TiN), on which nucleation of the crystal is markedly lower than on the metallic surface of the substrate 200, may be used as the first layer for reducing and / or defining the crystal growth area. The substrate may have a metallic surface larger than 100 nm, but the metallic surface is incompatible with growth of a crystal. In this case, a first layer is needed for reducing the diameter to below 100 nm and a conductive plug is required. The first layer may be of a conducting material having a lower probability of crystal nucleation than the crystal growth surface. Additionally, or alternatively, the substrate may have a contact surface which is non-metallic, for example highly doped semiconductor. In this case a conductive plug, e.g., a metallic conductive plug, is required, if the crystal cannot grow directly on the semiconductor surface. An alternative method may comprise: depositing a covering material on a substrate covering a conducting area; forming a plug hole through the covering material above at least a portion of the conducting surface; depositing a metallic material in the plug hole forming the crystal growth surface and in electric contact with the conducting surface of the substrate and extending at least partially through the plug hole; wherein the covering material has a lower probability of crystal nucleation than the crystal growth surface, and is made of an insulating material or of an electrically conducting material (for example TiN). In any of the embodiments mentioned, the metallic material or metallic surface for crystal growth may be any one of: W, Ti, Al, Ni or Au or a combination thereof. All embodiments may be adapted to be used as photodetectors for infrared light in the area of 0.8 – 14 µm, such as 1.2 – 10 µm, 4 – 8 µm or 6 – 7 µm. The photodetector may as well be used for visible light in the area of 0.4 – 0.8 µm. Suitable materials for visible light are: GaP or AlGaP. The person skilled in the art realizes that the present invention by no means is limited to the preferred embodiments described above. On the contrary, many modifications and variations are possible within the scope of the appended claims. For example, it is readily understood that the photodetection device may be used for wavelengths outside the IR spectrum, or as a photovoltaic cell. Variations to the disclosed embodiments can be understood and effected by the skilled person in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

CLAIMS 1. A method for fabricating a photodetector (100), the method comprising: depositing (S10) a first layer (110) on a substrate (200); creating (S20) a first array of first throughgoing holes (111) in the first layer (110), exposing a conductive surface (210) of the substrate (200), wherein the first throughgoing holes (111) have a first width (w1); depositing (S30) a second layer (120) on top of the first layer (110); arranging (S40) a mask layer (130) on top of the second layer (120), the mask layer (130) comprising a second array of second throughgoing holes (131), wherein the second throughgoing holes (131) have a second width (w2) being larger than the first width (w1); etching (S50) the second layer (120) through the second throughgoing holes (131) in the mask layer (130) thereby exposing the conductive surface (210) of the substrate (200) and forming an array of cavities (121); selectively growing (S60) a respective crystal (300) from the respective conductive surface (210) such that each respective crystal (300) fills up each respective cavity (121) of the array of cavities; wherein the first layer (110) is of a material different from a material of the second layer (120), and wherein the materials of the first and second layers (110, 120) are selected such that for given crystal growth conditions a probability for crystal nucleation is lower than on the conductive surface (210).

2. The method according to claim 1, further comprising removing (S70) material of each respective crystal (300) protruding from each respective cavity (121).

3. The method according to claim 1 or 2, further comprising p- or n- doping (S61) a lower portion of the crystal (310) abutting the conductive surface (210) of the substrate (200) and n- or p-doping (S62) an upper portion (320) of each crystal (320) such that the upper portion (320) has opposite doping with respect to the lower portion (310).

4. The method according to claim 3, wherein n- or p-doping (S62) an upper portion of each crystal (320) comprises extending each crystal (300) with an n- or p-doped region.

5. The method according to any one of claims 1-4, further comprising depositing (S80) a contact (400) on each respective crystal (300).

6. The method according to any one of claims 1-5, wherein the first width (w1) is smaller than 100 nm.

7. The method according to any one of claims 1-6, wherein a second width (w2) to first width (w1) ratio is at least 10:

1.

8. The method according to any one of claims 1-7, wherein the crystal (300) comprises a III-V semiconductor, such as InAs, InSb, GaSb, InP, InAs1-xSbx, InxGa1-xAs or InAs1-xPx.

9. The method according to any one of claims 1-8, wherein the first layer (110) comprises Si3N4, ZrO2 and / or HfO2 and the second layer (120) comprises SiO2, Si2N3 and / or Al2O3.

10. The method according to any one of claims 1-9, wherein the selectively growing (S60) a respective crystal is made via metal organic vapor phase epitaxy, MOVPE, or metal organic chemical vapor deposition, MOCVD.

11. The method according to any one of claims 1-10, wherein the mask layer comprises at least one of an organic photoresist, a carbon layer, a metal layer, and an inorganic dielectric layer.

12. The method according to any one of claims 1-11, wherein the etching (S50) of the second layer (120) is an anisotropic dry etch in which part of the second layer (120) below the respective second throughgoing holes (131) is removed.

13. The method according to any one of claims 1-11, wherein the etching (S50) of the second layer (120) is an isotropic wet chemical etch, in which the etching leads to under-etching of the second throughgoing holes (131) and an expansion of a pixel size laterally, at least to a distance in either direction corresponding to a thickness of the second layer.

14. The method according to any one of claims 1-13, wherein the first and second arrays of throughgoing holes are overlapping.

15. The method according to any one of claims 1-14, wherein a shape of the second throughgoing holes are circular, hexagonal or square.

16. The method according to any one of claims 1-15, further comprising extending the conductive surface (210) of the substrate (200) through the first throughgoing holes (111) by depositing a metallic material in the first throughgoing holes (111).

17. The method according to claim 16, wherein extending the conductive surface (210) is performed such that the conductive surface (210) extend to a same thickness as the first layer (110) or lower.

18. The method according to claim 16 or 17, further comprising planarizing the metallic material after deposition.

19. The method according to any one of claims 16-18, wherein the metallic material comprises one or more of W, Ti, Al, Cu, Ni, and Au.

20. The method according to any one of claims 1-19, further comprising providing a substrate comprising a readout integrated circuit, ROIC, wherein the provided substrate is the substrate onto which the first layer is deposited.

21. The method according to claim 20, wherein the ROIC comprises a complementary metal oxide semiconductor, CMOS, chip.

22. A photodetector produced by the method according to any one of claims 1-21.

23. A photodetection device (100), comprising from the bottom and up: a substrate (200) having a plurality of conductive elements (210a) constituting contacts to a readout integrated circuit, ROIC, comprised in the substrate (200); a first layer (110) comprising an array of throughgoing holes (111) overlapping the plurality of conductive elements (210a), wherein the throughgoing holes (111) have a first width (w1); a second layer (120) comprising an array of cavities (121), each cavity having a second width (w2) being larger than the first width (w1) and each cavity comprising a crystal (300), wherein each crystal (300) has a thickness that is at least equal to a thickness of the second layer (120) and each crystal (300) is in conductive contact with a respective conductive element (210a); and a contact (400) on each respective crystal (300); wherein the first layer (110) is of a material different from a material of the second layer (120).

24. The photodetection device (100) according to claim 23, further comprising an array of conductive protrusions (210b) arranged in the array of throughgoing holes (111) of the first layer (110) such that each throughgoing hole (111) is filled by a conductive protrusion (210b), wherein the conductive protrusions (210b) have the first width (w1).

25. The photodetection device (100) according to 24, wherein the conductive protrusions (210b) are made from a metallic material comprising one or more of W, Ti, Al, Cu, Ni, and Au.

26. The photodetection device (100) according to any one of claims 23-25, wherein the first width (w1) is smaller than 100 nm.

27. The photodetection device (100) according to any one of claims 23-26, wherein a second width (w2) to first width (w1) ratio is at least 10:1.

28. The photodetection device (100) according to any one of claims 23-27, wherein the crystal (300) comprises a III-V semiconductor, such as InAs, InSb, GaSb, InP, InAs1-xSbx, InxGa1-xAs or InAs1-xPx.

29. The photodetection device (100) according to any one of claims 23-28, wherein the first layer (110) comprises Si3N4, ZrO2 and / or HfO2 and the second layer (120) comprises SiO2, Si2N3 and / or Al2O3.

30. The photodetection device (100) according to any one of claims 23-29, wherein the throughgoing holes (111) and the cavities (121) are overlapping.

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