Device for stimulating an auditory nerve

Abstract

The invention relates to a device for stimulating an auditory nerve, comprising a (CMOS) chip; a plurality of optical elements for stimulating the auditory nerve; and at least one driver circuit for controlling the plurality of optical elements. The plurality of optical elements and the at least one driver circuit are integrated in the (CMOS) chip.

Description

[0001] Device for stimulating an auditory nerve

[0002] Description

[0003] Technical area

[0004] The present application relates to a device for stimulating an auditory nerve, in particular a fully integrated cochlear implant.

[0005] Background of the invention

[0006] The basic functionality of a multi-channel cochlear implant has long been known [1]. It helps people whose inner ear is damaged but whose auditory nerve remains intact. Conventional solutions bridge the damaged inner ear with an external microphone and speech processor on the one hand, and an implanted electrode array on the auditory nerve on the other. In this arrangement, the auditory nerve itself is directly stimulated by electrical impulses. The number of electrode stimulation points defines the different perceivable frequencies and thus contributes significantly to the actual perceived auditory impression.

[0007] Newer approaches pursue a promising optical approach instead of stimulation with electrodes [2], in which stimulation takes place through pLEDs and optogenetic manipulation of the auditory nerve. In this arrangement, micro-LED chips are built on a flexible substrate carrier and controlled externally. In this respect, the structure corresponds to the conventional process of external electronics and an implanted "stimulation electrode", although the manufacturing process is very complex [3]: The required substrate flexibility is initiated by a complex process with a polyimide layer on a Si wafer. Further steps of spin-coating, RIE, sputtering, lift-off, and electroplating (for an integrated temperature sensor) follow before the pLED itself is contacted. The achieved integration density is extremely low: 2-3 metal wiring levels, individual pLEDs, and a temperature sensor are achieved.This is not much more than the state of the art for conventional electrode arrays. The challenge of the connection between implanted and external electronics (and the associated ergonomic / aesthetic impact) remains. Therefore, it would be desirable to improve hearing aids to address the issues just described.

[0008] This object is achieved with a device for stimulating an auditory nerve according to claim 1.

[0009] Further embodiments and advantageous aspects of this device for stimulating an auditory nerve are mentioned in the respective dependent patent claims.

[0010] overview

[0011] The inventive device for stimulating an auditory nerve is based on the discovery that, for example, CMOS technology allows optical elements to be positioned very close to one another and, moreover, that a driver circuit for controlling the optical elements can be integrated into the same substrate as the optical elements. By integrating the driver circuit and the optical elements into a single chip, improvements are achieved in terms of switching frequency, control power, and dynamic losses compared to previous hearing aids, particularly since the driver circuit can be arranged close to, directly next to, or even below the optical elements. Using a (CMOS) process, the individual components can be integrated and linked together in a single chip.This provides a complete system that requires no assembly and interconnection technology (AVT) and thus enables simple manufacture of the device according to the invention. Furthermore, it was achieved that the electronics, such as the driver circuit, which could previously only be implemented externally, could be integrated directly with the stimulation unit, e.g., an array of a plurality of optical elements, in a common chip, allowing the stimulation unit to be implanted together with the electronics. As a result, the device according to the invention for stimulating the auditory nerve is fully implantable and thus overcomes the challenge of connecting the implanted stimulation unit to the external electronics.A further advantage of the present invention is that a large number of optical elements can be integrated into the (CMOS) chip, thereby achieving good frequency resolution when stimulating the auditory nerve. The invention is based, among other things, on the finding that a CMOS chip meets biocompatibility requirements and, in particular, can be designed to be so flexible that the (CMOS) chip according to the invention can be bent into a spiral shape and can therefore be introduced and implanted into a cochlea. Other manufacturing technologies besides CMOS would also be conceivable. The new method is further characterized in that, according to exemplary embodiments, all functional elements (light generation, wiring, active circuit elements, temperature sensor) are monolithically integrated at wafer level. This allows standard processes from semiconductor manufacturing to be used.The flexibility is achieved through a special process in which the wafer stack is extremely thinned from the front and back, thereby making the substrate flexible.

[0012] A corresponding embodiment relates to a device, e.g., an optoelectronic hearing aid, for stimulating an auditory nerve, comprising a (CMOS) chip, a plurality of optical elements for stimulating the auditory nerve, and at least one driver circuit for controlling the plurality of optical elements. The plurality of optical elements and the at least one driver circuit are integrated into the (CMOS) chip.

[0013] The chip can be implemented, for example, as a semiconductor chip, such as a CMOS chip. According to one embodiment, the plurality of optical elements and the at least one driver circuit are monolithically integrated in the semiconductor chip. The term "monolithic" refers, for example, to the fact that the plurality of optical elements and the at least one driver circuit are manufactured on a single semiconductor substrate, usually silicon, e.g., without bonding steps or AVT steps. Semiconductor-based light emitters, e.g., light-emitting diodes (LEDs or pLEDs) or laser diodes, can be used as optically (active) elements in semiconductor chips. Using processes from semiconductor manufacturing, such as CMOS technology, the optical elements are integrated into the semiconductor substrate together with the at least one driver circuit. If the chip is implemented as a COMS chip, then, for example,The optical elements are manufactured using the same process as other CMOS components. The manufacturing process involves creating the required structures and doping regions within the semiconductor substrate to form the optical elements. This process typically includes steps such as oxidation, layer deposition, photolithography, etching, doping, annealing (temperature treatment), and / or metallization, similar to those used in the manufacture of CMOS transistors. In addition to using CMOS technology, the optical elements, together with at least one driver circuit, can also be monolithically integrated into the chip using III-V semiconductor materials, such as GaN (gallium nitride).The monolithic design is based on the realization that a chip designed in this way exhibits high resistance in the liquid environment within the cochlea, thus contributing to the longevity of the device. Furthermore, the monolithic design significantly simplifies the manufacturing process. A hybrid design is also conceivable, in which the components—i.e., the optical elements and the driver circuit—are made from different semiconductor materials or are produced using different technologies. For example, the driver circuit can be integrated into the chip using CMOS processes, and the optical elements can be integrated into the chip using III-V semiconductor materials, or vice versa.According to one embodiment, the at least one driver circuit can be integrated into the chip by means of CMOS, using thin-film transistors (TFTs for short) or using III-V semiconductor material or SiC material, and the majority of optical elements can be integrated into the chip by means of CMOS, using III-V semiconductor material or using OLED.

[0014] According to one embodiment, the chip can be embodied as a layer stack, wherein the at least one driver circuit is arranged in a first layer stack region and the plurality of optical elements are arranged in a second layer stack region, wherein the first layer stack region and the second layer stack region are arranged vertically one above the other. Wiring or connection levels are optionally arranged between the first layer stack region and the second layer stack region. The wiring or connection levels can be implemented using CMOS technology. The plurality of optical elements are formed in the form of OLEDs in the second layer stack region, for example by applying organic materials to a main surface region of a layer of the layer stack, e.g. using techniques such as thermal vacuum evaporation or organic vapor deposition (OVPD).These organic layers typically comprise an emitting layer, a hole transport layer, an electron transport layer, and other functional layers. As described in connection with the figures, one embodiment of a chip with OLED can be realized by embedding a plurality of pixel electrodes in a layer of organic material. The pixel electrodes are connected, for example, to the at least one driver circuit. Optionally, each pixel electrode is connected to its own driver circuit. One embodiment relates to a chip with a CMOS driver circuit in conjunction with optical elements in the form of OLEDs. A particular advantage of OLED on CMOS is that the OLED layers can be applied monolithically to the CMOS substrate, usually by evaporation. Optionally, the OLED layers can be encapsulated with a very thin layer. The thin encapsulation layer is, for example,The OLEDs are applied directly to the OLED layers by atomic layer deposition (ALD), chemical vapor deposition (CVD), or sputtering. No bonding or AVT processes are used to integrate the majority of optical elements and at least one driver circuit into the chip. This makes the device particularly robust for the liquid environment within the cochlea and enables highly efficient device manufacturing.

[0015] According to one embodiment, the device has a plurality of driver circuits that are bijectively assigned to the plurality of optical elements. Each of the plurality of driver circuits is designed to control one of the plurality of optical elements. The device thus has a driver circuit for each of the plurality of optical elements, for controlling the respective optical element. The driver circuits are integrated in the (CMOS) chip. This enables flexible and individual control of each individual optical element of the device. It is particularly advantageous if the respective driver circuit is arranged in the immediate vicinity of or below the respective optical element that is controlled by the driver circuit, i.e. if the respective driver circuit is arranged in the immediate vicinity of the optical element assigned to the driver circuit.This allows advantageous dynamics, in particular a high duty cycle, to be achieved.

[0016] According to one embodiment, one or more components from the group comprising a speech processor, a wireless interface, a microphone, and a power supply for providing energy obtained from cellular energy, chemical energy, thermal energy, or kinetic energy are further integrated into the (CMOS) chip. The speech processor corresponds, for example, to an electronic unit for acoustic data preprocessing, e.g., for converting an acoustic signal into an electrical signal. The wireless interface is designed, for example, to transmit data and / or energy between an external unit and the device, e.g., for power supply / energy supply and / or data transmission. The wireless interface is designed, for example, to transmit the data and / or energy via an electric field, via a magnetic field, by light, or mechanically. The microphone is, for example,designed to record acoustic signals. The speech processor, for example, is designed to receive and process the acoustic signals recorded by the microphone, i.e., convert them into electrical signals. The power supply is designed, for example, to generate energy from cellular energy, chemical energy, or kinetic energy. By integrating one or more of these components, a unit attached externally to the ear can be made smaller. Depending on which components are integrated, it may even be possible to do without an external unit entirely, making the system fully implantable. By integrating one or more of the components, external interference, ergonomic impairments, and / or aesthetic impairments can be reduced.

[0017] According to one embodiment, the (CMOS) chip has a first section that is designed to be inserted into a cochlea, i.e., the cochlea. Furthermore, the (CMOS) chip has a second section, e.g., adjoining / adjacent to the first section, which is designed to be arranged outside the cochlea. The (CMOS) chip has, e.g., a common substrate for the first section and the second section, i.e., the (CMOS) chip is monolithic. The plurality of optical elements and the at least one driver circuit are integrated in the first section of the (CMOS) chip, and the one or more components listed above, e.g., the speech processor, the wireless interface, the microphone, and / or the power supply, are integrated in the second section of the (CMOS) chip.The first section thus forms a stimulation unit that can be inserted, for example, into the scala tympani of the cochlea. The optical units are designed, for example, to emit light and thus specifically stimulate the auditory nerve. The auditory nerve is, for example, optogenetically manipulated so that it can be stimulated by light. The second section of the (CMOS) chip, for example, is not intended to be inserted into the cochlea. This special division has the particular advantage that the components listed above are not located in the fluid contained in the scala vestibuli and scala tympani. This makes the device extremely robust and long-lasting. Furthermore, it has been recognized that the microphone in particular can record high-quality acoustic signals outside the cochlea, which is why it is advantageous to arrange it in the second section.A further advantage of this arrangement is that the first section of the (CMOS) chip, which is to be inserted into the approximately pea-sized cochlea, has small dimensions, ie a very small diameter, since the at least one driver circuit and the optical elements can be realized very small in the (CMOS) chip.

[0018] According to one embodiment, the device has an RF antenna integrated in the first section of the (CMOS) chip. By means of the RF antenna, data can be transmitted between the device and an external unit. The RF antenna is used, for example, for communication with the external unit or other external devices. According to one embodiment, the (CMOS) chip has a thickness, i.e., an extension perpendicular to a plane in which the plurality of optical elements is arranged, of a maximum of 100 pm, 90 pm, 80 pm, 70 pm or down to 20 pm. This achieves a high degree of flexibility of the device, so that it can follow the shape of the cochlea. Thus, damage within the cochlea during insertion of the device can be reduced, whereby a high hearing quality can be achieved with the device after its implantation.

[0019] According to one embodiment, the device has at least one beam-shaping element, e.g. a lens, such as a convex lens or a converging lens. The (CMOS) chip has, for example, a first main surface, which, for example, the plurality of optical elements face. One optical element of the plurality of optical elements is designed to couple out light via the first main surface within an emission region, and the at least one beam-shaping element is arranged or fixed on the first main surface in the emission region and is designed, for example, to shape, bundle, and / or focus the light of the optical element. In a plan view, for example, the beam-shaping element and the optical element are arranged to completely overlap.The beam-shaping element and the optical element are aligned, for example, along the same axis, wherein the axis represents, for example, an axis of symmetry of the beam-shaping element and the optical element. Optionally, the device has a beam-shaping element for each of the plurality of optical elements, i.e. the device has a plurality of beam-shaping elements. Between two adjacent beam-shaping elements of the plurality of beam-shaping elements, for example, an diaphragm, e.g. an opaque element, is arranged. The auditory nerve can be stimulated in a very targeted manner by means of the beam-shaping element. This makes it possible to reduce the distance between the optical elements of the plurality of optical elements because the light is provided in a very focused manner and thus the emitted light from two adjacent optical elements does not overlap or only slightly overlaps.This allows the optical elements to be positioned close together and yet still stimulate individual groups of nerve cells in the auditory nerve, thus achieving a high frequency resolution in the user's auditory perception.

[0020] According to one embodiment, the (CMOS) chip has a first main surface and a second main surface opposite the first main surface. The (CMOS) chip has a transparent or semi-transparent region for coupling out light from the plurality of optical elements via the first main surface and the second main surface, i.e., the (CMOS) chip is transparent or semi-transparent in one or more regions. The material of the COMS chip is, for example, translucent / transparent in this region or these regions.

[0021] According to one embodiment, the optical elements of the plurality of optical elements are configured to emit light in two opposite directions. When the device is inserted into the cochlea, the device winds around the auditory nerve. However, the device may twist in the process, which may result in the optical elements in a certain area not facing the auditory nerve, thereby reducing the stimulation quality in that area. This can be counteracted by emitting light in two opposite directions according to the invention. This ensures that the device achieves a high stimulation quality even if the (CMOS) chip is twisted within the cochlea.

[0022] According to one embodiment, the (CMOS) chip is formed as a layer stack, with the plurality of optical elements arranged in a first layer of the layer stack, and the at least one driver circuit arranged in a second layer of the layer stack. Additional layers can be arranged between the first layer and the second layer.

[0023] According to an alternative embodiment, the (CMOS) chip is formed as a layer stack, and the plurality of optical elements comprises a first set of optical elements and a second set of optical elements. The first set of optical elements is arranged in a first layer of the layer stack, and the second set of optical elements is arranged in a second layer of the layer stack. The optical elements of the first set of optical elements face a first main surface of the (CMOS) chip, and the optical elements of the second set of optical elements face a second main surface of the (CMOS) chip, wherein the second main surface corresponds to a surface of the (CMOS) chip opposite the first main surface. Thus, the optical elements of the first set emit light in the opposite direction to the optical elements of the second set.Similar to what was already explained above for bilaterally emitting optical elements, this design also makes it possible for the device to achieve a high stimulation quality even when the (CMOS) chip is rotated within the cochlea, since the special arrangement of the optical elements means that the stimulation light is coupled out on two opposite sides of the (CMOS) chip. It is particularly advantageous if the optical elements of the first set are aligned with the optical elements of the second set so that, for example, one axis, e.g. an axis of symmetry, of an optical element of the first set coincides with one axis, e.g. an axis of symmetry, of an optical element of the second set. Thus, for example, one optical element of the first set and one optical element of the second set are located opposite each other within the (CMOS) chip.

[0024] According to one embodiment, the at least one driver circuit is arranged in a third layer of the layer stack, wherein the third layer is arranged between the first layer and the second layer. Optionally, for example, two opposing optical elements always share an intermediate driver circuit. As a result, the driver circuit is arranged very close to the optical elements to be controlled, which allows for advantageous dynamics, in particular a high duty cycle, to be achieved.

[0025] According to one embodiment, the at least one driver circuit at least partially overlaps, in a plan view, with at least one of the plurality of optical elements. Alternatively, the at least one driver circuit is arranged, in a plan view, between two optical elements of the plurality of optical elements arranged adjacently within a plane or layer. By means of this special arrangement, the driver circuit is arranged very close to the optical elements to be controlled, whereby advantageous dynamics, in particular a high duty cycle, can be achieved.

[0026] Short character description

[0027] Some exemplary embodiments are illustrated in the drawings and explained below. They show:

[0028] Fig. 1 is a schematic representation of a device for stimulating an auditory nerve;

[0029] Fig. 2 is a schematic representation of a device for stimulating an auditory nerve with a CMOS chip designed as a layer stack;

[0030] Fig. 3 is a side sectional view of a CMOS chip of a device for stimulating an auditory nerve;

[0031] Fig. 4 is a side sectional view of a CMOS chip of a device for stimulating an auditory nerve with beam-forming elements; Fig. 5 is a side sectional view of a CMOS chip of a device for stimulating an auditory nerve with transparent regions;

[0032] Fig. 6 is a side sectional view of a CMOS chip of a device for stimulating an auditory nerve with double-sided emitting optical elements;

[0033] Fig. 7 is a side sectional view of a CMOS chip of a device for stimulating an auditory nerve with two sets of optical elements arranged on opposite sides; and

[0034] Fig. 8 is a plan view of a device for stimulating an auditory nerve.

[0035] Detailed description of the embodiments according to the figures

[0036] Examples of the present disclosure are described in detail below using the accompanying descriptions. Many details are described in the following description to provide a more thorough explanation of examples of the disclosure. However, it will be apparent to those skilled in the art that other examples may be implemented without these specific details. Features of the various described examples may be combined with one another unless features of a corresponding combination are mutually exclusive or such a combination is expressly excluded.

[0037] It should be noted that identical or similar elements, or elements having the same functionality, may be provided with identical or similar reference symbols or be designated alike. A repeated description of elements that are provided with the same or similar reference symbols or are designated alike is typically omitted. Descriptions of elements that have the same or similar reference symbols or are designated alike are interchangeable or applicable to one another.

[0038] To facilitate the description of the various embodiments, some of the figures feature a Cartesian coordinate system x, y, z, where the xy plane corresponds to, i.e., is parallel to, a main surface of a substrate (= a reference plane = xy plane), the vertically upward direction relative to the reference plane (xy plane) corresponding to the "+z" direction, and the vertically downward direction relative to the reference plane (xy plane) corresponding to the "-z" direction. In the following description, the term "lateral" means a direction parallel to the x and / or y direction, i.e., parallel to the x-y plane, and the term "vertical" means a direction parallel to the z direction.

[0039] Furthermore, optical radiation is described here using light as an example, for example, radiation in a spectrum visible to humans. However, optical radiation in other wavelength ranges can also be used with the device.

[0040] Fig. 1 schematically shows a device 100 for stimulating 10 an auditory nerve 20. In Fig. 1, the device is at least partially inserted into a cochlea 30. The cochlea 30 is shown cut open in Fig. 1 to visualize the positioning of the device 100 within the cochlea.

[0041] The device 100 has a CMOS chip 110 in which a plurality of optical elements 120 and a driver circuit 130 are integrated.

[0042] The device 100 can, for example, be divided into two sections. A first section 112 of the device 100 can be inserted into the cochlea 30, and a second section 114 of the device 100 can be positioned outside the cochlea 30. The second section 114 is located, for example, behind the user's ear beneath the skin. The first section 112 and the second section 114 form an inseparable unit, i.e., they share a substrate of the CMOS chip 110. The complete device 100 is implantable.

[0043] The plurality of optical elements 120 is arranged in the first section 112. The optical elements 120 of the plurality of optical elements 120 are configured to emit or radiate light 122 in order to stimulate the auditory nerve 20. The optical elements 120 of the plurality of optical elements 120 are arranged linearly in the CMOS chip 110, for example. The plurality of optical elements 120 form a linear stimulation array in the CMOS chip 110, for example. In Fig. 1, for example, no distance is shown between the optical elements 120 of the plurality of optical elements 120. However, it is clear that the optical elements 120 of the plurality of optical elements 120 can also be arranged at a distance from one another within the CMOS chip 110.

[0044] The driver circuit 130 is arranged, for example, in the second section 114 of the device 100 in Fig. 1. However, it may be advantageous if it is also arranged in the first section 112, in the vicinity of the plurality of optical elements 120. The driver circuit 130 is designed to control the plurality of optical elements 120. Individual optical elements 120 of the plurality of optical elements 120 can be controlled individually, or several optical elements 120 of the plurality of optical elements 120 can be controlled simultaneously. Fig. 1 shows, by way of example, the simultaneous control of three optical elements 120.

[0045] Furthermore, it is possible for the device 100 to have multiple driver circuits 130 and not just one. According to one embodiment, the device 100 can, for example, have a plurality of driver circuits 130, wherein each optical element 120 of the plurality of optical elements 120 is assigned a driver circuit 130 of the plurality of driver circuits 130. The driver circuits 130 of the plurality of driver circuits 130 are designed to control the optical element 120 assigned to the respective driver circuit 130. It is particularly advantageous if the plurality of driver circuits 130 is arranged in the first section 112 and not in the second section 114. For example, an optical element 120 and a driver circuit 130 assigned to this optical element 130 can be arranged in close proximity to one another within the CMOS chip.

[0046] According to one embodiment, a protective layer, e.g., a biocompatible protective layer, is arranged around the CMOS chip 110, i.e., the CMOS chip is encapsulated. The protective layer is transparent or semi-transparent at least in certain regions, e.g., at the emission windows of the optical elements 120 or in the entire first section 112, so that the light 122 of the plurality of optical elements 120 can be coupled out of the device 100.

[0047] According to one embodiment, the device 100 has a round cross-section. A maximum diameter of the device 100 is 120 pm, 110 pm, 100 pm, or 90 pm. This achieves a high degree of flexibility of the device 100, so that it can follow the shape of the cochlea 30. A maximum diameter of 120 pm, 110 pm, 100 pm, or 90 pm enables a spiral bending of the device 100 and facilitates insertion of the first section 112 into the cochlea 30. Optionally, only the first section 112 of the device 110 has a maximum diameter of 120 pm, 110 pm, 100 pm, or 90 pm, and the second section 114 can also be realized with a larger diameter or other dimensions. However, it is particularly advantageous if the first section and the second section 114 have the same dimensions, e.g., the same diameter or the same width and height. Further details of the device 100 are presented below.The device 100 may have features and / or functionalities as illustrated in connection with Figures 2 to 8.

[0048] An arrangement according to the invention, e.g., device 100, comprises only a single flexible CMOS chip 110, which in turn comprises a plurality of optically stimulating elements, e.g., optical elements 120, and optionally further components, e.g., driver circuits 130. Fig. 2 illustrates this basic arrangement in a schematic cochlea 30. The advantage of this new arrangement as a single CMOS chip 110 eliminates a number of design problems of hybrid approaches.

[0049] In addition to CMOS, other manufacturing technologies could of course also be used.

[0050] Fig. 2 shows, by way of example, how a plurality of optical elements 120 and a plurality of driver circuits 130 can be integrated into a layer stack of the CMOS chip 110. Each driver circuit 130 and an optical element 120 associated with the driver circuit 130 form, for example, an electro-optically active element, i.e., an active stimulation element 140. A linear array of stimulation elements 140 is arranged in the CMOS chip 110, for example. The array of stimulation elements 140 forms, for example, a stimulation unit of the device 100.

[0051] According to the embodiment in Fig. 2, the device 100 can be implanted completely within the cochlea 30. Optionally, however, it is also possible for the device 100, as described in connection with Fig. 1, to further comprise a second portion that can be positioned outside the cochlea 30.

[0052] The optically stimulating elements, i.e., the optical elements 120, are embodied, for example, as an integrable light source. These can be, for example, organic LEDs (light-emitting diodes), pLEDs, or QDs (quantum dots).

[0053] The required flexibility of the substrate is achieved, for example, by a thinning process. For this purpose, the silicon CMOS chip 110 is thinned, for example, to a thickness 116 significantly below 10 μm. The thickness of the CMOS chip 110 should, for example, be in a range of 10 μm-100 μm, 10 μm-70 μm, 10 μm-50 μm, 30 μm-100 μm, 30 μm-80 μm, or 30 μm-60 μm. A possible lower limit can be 10 μm or 20 μm. Figures 3 to 7 show exemplary detailed views or enlarged schematic sections of the CMOS chip 110 of the device 100 from Fig. 1 and / or the device 100 from Fig. 2.

[0054] In Figures 3 to 7, the CMOS chip is embodied as a layer stack. Each shows a schematic representation of a cross section through two electro-optically active elements 140 of the device 100. An electro-optically active element 140 has at least one optical element 120 and a driver circuit 130, which are arranged, for example, in different layers of the layer stack. The optical elements 120 of the plurality of optical elements 120 are arranged, for example, in a first layer 1111, and the driver circuits 130 of the plurality of driver circuits 130 are arranged, for example, in a second layer 1111 of the layer stack of the CMOS chip 110.

[0055] The CMOS chip 110 has, for example, a first main surface 113i. The optical elements 120 of the plurality of optical elements 120 face the first main surface 113i. The optical elements 120 of the plurality of optical elements 120 are designed, for example, to couple light 122 out of the CMOS chip 110 via the first main surface. Opposite the first main surface 113i, the CMOS chip 110 has a second main surface 1132, which lies, for example, in the reference plane (xy plane). The first layer 111i lies above the second layer 1112 in the layer stack direction, i.e., in the +z direction. The plurality of optical elements 120 are thus arranged within the layer stack between the first main surface 113i and the plurality of driver circuits 130.

[0056] The optical elements 120 of the plurality of optical elements 120 and the driver circuits 130 of the plurality of driver circuits 130 can, for example, be arranged in their respective layers such that a driver circuit 130 and the associated optical element 120 are always arranged one above the other. In a plan view, for example, the driver circuit 130 and the associated optical element 120 overlap at least partially or completely. In Figures 3-5, the outer edges of the driver circuit 130 and the associated optical element 120 are, for example, in alignment. However, this is not absolutely necessary, as can be seen, for example, in Figures 6 and 7. For example, the axis of symmetry of the driver circuit 130 can be offset from the axis of symmetry of the optical element. Further layers I H3 can be arranged between the first layer I H2 and the second layer I H2.These layers I H3 are, for example, insulation layers in which electrical connections can be arranged. These layers I H3 can, for example, have connection or wiring levels 160. Optionally, these layers 1113 can have transparent or semi-transparent material. The layers 1113 represent, for example, transparent insulation layers. Only the connection or wiring levels 160 are made of electrically conductive material, for example, which is not transparent.

[0057] The first layer 1111 corresponds, for example, to an optically active element, such as OLED (organic LED) or uLED (Ultra LED), with a plurality of pixel electrodes, i.e., the optical elements 120.

[0058] The second layer 1112 is, for example, a layer with electrically active components, e.g., CMOS transistors. A driver circuit 130 is formed, for example, from a plurality of electrically active components within the second layer 1 H2.

[0059] A typical driver circuit consists of several active CMOS transistors and, depending on the driver concept, implements a current or voltage source that supplies the optically active element with electrical energy. This current or voltage control can also be combined with a modulation method. This can be, for example, a time-controlled pulse width modulation or another type of modulation with different signal shapes (e.g., sine, triangle, etc.).

[0060] The second layer 1112 can, for example, be arranged on a carrier substrate 1114, e.g., made of silicon material, e.g., a wafer substrate, see Figures 3 and 4. Optionally, the carrier substrate 1114 can also be removed, as can be seen, for example, in Figures 5 to 7. This makes the arrangement 200 partially transparent 152. The CMOS chip 110 thus has transparent regions 150 and non-transparent regions, e.g., the regions in which the electro-optically active elements 140 are arranged. As a result, the light from the optical elements 120 can not only be coupled out of the first main surface 113i, but can also be guided through the CMOS chip 110 and coupled out of the second main surface 1132.

[0061] Optionally, the CMOS chip 110 has an encapsulation layer 111s, e.g., a protective layer. The encapsulation layer 111s is, e.g., made of transparent or semi-transparent material. Optionally, the material of the encapsulation layer 111s is also biocompatible. The encapsulation layer 1115 protects, on the one hand, the device 100 from external influences and, on the other hand, the user from harmful influences caused by the device 100. The encapsulation layer 1115 is arranged, e.g., in the layer stacking direction, i.e., +z direction, directly adjacent to the first layer 1111. A surface of the encapsulation layer 1115 facing away from the first layer 1111 corresponds, e.g., to the first main surface 113i.

[0062] In order to achieve good light power transmission to the auditory nerve, the arrangement can be supplemented by further beam-shaping elements 170, for example microlenses or fiber optic components, as shown by way of example in Fig. 4. Such an arrangement reduces lateral optical scattering and thus improves the frequency resolution achieved in the ear. The beam-shaping elements 170 are arranged or fixed on the first main surface 113i of the CMOS chip 110. The optical elements 120 are designed, for example, to couple out light 122 via the first main surface 113i within a radiation area 124. The beam-shaping elements 170 are arranged at the radiation areas 124 and designed to shape 174 the light 122 of the respective optical element 120, for example, to bundle or focus it., in the layer stacking direction, one of a plurality of beam-shaping elements 170 is arranged or fixed above each of the plurality of optical elements 120. Between each two adjacent beam-shaping elements 170, an e.g., optically active, aperture 172, e.g., an opaque element, is optionally arranged. The apertures 172 are designed, for example, to reduce optical cross-coupling between the electro-optically active elements 140.

[0063] According to the embodiment in Fig. 6, semi-transparent pixel electrodes can be integrated into the CMOS chip 110 as the optical elements 120. As a result, the light 122 is emitted away from the arrangement 200 (see 122i), as well as through the arrangement 200 (see 1222). Thus, the light 122 can be coupled out both via the first main surface 113i and via the second main surface 1132. Transparent regions 150 and non-transparent regions with light emission upwards are formed, e.g., the regions in which the electro-optically active elements 140 are arranged, as well as partially transparent regions 154 with light emission upwards (see 122i), and downwards (see 1222).

[0064] The transparent regions 150 in the CMOS chip 110, for example, do not have any optical elements 120, any connection or wiring levels 160, or any driver circuit 130. The transparent regions are formed, for example, by the transparent material of the individual layers of the layer stack.

[0065] In the partially transparent regions 154, only the pixel electrode, i.e., the optical element 120, separates the layer stack into two transparent regions. The pixel electrode emits, for example, light 122 in two opposite directions, e.g., once toward the first main surface 113i and once toward the second main surface 1132. The two transparent regions separated from each other by the pixel electrode are formed, for example, by the transparent material of the individual layers of the layer stack. Partially transparent regions 154 are formed in the CMOS chip 110, for example, by the pixel electrode extending over a larger area in a plan view than a driver circuit 130 and / or connection or wiring levels 160 that at least partially overlap with the pixel electrode in the plan view.The overlap area is considered a non-transparent area, and the area beyond it defined by the pixel electrode is considered a partially transparent area 154.

[0066] Fig. 7 shows an alternative embodiment with an additional pixel electrode on the underside of the arrangement 200. For this purpose, a via 162, for example, is introduced into the layer with the active components, i.e., into the second layer 1112, in order to electrically connect the pixel electrode. In this case, the plurality of optical elements 120 comprises, for example, a first set of optical elements, see 120i, and a second set of optical elements, see 1202. The optical elements 120i of the first set of optical elements 120 are arranged, for example, in the first layer 1111, and the optical elements 1202 of the second set of optical elements 120 are arranged, for example, in a third layer 1116 of the layer stack. The second layer 1112 and optionally further layers 1113 are arranged between the first layer 1111 and the third layer 1116.According to one embodiment, two opposing optical elements 120 always share an intermediate driver circuit 130. According to Fig. 7, two optical elements 120 and a driver circuit 130 can thus form an electro-optically active element 140 within the CMOS chip 110.

[0067] According to one embodiment, all components of an electro-optically active element 140 are aligned with one another within the layer stack of the CMOS chip 110, so that they are arranged one above the other and, for example, occupy as little area as possible when viewed from above. Like the first layer 1111, the third layer 1116 can correspond to an optically active element, such as an OLED (organic LED) or uLED (ultra LED), with a plurality of pixel electrodes, i.e., the optical elements 120.

[0068] Optionally, a further encapsulation layer 1115 is arranged directly adjacent below the third layer 1116 in the layer stacking direction, i.e., the +z direction. This optionally encapsulates the CMOS chip 110. The further encapsulation layer 1115 is, for example, made of the same material as already described above in connection with the encapsulation layer H on the first layer 1111 and can also have the same properties. A surface of the encapsulation layer H5 facing away from the third layer 1116 corresponds, for example, to the second main surface 1132.

[0069] As can be seen in Fig. 7, transparent regions 150 and non-transparent regions, see 140, are formed. In the area of ​​the non-transparent regions, light 122 can be emitted from both sides in this structure, since, for example, the optical elements 120 of the first set of optical elements 120i face the first main surface 113i and the optical elements 1202 of the second set of optical elements 120 face the second main surface 1132.

[0070] The use of a CMOS chip 110 enables the integration of additional components, as can be seen in the schematic top view of the device 100 in Fig. 8. In addition to the driver circuit 130 (arranged below the optical elements 120) for the optical elements 120, other components can also be integrated, such as a speech processor / audio processor / sound processor 210, a data and / or energy transmission unit 220, e.g., a wireless interface for power supply and external data transmission or a row of contacts, e.g., for a direct connection, up to the integrated microphone 230. Optionally, alternatively or additionally, a wireless RF interface 240 and / or a fully integrated RF antenna 250 (radio frequency antenna) can be integrated. The RF antenna is used, for example, for communication with the external unit or other external devices. The positioning does not have to be in the area of ​​the stimulation units.Other possible positions are: Regarding the surroundings, positioning outside would probably be even more advantageous. Due to the greater length of the stimulation unit, positioning the antenna next to these might be advantageous (depending on the RF wavelengths used).

[0071] Such a "fully integrated" system could be implanted encapsulated in the ear. Any external connections and the associated potential infections could be completely avoided, for example, by implementing the wireless interface rather than the row of contacts.

[0072] The device 100 can have two sections, wherein a first section 112 can be inserted into the cochlea and a second section 114 can be positioned outside the cochlea.

[0073] The energy supply of the system, ie the device 100, can be realized by various variants:

[0074] • Self-sufficient energy harvesting from cellular energy, chemical energy or kinetic energy, generally “bio-energy”

[0075] • Externally supplied by energy coupled directly into the chip or package, e.g. via: o Electric field o Magnetic field o Light, preferably infrared o Mechanical

[0076] The present invention describes a fully integrated cochlear implant, ie, the device 100. The core of the invention is the very high integration density of elements for stimulating the auditory nerve, ie, the optical elements 120, a corresponding signal processing, e.g., the speech processor / audio processor / sound processor 210, as well as a wireless interface 220 for data transmission in a single, encapsulated chip, while simultaneously being implantable in the ear canal.

[0077] General advantages:

[0078] • Complex process is drastically simplified

[0079] • Standard semiconductor technology processes are used

[0080] • Single substrate for all components, no AVT required

[0081] • Integrated approach enables more optical elements and thus frequency resolution

[0082] • Light sources can be positioned very close to each other, ie higher density of light sources per mm possible than with pLEDs

[0083] • Light can be coupled out on both sides of the CMOS chip Further embodiments of the device 100 described above are set out below, which can be included individually or in combination in the embodiments described above.

[0084] One embodiment relates to an optoelectronic hearing aid, ie, device 100, which enables direct stimulation of the auditory nerve in the event of inner ear damage. Device 100 has an active, optically stimulating component (see 140 in Figures 3 to 7), which is directly integrated onto a CMOS chip 110. Furthermore, device 100 has additional integrated electronics for preprocessing and controlling the active optical components (see 140). The overall system, ie, device 100, is highly flexible, ie, the thickness of CMOS chip 110 is less than 100 μm.

[0085] In addition to the active optical components (see 140), further passive optical components can be integrated into the CMOS chip 110. Possible embodiments for these passive optical components are optical filters that change the spectral behavior or polarization of the generated light 122. Examples include absorption filters, dielectric mirrors, metal grating filters, plasmonic filters, etc.

[0086] The active, optically stimulating elements are partially or completely supplemented by additional electrical ones.

[0087] For example, parts of the integrated electronics lack flexibility.

[0088] The integrated electronics comprises, for example, acoustic data preprocessing, see 210 in Fig. 8, a wireless interface (e.g. inductive or optical) for data transmission and / or power supply, see 220 in Fig. 8, and / or a microphone, see 230 in Fig. 8.

[0089] According to one embodiment, the integrated electronics are supplemented by an electrical energy storage device integrated in the CMOS chip 110.

[0090] The entire system may additionally include an encapsulation layer. The encapsulation layer 111s discussed in Figures 3 to 7 may, for example, enclose or encapsulate the entire CMOS chip 110.

[0091] The flexible CMOS chip 110 is partially transparent. A technology other than CMOS, such as TFTs (e.g., a-Si, LTPS, IGZO, organic field-effect transistors), III-V semiconductors, SiC, etc., is used as the active driver circuit.

[0092] The device 100 can have an additional element for bio-energy generation (“bio-energy harvester”) for an autonomous power supply of the entire system.

[0093] The energy required for the device 100 is introduced, for example, from external sources directly into the chip or package.

[0094] The above-described embodiments are merely illustrative of the principles of the present invention. It is understood that modifications and variations of the arrangements and details described herein will be apparent to others skilled in the art. Therefore, it is intended that the invention be limited only by the scope of the following claims and not by the specific details presented in the description and explanation of the embodiments herein.

[0095] References

[0096] [1] Adam Kissiah, Implantable Electronic Hearing Aid, Patent US000004063048, 1978

[0097] [2] Dieter et al., “pLED-based optical cochlear implants for spectrally selective activation of the auditory nerve,” EMBO Molecular Medicine, 2020

[0098] [3] Keppeler et al., „Multichannel optogenetic stimulation of the auditory pathway using microfabricated LED cochlear implants in rodents”, SCIENCE TRANSLATIONAL MEDICINE, 2020

Claims

Patent claims 1. A device (100) for stimulating (10) an auditory nerve (20), comprising a chip (110); a plurality of optical elements (120) for stimulating the auditory nerve (20); and at least one driver circuit (130) for controlling the plurality of optical elements (120); wherein the plurality of optical elements (120) and the at least one driver circuit (130) are integrated in the chip (110).

2. Device (100) according to claim 1, wherein the chip (110) is implemented as a CMOS chip.

3. Device according to claim 1 or claim 2, wherein the chip (110) comprises a TFT, in particular a-Si, LTPS or IGZO with or without an organic field effect transistor, or a III-V semiconductor material or SiC material.

4. Device (100) according to one of claims 1 to 3, wherein the device (100) has for each of the plurality of optical elements (120) a driver circuit (130) for controlling the respective optical element (120), which is integrated in the chip (110).

5. Device (100) according to one of claims 1 to 4, wherein the chip (110) further integrates one or more of the following components: a speech processor (210), a wireless interface (220), a microphone (230), and a power supply for providing energy obtained from electromagnetic energy, optical energy, cellular energy, chemical energy, thermal energy or kinetic energy.

6. The device (100) of claim 5, wherein the chip (110) has a first portion (112) configured to be inserted into a cochlea (30) and a second portion (114) configured to be arranged outside the cochlea (30), and wherein the plurality of optical elements (120) and the at least one driver circuit (130) are integrated in the first portion (112) of the chip (110) and wherein the one or more components are integrated in the second portion (114) of the chip (110).

7. Device (100) according to one of claims 1 to 6, comprising an RF antenna (250) integrated in the chip (110).

8. Device (100) according to one of claims 1 to 7, wherein the chip (110) has a thickness (116) of at most 100 pm.

9. Device (100) according to one of claims 1 to 8, with at least one beam-shaping element (170), wherein the chip (110) has a first main surface (113i), wherein an optical element (120) of the plurality of optical elements (120) is designed to couple out light (122) via the first main surface (113i) within an emission region (124), wherein the at least one beam-shaping element (170) is arranged in the emission region (124) on the first main surface (113i).

10. Device (100) according to one of claims 1 to 9, wherein the chip (110) has a first main surface (113i) and a second main surface (1132) opposite the first main surface, and wherein the chip (110) has a transparent or semi-transparent region for coupling out light from the plurality of optical elements (120) via the first main surface (113i) and via the second main surface (1132).

11. The device (100) according to any one of claims 1 to 10, wherein the optical elements (120) of the plurality of optical elements (120) are configured to emit light in two opposite directions.

12. Device (100) according to one of claims 1 to 11, wherein the chip (110) is designed as a layer stack and the plurality of optical elements (120) is arranged in a first layer (1111) of the layer stack and the at least one driver circuit (130) is arranged in a second layer (1112) of the layer stack.

13. The device (100) according to one of claims 1 to 12, wherein the chip (110) is formed as a layer stack, wherein the plurality of optical elements (120) comprises a first set of optical elements (120) and a second set of optical elements (120), and wherein the first set of optical elements (120) is arranged in a first layer (1111) of the layer stack, facing a first main surface (113i) of the chip (110), and wherein the second set of optical elements (120) is arranged in a second layer (1116) of the layer stack, facing a second main surface (1132) of the chip (110), wherein the second main surface (1132) corresponds to a surface of the chip (110) opposite the first main surface (113i).

14. The device (100) of claim 13, wherein the at least one driver circuit (130) is arranged in a third layer (1112) of the layer stack, and wherein the third layer (1112) is arranged between the first layer (1111) and the second layer (111 e).

15. Device (100) according to one of claims 1 to 14, wherein in a plan view the at least one driver circuit (130) at least partially overlaps with at least one of the plurality of optical elements (120) or wherein in the plan view the at least one driver circuit (130) is arranged between two adjacently arranged optical elements (120) of the plurality of optical elements (120).

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