Device and method for a similarity evaluation

Abstract

The invention relates to a device for carrying out a similarity evaluation for an attention mechanism with: a capacitor (C1) for storing a key (K); an input for a query (Q); a comparator (Com) for comparing a query (Q); a key (K) stored in the capacitor (C1), wherein the comparator (Com) outputs an analogue similarity value (S) as the result of the comparison. The invention also relates to a method for carrying out a similarity evaluation using a device claimed, wherein keys (K) are stored in capacitors (C1), a query (Q) is then compared with the stored keys (K) by comparators (Com) in order to obtain a similarity. Similarity evaluations can be carried out quickly and efficiently.

Description

[0001] Apparatus and method for similarity assessment

[0002] The invention relates to a device and a method for carrying out a similarity assessment.

[0003] Similarity assessments are performed using an attention mechanism (better known as "attention"). Using an attention mechanism, the efficiency of a machine learning model can be improved. An attention mechanism pays special attention to certain parts of a query or input data when generating the output data. An attention ("attention") is determined for this. The following equation can be used to determine attention.

[0004] (OK T \

[0005] Attention(Q, K, V") = softmax I — =- IV

[0006] \ Vdk ) with

[0007] Q = Query

[0008] K = Key

[0009] V = Value.

[0010] The equation performs a similarity assessment between queries (Q) and keys (K) to weight the information of the value (V). K can be sequence elements from the future, present, and past, while Q is the current input data.

[0011] Attention weights are calculated using scaled dot product similarities. The scaled dot product measures similarity. The softmax function converts the results into attention weighting probabilities.

[0012] The above equation for Attention(Q,K,V) outputs a weighted sum of values ​​that allows for focusing on the important parts of a query. Attention is the ability to focus on specific information while ignoring irrelevant parts. In machine learning, attention is used to train models to focus on important elements of the input data in order to improve task performance.

[0013] Transformers are based on the attention mechanism. A transformer allows a computer to translate one sequence of characters into another. For example, a text can be translated from one language to another. To do this, a transformer is trained using machine learning on sample data. The trained model can then be used for translation.

[0014] Attention in transformers requires very large matrix operations that consume a lot of power.

[0015] Against this background, the aim of the present invention is to be able to perform similarity searches in a technically efficient manner. In particular, it should be possible to determine an attention (Q, K, V) quickly and with low energy expenditure. It should preferably be possible to perform dynamic, frequently changing similarity searches.

[0016] A device for solving the problem may comprise the features of the first claim. The secondary claim relates to a method for similarity search.

[0017] A device for performing a similarity assessment for an attention mechanism may comprise a capacitor for storing a key (K). Such a device may comprise an input for a query. Such a device may comprise a comparator for comparing a query with a key stored in the capacitor. The comparator may, in particular, output an analog similarity value as the result of the comparison.

[0018] A capacitor can temporarily store electrical charge. A capacitor comprises two electrically conductive elements that are electrically separated from each other. The electrically conductive elements can be two electrically conductive layers. The two electrically conductive layers can be separated by an electrically non-conductive layer. The electrically non-conductive layer can be a dielectric. The layers can be parallel to each other. "To store a key" means that the device is configured so that a predetermined electrical charge can be stored in the capacitor as a measure of a key.

[0019] A voltage can be applied to the input of the device intended for a query as a measure for the query.

[0020] A comparator is an electronic circuit with two inputs for two voltages that can be compared by the comparator. The device is configured so that the comparator can compare a voltage applied to the input of the device as a query with the voltage of the capacitor, which is present due to an electrical charge stored as a key.

[0021] The comparator can have an output through which a signal can be output as the result of the comparison. The signal can be a voltage.

[0022] The signal can be a digital signal. The voltage curve dependent on the comparison then has such a steep edge that, in practice, only a distinction is made between a "low" and a "high" signal. The signal can be an analog signal. The voltage curve dependent on the comparison then does not have a steep edge, so that signals lying between the "high" and "low" signals are also recorded.

[0023] The comparator can have two electrical connections for a voltage supply.

[0024] One input of the comparator can be a positive, non-inverting input. The other input of the comparator can be a negative, inverting input. If a voltage applied to the positive, non-inverting input is higher than a voltage applied to the negative, inverting input, a positive voltage can be output as a signal. If a voltage applied to the positive, non-inverting input is lower than a voltage applied to the negative, inverting input, a negative voltage can be output as a signal.

[0025] The comparator can output a signal in digital or analog form as the result of the comparison. The comparator is preferably configured to output an analog similarity value in the form of an analog voltage as the result of the comparison.

[0026] The comparator can therefore at least output as a signal whether a voltage applied as a query is greater and / or smaller than a voltage generated by a charge stored as a key in the capacitor.

[0027] The device may comprise a multiplier that multiplies the similarity value by a value and outputs an attention as a result of the multiplication.

[0028] The multiplier may, for example, comprise an analog-to-digital converter that digitizes the similarity value. The multiplier may comprise a processor that multiplies the digitized similarity value by a digitized value such that an attention (Attention(Q,K,V)) is output as the result of the multiplication. A digital result is then output as the attention.

[0029] The multiplier can also be an analog multiplier, which multiplies the similarity value by the value to obtain attention. This can be implemented using a so-called "crossbar array" or a "memristor crossbar array" (see https: / / doi.org / 10.1038 / s41467-021-23719-3). An alternative is a transimpedance amplifier.

[0030] Attention refers to a value that is at least equal to Attention(Q,K,V). The result is equal to the calculated value Attention(Q,K,V) or at least close enough to be used, for example, for transformers.

[0031] The capacitor can be connected via a switch to a digital-to-analog converter for storing a key (K). The switch and capacitor can then form a memory cell. By turning on the switch, the capacitor can be written to. By turning on the switch, the capacitor can be electrically charged. Once the capacitor has been charged to the desired level, the switch can be turned off. The capacitor then stores the electrical charge temporarily. The digital-to-analog converter can convert a digitized key into an analog signal in the form of a voltage. If the switch is then opened, the capacitor is charged according to the voltage provided by the digital-to-analog converter and thus in the desired way.

[0032] The value to be stored can come directly from a previously performed analog operation, such as a vector matrix multiplication of a memristor crossbar array. These vector matrix multiplications are the linear projections that, in the case of a transformer, calculate the vectors Q, K, and V.

[0033] The switch can be a transistor. The transistor can be switched on and off by a voltage source. If the transistor is switched on, a current can flow through it. The capacitor can then be charged. If the transistor is switched off, no current can flow through it. The capacitor cannot be charged. Therefore, depending on the switching state of the transistor, a key (K) can be stored in the capacitor in the form of an electrical charge.

[0034] One input of the comparator can be connected to a digital-to-analog converter for comparing a query with a key stored in the capacitor. The digital-to-analog converter can convert a digitized query into an analog electrical signal, which can then be presented as a voltage. This voltage can then be compared with the voltage generated by the electrical charge stored in the capacitor.

[0035] A digital-to-analog converter can be present, which is connected to the capacitor via a switch for charging the capacitor, and to a comparator input for a query, on the other hand. A digital-to-analog converter can then be used both for charging the capacitor and for performing a query. The number of digital-to-analog converters used is thus kept to a minimum. The digital-to-analog converter can be directly connected to one of the comparator inputs via an electrical line. In the case of a direct connection, there is only the electrical line for the connection.

[0036] The capacitor is preferably a MOM capacitor so that the device can be manufactured as a chip or integrated circuit. MOM stands for "metal oxide metal." An alternative is the silicon capacitor, which can be used directly in integrated circuits and whose production is based on standard semiconductor manufacturing processes. The device is preferably designed as an integrated circuit to allow for very small device sizes.

[0037] For reasons of compactness, the device may comprise one or more transistors and one or more capacitors in a first level. One or more transistors may be present in a second level. The second level is located above or below the first level. For reasons of compactness, at least one transistor of the device is arranged on a capacitor and thus in the second level. This is possible, for example, if the transistor is a MOM capacitor.

[0038] For mass production, it is preferable that the device, or at least parts of it, be manufactured using a DRAM manufacturing process. DRAM stands for Dynamic Random Access Memory. A DRAM capacitor is then not a MOSFET capacitor. The transistor of a DRAM can be a MOS field-effect transistor. A capacitor can then be integrated into a transistor. A DRAM can be implemented as an individual integrated circuit or as a memory cell in a larger chip.

[0039] A capacitor can be layered or "stacked" on a substrate. Multilayer and cylindrical capacitors can be used to provide large capacitance. A capacitor can be manufactured by drilling a deep hole or "trench" into a substrate.

[0040] Two transistors can be used to read a query. The two transistors can be connected in series. It may be possible for the two transistors to be switched by the comparator. The electrical resistance of the series-connected transistors can then be a measure of the query result. For example, this makes it possible to implement a CAM cell with only one comparator.

[0041] To determine the electrical resistance of the series-connected transistors, the current flowing through them can be measured. The current strength then serves as a measure of the test result.

[0042] The device can be connected so that the electrical resistance of the series-connected transistors is minimal when a query matches a stored key. The greater the electrical resistance of the series-connected transistors, the less a query matches a stored key.

[0043] The device can be connected so that the electrical resistance of the series-connected transistors is maximum when a query matches a stored key. The smaller the electrical resistance of the series-connected transistors, the less likely a query matches a stored key.

[0044] One transistor may be an N-channel MOSFET. In an N-channel MOSFET, the conducting channel consists of an N-type semiconductor, meaning it conducts electrons. The N-type semiconductor is located between two P-type semiconductors. One P-type semiconductor is the source terminal of the N-channel MOSFET. The other P-type semiconductor is the drain terminal of the N-channel MOSFET. The on state of the N-channel MOSFET can be activated by a positive voltage at the gate terminal of the N-channel MOSFET. For switching, the output of the comparator is therefore connected to the gate terminal of the transistor.

[0045] The other transistor can be a P-channel MOSFET. In a P-channel MOSFET, the conducting channel consists of a P-type semiconductor, which means it conducts through defects or holes. The P-type semiconductor is located between two N-type semiconductors. The N-type semiconductors are the source and drain terminals, respectively. If the voltage at the gate terminal of a MOSFET is identical to the voltage at the source terminal of the MOSFET, then the transistor is blocked. No current can flow between the drain terminal and source terminal (apart from a leakage current of a few microamperes). If a voltage lower than the voltage at the source terminal is applied to the gate terminal by the comparator, the transistor can conduct. The drain terminal and source terminal are then electrically connected.

[0046] The device can be configured so that the result of a query can be converted into an electrical current. To achieve this, the comparator output can, for example, be connected to the two aforementioned transistors in such a way that the two transistors can be switched via the comparator output. The current can then flow through the two transistors. The current intensity depends on the electrical resistance of the series-connected transistors. One transistor may be sufficient, and can be switched across the comparator output. The electrical resistance of one transistor then regulates the current intensity that can flow through the transistor.

[0047] There may be a measuring device that can determine the strength of the flowing current.

[0048] The device may include a CAM cell. The CAM cell may be an analog CAM cell.

[0049] CAM is an abbreviation for "Content-Addressable Memory." Unlike conventional memory types such as RAM (Random Access Memory), where data is accessed via the memory address, a CAM allows data to be accessed based on its content. This means that you can search for specific data in a CAM without knowing the exact memory address. This is often referred to as "associative memory." It is possible to apply an input signal to a CAM. The input signal can be a voltage applied to the CAM, and thus an analog signal. The CAM can then output whether the input signal is stored or not. This can be done, for example, by outputting a "0" or a "1," i.e., by outputting a digital value. For example, a CAM can output the value "0" if the entered memory value is not stored in the associative memory.A CAM can output the value “1” if the entered memory value is stored in the CAM.

[0050] An analog CAM cell can also indicate how similar a query is to a stored key. Examples of analog CAM cells are described in German patent application 102023205689.5.

[0051] A CAM cell can be such that the CAM cell can determine whether a query Q lies within a window corresponding to a key K. The width of a window can determine the tolerance with which K is treated. An analog CAM cell can also be such that the CAM cell can determine whether a query Q is similar to a window corresponding to a key K. A window is a range. If the query is in the form of a voltage, the CAM cell can at least determine whether the voltage lies within a range called a window. The analog CAM cell can comprise a first circuit with a first capacitor for storing a key. The first circuit can comprise a first input for a query. The first circuit can comprise a first comparator for comparing a query with a key stored in the first capacitor.The first comparator can output an analog similarity value for a query as the result of the comparison. One terminal of the first capacitor can be connected to an input of the first comparator. The other terminal of the first capacitor can be connected to a first switch of the first circuit for charging. The other terminal of the first capacitor can be connected to a digital-to-analog converter for charging, either directly or indirectly via the first switch. The first capacitor can be a transistor, such as a MOSFET. The first comparator can output whether a query is greater than a stored key.

[0052] The analog CAM cell can comprise a second circuit with a second capacitor for storing a key. The second circuit can comprise a second input for a query. The second circuit can comprise a second comparator for comparing a query with a key stored in the second capacitor. The second comparator can output an analog similarity value as the result of the comparison for a query. One terminal of the second capacitor can be connected to an input of the second comparator. The other terminal of the second capacitor can be connected to a second switch of the second circuit for charging. The other terminal of the second capacitor can be connected to a digital-to-analog converter for charging, directly or indirectly via the second switch. The second capacitor can be a transistor, such as a MOSFET.The second comparator can output whether a query is smaller than a stored key.

[0053] A key can match a query if the query results in the query being both greater and smaller than the respective stored keys, i.e. the query lies within a window. The boundaries of the window can be defined by stored keys and / or by the comparator. It may be sufficient for the CAM cell to only comprise a first circuit and no second circuit. For example, the CAM cell can be set up in such a way that in a first step it is queried whether a voltage VDL is stored and in a second step it is queried whether an inverted voltage -VDL is present. For example, it can be queried in this way whether a voltage DL intended as a query lies within a window that corresponds to a sought-after key K.

[0054] The device may comprise a plurality of CAM cells connected to an electrical line for reading. The current flowing through the electrical line may be a measure of a match between a query Q and keys K.

[0055] The invention also relates to a method for performing a similarity assessment. The method can be carried out using a device as described above. In a first step, one or more keys can be stored in one or more capacitors of the device. Subsequently, a query can be compared with the one or more stored keys by one or more comparators in order to obtain a similarity that The result of the comparison can be multiplied by a value (V) to obtain a result that is at least similar to a calculated attention (Attention(Q,K,V).

[0056] The object of the invention can be achieved through "in-memory processing" or "in-memory computing (IMC)." The equation for Attention(Q,K,V) mentioned above can be at least partially replaced.

[0057] While the result may not be completely identical to the result of the equation for Attention(Q,K,V) mentioned above, studies have shown that the deviations are at least small and therefore not critical. For certain use cases, the deviations are even advantageous.

[0058] The invention brings the computation of a similarity search using at least one dRAM CAM closer to an electronic memory. This improves efficiency and keeps energy consumption low. The invention performs a search operation, namely, a query Q is searched for in the keys K in accordance with the equation for Attention(Q,K,V) mentioned above.

[0059] A memristor-based CAM is not suitable for high-performance applications due to its low write speed (>100 ps) and limited lifetime (< 1e 8 ) is not well suited to solving the problem at hand. In comparison, the dRAM CAM according to the invention enables significantly higher write speeds. The service life is also significantly longer. Writing can be very fast because the result does not need to be verified.

[0060] The invention is explained in more detail below with reference to figures.

[0061] It shows

[0062] Figure 1: Device for carrying out a similarity assessment;

[0063] Figure 2: Implementation of part of a device for performing a

[0064] similarity assessment;

[0065] Figure 3: CAM cell;

[0066] Figure 4: Design of an integrated circuit;

[0067] Figure 5: CAM cell;

[0068] Figure 6: CAM cell;

[0069] Figure 7: CAM cell;

[0070] Figure 8: Comparator;

[0071] Figure 9: CAM cell.

[0072] Figure 1 schematically illustrates an example of a device for performing a similarity assessment. A query Q is compared with keys K by a device 1, which are stored in capacitors of the device 1. The device 1 outputs a similarity value S as the result of the comparison. The similarity value S is an analog value. The similarity value S is therefore a measure of the extent to which the query Q matches the keys K. The similarity value is multiplied by the value vector V by a device 2. This multiplication can be done digitally or analogically. The result is the attention Attention(Q, K, V). The attention thus obtained corresponds at least sufficiently accurately to the attention that can be calculated using the equation for Attention(Q, K, V) mentioned above and known from the prior art.

[0073] Figure 2 shows an implementation of part of a device for performing a similarity assessment. Using a digital-to-analog converter DAC, a capacitor C1 can be charged with a programmed electrical charge Vstored via a transistor M1. The programmed electrical charge Vstored corresponds to a predetermined key K. Using a switchable voltage source U, the transistor M1 can be switched on. The voltage source U can be switched on to apply a high voltage to the gate terminal of the transistor M1. If the transistor M1 is switched on, the capacitor C1 is charged with the programmed electrical charge Vstored. The capacitor C1 can therefore be written to with the help of the digital-to-analog converter DAC with a previously digitally predetermined key K.

[0074] If transistor M1 is not switched to conduction, the programmed charge Vstored can be temporarily stored in capacitor O1. If capacitor O1 has been written with a key K, the transistor can be switched by switching off the voltage source U so that the charge Vstored and thus the key K are temporarily stored in capacitor O1.

[0075] If a key K is stored in capacitor O1, a digital query Q can now be converted into a voltage VDL using the digital-to-analog converter. The voltage VDL can be applied to the + input of the comparator Corn. The capacitor O1 can then be connected to the - input of the comparator Corn. The comparator Corn can then compare the voltage VDL with the voltage Vstored stored in the capacitor. The comparator Corn can then check whether the voltage VDL is greater than the voltage Vstored. If the voltage VDL is less than the voltage Vstored, the comparator can output an analog electrical signal. The circuit can also be designed such that the comparator can output an analog electrical signal if the voltage VDL is greater than the voltage Vstored. The greater the difference between the two voltages VDL and Vstored, the greater the electrical signal output by the comparator Corn can be.The analog electrical signal output by the comparator Corn can be upper-limited. For example, the comparator Corn can output an electrical signal that lies between "low" and "high," or 0 and 1. The comparator Corn can thus output information about a desired similarity.

[0076] The components shown in Figure 2—transistor M1, capacitor C1, and comparator Corn—can be considered part of a dRAM CAM memory cell because a key K is stored as in a dRAM and can otherwise function like a CAM, which can be used to determine whether a desired piece of information is stored. It can be an aCAM cell. An aCAM can provide information about the degree of similarity between stored information and information being searched for in the memory.

[0077] The first circuit shown in Figure 2 can, for example, output similarity information for the case where the voltage VDL is greater than the voltage Vstored. In order to also obtain similarity information for the case where the voltage VDL is less than the voltage Vstored, the circuit shown in Figure 2 can be provided in pairs. The voltage VDL can be applied to the first circuit of a pair, as shown in Figure 2. The voltage -VDL, i.e., an inverted voltage VDL, can be applied to the second circuit of the pair. If there is a 100 percent match between a query Q and a key K, the electrical signals of the two circuits then match. The two electrical signals of the two circuits can be compared with each other. The greater the match between the two electrical signals, the greater the match between the query Q and the key K.A first and a second circuit can therefore be part of a CAM cell.

[0078] A query Q can be composed of a plurality of voltages VDL. The voltages VDL can be of different magnitudes. In order to be able to compare such a query Q with a plurality of different keys K, the device for performing a similarity assessment can have a plurality of CAM cells. Identical keys K can be stored in the capacitors C1 of a first and a second circuit of a CAM cell. A different key can be stored in each CAM cell. A query Q composed of a plurality of voltages VDL can thus be compared with a plurality of keys K.

[0079] To determine similarities, the analog electrical signal from a comparator Corn can control a current flow through a transistor M2. For example, transistor M2 can be a pull-down transistor. The larger the analog electrical signal output by the comparator Corn, the greater the current flowing through transistor M2 can be. The electrical resistance of transistor M2 can therefore be a measure of similarity.

[0080] Transistor M2 can be connected to an electrical line ML ("match line"). A plurality of the circuits shown in Figure 2 can be connected to the line ML in this way. The current flowing through the electrical line ML results from the sum of the electrical currents flowing through the capacitors M2 of the circuits connected to the electrical line ML. The current flowing through the line ML can then provide information about the degree of similarity.

[0081] It may be that the two currents of a pair of first and second circuits of a CAM cell cancel each other out if a voltage DL matches a stored voltage Vstored. If a plurality of such pairs are connected to the line ML, then no current flows through the line ML if each voltage VDL matches a stored voltage Vstored. Thus, a query Q maximally matches keys K if no current flows through the line ML.

[0082] It may be that no current flows through the transistors M2 of a pair of first and second circuits of a CAM cell in the event of a match. If a plurality of such pairs are connected to the ML line, then no current flows through the ML line if each voltage VDL of one matches a stored voltage Vstored. Thus, a query Q maximally matches keys K if no current flows through the ML line.

[0083] Figure 3 shows a CAM cell comprising a first circuit dRAM CAM and a second circuit dRAM CAM. Both circuits are connected to an electrical line ML, as in the case of Figure 2. A voltage VDL applied for a query Q can be compared with the voltage Vstored, which may be stored in the circuit dRAM CAM shown on the left. The voltage VDL applied for a query Q can be inverted into a voltage -VDL by an inverter I and then compared with the same voltage Vstored, which may be stored in the capacitor of the circuit dRAM CAM shown on the right. If the voltage VDL applied for a query Q matches the stored voltage Vstored, then no current flows through the electrical line ML. If there is a discrepancy between the two voltages VDL and Vstored, then a current flows through the electrical line ML.In Figure 3, additional lines Vsl are shown as power supply.

[0084] If a large number of the Cam cells shown in Figure 3 are connected to the electrical line ML, an "OR" operation can result. If there is a 100 percent match, no currents result. The result is then no current or a zero. If the result is inverted, a "1" represents a 100 percent match. This is then a NOR operation. As soon as a query Q does not match a stored key K, a current flows, which can be interpreted as a deviation from a 100 percent match.

[0085] It may be that no pairs are used to form a CAM cell, but instead, in a circuit like the one shown in Figure 2, a voltage VDL is first sampled and then the inverted voltage VDL is sampled to find a complete match. This can happen simultaneously.

[0086] A device for performing a similarity evaluation can comprise a plurality of the circuits shown in Figure 2 or 3, but only one DAC, with which the capacitors C1 can then be sequentially written or compared with a voltage VDL or -VDL. For sequential writing, the transistor M1 or the two transistors M1 of a first CAM cell can be switched on, i.e., switched to conduction, by a voltage prog_en_0_0 shown in Figure 4, in order to supply a first capacitor C1 or two first capacitors C1 with a voltage V provided by the DAC. stored_o_o, i.e., to charge it accordingly. After writing, the transistor can be turned off by switching off the voltage prog_en_0_0. Subsequently, the transistor M1 or the two transistors M1 of a second CAM cell can be switched on by a voltage prog_en_0_1 in order to charge a second capacitor C1 or two second capacitors C1 with a voltage V provided by the DAC. s tored_i_o. Transistor M1 can then be turned off again by turning off the voltage prog_en_0_1. This can be continued until all capacitors C1 have been written. Figure 4 shows this for four capacitors C1 or pairs of capacitors C1.

[0087] However, all capacitors in a horizontal row shown in Figure 4 can also be written to simultaneously. Each horizontal row can contain more than the two capacitors shown.

[0088] However, it is not impossible that initially all transistors M1 are switched on. In this case, the smallest voltage V s tored_o_o are generated by the DAC. After charging the desired capacitor C1 or both desired capacitors C1, the corresponding transistor M1 can be turned off. Subsequently, the next higher voltage V s tored_i_o can be applied to write to the next capacitor C1 or to the next two capacitors C1. This can be continued until all capacitors C1 have been written.

[0089] Figure 4 shows the design of an integrated circuit with four cells cell_0_y, cell_x_y, cell_0_0 and cell_x_0, i.e. a 2x2 array. Each cell comprises a transistor M1, a capacitor and a comparator Corn. The two cells cell_0_y, cell_x_y are arranged in a first row and the cells cell_0_0, cell_x_0 are arranged in a second row below the first row. The two cells cell_0_y, cell_x_y in the first row are connected to an electrical line ML_0_y for reading out a result and to a switchable voltage source prog_en_0_y for switching the transistors M1. An OR circuit thus links cells in a row. Such a circuit is also called a NOR circuit. The two cells cell_0_0, cell_x_0 of the second row are connected to an electrical line ML_0_0 for reading out a result to a switchable voltage source prog_en_0_0 for switching the transistors M1.Stacked cells of a first column (cell_0_y, cell_0_0) are programmed via a first digital-to-analog converter (DAC_0_0). Stacked cells (cell_x_y, cell_x_0) of a second column are programmed via a second digital-to-analog converter (DAC_x_0). The two cells of each column can form a CAM cell, so that no current flows through the line ML_0_y or ML_0_0 if the voltages VDL and Vstored match appropriately, i.e., a request Q with the same key K stored in the cells of a row. The DAC_0_0 then generates the voltage VDL for a query. The DAC_x_0 then generates the voltage -DL for a query. The respective comparator then does not provide a signal.

[0090] Figure 5 shows a design of a CAM cell that comprises just one transistor M1, one capacitor C1, and one comparator COM. This is achieved by a connection to the electrical line ML that is different from that in Figure 2, and that includes two transistors M2 and M3. The transistors M2 and M3 are connected in series and can be switched by the comparator COM. A voltage relative to ground gnd, shown bottom right, is applied to the line ML. If there is a match between a request Q and a stored key K, the comparator outputs an average voltage signal that lies between the maximum possible voltage signal "high" and the minimum possible voltage signal "low." This means that both transistors M2 and M3 are switched on.If there is no match, the comparator Corn outputs either a "low" signal as a voltage or a "high" signal. If a "low" signal, i.e. no voltage, is output, then one of the transistors M3 is turned off, and no current can flow through it. If a "high" signal, i.e. a maximum possible voltage, is output, then one of the transistors M2 is turned off, and no current can flow through it. In the case of a "high" or "low" signal, therefore, no current can flow from the electrical line ML through the two transistors M2 and M3 to ground gnd. A maximum current flows from the line ML to ground gnd when a request Q matches a stored key K, i.e. VDL matches Vstored. If a request Q is similar to a stored key K, then an electrical current IML flows from the line ML to ground gnd that is less than the maximum possible current.The current strength is thus a measure of the similarity between a query Q and a key K. To achieve this, the transistor M2 can be a PMOS transistor or p-channel MOSFET and the transistor M3 can be an NMOS transistor or n-channel MOSFET, as shown graphically by the circuit symbols for the two transistor types in Figure 5.

[0091] Figure 6 shows an embodiment with two cells HBU and LBU. Each cell HBU, LBU comprises a transistor M1, a capacitor C1 and a comparator Com. Each cell HBU, LBU is connected via a transistor M2, M3 to an electrical line ML such that the respective comparator Corn switches the associated transistor M2, M3. The transistor M2 of the cell HBU can be a MOSFET. The transistor M3 of the cell LBU can be a MOSFET. One transistor can in turn be a PMOS transistor and the other an NMOS transistor. The two transistors M2 and M3 can be connected in series. One transistor M2 can be switched on when the comparator Corn of the cell HBU outputs a “low” signal, i.e. no voltage. The other transistor M3 of the cell LBU can be switched off when the comparator Corn of the cell HBU outputs a “high” signal, i.e. a maximum possible voltage.One transistor M2 can be turned off when the comparator Corn of the cell HBU outputs a "high" signal. In this case, no current IML can flow through the line ML. The other transistor M3 of the cell LBU can be turned on when the comparator Corn of the cell HBU outputs a "low" signal. In this case, no current IML can flow through the line ML. A current IML can flow through the line ML when the two comparators Corn of the two cells HB and LBU output an average voltage in the case of a match between a query Q and the stored key K. If a current IML flows through the line ML, this is therefore a measure of a match between a query Q and a stored key K. Figure 6 therefore shows a CAM cell with an AND operation, which can indicate the degree of a match between a query Q and a key K by a current IML flowing through the line ML.If no current IML flows through the line ML, the query Q does not match the stored key K. If a maximum current IML flows through the line ML, the query Q matches the stored key K to the maximum.

[0092] HBU is an abbreviation for "High Boundary Voltage." LBU is an abbreviation for "Low Boundary Voltage." The two cells, HBU and LBU, specify a lower and an upper limit for a window within which the voltage DL must lie to be considered a match. The two cells, HBU and LBU, form a CAM cell.

[0093] Figure 7 shows a further embodiment of a CAM cell in which, similar to the case in Figure 6, a maximum current IML can flow through two transistors M2 and M3 if a request Q matches a stored key K or a voltage DL lies within a window specified by the cells HBU and LBU by storing a voltage Vstored in capacitor C1. In the case of Figure 7, in the event of a match, a current IML flows through the electrical line ML to ground gnd.

[0094] Figure 8 shows an example of a comparator design using standard circuit symbols. The implementation shown in Figure 8 consists of an open-loop operational amplifier. It includes a dRAM stage 2, a differential stage 3, and an inverter stage 4. Further examples of comparators are known from the publication "David A. Johns Kenneth W. Martin Tony Chan Carusone. Analog Integrated Circuit Design. Ed. by Joyce Pohm. Don Fowley John Wiley Sons, Inc., 2012. ISBN: ISBN 978-0-470-77010-8."

[0095] A two-stage comparator with positive feedback is described in "B.-S. Song, S.-H. Lee, and M.F. Tompsett. “A 10-b 15-MHz CMOS recycling two-step A / D converter”. In: IEEE Journal of Solid-State Circuits 25.6 (1990), pp. 1328-1338. DOI: 10.1109 / 4.62176". A two-stage comparator with locking is known from the paper "SR Norsworthy, IG Post, and H.S. Fetterman. “A 14-bit 80-kHz sigma-delta A / D converter: modeling, design and performance evaluation. In: IEEE Journal of Solid-State Circuits 24.2 (1989), pp. 256-266. DOI: 10.1109 / 4.18584".

[0096] Figure 9 shows a further developed embodiment of the invention compared to the embodiment shown in Figure 5.

[0097] Instead of a transistor M1 acting as a switch to write to capacitor C1, there can be two transistors M1a and M1b. The two transistors M1a and M1b can be connected in parallel so that they can act as switches. One write transistor M1a can be a PMOS transistor and the other transistor M1b can be an MMOS transistor. The voltage range that can be provided for writing can thereby be increased compared to the embodiment shown in Figure 5. Voltages from 0 volts up to the supply voltage can be stored by capacitor C1. Furthermore, the writing speed can be increased.

[0098] Instead of one comparator Corn, two comparators Com-a and Com-b can be present. The capacitor C1 can be connected to a - input of one comparator Com-a. The capacitor C1 can be connected to a + input of the other comparator Com-b. A voltage VDL_H can be applied to the other input of one comparator Com-a during operation. A voltage VDL_L can be applied to the other input of the other comparator Com-b. One comparator Com-a can then compare a charge stored by the capacitor C1 or a resulting voltage Vstore with the voltage VDL_H. The other comparator Com-b can then compare the charge stored by the capacitor C1 or the resulting voltage with the voltage VDL_L. The output of one comparator Com-a can be connected to the gate terminal of a transistor M2.The output of the other comparator, Com-b, can be connected to the gate terminal of another transistor, M3. Each comparator, COM-a, Com-b, can switch a transistor, M2 or M3, respectively.

[0099] The two transistors M2 and M3 can be connected in series. In the event of a match between a query Q and a stored key K, a voltage can be output as a signal, which can be between the voltage VDL_L and the voltage VDL_H. The circuit can be configured such that, in this case, both transistors M2 and M3 are switched to conduction. An electric current iMatch can then flow through both transistors M2 and M3.

[0100] For example, a request may result in a desired voltage of 0.5 volts. The desired voltage would then be 0.5 volts. The two voltages VDL_L and VDL_H are then selected to create a window within which the desired voltage lies. A window width AV can be selected, which could be 0.1 volts, for example. Half a window width, i.e. 0.05 volts, can then be subtracted from the desired voltage to set a lower limit. Half a window width, i.e. 0.05 volts, can then be added to the desired voltage to set an upper limit. The voltage VDL_L can then be slightly lower than the desired voltage, for example 0.45 volts. The voltage VDL_H can then be slightly higher than the desired voltage, for example 0.55 volts.The window is then set, also for other CAM cells to which the two voltages VDL_L and VDL_H are applied accordingly. If a charge is stored in the capacitor Vstore, through which a voltage of 0.5 volts can be applied to the inputs of the two comparators Com-a and Com-b, both transistors M2 and M3 can be switched on. The transistor M2 can be a PMOS transistor for this purpose. The transistor M3 can be an NMOS transistor. 0 volts can be applied to the gate terminal of the transistor M2 for this purpose. A supply voltage can be applied to the gate terminal of the transistor M3 for this purpose. A current iMatch can then flow through the two transistors M2 and M3. If the capacitor V... sIf a charge is stored in the capacitors such that a voltage of less than 0.45 volts or more than 0.55 volts can be applied to the inputs of the two comparators Com-a and Com-b, then only one transistor M2 or M3 can be switched on. In this case, no current IMatch can flow through the two transistors M2 and M3. A current IMatch flowing through the two transistors M2 and M3 can therefore signal when a desired charge is stored in the capacitor Vstore. A window width can therefore be, for example, 10% of the maximum available voltage. For example, the maximum available voltage is 1 volt. The window width is then 0.1 volt. A window width can be at least 1% or at least 5% of the maximum available voltage. A window width can be no more than 50%, no more than 20%, or no more than 15% of the maximum available voltage. A suitable window width can be determined experimentally.

[0101] The CAM cell shown in Figure 9 may be a CAM cell of a circuit comprising m further such CAM cells in the m-direction (indicated by an arrow m) and n further such CAM cells in the n-direction (indicated by an arrow m).

Claims

Claims 1. Device for carrying out a similarity assessment for an attention mechanism with a capacitor (C1) for storing a key (K), with an input for a query (Q), with a comparator (Corn) for comparing a query (Q), with a key (K) stored in the capacitor (C1), wherein the comparator (Corn) outputs an analog similarity value (S) as a result of the comparison.

2. Device according to the preceding claim with a multiplier which multiplies the analog similarity value (S) by a value (V) and outputs an attention (Attention(Q,K,V)) as a result of the multiplication.

3. Device according to the preceding claim, characterized in that the multiplier comprises an analog-to-digital converter (DAC) which digitizes the analog similarity value (S) and a processor which multiplies the digitized similarity value by a digitized value vector (V).

4. Device according to one of the preceding claims, characterized in that the capacitor (C1) is connected via a switch (M1) to a digital-to-analog converter for storing a key (K).

5. Device according to the preceding claim, characterized in that the switch (M1) is a transistor which can be switched by a voltage source (II) such that a key (K) can be stored in the capacitor (C1) depending on the switching state of the transistor (M1).

6. Device according to one of the preceding claims, characterized in that an input (+ or -) of the comparator (Corn) is connected to a digital-to-analog converter (DAC) for comparing a query (Q) with a key (K) stored in the capacitor (C1).

7. Device according to one of the preceding claims, characterized in that a digital-to-analog converter (DAC) is present, which on the one hand is connected to the capacitor (C1) via a switch (M1) for charging the capacitor (C1) and on the other hand is connected to an input (- or +) of the comparator (Corn) for a query (Q).

8. Device according to one of the preceding claims, characterized in that two transistors (M2, M3) are present which are connected in series for reading out a query and which can be switched via the output of the comparator (Corn).

9. Device according to the preceding claim, characterized in that one transistor (M3) is an N-channel MOSFET and the other transistor is a P-channel MOSFET (M2).

10. Device according to one of the preceding claims, characterized in that the device is arranged so that the result of a query is converted into an electrical current, and a measuring device is provided with which the current intensity of the flowing current is determined.

11. Device according to one of the preceding claims, characterized in that an analog CAM cell is present.

12. Device according to the preceding claim, characterized in that a plurality of CAM cells are present which are connected to an electrical line (ML) for reading.

13. Device according to one of the preceding claims, characterized in that the device is an integrated circuit.

14. A method for carrying out a similarity assessment with a device according to one of the preceding claims, wherein keys (K) are stored in capacitors (C1), followed by a query (Q) being compared with the stored keys (K) by comparators (Corn) to obtain a similarity.

15. Method according to the preceding claim, characterized in that the result of the comparison is multiplied by a value (V) and thus a result is obtained which corresponds to a calculated attention (Attention(Q,K,).

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