Method and carrier substrate for producing a component comprising aluminum nitride

Abstract

The invention relates to a method (600) for producing a semiconductor component (100) with at least one exposed membrane portion, wherein the method (600) comprises the following steps: - providing (610) a semiconductor material (102) having a carrier substrate (104) provided with a passivation layer (108); - applying a membrane layer (110) to the passivation layer (108), the membrane layer (110) being formed from an aluminum nitride material in which a ratio of aluminum to nitrogen is within a range between 1.05 to 1.4; - applying a protective layer (114) to the membrane layer (110), the membrane layer (110), on a side opposite the passivation layer (108), being covered by the protective layer (114); - removing (620) a part of the carrier substrate (104) using a wet-chemical process, in order to obtain a region (130) of the passivation layer (108) that is devoid of the substrate; and - exposing (630) a section of the membrane layer (110) in the region (130) that is devoid of the substrate by means of a first dry etching step for etching the passivation layer and a second dry etching step for etching the protective layer, in order to obtain the exposed membrane section (140).

Description

[0001] METHOD AND CARRIER SUBSTRATE FOR PRODUCING A COMPONENT WITH ALUMINUM NITRIDE

[0002] The present invention relates to a method and a device for producing a component with a membrane section exposed on both sides made of aluminum nitride with an aluminum excess according to the main claims.

[0003] A membrane made of AIN, BN, or quartz is known from KR 10-2021-0084381 A. A phase-shifting mask with a metal nitride layer, for example made of AIN, is known from KR 10-2018-0057813 A. Another membrane made of AIN, as well as a component with such a membrane, is known from KR 10-2018-0029384 A.

[0004] DE 10 2011 005 249 A1 discloses a device for converting mechanical energy into electrical energy and a method for its manufacture. The method describes the production of a curved piezoelectric membrane.

[0005] From JP 2013-160706A a flow detector on a semiconductor substrate with an exposed sensor area is known.

[0006] DE 10 2022 111 943 B3 describes a method and a carrier substrate for producing a semiconductor component, wherein a membrane layer is formed from AIN.

[0007] Modern semiconductor components often require a high degree of flexibility in terms of material properties, so that, for example, good guidance of a light beam can be achieved in optical semiconductor components. For the purposes of this invention, a semiconductor component can be understood as a component that is manufactured on a semiconductor substrate as a carrier substrate, for example a semiconductor wafer, for example a silicon wafer. This can be a mechanical and / or optical component, for which the semiconductor properties of the substrate may be irrelevant for the function. It can be a mechanical component, an optical component, a component for the NIR range, the visible range, the UV range, the EUV range, or the X-ray range of electromagnetic waves.Such semiconductor components can be manufactured using techniques typical of the semiconductor industry. However, it is problematic that some advantageous material properties belong to material types that are difficult to process. For example, a material may have a good, desirable material property such as high mechanical strength, high thermal conductivity, a desired electrical resistance, a desired elastic modulus and / or a certain refractive index, which can interact particularly well with another material, such as air, at an interface. Aluminum nitride can have excellent properties for such applications as a thin membrane. Advantageous material properties can be achieved by a non-stoichiometric composition of the aluminum nitride. At the same time, however, this material can also be water-soluble or, for example,be hydrolyzable, so that some process steps used in conventional semiconductor manufacturing processes cannot be used to process such a material.

[0008] Based on this problem, a possibility is now presented that enables improved processing and thus the production of a component with a thin, non-stoichiometric aluminum nitride membrane with improved properties.

[0009] This problem is solved by the subject matter of the main claims.

[0010] The approach presented here provides a method for producing a semiconductor component with at least one exposed membrane section, the method comprising the following steps: a) providing a semiconductor material having a carrier substrate provided with a passivation layer; b) applying a membrane layer to the passivation layer, the membrane layer being formed from an aluminum nitride material in which the ratio of aluminum to nitrogen is in the range between 1.05 and 1.4; c) applying a protective layer to the membrane layer, the membrane layer being covered by the protective layer on a side opposite the passivation layer; d) removing part of the carrier substrate using a wet-chemical process to obtain a substrate-free region of the passivation layer;and e) exposing a portion of the membrane layer in the substrate-free region by means of a first dry etching step for etching the passivation layer and a second dry etching step for etching the protective layer to obtain the exposed membrane portion.;

[0011] Advantageously, steps ae can be performed in the specified order. The exposed membrane section can be exposed on both sides by completely removing the passivation layer and the protective layer in this section. When etching the protective layer, it can be completely removed from the entire semiconductor material or only in certain regions, particularly in the areas where the exposed membrane sections are provided.

[0012] Advantageously, a cleaning step using a water-based cleaning agent, in particular a wet-chemical cleaning process, can be carried out before step e. In particular, the cleaning step can be carried out after step d.

[0013] The exposed membrane section may, but does not have to, be perforated.

[0014] A carrier substrate can be understood, for example, as a conventional substrate, for example made of silicon. It can be a single-crystal silicon wafer. This carrier substrate can be provided with a passivation layer, which, for example, comprises or consists of silicon nitride.

[0015] A membrane layer can be understood as a layer that has a particularly advantageous property, for example with regard to its optical and / or mechanical behavior, but which comprises or consists of a non-stoichiometric aluminum nitride material whose structure and / or composition can be changed by water, in particular is hydrolyzed. For example, a mechanical structure of this material can degrade if the material comes into contact with water or a layer made of this material breaks or tears. Hydrolysis can be understood as the incorporation of water molecules, whereby this material can then precipitate or crystallize upon evaporation or evaporation of the water. During hydrolysis, however, the material can also be chemically decomposed by contact with water. Aluminum nitride, for example, can be hydrolyzed close to the surface with the formation of ammonia.For example, aluminum nitride can be quite resistant to water exposure as a compact material or as a thick layer, but can be rapidly destroyed by hydrolysis when present as a thin layer. Thin layers of non-stoichiometric aluminum nitride, especially those with an excess of aluminum, can be particularly susceptible to water exposure. On the other hand, an excess of aluminum can promote permanent tensile stress in the membrane, which is desirable for some applications.

[0016] The present approach is based on the finding that the use of an aluminum nitride material for the membrane layer, in which the ratio of aluminum to nitrogen is in the range of 1.05 to 1.40, particularly advantageously in the range of 1.10 to 1.30, has very positive properties both with regard to the optical refractive behavior and with regard to the mechanical stability of a membrane layer made from such a material. In addition, a desired mechanical tensile stress can be reproducibly adjusted. To obtain a flat, free-standing AIN membrane, the layer tension of the membrane can, for example, be set to a tensile stress of 100 MPa to 1000 MPa. The ratio of aluminum to nitrogen can be assumed to be the atomic ratio of aluminum atoms to nitrogen atoms, which can also be referred to as the molar ratio.The ratio presented here allows for a significant increase in flexibility in the design of a component, which, on the one hand, can be adapted specifically for different optical applications and, on the other hand, also enables use in robust applications, as the membrane layer exhibits high mechanical stability. This also enables significantly improved handling of the carrier substrate or semiconductor material during processing, as the failure rate due to mechanical damage to the components manufactured using the approach presented here can be reduced. The solution presented here can lead to an improvement in the mechanical and optical properties, manufacturability, and long-term stability of the component.In addition, the service life of the membrane layer, especially when it is present as a free-standing membrane, can be extended by preventing or slowing down degradation due to a reduction in the tensile stress of the membrane compared to known membrane layers made of stoichiometric AIN.

[0017] In this case, a protective layer can be understood as a covering of the membrane layer. The protective layer and the passivation layer, which advantageously consist of or contain a material that is non-water-soluble or whose structure and / or composition cannot be changed by water, ensure that the membrane layer is fluid-tightly sealed from the surroundings of the semiconductor component (except, for example, the lateral edges of the wafer). This ensures that the membrane layer is not damaged during the processing or structuring of areas of the carrier substrate or the semiconductor component, thus preventing the destruction of the semiconductor component to be manufactured.A wet-chemical process can be understood as one process step or multiple process steps of a wet etching process or a wet cleaning process in which a liquid etching and / or cleaning agent is used to introduce structures into the semiconductor material or to clean a surface of the semiconductor material. A dry etching process can be understood as a process step in which the semiconductor material is structured using a physical or mechanical removal process or using a gaseous etchant. Furthermore, the first and second dry etching steps can, but do not have to, be carried out using an identical dry etching process and / or be carried out in one process step. Two dry etching steps carried out one after the other, each from one side of the semiconductor component, are also advantageous.The sequence of the steps of providing, removing and exposing can also advantageously be carried out in the specified sequence, wherein the first and second dry etching steps can be carried out as sub-steps of the exposing step and can also be carried out in any desired order.

[0018] The approach proposed here offers the advantage of ensuring, by using different etching or cleaning processes at different processing stages, that the membrane system, which is made of a material sensitive to an etching or cleaning material used in one of the process steps, remains as undamaged as possible. An embodiment of the approach proposed here with an additional step f) applying a cover layer to the protective layer is advantageous. The protective layer forms a layer stack with the cover layer as a protective layer, with a material of the protective layer being different from a material of the cover layer.

[0019] The application of the cover layer can advantageously be carried out after the application of the protective layer according to step c) and before the exposure according to step e), particularly advantageously before the removal of a part of the carrier substrate according to step d)

[0020] In particular, the material of the cover layer may comprise a reflective material and / or a metal.

[0021] The method may further comprise a step to be carried out before the second dry etching step, in particular before the step of removing part of the carrier substrate (step d): g) structuring the protective layer, wherein the protective layer is exposed, at least in places, by removing the cover layer, in particular using an auxiliary mask by means of an etching process used in the first or second dry etching process or a further etching process.

[0022] Such an embodiment offers the advantage of being able to structure the protective layer very flexibly thanks to the different materials of the layers of the protective layer, so that a flexible design of the exposed membrane layer can also be achieved in a later process step. By using a metal for the cover layer, electrical conductor tracks can be created on the component surface. By using a reflective material for the cover layer, for example, desired optical properties of the finished component can be realized and / or reflective markings can be applied for positioning the semiconductor component or the wafer, on which multiple semiconductor components can be located.To form the freestanding membrane, a section of the carrier substrate in the structured region can be removed during the structuring step, creating a substrate-free region. Such an embodiment of the approach proposed here offers the possibility of preparing the semiconductor material or the semiconductor component using known, efficient processing steps such that the dry etching process can be used exclusively in the subsequent exposure step. In this way, the prior processing of the semiconductor material can prevent damage to a potentially already exposed surface of the membrane layer by an etching or cleaning agent that is too aggressive for the material of the membrane layer.

[0023] Particularly advantageous is an embodiment of the approach proposed here in which the structuring step is carried out such that the membrane layer is sealed against an etching or cleaning agent of the wet-chemical process by the passivation layer and at least part of the protective layer. Such an embodiment offers the advantage of reliably protecting the membrane layer against the etching agent of the wet-chemical process and thus preventing damage to the membrane layer.

[0024] According to a further embodiment of the approach proposed here, the passivation layer and at least part of the protective layer can be removed using the dry etching process in the exposure step. Such an embodiment of the approach proposed here offers the advantage that the dry etching process is already applied when the membrane layer is first exposed, thus allowing the membrane layer to be protected and structured as effectively as possible.

[0025] Semiconductor components designed to be particularly delicate and efficient for a specific application can be manufactured if the membrane layer itself is not only exposed but also structured. For this purpose, through-holes can be introduced into the membrane layer, for example, to enable the implementation of an electromagnetic radiation attenuator or an optical structure, such as a diaphragm structure, in the membrane layer in the exposed membrane section. Such a diaphragm structure can have through-holes with a diameter larger than a design light wavelength of the component, forming conventional diaphragms.According to a particularly advantageous embodiment, the membrane layer can therefore be at least partially removed in the exposure step to obtain a perforated, exposed membrane section, in particular wherein a structured region of the protective layer and / or a resist mask applied to the protective layer and / or to the cover layer can be used as an etching mask. Such a perforation can have perforation holes that have a larger diameter than a design wavelength of the component in order to form conventional apertures. Perforation holes can also be provided that have a smaller diameter than a design light wavelength of the component in order to produce evanescent electromagnetic waves or to act as a short-pass filter. The perforated membrane section can represent a diffraction grating for electromagnetic radiation.It should be noted that electromagnetic radiation, within the meaning of this invention, can be understood as X-rays, EUV radiation (XUV), UV radiation, visible light, and infrared light. The optical function of the component (at a design wavelength) can be provided in any of the aforementioned wavelength ranges. Tensile stress on the membrane can prevent unwanted warping of the membrane.

[0026] Such components can also be used as ultrasound detectors. Membrane deflection can be evaluated, for example, capacitively or optically. The permanently maintained tensile stress of the membrane can be particularly relevant for this application.

[0027] Furthermore, such devices with through-holes in the membrane can be used as effective pressure reducers for gases. The size of the openings can be chosen so small that they enable Knudsen flow or molecular flow. This allows, for example, a small amount of a trace gas to be reproducibly metered into a gas stream. Such a pressure reducer can also be used as a test leak for testing high-vacuum systems.

[0028] Furthermore, according to a further embodiment of the approach presented here, in the step of structuring and exposing, the membrane layer, the carrier substrate, the protective layer, a masking layer, and the passivation layer can be removed in a pass-through region laterally adjacent to the structured region in such a way that an opening is formed into which no portion of the membrane layer protrudes. Such an embodiment of the approach proposed here offers the advantage that other regions of the semiconductor material can also be structured using the method presented here, in which no exposed portions of the membrane layer are required. In this way, the structuring of the semiconductor material or the semiconductor component can be carried out compactly with few work steps, thereby reducing manufacturing costs and manufacturing time.

[0029] A particularly favorable embodiment is furthermore in which, in the structuring step, a holding material is applied to a section of the passivation layer exposed in the passivation region. In the exposure step, after removal of the carrier substrate and the passivation layer in the passivation region, the holding material is removed to form the opening. A holding material can be understood, for example, as a plastic material, such as a photoresist, which can also be used to introduce structures into different layers of the semiconductor material. The holding material can also be applied together with another material to a surface of the semiconductor material or the semiconductor component.By using such a semiconductor material, which is applied, for example, directly to the passivation layer, it is possible to prevent flakes or fragments of a layer to be removed from falling uncontrolled into the processing space and causing defects in a subsequent step. Rather, such fragments, which may arise from a continuous reduction in the thickness of the layer to be removed, can be supported or held firmly in place by the holding material, enabling complete removal or dissolution of these fragments. The holding material can advantageously be applied to the side of the passivation layer facing away from the substrate, in the area of ​​the intended passivation band.

[0030] A very flexible embodiment of the approach proposed here can also be used, in which the opening is formed in the exposure step such that it has a larger diameter than an opening in the exposed region of the membrane layer. Such an embodiment offers the advantage of being able to introduce differently dimensioned structures into the semiconductor material using a uniform method or process, allowing the efficient implementation of desired functions in a component.

[0031] A semiconductor component with particularly favorable properties can be realized specifically by providing a semiconductor material in which the passivation layer and / or a masking layer at least partially comprises a silicon nitride, and / or in which the membrane layer at least partially comprises an aluminum nitride, a germanium oxide, and / or an aluminum oxide, and / or wherein the cover layer comprises a metal, in particular chromium, and / or the protective layer comprises silicon and / or silicon nitride. In this way, semiconductor components designed very advantageously, especially for optical applications, can be realized.

[0032] Particularly advantageously, for the realization of the different steps of the approach proposed here, an embodiment can be used in which, in the structuring step, a wet etching process using potassium hydroxide or tetramethylammonium hydroxide as etchant is carried out as a wet-chemical process and / or a wet-chemical cleaning process and / or wherein, in the exposing step, a dry etching process is carried out using a physical dry etching process, a chemical dry etching process and / or a physico-chemical dry etching process.

[0033] The thickness of the membrane layer can be between 5 nm and 1000 nm, advantageously between 10 nm and 500 nm, particularly advantageously between 20 nm and 200 nm, and very particularly advantageously between 40 nm and 150 nm. Such an embodiment offers the advantage of being able to realize very favorable electromagnetic properties of the membrane layer or of the component comprising the membrane layer compared to the prior art due to the low thickness. For example, the refractive index of the free-standing membrane in the short-wave range can be close to 1 and the absorption coefficient >0.03. At the same time, this thickness can still realize a sufficiently stable membrane layer when choosing the aforementioned stoichiometric ratio (also due to the occurrence of stresses). For this purpose, a thickness of the membrane layer of at least 10 nm, advantageously at least 20 nm, likewise advantageously at least 40 nm, can advantageously be provided.In this way, the possible applications of a component manufactured in this way can be significantly expanded, since the design of the component can be extended to include use in very different technical fields or different wavelength ranges.

[0034] A particularly advantageous embodiment of the approach proposed here is one in which a plasma process, in particular for cleaning the applied membrane layer, is carried out during the step of applying the membrane layer, in particular wherein the plasma process uses a hydrogen and / or oxygen plasma. Such an embodiment offers the advantage of obtaining a cleaned membrane layer through the plasma process, which, on the one hand, has high-quality optical properties and, on the other hand, is subjected to mechanical stresses that have a very beneficial effect on the stability of such a component.Another advantageous embodiment of the approach proposed here is one in which, in the step of applying the membrane layer, nitrogen is supplied to a processing chamber in which the membrane layer is applied to the passivation layer, in particular wherein an amount of nitrogen is supplied to the processing chamber that is less than the amount of nitrogen required to produce a stoichiometric membrane layer. Such an embodiment offers the advantage of being able to very precisely adjust the ratio of aluminum to nitrogen during the deposition or formation of the membrane layer through the controlled supply of nitrogen, so that such an embodiment enables a high degree of flexibility in the realization of desired material parameter combinations during the production of the membrane layer.

[0035] Advantageously, the lateral extension of the exposed area of ​​the membrane can be between 50pm and 5000pm, particularly advantageously between 100pm and 500pm.

[0036] The membranes can be perforated, for example, with a hole pattern whose lateral hole spacing is between 50 nm and 5000 nm, advantageously 100 nm to 1000 nm. The membranes can be used, for example, to absorb and / or diffract electromagnetic radiation.

[0037] Another advantageous embodiment of the approach presented here is when the substrate-free region of the semiconductor material has edges whose normals form an angle of less than 60°, in particular 54.7°, to a surface normal of the carrier substrate, in particular where the semiconductor material is monocrystalline and the edges are formed by etch-resistant crystal planes. For example, a silicon wafer with a {100} surface can be used. If the edges are formed by {111} and equivalent crystal planes, the angle can be 54.74°.

[0038] These variants of methods can be implemented, for example, in software or hardware or in a mixed form of software and hardware, for example as control commands in a control unit or device.

[0039] The approach presented here further provides a device designed to perform, control, or implement the steps of a variant of a method presented here in corresponding devices. This embodiment of the invention in the form of a device also allows the problem underlying the invention to be solved quickly and efficiently.

[0040] For this purpose, the device can have at least one computing unit for processing signals or data, at least one memory unit for storing signals or data, at least one interface to a sensor or an actuator for reading sensor signals from the sensor or for outputting data or control signals to the actuator, and / or at least one communication interface for reading or outputting data embedded in a communication protocol. The computing unit can be, for example, a signal processor, a microcontroller, or the like, wherein the memory unit can be a flash memory, an EEPROM, or a magnetic storage unit.The communication interface can be designed to read in or output data wirelessly and / or wired, wherein a communication interface that can read in or output wired data can read this data, for example, electrically or optically from a corresponding data transmission line or output it to a corresponding data transmission line.

[0041] In this case, a device can be understood as an electrical device that processes sensor signals and outputs control and / or data signals depending on them. The device can have an interface, which can be implemented in hardware and / or software. In a hardware implementation, the interfaces can, for example, be part of a so-called system ASIC, which contains a wide variety of functions of the device. However, it is also possible for the interfaces to be separate integrated circuits or to consist at least partially of discrete components. In a software implementation, the interfaces can be software modules that are present, for example, on a microcontroller alongside other software modules.

[0042] Also advantageous is a computer program product or computer program with program code that can be stored on a machine-readable carrier or storage medium such as a semiconductor memory, a hard disk memory, or an optical memory and is used to carry out, implement, and / or control the steps of the method according to one of the embodiments described above, particularly when the program product or program is executed on a computer or device. A further aspect of the invention is a carrier substrate for producing at least one component with at least one exposed membrane section, with a passivation layer arranged on a first side, wherein a membrane layer is arranged on the passivation layer, wherein the membrane layer is formed from an aluminum nitride material in which the ratio of aluminum to nitrogen is in the range between 1.05 and 1.4.The membrane layer is covered by a protective layer on a side opposite the passivation layer, the protective layer comprising silicon and / or silicon nitride. The protective layer forms a layer stack with a cover layer as a protective layer. A material of the protective layer differs from a material of the cover layer, and the cover layer comprises a metal. Furthermore, an etching mask for wet etching the substrate is applied to a second side of the carrier substrate opposite the first side. This carrier substrate can advantageously be used to manufacture the component.

[0043] Examples of the approach presented here are shown in the drawings and explained in more detail in the following description. It shows:

[0044] Fig. 1A to IE show several partial representations, each showing a cross section of a semiconductor component to be produced according to a first embodiment in different process steps;

[0045] 2A to 21 show several partial views each showing a cross section of a semiconductor component to be manufactured according to a second embodiment in different process steps;

[0046] Fig. 3 shows several partial representations, each showing a cross section of a semiconductor component to be produced according to a third embodiment in different process steps;

[0047] Fig. 4 shows a schematic cross-section of the layer stack used as starting material for the semiconductor component;

[0048] Fig. 5 shows a cross-section of a structured wafer with a semiconductor device; Fig. 6 shows a top view of a structured aluminum nitride membrane fabricated using the proposed process flow;

[0049] Fig. 7 is a flowchart of an embodiment of a method for manufacturing a semiconductor device; and

[0050] Fig. 8 is a block diagram of an embodiment of an apparatus for producing a semiconductor component.

[0051] In the following description of advantageous embodiments of the present invention, the same or similar reference numerals are used for the elements shown in the various figures and having a similar effect, whereby a repeated description of these elements is omitted.

[0052] Figure 1 shows, in several partial representations, which are reproduced as Figure 1A to Figure 1E, a cross section of a semiconductor component 100 to be produced according to a first embodiment after different process steps.

[0053] Figure 1A initially shows a semiconductor material 102 in the form of a stack of multiple layers. The semiconductor material 102 comprises a carrier substrate 104, which is made, for example, of silicon or comprises this material. The semiconductor substrate 104 further comprises a lower masking layer 106 and a passivation layer 108, each of which, for example, comprises a silicon nitride (SiBNi) or comprises this material. The masking layer 106 and the passivation layer 108 can, for example, be formed on the carrier substrate 104 in a single manufacturing step. The membrane layer 110, which consists of aluminum nitride with an aluminum-to-nitrogen ratio in the range between 1.05 and 1.4, is arranged on the passivation layer 108. A protective layer 114 is arranged on the membrane layer 110.This protective layer 114 can, for example, comprise silicon, silicon nitride, silicon oxide, and / or a metal, or consist of one of the aforementioned materials. However, it can also be a resist layer, such as a photoresist.

[0054] In a first process step, according to this embodiment, the masking layer 106 is structured, for example using a photoresist to be exposed and / or using a wet etching process or alternatively a dry etching process.

[0055] Figure 1B shows a cross-sectional view through a semiconductor component 100 in a state after execution of this method step.

[0056] According to the first exemplary embodiment for the production of the semiconductor component 100 shown in Figure 1, a further method step now involves etching through the carrier substrate 104 using a wet etching process. The use of the wet etching process allows for the formation of sloped flanks through the openings of the masking layer 106 in the carrier substrate, as is made possible by the use of the wet etching process with appropriate alignment of the crystal structure of the carrier substrate 104. The formation of such flanks is very advantageous for optical applications, as will be explained in more detail below. The etching then takes place until the rear-side exposure of the passivation layer 108, which serves as a stop layer for the wet etching process, is achieved. In this way, it can be avoided that the water-soluble or water-sensitive membrane layer 110 is attacked by the wet etching process and thus damaged or destroyed.In modifications of this embodiment not shown in the figures, the flanks of the trenches can also be etched perpendicular to the masking layer and / or the masking layer can be undercut.

[0057] Figure 1C shows a cross-sectional view through a semiconductor component 100 in the state after execution of this method step. A substrate-free

[0058] Area 130. In this area 130, the passivation layer 108 is exposed on one side, in the illustration on the underside. At the same time, this state of the

[0059] Semiconductor component 100 is the final state in this manufacturing embodiment, which can be processed by a wet etching step. The subsequent steps are performed using the dry etching process to prevent damage or destruction of the membrane layer 110 due to the action of water molecules.

[0060] In a further step, the passivation layer 108 is removed in the substrate-free region 130 in a first sub-step, and the protective layer 114 is removed in a second sub-step. These two sub-steps can be carried out in any order or simultaneously. A dry etching process is used for this removal. Using a process step of a wet etching process in this state would also attack and damage the membrane layer 110, so that according to the approach presented here, only a dry etching process may be used to process the semiconductor component 100 from this process stage onwards. In the first exemplary embodiment shown, the passivation layer is only removed in the substrate-free region 130, since other locations where the substrate is still present are not accessible to the etching process.In the illustrated embodiment, the protective layer is only partially removed in an area encompassing the freestanding membrane. For this purpose, the protective layer can be selectively etched using an auxiliary mask (not shown in the figure).

[0061] Figure 1D shows a cross-sectional view through a semiconductor component 100 in the state after performing this method step. The masking layer 106 can, as shown, but need not, remain on the component. In the example shown, the protective layer 114 was only partially removed, namely in an area that was selected to be somewhat larger than the substrate-free area 130. In a modification not shown in the figure, the protective layer 114 is removed in an area that corresponds to the substrate-free area 130. In a further modification not shown in the figure, the protective layer 114 is removed in an area that is smaller than the substrate-free area 130.

[0062] Figure 1E shows a cross-sectional view through a semiconductor component 100 in a further modification of the first embodiment. Here, the protective layer has been completely removed. In a further modification of the first embodiment, the masking layer 106 is removed in a subsequent step and, if necessary, the individual parts of the semiconductor component 100 are separated.

[0063] Figure 2 shows, in several partial representations, which are reproduced as Figure 2A to Figure 2I, a cross section of a semiconductor component 100 to be produced according to a second exemplary embodiment after different process steps.

[0064] Figure 2A initially shows a semiconductor material 102 in the form of a stack of multiple layers. The semiconductor material 102 comprises a carrier substrate 104, which is made, for example, of silicon or comprises this material. The semiconductor substrate 104 further comprises a lower masking layer 106 and a passivation layer 108, each of which, for example, comprises a silicon nitride (Si3N4) or comprises this material. The masking layer 106 and the passivation layer 108 can, for example, be formed on the carrier substrate 104 in a single manufacturing step. The membrane layer 110, which consists of aluminum nitride, in which the ratio of aluminum to nitrogen is in the range between 1.05 and 1.4, is arranged on the passivation layer 108. A protective layer 112 is arranged on the membrane layer 110, which comprises, for example, a protective layer 114 and a cover layer 116 arranged on the protective layer 114.This protective layer 114 may comprise a silicon-based semiconductor material and be formed as an etch stop layer. The cover layer 116 may, for example, comprise or consist of a reflective material and / or metal, such as chromium.

[0065] In a first processing step, the cover layer 116 is structured, for example, with the reflective material. For this purpose, a photoresist can be used, for example, which is exposed in accordance with a structure to be introduced into the cover layer 116. A wet etching process or, alternatively or additionally, a dry etching process can be used for structuring the cover layer 116.

[0066] Figure 2B shows a cross-sectional view through a semiconductor component 100 in a state after execution of the above-mentioned method steps.

[0067] Subsequently, according to this exemplary embodiment, the masking layer 106 is structured, for example again using a photoresist to be exposed and / or using a wet etching process or alternatively a dry etching process.

[0068] Figure 2C shows a cross-sectional view through a semiconductor component 100 in a state after execution of this method step.

[0069] In a further method step, structuring is performed using a photoresist as etching mask 120 to realize structures, for example, different grating types, in the semiconductor component 100. This allows a substrate grating type 122 and, on the other hand, a membrane grating 124 to be structured in a further region.

[0070] Figure 2D shows a cross-sectional view through a semiconductor component 100 in the state after this method step has been carried out. According to the exemplary embodiment for the production of the semiconductor component 100 shown in Figure 2, a further method step now involves etching through the carrier substrate 104 using a wet etching process. By using the wet etching process, sloping flanks instead of trenches can be formed through the openings of the masking layer 106 in the carrier substrate, as is made possible by using the wet etching process with appropriate alignment of the crystal structure of the carrier substrate 104. The formation of such flanks is very advantageous for optical applications, as will be explained in more detail below. The etching then takes place until the rear-side exposure of the passivation layer 108, which serves as a stop layer for the wet etching process.In this way, it can be avoided that the water-soluble or water-sensitive membrane layer 110 is attacked by the wet etching process and thus damaged or destroyed.

[0071] Figure 2E shows a cross-sectional view of a semiconductor device 100 in the state after performing this method step. At the same time, this state of the semiconductor device 100 is the final state in this manufacturing embodiment, which can be processed by a wet etching step. The subsequent steps are performed using the dry etching process to avoid damage or destruction of the membrane layer 110, which consists of or comprises the water-soluble material.

[0072] In a subsequent step, sacrificial layers can be removed, which in the present exemplary embodiment can be the exposed part of the passivation layer 108 from the back side of the carrier substrate 104 as well as the part of the protective layer 114 not covered by the photoresist as etching mask 120 and / or the cover layer 116. A dry etching process is used for this removal, since the membrane layer 110 is now exposed in a structured region 130 and in a transmission region 132. By using a process step of a wet etching process, the membrane layer 110 would also be attacked and damaged in this state, so that according to the approach presented here, only a dry etching process may be used to process the semiconductor component 100 from this process stage onwards.

[0073] Figure 2F shows a cross-sectional view through a semiconductor component 100 in the state after this method step has been performed. Subsequently, in a further method step, for example, the removal of the membrane layer 110 in the transmission region 132 can take place, creating a wide opening 136 through the semiconductor component 100. Furthermore, in the structured region 130, the membrane layer 110 exposed by the structured protective layer 112, specifically the structured protective layer 114 and the structured cover layer 116, can also be removed, which can be achieved, for example, by a dry etching process acting from above. In this way, the membrane layer 110 comprising the water-soluble or water-sensitive material can be structured as desired.At the same time, very fine structures such as holes 138 in the structured area 130 in the membrane layer 110 can be realized, which makes it possible, for example, to form the subsequently produced exposed membrane layer 110 as a movable element.

[0074] Figure 2G shows a cross-sectional view through a semiconductor component 100 in the state after execution of this method step.

[0075] Furthermore, in a subsequent step, the area of ​​the protective layer 112 not covered by the etching mask 120, i.e., the uncovered part of the protective layer 114 and the cover layer 116, is (dry) etched or removed, creating an exposed membrane section 140 of the membrane layer 110, which, for example, also has fine structures such as through-holes 138. These through-holes 138 can also be significantly smaller in diameter than the opening 236 in the through-hole region 132.

[0076] Figure 2H shows a cross-sectional view through a semiconductor component 100 in the state after execution of this method step.

[0077] Finally, in a subsequent step, the etching mask 120 is removed or (dry) etched and, if necessary, the individual parts of the semiconductor component 100 are separated.

[0078] Figure 21 shows a cross-sectional view through a semiconductor component 100 in the state after performing this process step. The sub-figures of Figure 2 thus show a schematic of an exemplary embodiment of a process flow for producing free-standing, structured, non-stoichiometric aluminum nitride membranes using sacrificial protection layers and standard CMOS process steps. During all critical steps, the sensitive layers such as membrane layer 110 are protected, enabling the use of wet and thus cost-effective process steps.

[0079] With the approach presented here, the production of ultra-thin, free-standing and structured membranes as membrane layer 110 made of layered material that is sensitive to wet processes can be carried out. In this way, the production of free-standing, ultra-thin membranes, which typically requires many wet-chemical process steps such as lithography and wafer cleaning, can nevertheless be realized efficiently. To produce the free-standing membranes, the entire wafer is typically etched through either by dry or wet etching. While dry etching processes such as DRIE (deep reactive ion etching) produce approximately vertical etch profiles through the wafer, wet etching processes can also produce oblique etch profiles in the etched groove.For optical applications, a sloped V-shaped sidewall with wet etching is preferred to transmit electromagnetic radiation with high NA (numerical aperture) through a membrane without shadowing at the sidewalls of the wafer hole. If the membrane is used for fluidic tasks, sloped sidewalls can have a nozzle or diffuser effect. However, the use of wet etching processes with known technologies is difficult or impossible if the membrane is to be formed from aluminum nitride. In contrast, the approach presented here presents a process flow that enables the production of virtually any freestanding membrane material. In addition, a method for fabricating structured membranes is described.

[0080] The production of free-standing membranes is a widely used technology for applications such as MEMS products or optical sensors. Typically, robust materials such as SiN or metals are used as the membrane material or material for the membrane layer 110. Depending on the application, however, the use of aluminum nitride may also be desirable. However, this material, at least in thin layers, is hydrolyzable under the influence of water, so a wet process step is not directly feasible. Cleaning processes with the commonly used water-based cleaning chemicals are also not possible. With the method presented here, the desired component can be manufactured inexpensively using wet chemistry and can also have angled substrate etched edges. The basic idea of ​​the invention is various sacrificial layers that protect the sensitive layer of the membrane layer 110 from the wet environment.This approach makes it possible to pattern the membranes from non-stoichiometric aluminum nitride and also to locally deposit a suitable reflective material for light or ultrasound sensing purposes. There are no limitations on the patterning precision other than the resolution limit of the lithography and etching tools used. Here, we demonstrate a minimum feature size of < 200 nm, which is within the resolution limit of the tools.

[0081] The proposed process is described based on the processing stages of the semiconductor device shown in the subfigures of Figure 2. It includes various standard process steps such as coating, lithography, cleaning, wet and dry etching. Using the proposed process route, more wet cleaning steps can be performed, thereby improving the overall quality of surface defects. In particular, it is even possible to utilize the critical wet etching step, at least in part, for device fabrication.

[0082] An important aspect of the proposal presented here is the use of protective layers below (silicon nitride) and above the moisture-sensitive layers during all wet process steps. These protective layers are ultimately etched away. The layer stack is chosen so that individual layers can be selectively etched without etching the other masking and / or protective layers. A further advantage of the proposed approach or layer stack is the possibility of adjusting the optical reflectivity through the selected materials and / or layer thicknesses. The introduction of the protective layer, for example, offers the possibility of reducing the reflectivity to almost zero, for example, in green light, or of achieving maximum reflectivity simply by changing the layer thickness.

[0083] In the proposed process flow, the step between the processing stages shown in Figures 1F and 1G is challenging. When etching through the last free-standing layer to open large holes, such as in the area of ​​the through-hole 136, this layer is slowly thinned. If the remaining layer is too thin (a few nanometers) to remain intact, the membrane, or in this case, the membrane layer 110, will break before the etching process is complete and curl up into flakes. These flakes, which may consist of the moisture-sensitive material, act as an undesirable masking layer in the subsequent processes. For this reason, a further optimized process flow was developed to avoid these flakes, which could be created by the large openings.

[0084] Figure 3 shows, in several partial representations, a cross-section of a semiconductor component 100 to be manufactured according to a third exemplary embodiment in different process steps. Starting from the processing state of the semiconductor component 100 shown in Fig. 2C, a shading mask 200 is now used in a first intermediate step shown on the right, which is used in a dry etching step to remove the protective layer 114 in the through-passage region 132 using a dry etching process. In this way, the membrane layer 110 is exposed in the through-passage region 132. In a subsequent process step, the exposed membrane layer 110 is removed using a wet etching process or a dry etching process.Following this, the procedure shown in Figure 2D is then followed again, but now the etching mask 120 is additionally applied to the now exposed upper passivation layer 108. In the subsequent steps, specifically in the transition from the processing states between the semiconductor components 100 depicted in Figures 2F and 2G, it is thus ensured that the upper passivation layer 108 (and also the previously removed membrane layer 110 in the passband 132) cannot disintegrate into flakes, which could then act as a faulty optical mask.

[0085] Figure 3 thus shows an optimized scheme for avoiding flakes from the membrane layer material. Two new process steps are included to selectively etch the layers in the areas of the large membrane openings 136, i.e., the passband 132. All other process steps are the same or very similar to the previous process flow in Figure 2.

[0086] Two additional process steps (shown on the right in Figure 3) serve to selectively remove the moisture-sensitive, non-stoichiometric aluminum nitride layer (membrane system) 110 at the large openings. Various etching methods can be used. In the process diagram, we use a shadow mask to open the buffer layer. All other processes, for example, essentially correspond to the sequence previously described in Figure 2. The only difference is the use of a slightly adapted photomask in the step leading to the semiconductor device according to Figure 2D to keep the large openings closed by the photoresist as an etch mask 120. This improved process flow makes it possible to replace the critical step of etching through the freestanding moisture-sensitive layer with process steps in which etching occurs against a thick (freestanding) photoresist 120.This can prevent the occurrence of flakes or flakes during processing, which may consist of broken ultra-thin material, for example.

[0087] Figure 4 shows a schematic cross-section of an embodiment of a carrier substrate (104) for producing at least one component (100) with at least one exposed membrane section. A passivation layer (108) is arranged on a first side of the carrier substrate (104). A membrane layer (110) is arranged on the passivation layer (108), wherein the membrane layer (110) is formed from an aluminum nitride material in which an aluminum to nitrogen ratio is in the range between 1.05 and 1.4. The membrane layer (110) is covered by a protective layer (114) on a side opposite the passivation layer (108). The protective layer comprises (114) silicon and / or silicon nitride. The protective layer (114) forms a layer stack with a cover layer (116) as a protective layer (112), wherein a material of the protective layer (114) differs from a material of the cover layer (116). The cover layer (116) comprises a metal.An etching mask (106) for wet etching the substrate is applied to a second side of the carrier substrate opposite the first side.

[0088] In an advantageous specific embodiment of the aforementioned embodiment, the masking layer 106 and the passivation layer 108 can be designed, for example, as an etch stop layer. They can, for example, each comprise a 100 nm thick silicon nitride layer. In a further advantageous specific embodiment of the aforementioned embodiment, the membrane layer 110 can have a thickness of, for example, 50 nm to 150 nm. In a further advantageous specific embodiment of the aforementioned embodiment, the protective layer 114 can, for example, have a thickness of 20 nm to 200 nm. In a further advantageous specific embodiment of the aforementioned embodiment, the protective layer 114 can be designed as stoichiometric silicon nitride Si(Si)N4 or also non-stoichiometrically as any Six Ny, advantageously with an excess of silicon. In a further advantageous specific embodiment of the aforementioned embodiment, the cover layer 116 can be formed, for example, as a metal layer, for example made of chromium, with a thickness of, for example, 20 nm to 200 nm. Figure 5 shows a cross-section of a structured wafer with a semiconductor component 100, comprising reflective markings in the metal layer 116, large openings 136 that allow access to the backside of the wafer, and smaller through holes 138 as perforations of the freestanding, non-stoichiometric aluminum nitride membrane 140.

[0089] The lateral dimensions of the markings structured in the metal layer 116 and the structured holes 138 in the free-standing part 140 of the aluminum nitride membrane 110 are limited only by the resolution limit of the lithographic tool in combination with the dry etching tools. Structures with lateral dimensions of approximately 100 nm can be realized.

[0090] Figure 6 shows a top view, as typically observed in a SEM (scanning electron microscope) image, of a structured freestanding AlN membrane 110 fabricated using the proposed process flow. The circles are holes 136 in the through-hole region 132 in the non-stoichiometric aluminum nitride membrane, which allow a clear path through the membrane 110 and the entire wafer 104. There are also substrate-free regions 130 where the freestanding non-stoichiometric aluminum nitride membrane 140 is perforated with through-holes 138.

[0091] Figure 7 shows a flow diagram of a method 600 for producing a semiconductor component with at least one exposed membrane section, the method comprising a step 610 of providing a semiconductor material comprising a carrier substrate provided with a passivation layer, wherein a membrane layer is arranged on the passivation layer, formed from an aluminum nitride material in which the ratio of aluminum to nitrogen is in the range between 1.05 and 1.4, wherein the membrane layer is covered by a protective layer on a side opposite the passivation layer. Furthermore, the method 600 comprises a step 620 of removing a portion of the carrier substrate using a wet-chemical method in order to obtain an exposed region of the passivation layer in a substrate-free region of the semiconductor material.Finally, the method 600 comprises a step 630 of exposing a portion of the membrane layer in the substrate-free region by means of a first dry etching step for etching the passivation layer and a second dry etching step for etching the protective layer in order to obtain the exposed membrane portion. Figure 8 shows a block diagram of an apparatus 700 for producing a semiconductor component. The apparatus 700 comprises a unit 710 for providing a semiconductor material which has a carrier substrate provided with a passivation layer, wherein a membrane layer is arranged on the passivation layer, wherein the.

[0092] The diaphragm layer is formed from an aluminum nitride material in which the ratio of aluminum to nitrogen is in the range between 1.05 and 1.4, wherein the diaphragm layer is covered by a protective layer on a side opposite the passivation layer. Furthermore, the device 700 comprises a unit 720 for removing 620 a portion of the carrier substrate 104 using a wet etching process to obtain a substrate-free region of the semiconductor material. Finally, the device 700 comprises a unit 730 for exposing a portion of the diaphragm layer in the substrate-free region using a dry etching process to obtain an exposed diaphragm portion.

Claims

Patent claims 1. A method (600) for producing a semiconductor component (100) with at least one exposed membrane section, the method (600) comprising the following steps: a) providing (610) a semiconductor material (102) which has a carrier substrate (104) provided with a passivation layer (108), b) applying a membrane layer (110) to the passivation layer (108), the membrane layer (110) being formed from an aluminum nitride material in which a ratio of aluminum to nitrogen is in the range between 1.05 and 1.4, c) applying a protective layer (114) to the membrane layer (110), the membrane layer (110) being covered by the protective layer (114) on a side opposite the passivation layer (108); d) removing (620) a portion of the carrier substrate (104) using a wet chemical process to obtain a substrate-free region (130) of the passivation layer (108);and e) exposing (630) a portion of the membrane layer (110) in the substrate-free region (130) by means of a first dry etching step for etching the passivation layer and a second dry etching step for etching the protective layer to obtain the exposed membrane portion (140); 2. The method (600) according to claim 1, wherein the membrane layer has a thickness between 10nm and 500nm.

3. Method according to one of the preceding claims, further comprising a step to be carried out before step e, in particular before step d and after step c: f) applying a cover layer (116) to the protective layer (114), wherein the protective layer (114) forms a layer stack with a cover layer (116) as a protective layer (112), wherein a material of the protective layer (114) differs from a material of the cover layer (116), in particular wherein the material of the cover layer (116) comprises a reflective material and / or a metal, and further comprising a step to be carried out before the second dry etching step, in particular before the step (620) of removing a part of the carrier substrate: g) structuring the protective layer (112), wherein the protective layer (114), at least in places by removing the cover layer (116), in particular using an auxiliary mask by means of a etching process used in the dry etching process or another etching process.

4. The method (600) according to claim 3, characterized in that in the step of structuring and exposing (630) in a passage region (132) laterally adjacent to the substrate-free region (130), the membrane layer (110), the carrier substrate (104), the protective layer (114) and the passivation layer (108) are removed in such a way that an opening (136) passing through the semiconductor component (100) is formed, in particular into which no section of the membrane layer (110) projects.

5. The method (600) according to claim 4, characterized in that in order to avoid contamination by detaching material residues of the passivation layer to be removed, in the structuring step a holding material (210) is applied to a section of the passivation layer (108) exposed in the passage region (132), wherein in the exposing step (630) after removal of the carrier substrate (104) and the passivation layer (108) in the passage region (132), the holding material (210) is removed in order to form the opening (136).

6. The method (600) according to claim 4 or 5, wherein in the step of exposing (630), the opening (136) is formed such that it has a larger diameter than an opening (138) in the exposed region (140) of the membrane layer (110).

7. The method (600) according to any one of the preceding claims, characterized in that in the structuring step, as a wet-chemical method, a wet etching method using potassium hydroxide or tetramethylammonium hydroxide as etchant is carried out and / or wherein in the exposing step (630) the first and / or second dry etching step is carried out using a physical dry etching method, a chemical dry etching method and / or a physico-chemical dry etching method.

8. Method (600) according to one of the preceding claims, characterized in that several semiconductor components are produced simultaneously on the carrier substrate.

9. Method (600) according to one of the preceding claims, characterized in that before the step of exposing (630) a portion of the membrane layer (110), at least one cleaning step with a water-containing cleaning agent, in particular a wet-chemical cleaning process, is provided.

10. Method (600) according to one of the preceding claims, characterized in that in the step of exposing (630) the membrane layer (110) is at least partially removed in order to obtain a perforated exposed membrane section (140), in particular wherein a resist mask (120) applied to the protective layer (114) and / or to the cover layer (116) is used as an etching mask.

11. Method (600) according to one of the preceding claims, characterized in that in the step of providing (610) a semiconductor material (102) is provided in which the passivation layer (108) at least partially comprises a silicon nitride, and / or wherein the cover layer (116) comprises a metal, in particular aluminum or a transition metal, in particular at least one of the transition metals titanium, nickel, chromium, tantalum, tungsten, platinum and / or the protective layer (114) comprises silicon and / or silicon oxide and / or silicon nitride.

12. The method (600) according to any one of the preceding claims, wherein the substrate-free region (130) of the semiconductor material (102) has edges whose normal has an angle of less than 60°, in particular 54.7°, to a surface normal of the carrier substrate, in particular wherein the semiconductor material is monocrystalline and the edges are formed by etch-resistant crystal planes.

13. Device (700) which is configured to carry out and / or control the steps (610, 620, 630) of the method (600) according to one of the preceding claims 1 to 11 in corresponding units (710, 720, 730).

14. Computer program which is configured to execute and / or control the steps of the method (600) according to one of the preceding claims 1 to 10 when the computer program is executed on a computer unit.

15. A carrier substrate (104) for producing at least one component (100) with at least one exposed membrane section, with a passivation layer (108) arranged on a first side, wherein a membrane layer (110) is arranged on the passivation layer (108), wherein the membrane layer (110) is formed from an aluminum nitride material, in which a ratio of aluminum to Nitrogen is in the range between 1.05 to 1.4, wherein the membrane layer (110) is covered on a side opposite the passivation layer (108) by a protective layer (114), wherein the protective layer (114) comprises silicon and / or silicon nitride, wherein the protective layer (114) forms a layer stack as a protective layer (112) with a cover layer (116), wherein a material of the protective layer (114) is distinguished from a material of the cover layer (116) and the cover layer (116) comprises a metal and, in addition, an etching mask (106) for wet etching the substrate is applied to a second side of the carrier substrate opposite the first side.

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