Inference model for optimizing a front-end module (FEM) in a wireless communication device

Abstract

A distributed inference model for optimizing a front-end module (FEM) in a wireless communication device is disclosed. In one aspect, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., through machine learning or deep learning artificial intelligence (AI) techniques). The inference model may then associate with a microprocessor in the transceiver. The model will use as inputs a current operating condition based on data from a baseband processor (BBP) and the FEM and compute appropriate settings for the adjustable elements within the FEM. Additionally, the inference model may be distributed amongst a variety of microprocessors within the FEM or BBP. The distributed inference model may be sized according to the size and power of the respective associated microprocessor.

Description

INFERENCE MODEL FOR OPTIMIZING A FRONT-END MODULE (FEM) IN A WIRELESS COMMUNICATION DEVICEPRIORITY APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Patent Application Serial No. 63 / 472,217, filed on June 9, 2023, and entitled “SYSTEMS AND METHODS FOR OPTIMIZING A FRONT-END MODULE (FEM) IN A WIRELESS MOBILE DEVICE,” the contents of which are incorporated herein by reference in its entirety.

[0002] The present application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 507,380, filed on June 9, 2023, and entitled “DISTRIBUTED BIG-SMALL SYSTEM WITH MULTIPLE EDGE Al DL / ML MODELS DRIVEN BY LOCAL FEM EVENTS TO RESPOND TO ENVIRONMENT CONDITIONS IMPACT ON FEM SETTINGS,” the contents of which are incorporated herein by reference in its entirety.

[0003] The present application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 507,376, filed on June 9, 2023, and entitled “SEQUENTIAL MULTI-STEP MODEM Al DL / ML MODEL TRAINING USING FEM, BASEBAND AND USER GENERATED DATASETS AND CALIBRATION DATA,” the contents of which are incorporated herein by reference in its entirety.

[0004] The present application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 539,361, filed September 20, 2023, and entitled “SYSTEMS AND METHODS FOR ITERATIVELY OPTIMIZING A FRONT-END MODULE (FEM) IN A WIRELESS COMMUNICATION DEVICE,” the contents of which are incorporated herein by reference in its entirety.

[0005] The present application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 539,367, filed September 20, 2023, and entitled “DISTRIBUTED INFERENCE MODEL FOR A FRONT-END MODULE (FEM) IN A WIRELESS COMMUNICATION DEVICE,” the contents of which are incorporated herein by reference in its entirety.

[0006] The present application also claims priority to U.S. Provisional Patent Application Serial No. 63 / 507,351, filed June 9, 2023, and entitled “MULTIDIMENSIONAL RF FEM PROGRAMMING ABSTRACTION LAYER FOR ENABLING MACHINE-LEARNING AND DEEP-LEARNING Al INFERENCE MODEL,” the contents of which are incorporated herein by reference in its entirety.BACKGROUNDI. Field of the Disclosure

[0007] The technology of the disclosure relates generally to front-end modules (FEMs) in wireless communication devices and ways to optimize operation through different operating conditions.II. Background

[0008] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to reduce power consumption. Wireless mobile communication devices rely on RF (radio frequency) front-end modules (FEM) and RF transceivers to send and receive wireless signals that enable or facilitate the use of the functions available on such devices. An RF FEM includes power amplifiers and other circuitry to condition signals for transmission in one direction and condition incoming signals for baseband processing in the other direction. Efficient operation of a FEM is one-way power consumption may be reduced. Accordingly, there is room for innovation in optimizing efficient operation in a FEM.SUMMARY

[0009] Aspects disclosed in the detailed description include a distributed inference model for optimizing a front-end module (FEM) in a wireless communication device. In particular, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., through machine learning or deep learning artificial intelligence (Al) techniques). The inference model may then be associated with a microprocessor in the transceiver. The model will use as inputs a current operating condition based on data from a baseband processor (BBP) and the FEM and compute appropriate settings for the adjustable elements within the FEM.

[0010] Additionally, the inference model may be distributed amongst a variety of microprocessors within the FEM or BBP. The distributed inference model may be sized according to the size and power of the respective associated microprocessor. In this manner, no one device bears the entire burden of handling the inference model. This may result in less traffic on communication buses and reduce the overall device size. Further, such optimization in the FEM may result in power savings and / or improved user experience.

[0011] Aspects disclosed in the detailed description also include systems and methods for iteratively optimizing a FEM in a WCD. In particular, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., through machine learning or deep learning Al techniques). The inference model is then associated with a microprocessor in the transceiver. The model will use as inputs a current operating condition based on data from a BBP and the FEM and compute appropriate settings for the adjustable elements within the FEM. Additionally, the FEM may provide measurements to a remote server that are then used as part of a training data set for future learning processes and to update the inference models used in the FEM. Use of such an inference model to compute settings for the FEM allows wide flexibility and opportunities for post-sale optimization of the FEM. Further, such optimization may result in power savings and / or improved user experience.

[0012] In this regard, in one aspect, a transceiver is disclosed. The transceiver includes a FEM comprising a bus interface configured to be coupled to a communication bus for receiving inference model settings from a BBP or application processor (AP). The FEM also includes a plurality of tunable elements, each with an associated control register and a model microprocessor comprising a first portion of an inference model, the first model microprocessor configured to write settings to at least one of the associated control registers while at least a second one of the associated control registers is configured to be written to, based on the inference model settings from the BBP. The FEM further includes a plurality of detectors configured to sense operating conditions and report measurements relating to the operating conditions to the model microprocessor.

[0013] In another aspect, a wireless communication device (WCD) is disclosed. The wireless communication device includes a communication bus and a FEM coupled to the communication bus, the FEM comprising setting registers and adjustable elements set by the setting registers. The wireless communication device also includes a BBP coupled tothe communication bus and an AP coupled to the communication bus. The wireless communication device further includes an inference model distributed amongst at least two of the FEM, BBP, and AP, wherein the inference model is configured to operate on the associated model microprocessor and configured to write settings to the setting registers in the FEM.

[0014] In another aspect, a method of controlling adjustable elements in a FEM is disclosed. The method includes receiving at the FEM through a communication bus, first information from a first portion of an inference model, and generating second information using a second portion of the inference model in a model microprocessor in the FEM. The method also includes writing settings into settings registers in the FEM based on the first information and the second information and adjusting tunable elements in the FEM based on the settings registers.

[0015] In this regard, in one aspect, a FEM is disclosed. The FEM includes a plurality of tunable elements, each with an associated control register and a model microcontroller comprising an inference model, the model microcontroller configured to write settings to each of the associated control registers based on reported operating conditions.

[0016] In another aspect, a BBP is disclosed. The BBP includes a bus interface configured to couple to a FEM through a communication bus and a model microcontroller. The model microcontroller is configured to use baseband information with an inference model to generate settings for control registers in the FEM and send the settings to the FEM through the bus interface.

[0017] In another aspect, a method of creating an inference model for use by a model microcontroller in a transceiver is disclosed. The method includes measuring outputs of a transceiver, linking the outputs to inputs for the transceiver to assemble a training data set, and providing the training data set to an artificial intelligence module to generate a possible inference model. The method also includes evaluating the possible inference model with a performance check, when the performance check fails, adjusting the training data set, and when the performance check passes, deploying the possible inference model to a transceiver.

[0018] In another aspect, a FEM is disclosed. The FEM includes a plurality of tunable elements, each with an associated control register and a model microcontroller comprising and running an inference model, the model microprocessor configured to write settings to each of the associated control registers based on reported operating conditions based on inference model outputs.

[0019] In another aspect, a BBP is disclosed. The BBP includes a bus interface configured to couple to a FEM through a communication bus. The BBP also includes a modem configured to use baseband information with an inference model to generate settings for control registers in the FEM and send the settings to the FEM through the bus interface.

[0020] In another aspect, an AP is disclosed. The AP includes a bus interface configured to couple to a FEM through a communication bus and a processor configured to use baseband information with an inference model to generate settings for control registers in the FEM and send the settings to the FEM through the bus interface.

[0021] In another aspect, a method of creating an inference model for use by a modem is disclosed. The method includes measuring outputs of a FEM, linking the outputs to inputs for the Modem to assemble a training data set, and providing the training data set to an artificial intelligence module to generate a possible inference model. The method also includes evaluating the possible inference model with a performance check, when the performance check fails, adjusting the training data set, and when the performance check passes, deploying the possible inference model to a BBP, FEM, or AP.

[0022] In another aspect, a method of creating an inference model for use in a lab environment without a modem. The method includes measuring outputs of a FEM, linking the outputs to inputs for lab equipment and server to assemble a training data set, and providing the training data set to an artificial intelligence module to generate a possible inference model. The method also includes evaluating the possible inference model with a performance check, when the performance check fails, adjusting the training data set, and when the performance check passes, deploying the possible inference model to a BBP, FEM, or AP.

[0023] In another aspect, a FEM is disclosed. The FEM includes a plurality of tunable elements, each with an associated control register and a model microcontroller comprising an inference model, the model microcontroller configured to write settings to each of the associated control registers based on reported operating conditions. The FM also includes a plurality of detectors configured to sense operating conditions and report measurements relating to the operating conditions to the model microcontroller, wherein the model microcontroller is further configured to collect information about operating conditions and settings and provide the information to a control circuit for storage in a memory and transmission to a remote location.

[0024] In one aspect, a BBP is disclosed. The BBP includes a bus interface configured to couple to a FEM through a communication bus. The BBP also includes a model microcontroller configured to use baseband information with an inference model to generate settings for control registers in the FEM, send the settings to the FEM through the bus interface, collect information about operating conditions, the settings, and outputs derived from the settings, and provide the information to a control circuit for storage in a memory and transmission to a remote location.

[0025] In another aspect, a WCD is disclosed. The wireless communication device includes a transceiver comprising a communication bus, a FEM coupled to the communication bus, the FEM comprising a plurality of tunable elements, and a plurality of sensors configured to provide information about operating conditions. The wireless communication device further includes a BBP coupled to the communication bus, an AP coupled to the BBP, and a model microcontroller located in one of the FEM, the BBP, or the AP, the model microcontroller comprising an inference model configured to generate settings for control registers in the FEM based on reported operating conditions. The wireless communication device also includes a memory and a control circuit coupled to the memory and communicatively coupled to the inference model. The control circuit is configured to collect information about operating conditions and settings, store the information in the memory, and cause the information to be transmitted to a remote location.

[0026] In another aspect, a method of updating an inference model for use by a model microcontroller in a transceiver is disclosed. The method includes creating an initial inference model using lab measurements of a FEM, receiving information from a plurality of FEMs deployed in WCD, and retraining a version of the initial inference model using the information from the plurality of FEMs.

[0027] In one aspect, a BBP is disclosed. The BBP includes a communication bus configured to communicate with at least a front-end module, FEM, having programmable registers therein. The BBP also includes a control circuit coupled to the communication bus and configured to request a write operation to the programmable registers in the FEM through a FEM software driver and receive from the FEM software driver a palette of register bundles, wherein each of the palette of register bundles is optimized for different operating conditions and select a register bundle from the palette based on operating conditions known to the control circuit.

[0028] In one aspect, a BBP is disclosed. The BBP includes a communication bus configured to communicate with at least a FEM having programmable registers therein. The BBP also includes a control circuit coupled to the communication bus and configured to request a write operation to the programmable registers in the FEM through a FEM software driver, wherein the request for write operation includes information about operating conditions and receive from the FEM software driver a register bundle derived from an inference model based on the information about operating conditions and write to the programmable registers based on the register bundle.

[0029] Further aspects of the present disclosure focus on how information is provided from the inference model so that the information may be written into the relevant registers to modify the behavior of the tunable elements in the transmission chain. More particularly, a programming abstraction layer (PAL) may exist between the inference model and an operating system in a device such as the BBP or the AP. The BBP or AP sends a request for a write command to the PAL, which queries the inference model and responds with a palette of options from which the BBP or AP selects based on operating criteria. This approach is particularly useful when the source of the inquiry possesses information relating to operating conditions that may not be available to the inference model.BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a block diagram of a conventional transceiver with a front-end module (FEM) and baseband processor (BBP) that may adjust settings based on operating conditions;

[0031] Figure 2A is a block diagram of a transmit chain from the transceiver of Figure 1 with two adjustable items that may be adjusted based on operating conditions;

[0032] Figure 2B is a look-up table (LUT) that may store values for the adjustable items of Figure 2 A;

[0033] Figure 3 is a block diagram of a conventional transceiver with a FEM and BBP and many items that may be adjusted based on operation conditions;

[0034] Figure 4A is a block diagram of a transceiver with an inference model in the BBP according to an aspect of the present disclosure;

[0035] Figure 4B is a block diagram of a transceiver with an inference model in the FEM according to an aspect of the present disclosure;

[0036] Figure 5 is a flowchart showing how the inference model is created for use in a transceiver;

[0037] Figure 6 is a flowchart showing how the inference model is then used in the transceiver;

[0038] Figure 7 A is a block diagram of a training environment reliant on information from just the FEM to construct the training data set according to an exemplary aspect of the present disclosure;

[0039] Figure 7B is a block diagram of a training environment that uses information from both the BBP and the FEM to construct the training data set according to an exemplary aspect of the present disclosure;

[0040] Figure 8A is a block diagram of a transceiver having a model microprocessor that uses the inference model placed in a BBP according to an exemplary aspect of the present disclosure;

[0041] Figure 8B is a block diagram of a transceiver having a model microprocessor that uses the inference model placed in a FEM according to an exemplary aspect of the present disclosure;

[0042] Figure 8C is a block diagram of a transceiver having a model microprocessor that uses the inference model placed in an external processor according to an exemplary aspect of the present disclosure;

[0043] Figure 9 is a more detailed block diagram of a FEM that has adjustable elements that may be tuned based on settings provided by an inference model according to aspects of the present disclosure;

[0044] Figure 10 is a block diagram of a wireless communication device with multiple FEM components, which may all be controlled using an inference model according to exemplary aspects of the present disclosure;

[0045] Figure 11 is a block diagram of a transceiver where all tunable elements are controlled by an inference model according to exemplary aspects of the present disclosure;

[0046] Figure 12 is a block diagram of a transceiver where some tunable elements are controlled by a static LUT, and others of the tunable elements are dynamically controlled by an inference model according to exemplary aspects of the present disclosure;

[0047] Figure 13 is a block diagram of a transceiver that uses carrier aggregation that create multiple blockers whose performance is optimized by an inference model according to exemplary aspects of the present disclosure;

[0048] Figure 14 is a block diagram of a transceiver that has beam steering and multiple input-multiple output antenna arrays whose performance is optimized by an inference model according to exemplary aspects of the present disclosure;

[0049] Figure 15 is a block diagram of a mobile terminal, which may include the inference model of Figures 4A-14 according to the present disclosure;

[0050] Figure 16 is a flowchart showing an iterative process for training the inference model of the present disclosure and subsequent redeployment of an updated inference model to communication equipment;

[0051] Figure 17 A is a block diagram of a first inference model that may benefit from the iterative updating of the present disclosure where the wireless communication device has no artificial intelligence in the wireless communication device;

[0052] Figure 17B is a block diagram of a second inference model that may benefit from the iterative updating of the present disclosure that is implemented in software within the wireless communication device;

[0053] Figure 17C is a block diagram of a third inference model that may benefit from the iterative updating of the present disclosure that is implemented in hardware within the wireless communication device;

[0054] Figure 18 is a block diagram of a system that collects information from a plurality of deployed communication devices, retrains the inference model based on this information, and then redistributes an updated inference model to the plurality of communication devices as well as updating the inference model being provided in newly sold devices;

[0055] Figure 19 is a block diagram illustrating how the training set may be pruned so that an end-product inference model is sized to fit smaller computing devices;

[0056] Figure 20 is a block diagram illustrating an inference model distributed across multiple chips in a FEM;

[0057] Figure 21 is a block diagram illustrating an inference model distributed across multiple chips in the FEM as well as in an application processor;

[0058] Figure 22 is a block diagram illustrating a transceiver with a distributed inference model where primary processing occurs in a BBP and difference adjustments are made by the inference model in the FEM;

[0059] Figure 23 is a block diagram of a transceiver where a power management integrated circuit (PMIC) is controlled by a distributed inference model;

[0060] Figure 24 is a block diagram of a transceiver where the PMIC includes part of the distributed inference model;

[0061] Figure 25 is a block diagram of a transceiver and application processor (AP), where the inference model is distributed between the BPP and the AP while controlling multiple FEMs;

[0062] Figure 26 is a block diagram of a transceiver and AP where the inference model is distributed between the BPP, the AP, and multiple FEMs;

[0063] Figure 27 is a block diagram of a transceiver with multiple FEM and multiple PMICs, with the inference model distributed across multiple chips in the transceiver;

[0064] Figure 28 is a block diagram of a transceiver and an AP with the inference model distributed across the FEMs and the AP;

[0065] Figure 29 is a block diagram illustrating that a training set for a FEM inference model may be based on FEM-only measurements;

[0066] Figure 30 is a block diagram illustrating that a training set for an inference model in the AP may be based on measurements of the BBP, AP, and / or the FEM;

[0067] Figure 31 is a block diagram of a beam former in a millimeter wave (mmWave) FEM that may be used with a transceiver of the present disclosure where an inference model is distributed into the beam former; and

[0068] Figure 32 is a block diagram of a wireless communication device with multiple mmWave FEMs and a distributed inference model;

[0069] Figure 33 is a block diagram of a FEM driver responding to a request for write from a BBP where the BBP provides information about operating conditions from which the FEM driver may select a bundle of register settings from a palette according to aspects of the present disclosure;

[0070] Figure 34 is a block diagram of a FEM driver responding to a request for write from a BBP where the BBP provides information about operating conditions from which the FEM driver may select a bundle of register settings from a multi-dimensional palette according to aspects of the present disclosure;

[0071] Figure 35 is a block diagram of a FEM driver responding to a request for write from a BBP where the BBP does not provide information about operating conditions, but the BBP may make the bundle selection from a provided palette based on information known by the BBP about the palette;

[0072] Figure 36 is a block diagram of a FEM driver responding to a request for write from a BBP where the BBP does not provide information about operating conditions, and the FEM driver provides the palette to the BBP for the BBP to make a selection; and

[0073] Figure 37 is a block diagram illustrating the programming abstraction layer, which may facilitate an interface with the inference model.DETAILED DESCRIPTION

[0074] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0075] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0076] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, no intervening elements are present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. Incontrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0077] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0078] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a," “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises," “comprising," “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0079] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0080] As a note of initial nomenclature, it is appreciated that certain classes of linguistic purists may distinguish between a baseband processor (BBP), a transceiver (which may be an intermediate frequency processing circuit or chip), and a front-end module (FEM). However, other technical publications define the transceiver as including everything from and including the BBP to the antenna. FEMs may variously be defined as everything between the antenna and the digital BBP; just the transmit / receive switches, filters, and diplexers for band switching; or the switching elements with amplifiers. Given this disparate usage, the present disclosure specifically defines a transceiver to be the BBP, any intermediate frequency processing (IF) circuit, and the FEM (basically the BBP up to the antenna in the transmit direction or everything after the antenna through the BBP in the receive direction). While this definition may offend certain purists, the explicit definition is provided to avoid confusion. Likewise, FEM is defined to be power amplifiers, switching elements, and filters that lie between the antenna and any IFprocessing circuitry. Where relevant, to distinguish between the use of “transceiver” to refer to both the IF circuit and the entire path up to the antenna, the terms “transceiver circuit” and “transceiver chain” are used, respectively. It should be appreciated that in some aspects, all elements may be provided in a single board (i.e., multiple integrated circuits, surface-mounted elements, and the like) or on separate elements.

[0081] Additionally, to the extent that the term “approximately” is used in the claims, it is herein defined to be within five percent (5%).

[0082] Aspects disclosed in the detailed description include a distributed inference model for optimizing a FEM in a wireless communication device. In particular, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., through machine learning or deep learning Al techniques). The inference model may then associate with a microprocessor in the transceiver. The model will use as inputs a current operating condition based on data from a baseband processor (BBP) and the FEM and compute appropriate settings for the adjustable elements within the FEM.

[0083] Additionally, the inference model may be distributed amongst a variety of microprocessors within the FEM or BBP. The distributed inference model may be sized according to the size and power of the respective associated microprocessor. In this manner, no one device bears the entire burden of handling the inference model. This may result in less traffic on communication buses and reduce the overall device size. Further, such optimization in the FEM may result in power savings and / or improved user experience.

[0084] Aspects disclosed in the detailed description include systems and methods for optimizing a FEM in a wireless mobile device. In particular, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., through machine learning or deep learning Al techniques). The inference model is then associated with a microprocessor in the transceiver. The model will use as inputs a current operating condition based on data from a BBP and the FEM and compute appropriate settings for the adjustable elements within the FEM. Additionally, the FEM may provide measurements to a remote server that are then used as part of a training data set for future learning processes. Use of such an inference model to compute settings for the FEM allows wide flexibility and opportunities for post-sale optimization of the FEM. Further, such optimization may result in power savings and / or improved user experience.

[0085] Aspects disclosed in the detailed description include systems and methods for iteratively optimizing a FEM in a wireless communication device. In particular, various tunable elements within the FEM may have optimal settings based on operating conditions. Optimal settings may be found by creating an inference model (e.g., through machine learning or deep learning Al techniques). The inference model is then associated with a microprocessor in the transceiver. The model will use as inputs a current operating condition based on data from a BBP and the FEM and compute appropriate settings for the adjustable elements within the FEM. Additionally, the FEM may provide measurements to a remote server that are then used as part of a training data set for future learning processes and to update the inference models used in the FEM. Use of such an inference model to compute settings for the FEM allows wide flexibility and opportunities for post-sale optimization of the FEM. Further, such optimization may result in power savings and / or improved user experience.

[0086] Further aspects of the present disclosure focus on how information is provided from the inference model so that the information may be written into the relevant registers to modify the behavior of the tunable elements in the transmission chain. More particularly, a programming abstraction layer (PAL) may exist between the inference model and an operating system in a device such as the BBP or the AP. The BBP or AP sends a request for a write command to the PAL, which queries the inference model and responds with a palette of options from which the BBP or AP selects based on operating criteria. This approach is particularly useful when the source of the inquiry possesses information relating to operating conditions that may not be available to the inference model.

[0087] Before addressing exemplary aspects of the present disclosure, an overview of a conventional approach to providing adjustments based on operating conditions is provided with reference to Figures 1-3. A discussion of broad aspects of using a machine learning process with a resultant inference model begins below with reference to Figures 4-6, with additional details and variations explored in the subsequent Figures. An exploration of an iterative process of improving the inference model according to aspects of the present disclosure begins below with reference to Figure 16. A discussion of the distributed inference model begins below with reference to Figure 20.

[0088] In this regard, Figure 1 is a block diagram of a conventional transceiver 100 with a BBP 102 and a FEM 104. IF processing circuitry is omitted for the sake of clarity. Again, while this use of transceiver may be inconsistent with some published definitions,this use of transceiver is consistent with the definition provided above. The FEM 104 is coupled to an antenna 106, which may be an antenna array in some instances. The FEM 104 includes a transmit chain 108 and a receive chain 110. The transmit chain 108 may include a driver amplifier 112 and an output amplifier 114, as well as other circuitries such as filters, switches, or the like. Likewise, there may be additional amplifier stages (not shown). The receive chain 110 may include a plurality of low noise amplifiers 116(1)-116(M) as well as other circuitry (not shown).

[0089] In an effort to keep operation efficient, changes may be made to certain “tunable” elements within the FEM 104 based on operating conditions. For example, as better illustrated in Figure 2A, a power amplifier control circuit 200 may be coupled to a power amplifier circuit 202. More particularly, a controller 204 may receive a signal 206 from the BBP 102 (not shown in Figure 2A) through a digital input / output (I / O) 208. The signal 206 may include, for example, information about a power level and / or a frequency band of operation. Based on the signal 206, the controller 204 may access a look-up table (LUT) 210 (better illustrated in Figure 2B) to determine bias levels that, when applied to the amplifiers 112, 114, will cause more efficient operation. In particular, the controller 204 may use bias generator circuits 212A, 212B to send bias signals to bias circuits 214A, 214B, respectively, to provide the selected biases to the amplifiers 112, 114.

[0090] The LUT 210 may be, in the example of Figure 2B, a two-dimensional matrix that sets the operational frequency band (Y-axis 220) against power (X-axis 222), where the power level is coarsely divided into low, mid, and high bands 224A-224C. Based on the signal 206, two bits (e.g., Bl, B2) are found in the LUT 210 and provided to the bias generator circuits 212A, 212B to cause a desired bias to be generated.

[0091] In early generations, this simple two-dimensional LUT 210 was adequate. However, the continuing evolution of wireless standards coupled with the proliferation of multiple transceiver devices (e.g., a smartphone may have a cellular transceiver, a WIFI transceiver, a BLUETOOTH transceiver, an infrared transceiver, and the like) with multiple tunable elements greatly increases the complexity of the spectrum of tunable elements with a corresponding increase in the complexity of the LUT.

[0092] By way of example, Figure 3 illustrates a block diagram of a conventional transceiver 300 with a BBP 302 and a FEM 304 (again, IF circuitry omitted for clarity) within a mobile device. The FEM 304 may send and receive signals to and from the BBP 302, including information about the frequency band, power level, modulation scheme, and the like (e.g., BB info). Additionally, information from detectors 306(l)-306(P),including local temperature, local supply voltage, a process comer, voltage levels at particular points of the FEM 304, current levels at particular points of the FEM 304, and the like (e.g., FEM info) may be collected to further define operating conditions in the transceiver 300. This information may be used in a multi-dimensional LUT 308 to provide register settings for registers that control tunable elements 310(l)-310(Q). The tunable elements 310(l)-310(Q) may include bias circuits, load lines, switches, filters, couplers, and the like.

[0093] Creating the entries for the LUT 308 is an enormous task. Historically, a brute force approach is used where a single input variable is changed through a variety or range of settings while keeping other input variables constant and outputs measured. From these outputs, register settings may be determined and stored in the LUT 308. After sweeping through the range of settings, one other input variable is adjusted, and the process is repeated until each axis of inputs has been tested against a reasonable number of possible values on each of the other axes. This brute force process may be performed from scratch for each new product and potentially for each time a product is updated. The alternative is to have a coarser resolution in the LUT 308, which may lead to inefficient operation as certain combinations of operating conditions do not have optimal register settings in the LUT 308.

[0094] The parent disclosures describe using an inference model developed based on machine learning or deep learning artificial intelligence techniques to assist in optimal operation. The inference model may be generated in a lab setting using a basic set of inputs and then associated with a microprocessor in a BBP or FEM, as better illustrated in Figures 4A and 4B, respectively. In this regard, Figure 4A illustrates a transceiver 400 with a BBP 402 and a FEM 404 within a mobile device. Again, it is appreciated that this definition of transceiver may be overgenerous but is consistent with the explicit definition provided above. The BBP 402 may include a microprocessor 406 loaded with the inference model. The BBP 402 may use the microprocessor 406 to compute dynamically a “best” optimized collection of settings for all tunable elements in the FEM 404 (e.g., elements within a transmit chain 408 or receive chain 410) for a given operating condition. In contrast, Figure 4B illustrates a transceiver 420 with a BBP 422 and a FEM 424. The FEM 424 may include a microprocessor 426 loaded with the inference model. The FEM 424 may use the microprocessor 426 to compute dynamically a “best” optimized collection of settings for all tunable elements (e.g., elements within a transmit chain 428 or a receive chain 430) in the FEM 424 for a given operating condition.

[0095] In either case, the settings are dynamically computed. However, there may also be some settings that are adjusted statically based on the operating condition, and the present disclosure encompasses this hybrid approach to providing settings for optimal operation of the FEM.

[0096] The aspects illustrated in Figures 4A and 4B contemplate a single inference model located in a single device or associated with a single microprocessor. However, aspects of the present disclosure contemplate a distributed inference model that may have portions of the model located in different devices and / or associated with different microprocessors. These aspects are discussed below with reference to Figure 20. However, before addressing those aspects, more context is provided.

[0097] Figure 5 is a flowchart showing a general process 500 for creating the inference model for use in a transceiver such as a transceiver 400 or 420. The process 500 begins by defining which elements are to be controlled by the inference model (e.g., which are dynamic, and which are statically defined) (block 502). Then, a series of inputs are provided to a transceiver (block 504) (and, more particularly, the FEM portion of the transceiver), and outputs based on these inputs are measured (block 506). The inputs and outputs are assembled into a training data set (block 508). This assembly may include cleaning and labeling the data set. An Al is then trained using the training data set (block 510). While the precise parameters of the training data set may be varied, it is contemplated that the training data set will include input data from the BBP such as the band of operation, power level, bandwidth, modulation type or generation, known blockers (either self or detected), carrier aggregation mode, modulation maximum back off power ratio (MPR), modulation peak to average ratio (PAR), and the like; data from the FEM such as local temperature, local supply voltage, process corner, any current FEM settings, and the like; and communication link performance data such as bit error rate (BER), signal-to-noise ratio (SNR), and the like.

[0098] In the past, during lab evaluation of a FEM, a large amount of data is measured. In most cases, extensive sweeps of different adjustable settings are done to determine the optimal setting for a given operation case. Most of such data was discarded, and only the “optimal” settings were saved in the LUT. In contrast, the present disclosure contemplates using all the data measured in the lab during evaluation as part of the training data set.

[0099] Note that this Al may be a machine learning (e.g., relying on machine learning (e.g., using non-convolutional methods) or deep learning (e.g., using convolutionalmethods). The Al will output an inference model, which is then enabled (block 512) and given a performance check (block 514). If the inference model fails the performance check at block 514, the training data set is adjusted (block 516), and the new data set is used to train the Al returning to block 510 to develop a new candidate inference model. Once the performance check is passed, the model is deployed to hardware (block 518) (e.g., installed with a microprocessor in a FEM, BBP, or other external processor such as an application processor (AP)). In an exemplary aspect, this deployment may be software only, hardware only, or a hybrid approach.

[0100] Figure 6 provides a flowchart of a process 600 for the use of the inference model developed by the process 500 of Figure 5. The process 600 begins after deployment, where inputs are received at the microprocessor (block 602) associated with the inference model. These inputs can be from detectors in the FEM and / or also from the BBP. The microprocessor uses the inference model to compute settings dynamically for tunable elements of the FEM (block 604). The FEM implements the settings and operates (block 606). Optionally, the FEM measures the outputs (block 608) and reports this output data to a training site (block 610). The training site may then add this data to the training data set and update the model (block 612). The training site may then send out a patch, and the model deployed in hardware (e.g., a phone) may be patched (block 614) with the updated model. More detail on this is provided beginning below with reference to Figure 16.

[0101] The discussions of Figures 4A-6 provide an accurate description of high-level aspects of the present disclosure with an effort to at least touch on possible and / or likely variations within the material. However, in the interests of completeness, the following Figures 7 A- 14 step through specific permutations of use of an inference model. The process of iteratively improving the inference model is discussed below beginning at Figure 16. The aspects related to a distributed inference model are discussed below beginning at Figure 20. Discussion of aspects relating to the nature of the interface for the inference model begins below beginning at Figure 33.

[0102] In this regard, Figure 7 A illustrates one permutation of block 504 of Figure 5 and, specifically, the situation where there is little or no information from the BBP. Such a situation may occur where a BBP provider also sells a FEM and does not collaborate with other FEM providers to help optimize the settings. Accordingly, Figure 7A illustrates a training environment 700 where a generator 702 provides input signals 704 to a FEM 706. The input signals 704 may be the signal to be transmitted, as well as anyinput qualifiers such as modulation type, modulation bandwidth, peak-to-average ratio (PAR), or the like. Concurrently, the FEM 706 may have registers 708 populated with candidate settings by an input device (not shown) through an input interface 710 (sometimes referred to as an input-output (I / O) interface). The FEM 706 generates output signals 712, which may include actual transmission / received signals as well as signals generated by any or all of the detectors within the FEM 706. Measurement equipment 714 may measure the output signals 712. A data set 716 may receive the settings, the input qualifiers, the measurements, and output qualifiers (e.g., noise, adjacent channel leakage ratio (ACLR), signal-to-noise and distortion ratio (SNDR), and the like). As such, a first data set type can he extracted using measurements from the FEM 706 with no interaction or knowledge of the baseband correspondent of the radio frequency (RF) signals.

[0103] Conversely, Figure 7B illustrates a training environment 740 where a BBP 742 cooperates with a FEM 744 and provides additional data for a data set 746. Specifically, the BBP 742 may provide input signals, output signals, input qualifiers, and output qualifiers to the data set 746. The BBP 742 may also provide the candidate settings to the FEM 744 for use by the registers 748. The FEM 744 or the BBP 742 may provide the candidate settings to the data set 746. Additionally, the BBP 742 may provide more robust qualifiers, including bit error rate (BER), error vector magnitude (EVM), and the like.

[0104] After construction of the data set 716 or 746, higher-power computing modules, such as a dedicated Al server, are used to train the inference model. As noted in Figure 5, multiple iterations of model training may occur until the model is acceptable. Likewise, the model may be updated using the same sort of higher-power computing modules based on reported data from deployed hardware. As noted in the process 500, once the model is trained, it may be deployed into a piece of hardware where it can run and generate the FEM settings based on detected operating conditions. Note that while cellular devices are specifically contemplated, the present disclosure is not so limited and may be deployed in any device that includes a wireless transceiver (or, as explained in greater detail below, multiple wireless transceivers) including, but not limited to, base stations, mobile terminals, set top boxes, or the like.

[0105] Depending on whether the BBP coordinates with the FEM, the model may be deployed to the BBP or the FEM, as shown above in Figures 4 A and 4B, as well as in more detail with reference to Figures 8A and 8B. Note, as further explained belowbeginning with reference to Figure 20, the deployment may be distributed across multiple devices concurrently. In this regard, Figure 8A illustrates a wireless mobile device 800 with a BBP 802 and a FEM 804. Optionally, an intermediate RF transceiver circuit 806 (note that this use is more consistent with some of the alternate definitions and thus is described as a transceiver circuit) may exist that upconverts signals from a baseband to an intermediate frequency or downconverts RF signals to an intermediate frequency and conditions (e.g., filters, amplifies, or the like) the intermediate frequency signals before passing the conditioned signals upstream or downstream. Alternatively, the intermediate RF transceiver circuit 806 may instead upconvert and downconvert between baseband frequencies and RF. The BBP 802 may include a first signal processor 808 (also referred to as a modem in the Figures) that operates to generate the signals to be transmitted or processes the received signals. Additionally, the BBP 802 may include a model microprocessor 810 that operates with the inference model 812 to generate register settings (FEM settings) based on operating conditions. As used herein, the term “model microprocessor” is used to indicate a microprocessor configured to work with the inference model developed by the process 500. That is, it remains a processing core or other piece of hardware that is capable of using the Al-generated model. What is excluded from this term is a piece of software that models a microprocessor. Since most of the information the inference model 812 uses comes from the first signal processor 808 (e.g., BB Info), having the model microprocessor 810 in the BBP 802 may minimize data exchange over a digital bus 814. While the model microprocessor 810 is shown as a distinct element compared to the first signal processor 808, in some aspects, the first signal processor 808 may include the model microprocessor 810 (not shown explicitly). Regardless, the BBP 802 will send FEM settings over the digital bus 814 through a bus interface 816. The model microprocessor 810 may also receive FEM information (FEM info) from the FEM 804, which is used to help generate the register settings. In an exemplary aspect, the digital bus 814 may comply with the radio frequency front end (RFFE) standard set forth by MIPI, copies of which are available to members at www.mipi.org. While a digital bus is explicitly contemplated, the bus may be an analog bus if needed or desired.

[0106] With continued reference to Figure 8A, the FEM 804 may include a bus interface 818 that is configured to couple to the digital bus 814. FEM settings received through the digital bus 814 are stored in registers 820 and used to adjust tunable elements within the FEM 804 in either the receive chain 822 or the transmit chain 824 (or both).Detectors 826 may be used to collect information about the conditions (e.g., temperature, supply voltage, process comer, load voltage standing wave ratio (VSWR), or the like) for the FEM 804 and are provided to the BBP 802 through the digital bus 814.

[0107] In contrast, Figure 8B illustrates a wireless mobile device 830 with a BBP 832 and a FEM 834. An optional intermediate RF transceiver circuit 806, as described above, may also be present. The BBP 832 sends BB info to the FEM 834 through the digital bus 814. The FEM 834 may include a model microprocessor 836 that operates with the inference model 838 to generate FEM settings from the BB info and the FEM info provided directly to the model microprocessor 836 by the detectors 826.

[0108] Various factors may contribute to where the model microprocessor is located, including how much data must be sent across the digital bus 814. In many cases, the BB info is restricted to a few bytes. Depending on how many detectors 826 are present, the FEM info may be smaller, comparable, or larger than the BB info. The BBP 802 (or 832) is generally larger and has more processing power than the FEM 804 (or 834). Additionally, a computing device may have multiple FEMs for different purposes (low band, medium-high band, ultra-high band, E-UTRA New-Radio Dual Connection (ENDC), diversity receiver (DRX), Antenna Control System (ACS), etc.), and there may be advantages to having a centralized deployment of the inference model. It should be appreciated that there may be instances where the manufacturer of the BBP may not want to share operations with the FEM, which may dictate the location of the model microprocessor.

[0109] Another option would be to move the model processor to a third processor external to the BBP or the FEM, as better illustrated in Figure 8C. Specifically, Figure 8C illustrates a wireless mobile device 850 with a BBP 832 and a FEM 804. The optional intermediate RF transceiver circuit 806 may be present. The FEM 804 provides FEM info to the BBP 832 through the digital bus 814. The BBP 832 provides the BB info and the FEM info to an external processor 852. The external processor 852 may be an application processor or other microcontroller. The external processor 852 may communicate with the BBP 832 through a bus 854 and receive the FEM info and BB Info therethrough via a bus interface 856. The external processor 852 includes a model microprocessor 858 that works with the model 860. The model microprocessor 858 uses the model 860 to generate FEM settings which are passed to the FEM 804 through the BBP 832 and the digital bus 814.

[0110] Various factors may lead to the use of an external processor 852. An application processor is usually the largest, most powerful processor and is usually implemented in the most advanced semiconductor process. The application processor may have large compute power and memory storage and offer higher power efficiency. Additionally, the application processor may have a dedicated computation core developed for running Al applications such as the inference model. This dedicated core may speed up the determination of optimized FEM settings. However, using an application processor may extend the communication path and require additional bus links from the BBP to the external processor 852.

[0111] Regardless of location, using a model microprocessor and inference model means that the FEM settings are generated for each scenario separately, effectively eliminating the need for a LUT. However, as noted above, some settings may be set statically, and a LUT may still be present in such instances. The model microprocessor may be dedicated for Al applications and have a specific Al inference model deployment environment. Local placement of the model microprocessor provides shorter communication links (e.g., through the digital bus 814). The shorter distance for a local model microprocessor may result in an overall faster reaction time. Designers may weigh these tradeoffs and locate the model microprocessor according to their own design criteria.

[0112] Again, further details on how the various strengths of the different locations may be leveraged through a distributed inference model are discussed below with reference to Figure 20.

[0113] The discussion of the wireless mobile device 800, 830, and 850 has had a very simplified FEM. Figure 9 illustrates with greater detail a FEM 900 that may use the inference model of the present disclosure to set a variety of tunable elements and includes detectors that provide FEM info for use by the model microprocessor. Initially, a model microprocessor 902 with model 904 may be present within the FEM 900. Alternatively, a model microprocessor 902’ with model 904’ may be external to the FEM 900 and accessed through a communication bus 906, as discussed above.

[0114] With continued reference to Figure 9, the FEM 900 may include a bus interface 908 configured to be coupled to the communication bus 906. The bus interface 908 is broadly construed to cover not just the links used to exchange FEM info, BB info, and / or FEM settings but also links used to convey signals to be transmitted, received signals, and / or other control signals. The FEM 900 may include, without limitation, atransmit chain 910, a receive chain 912, a load line circuit 914, a distribution switch (DSW) 916, various filters 918(1)-918(R), an antenna switch 920, couplers 922A, 922B, a receive load circuit 924, and the like. Note that there may be multiple transmit chains and multiple receive chains (neither shown). The transmit chain 910 may include power amplifiers 926, 928. The receive chain 912 may include LNAs 930, 932. As shown, many of these elements may be tunable or adjustable and may have an associated register (not shown) that controls the tuning / adjusting. The FEM settings from the model microprocessor 902 (or 902’) may be written into these registers, and operation of the FEM 900 controlled thereby. Still further, many of these elements include detectors 934(1 )-934(S), which report operating conditions (i.e., FEM info) to the model microprocessor 902 (or 902’). Other detectors (e.g., temperature, supply voltage, process corner; none shown) may also be present and provide other FEM info to the model microprocessor 902 (or 902’). Numerous permutations of which elements are tunable and which elements have direct detectors are contemplated, and the precise disposition is not central to the present disclosure.

[0115] Figure 10 is a block diagram of a general portable device FEM 1000 with multiple types of modules 1002(l)-1002(T), including a low noise amplifier and duplexer (LPAMID) 1002(2), power management integrated circuit (PMIC) 1002(3), ENDC 1002(1), and the like. Each module 1002(1)- 1002(T) may have an adjustable element and / or a detector that reports FEM info to the model microprocessor 1004 for use by the model 1006. The FEM info may reach the model microprocessor 1004 through an interface 1008. Note further that many different modems with transceivers are contemplated, such as WIFI, BLUETOOTH, global positioning satellite (GPS), millimeter wave (mmWave), ultrawideband (UWB), and the like, in addition to the basic cellular wireless transceivers.

[0116] As noted above, the model microprocessor may use the model to determine all the settings for the FEM. This situation is shown in Figure 11, where a FEM 1100 includes a model microprocessor 1102 that uses a model 1104 to generate all settings for registers 1106, which control adjustable elements 1108(1)- 1108(U). This arrangement may put a lot of stress on the inference process. It should be noted that some settings may be easy to determine, even from a lab evaluation (i.e., the conventional approach). Removing these easy settings from the decision of the inference model may result in a small-size model that can be better optimized. Additionally, a small-size model may be generated in less time, potentially relative to a holistic model.

[0117] Figure 12 illustrates the alternate possibility, where a FEM 1200 includes a model microprocessor 1202 that uses a model 1204 to generate some settings for registers 1206 with other settings stored in a memory LUT 1208. Collectively, the registers 1206 control adjustable elements 1108( 1)- 1108(U).

[0118] A more challenging environment that is still able to be addressed by aspects of the present disclosure is the existence of higher-order carrier aggregation in the presence of multiple blockers. Figure 13 shows a transceiver 1300 that is able to use an inference model 1302 associated with a model microprocessor 1304. While shown as external to a FEM 1306, as explained above, the location of the model microprocessor 1304 is not central to this aspect. A BBP 1308 provides demodulation information as well as known blockers (e.g., WIFI and BLUETOOTH) and other BBP info to the model microprocessor 1304. Similarly, the FEM 1306 provides detected blocker information as well as FEM info to the model microprocessor 1304. Additional FEMs 1306X may be present and use the same inference model 1302.

[0119] Figure 14 shows a transceiver 1400 that has a BBP 1402 and a FEM 1404 with multiple antennas 1406(l)-1406(V). A model microprocessor 1408 works with a model 1410 according to aspects of the present disclosure to provide FEM settings for the FEM 1404. In the case of uplink-multiple input-multiple output (UL-MIMO), two or more UL transmit paths 1412 are using the antennas 1406(l)-1406(V) with finite isolation. Each transmit path has a dedicated output coupler 1414A, 1414B before going to the antennas 1406(l)-1406(V). The coupler signal, which is a direct measurement of the UL-MIMO signal, can be sent to the BBP 1402, where it is converted by an auxiliary demodulator 1416. The quality outcome signals from the auxiliary demodulator 1416 can be used as part of the training data for the inference model 1410. The FEM settings include elements that can tune separately the UL-MIMO paths. Each path may have a separate bias, optional load-line tuning, and the like. Such individual settings can be used to reduce the orthogonal MIMO components and associated intermodulation devices due to antenna coupling. Similar use of the inference model 1410 may be applied to receive MIMO paths. While having information from the BBP 1402 is useful for the transceiver 1400, there may be instances where such information is unavailable and may be derived from detectors in the FEM 1404.

[0120] With reference to Figure 15, the concepts described above may be implemented in various types of user elements 1500, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wirelesscommunication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user elements 1500 will generally include a control system 1502, a baseband processor 1504, transmit circuitry 1506, receive circuitry 1508, which form part of a transceiver which may include the inference model of the present disclosure, antenna switching circuitry 1510, multiple antennas 1512, and user interface circuitry 1514. In a non-limiting example, the control system 1502 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 1502 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 1508 receives radio frequency signals via the antennas 1512 and through the antenna switching circuitry 1510 from one or more base stations. A low noise amplifier and a filter of the receive circuitry 1508 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0121] The baseband processor 1504 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations. The baseband processor 1504 is generally implemented in one or more digital signal processors (DSPs) and ASICs.

[0122] For transmission, the baseband processor 1504 receives digitized data, which may represent voice, data, or control information, from the control system 1502, which it encodes for transmission. The encoded data is output to the transmit circuitry 1506, where a digital-to-analog converter(s) (DAC) converts the digitally encoded data into an analog signal, and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1512 through the antenna switching circuitry 1510 to the antennas 1512. The multiple antennas 1512 and the replicated transmit and receive circuitries 1506, 1508 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0123] Additionally, the user element 1500 may include a control circuit 1550 and associated memory 1552. Aspects of the present disclosure may be initiated by the control circuit 1550 and data stored in the memory 1552 as better explained below.

[0124] The above discussion presents the context and possible scope of possible use for an inference model in a wireless communication device. As noted, while the emphasis may be on mobile terminals such as cellular or smartphones, the present disclosure is not so limited and may be used in other wireless devices such as base stations or the like. One of the further advantages of an inference model is that increasingly sophisticated (and hopefully more accurate) models may evolve as additional data is used to train the inference model. Accordingly, the training AT may receive data at a training site from deployed wireless communication devices where the data relates to operating conditions, inputs, and outputs, as well as settings for tunable elements within the wireless communication devices. Note that the more wireless communication devices that contribute data, presumptively the better because this data may be added to the data set used to train the Al, and the process 500 may be iterated with the new data set that has much more data than the original lab data. Once the model passes a performance check, the model may be provided back to existing deployed wireless communication devices, such as through an over-the-air update or, in the case of a base station, a software patch through any means. Furthermore, this updated model may be sent to the device manufacturers such that subsequently sold devices may be sold with the updated version (instead of the original version). This process is set forth in greater detail in Figure 16.

[0125] In this regard, Figure 16 shows a process 1600 that begins with the process 500 (block 1602). The wireless communication device (WCD) enters service and collects data (block 1604) during normal operation (in essence, blocks 602, 604, 606, 608 of process 600). Upon being polled, periodically, or on reaching a threshold volume of collected data, the WCD communicates the data to a training facility (block 1606). More specifically, the control circuit 1550 may cause data to be collected during normal operation and stored in the memory 1552. The control circuit 1550 may have software that is configured to cause the WCD to respond to polling from the training facility or initiate a data transmission automatically (e.g., similar to automatic software updates). There may be a user prompt to share the information if needed or desired. As noted above, this data collection occurs across a plurality of deployed WCD. The training dataset is updated (block 1608) with the collected data from one or more deployed WCD. The inference model is retrained (block 1610) and performance checked (block 1612). If theperformance check fails, the model is retrained again at block 1610 until the performance check is passed. The new model is sent to manufacturer(s) with the FEM and or BBP (block 1614). Subsequently manufactured WCD includes the updated or latest model (block 1616). Concurrently or subsequently (or even before block 1614), patch is provided to already deployed WCD (block 1618) and the process repeats.

[0126] Note that there may also be an intermediate training step that has not been illustrated in Figures 15 or 16. Specifically, the FEM could be tested in isolation, and an initial FEM-only dataset used to train the model. This proto-model could then be updated after the FEM had been integrated into a device and lab testing done on the competed assembly. This new dataset could then be used to retrain the model. Then preliminary completed device testing could be done, and this new data could be used to retrain the model, all before device deployment.

[0127] Note that there are also multiple ways that the model can be deployed. In a first exemplary aspect, the model is actually not deployed. Rather the model is used to create a static LUT 1702, which is then deployed with the WCD 1700 as better illustrated in Figure 17A. The settings in the LUT 1702 are used to control tunable elements in the BBP 1704 and the FEM 1706. The inference model 1708 is still created in the training environment 1710 using data sets and lab testing and subsequent updates from deployed WCD as previously described. This arrangement imposes the least processing penalty on the WCD 1700 but has the least flexibility in adapting to changing conditions not contemplated by the settings in the LUT 1702.

[0128] Alternatively, as shown by the WCD 1720 of Figure 17B, the WCD 1720 may include a LUT 1722 in the BBP 1724 (or the FEM 1726) that uses a software or firmware implementation of the inference model that generates FEM settings for each operation scenario. Again, the training environment 1710 remains as described above.

[0129] Still, another alternative, as shown by the WCD 1740 of Figure 17C, may include a hardware implementation of the inference model that generates FEM settings for the FEM 1744 and / or the BBP 1746 from the LUT 1742.

[0130] As a further illustration of the multiple training levels and the multiple sources of information for a dataset, Figure 18 illustrates first training 1800 on just the component lab dataset (e.g., just the FEM), which may be done by the component vendor (e.g., the FEM vendor). This dataset is expanded, and the model retrained 1802 with the phone OEM dataset, which may be done by the phone OEM and / or the BBP vendor. This model created at 1802 is the model initially deployed in the first generation of the WCD. Thendata is collected from multiple WCD 1804(l)-1804(B) and sent back to the training facility for generation of iteratively optimized models 1806. These new models are then sent back out to the WCD 1804(l)-1804(B) as well as any newly made WCD.

[0131] Note that training with all the possible inputs and outputs may make a model that is too cumbersome for current processor cores that are commercially available and used in WCD. Accordingly, it may be possible to identify conditions that are weakly dependent such that they may be neglected without compromising performance. Figure 19 shows an example of a dependency matrix that may be eliminated due to weak or nonexistent dependence. Note that these are used just as an example and in reality, these may be more tightly dependent than suggested by graph 1900 of Figure 19. This sort of pruning may be done if a performance check fails or as part of conditioning the dataset. Further simplification can be done using quantization. This process is related to the number of bits used to describe different frequencies. If a dependence is nonlinear and has high sensitivity, a larger number of bits may be used to increase the resolution of the model. For the dependencies that are less nonlinear or have lower sensitivities, a lower number of bits may be used.

[0132] The above discussion focuses on the existence of an inference model and techniques through which the inference model may be iteratively improved. However, deploying an inference model to a wireless communication device may have additional opportunities to optimize operation. Specifically, different chips within the transceiver or wireless communication device may have differing processing capabilities and thus be able to handle larger or smaller inference models. Additionally, the placement of an inference model in a particular location in the chipset may impose communication delays as signals are routed to the inference model and an output generated. Accordingly, exemplary aspects of the present disclosure contemplate distributing the inference model across multiple parts of the wireless communication device. Distribution of the inference model in this fashion may reduce burdens on communication buses, reduce latency, and exploit the existing computational power of the difference elements in the wireless communication device.

[0133] In this regard, Figure 20 illustrates a transceiver 2000 with a BBP 2002, a FEM 2004, and an intermediate transceiver circuit 2006. The BBP 2002 may include a modem 2008, a model microprocessor 2010, and a bus interface 2012 (also referred to as a digital I / O in the Figures; the terms may be considered synonymous) configured to couple to a communication bus 2014. The model microprocessor 2010 is generallyrelatively robust, especially in comparison to a model microprocessor 2016 in the FEM 2004 or the model microprocessor 2018 in the intermediate transceiver circuit 2006. The inference model may be distributed across the model microprocessors 2010, 2016, and 2018.

[0134] With continued reference to Figure 20, signals to be transmitted (input signals) and received signals (output signals) may pass between the BBP 2002, the intermediate transceiver circuit 2006, and the FEM 2004 through separate buses 2020A, 2020B, as is well understood. The intermediate transceiver circuit 2006 may include a bus interface 2022 configured to be coupled to the communication bus 2014.

[0135] With continued reference to Figure 20, the FEM 2004 may include a bus interface 2024 configured to be coupled to the communication bus 2014. The FEM 2004 may further include a plurality of registers 2026, as well as a plurality of detectors 2028. The plurality of detectors 2028 may measure temperature, voltage, process corner, bias (BI), VSWR, or the like. Further, the FEM 2004 may include a plurality of adjustable elements 2030, such as a power amplifier or LNA.

[0136] As described above, the adjustable elements 2030 are changed by the settings in the registers 2026. The registers 2026 may be filled by the model microprocessor 2016, the model microprocessor 2010, or some combination of the two. Similarly, settings for adjustable elements in the intermediate transceiver circuit 2006 may be set by the model microprocessor 2018, the model microprocessor 2010, or some combination of the two. The detectors 2028 may provide information to the model microprocessor 2016, and / or an aggregated event from the detectors 2028 may be sent to the model microprocessor 2010. Because the BBP 2002 has more inherent processing power, it may be appropriate to have the model microprocessor 2010 do most of the heavy computations using the inference model and send FEM settings to the registers 2026 in the FEM 2004 through the communication bus 2014. Additionally, some BBP info may be sent through the communication bus 2014. The BBP info may be used by the inference model in the model microprocessor 2016 in some aspects.

[0137] While the transceiver 2000 is one possibility, the transceiver 2000 may be combined with an application processor (AP) 2100 having a model microprocessor 2102 therein, as shown in Figure 21. The inference model may be distributed across the various model microprocessors 2102, 2010, 2018, and 2016. The AP 2100 has much greater computational power, and accordingly, the model microprocessor 2102 may be the largest of the four. Accordingly, the heaviest calculations may be done in the modelmicroprocessor 2102. This approach puts more burden on the communication bus 2014 and may add latency, but it is also possible that the model microprocessor 2102 may have the capability to adapt the inference model in near real-time rather than require such adaptations to occur at the training facility.

[0138] Instead of having a full inference model at the FEM, a difference inference model may be used, as shown in transceiver 2200 of Figure 22. Specifically, the BBP 2002 still sends nominal FEM settings from the model microprocessor 2010, but the model microprocessor 2202 uses the information from the detectors 2028 to calculate a difference adjustment, which is combined in a combiner 2204 before being written into the registers 2026.

[0139] It should be appreciated that use of the inference model is not limited to the FEM but may also be applied to settings for a power management integrated circuit (PMIC) such as PMIC 2300 in Figure 23. While the transceiver 2200 (or 2000) may be used, the model microprocessor 2010 may provide PMIC settings over the communication bus 2014. The PMIC 2300 may include a bus interface 2302 configured to be coupled to the communication bus 2014 and use information provided therethrough to adjust average power tracking (APT) or envelope tracking (ET) activity in the PMIC 2300 so as to set a Vcc tracking voltage 2304 for power amplifiers in the FEM 2004.

[0140] Alternatively, in the spirit of a distributed inference model, the PMIC may include a model microprocessor and use the inference model to generate settings locally, as better seen in Figure 24, where a PMIC 2400 may include a model microprocessor 2402 that may receive information from local detectors 2404. Combined with information received from the communication bus 2014, settings may be generated for the Vcc tracker 2406.

[0141] While the above discussion contemplates distributing the inference model to several locations, it should be appreciated that there may be instances where it makes more sense to consolidate the inference model into one or two of the large model microprocessors. This arrangement may be appropriate, for example, when there are multiple FEMs, and a consolidated approach helps reduce the likelihood of interference. Figure 25 illustrates a transceiver 2500 with a plurality of FEMs 2502(l)-2502(4), which may be, for example, a low band, a medium-high band (MHB), an ultrahigh band (UHB), and ENDC, respectively. In this aspect, the inference model may be consolidated in the BBP 2504 (i.e., model 2504A), an AP 2506 (i.e., model 2506A), or distributed across both. A communication bus 2508 may carry settings to the FEMs 2502(l)-2502(4).

[0142] In contrast, the inference model may be distributed through the multiple FEMs, as shown in Figure 26. In particular, a transceiver 2600 may include FEMs 2602(l)-2602(4), with respective model microprocessors 2604(l)-2604(4). As with previous aspects, detectors 2606(l)-2606(4) may provide information to the respective model microprocessors 2604(1 )-2604(4) for use in determining register settings.

[0143] Still further, the inference model may be distributed across multiple PMICs associated with the multiple FEMs, as better shown in Figure 27. Specifically, PMICs 2700(l)-2700(2) may also include model microprocessors 2702(l)-2702(2) that work with the FEMs 2602(l)-2602(2) in the transceiver 2600. In this aspect, there is no model microprocessor in the AP. This keeps the traffic on the communication bus 2508 relatively short distances and likely does not introduce excessive latency.

[0144] However, such an approach is not required in all cases, and as shown in Figure 28, the inference model may be distributed in the AP and the FEMs. Specifically, in a transceiver 2800 with an associated AP 2802 with model microprocessor 2804 that works with a portion of the inference model. In this aspect, a BBP 2806 does not include a model microprocessor and does not work with the inference model. The FEMs 2602(1)- 2602(4) will accept the FEM settings from the communication bus 2508 as previously described.

[0145] It should be appreciated that training may be modified to accommodate the distributed inference model. Likewise, updating through the iterative process described above may be modified to accommodate the distributed inference model. In this regard, Figure 29 illustrates a training environment 2900 that gathers information only from a FEM 2902 using a generator 2904 and measurement equipment 2906. Thus, the dataset 2908 only has information about the FEM 2902.

[0146] In contrast, a training environment 3000, illustrated in Figure 30, may be a more holistic training environment that generates inputs with an AP 3002 and measures outputs from a BBP 3004 and a FEM 3006 to make dataset 3008 for training the AL

[0147] Note that the present disclosure may also be extended to beam formers, such as may work with a millimeter wave (mmWave) FEM. Again, the inference model may be distributed. For example, as shown in Figure 31, a mmWave FEM 3100 may have a local model microprocessor 3102 that receives information from detectors 3104 and receives further setting information from a model microprocessor 3106 over a communication bus 3108. The model microprocessor 3106 may receive information from a beam former circuit 3110 (or be embedded therein, not shown). The beam former circuit3110 may receive information from a BBP 3112, and while not shown, the BBP 3112 may also have a model microprocessor that supports a portion of the distributed inference model.

[0148] This approach works even when there are multiple beam formers, as shown in Figure 32. Here, there may be a centralized model microprocessor 3200 which works with the inference model and does the majority of the computing. However, each of the FEMs 3100( l)-3100(3) has its own respective model microprocessor 3102(l)-3102(3) respectively.

[0149] The above discussion has provided lots of details about how the inference model may be used within various hardware configurations but provides little guidance on how the inference model may actually work. The discussion of Figures 33-36 provides at least a few possible options for how the inference model may push settings to the hardware for writing to registers. In particular, a programming abstraction layer (PAL) may be used to provide an interface from an inquiry source to the inference model. As discussed above, the inference model may be associated with a microprocessor in the BBP, and when the BBP determines that an adjustment to the operation of the FEM (or other element) is needed (i.e., the BBP is going to cause the registers in the have new information written therein), software in the BBP may cause a request for register settings (e.g., as a write request) to be sent to a software driver. The PAL sits conceptually in front of the software driver and translates the request to an inquiry for the inference model. Responsive to the inquiry, the inference model returns a palette of possible register settings sorted by additional criteria (e.g., linearity, efficiency, low power operation, or the like). The software that receives this palette from the software driver selects a bundle of register settings from the palette and provides instructions to elements in the transmission chain (e.g., the transceiver circuit, the PMIC, and / or the FEM). These instructions may be write commands to the registers of the tunable elements and / or instructions to other parts of a distributed inference model.

[0150] This approach is also contrasted with conventional pull models where a BBP passes some parameters to a FEM software driver, obtains limited FEM RFFE settings in the form of a register address and register data, builds scripts, and hands the scripts to Layer- 1 to execute and program the RF FEM via the RFFE bus. The conventional approach is limited by how granular the FEM software driver’s library of settings is along with the bandwidth of the RFFE bus, as discussed above. Modern FEMs may need specific settings for lots of different communication scenarios. This need results in largemulti-dimensional LUTS for the FEM settings. Such large multi-dimensional LUTs are sub-optimal.

[0151] For the purposes of discussion, it is presumed initially that only elements of the FEM are tuned using the inference model. Thus, as explained above, a FEM may have a number of registers that need to be written before a signal is processed and transmitted. Each operating scenario is characterized by a number of specific conditions, such as band of operation, modulation signal type, modulation bandwidth, and the like as explained above. As a further assumption, not every BBP manufacturer configures the BBP to share this information with the FEM. However, as noted above, better FEM settings may be selected if this information is used in selecting the settings for the registers.

[0152] In this regard, Figure 33 illustrates a first exemplary aspect of how the inference model can be used to provide appropriate settings when the BBP does share information. More specifically, a transceiver chain 3300 may include a FEM 3302 with various tunable elements as described above. The FEM 3302 may communicate with a BBP 3304 through, for example, an RFFE bus 3306 (e.g., through bus interfaces 3306A, 3306B). The BBP 3304 may include a control circuit 3308, which may be aware of operating conditions as described above. The control circuit 3308 may send a write request to FEM software driver 3310, which may be associated with the inference model 3312. In an exemplary aspect, the inference model 3312 is external to the BBP 3304 and may include a microprocessor (not shown) as previously described). In an alternate aspect, the inference model 3312 and the FEM software driver 3310 are loaded into memory of the BBP 3304.

[0153] The FEM software driver 3310 receives the request and acts as an intermediary for the inference model. In an exemplary aspect, and as explained in greater detail below, there may be a PAL acting as an interface for the BBP 3304 such that all the lower-level operations are transparent to the BBP 3304. Responsive to this request, the FEM software driver 3310 asks for operating conditions for the given communication scenario from the BBP 3304. The BBP 3304 provides such information either responsive to the driver’s ask or as part of the initial request.

[0154] The FEM software driver 3310 may have a set of criteria 3314 that are used to analyze the operating conditions and select a set or bundle 3316(x) from a palette 3318 of possible FEM bundles 3316(1)-3316(N). The FEM bundles 3316(1)-3316(N) are assembled by the inference model 3312 so that there is a bundle for each possiblecommunication scenario. While the selection of the bundle may be based on modem- controlled operating conditions, other operating condition criteria may also be used (e.g., low power, low battery, maximum efficiency, maximum linearity, temperature, or the like). The BBP 3304 then causes the selected bundle 3316(x) to be written to the registers in the FEM 3302.

[0155] In an exemplary aspect, the information may be arranged in a multidimensional fashion (e.g., a matrix having two or more dimensions), as is better seen in transmission chain 3400 in Figure 34. A paged memory of bundles 3402(l)-3402(P) or the like can be used to store such multi-dimensional palette 3404. One option is to have the palette 3404 indexed based on the given operating conditions. Another option is that some criteria will be used to analyze the operating conditions and select the bundle 3402(l)-3402(P) from the palette 3404.

[0156] In other circumstances, the BBP may not provide operating conditions to the FEM driver software. In such cases, the FEM driver software may provide the entire palette to the BBP, and the BBP may select an appropriate bundle based on the BBP’s knowledge of the operating conditions. That is, the FEM driver software may provide a palette index along with some indications as to what bundles are appropriate for what operating conditions.

[0157] In this regard, Figure 35 illustrates a transmission chain 3500, which is similar to those previously described in that there is a FEM 3502 and a BBP 3504 communicatively coupled by a bus 3506. However, the software or control circuit 3508 of the BBP 3504 does not provide the operating conditions to FEM driver software 3510. Nevertheless, the FEM driver software 3510 may have used the inference model 3512 to generate a plurality of bundles 3516(l)-3516(N) into a palette 3518 and may provide an index 3520 of the palette 3518 to the control circuit 3508. This index 3520 may include some information about the palette 3518, indicating which bundles are appropriate for which operating conditions. Then, the control circuit 3508 using its knowledge of the operating conditions and a knowledge of what selection criteria 3514 are to be used, issues a request for write with a pointer 3522 as to which bundle 3516(x) is to be used. Then the FEM driver software 3510 writes those values to the registers in the FEM 3502. Note that this approach may also work when the BBP 3504 provides limited information for the desired FEM setting optimization (e.g., best linearity, best efficiency, balance between linearity and efficiency, etc.)

[0158] Alternatively, as shown by transmission chain 3600 in Figure 36, which causes a request to be sent to the FEM driver software 3610 from the control circuit 3608 of the BBP 3604. The FEM driver software 3610 responds by providing the palette 3618 (based on the inference model 3612) having a plurality of bundles 3616( 1 )-3616(N) to the control circuit 3608 (shown as palette 3618’). Based on the known operating conditions and criteria for selection, a selection is made, and the FEM driver software 3610 is instructed to write that bundle to the registers in the FEM 3602.

[0159] Figure 37 provides a block diagram of a transmission chain 3700 which illustrates the PAL and how the discussion of Figures 33-36 is not limited to just FEM settings. Specifically, the inference model may provide a palette 3702 (which may be a multi-dimensional LUT) with bundles as previously described, where for example there may be reconfigured registers 3702R (Rl-Rn), Non-bias registers 3702T (Tl-Tn), and bias registers 3702B (B 1-Bn), which are optimized based on multiple dimensions 3702D, operating conditions such as band modulation, MPR, bandwidth, power, or the like. Still further, system information 3702S, such as supply voltage (Vcc), any digital predistortion (DPD) coefficients, or the like, may be included.

[0160] As illustrated, the modem software 3704 (i.e., the control circuit of the BBP) may issue the request for write 3706 with some or no information to the FEM driver software 3708. The PAL 3710 translates the request for write to the appropriate query to interact with the inference model 3712 and any RF driver core 3714 such that the BBP or modem does not have any knowledge of how the inference model 3712 is structured. Similarly, the PAL 3710 may translate the information from the inference model 3712 to a format that is more readily processed by the modem software 3704. The modern software 3704 may then do any selection from the palette provided from the FEM driver software 3708, make any system adjustments (e.g., DPD corrections or the like), and perform the write to the elements of the transmission chain such as a transceiver circuit 3718, a FEM 3720, a PMIC 3722 or the like.

[0161] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerousdifferent modifications, as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0162] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

AMENDED CLAIMS received by the International Bureau on 25 Oct 2024 (25.10.2024)1. A power amplifier comprising: an amplifying transistor; a cunent mirroring transistor physically proximate the amplifying transistor, such that the cunent minoring transistor is embedded in the amplifying transistor such that a gate, drain, and source of the cunent minoring transistor are interleaved with elements of the amplifying transistor, and having a thermal path coupling the amplifying transistor and the cunent minoring transistor; and a controller circuit coupled to the cunent minoring transistor and configured to adjust an input signal for the amplifying transistor to compensate for thermal droop.

2. (Canceled)3. The power amplifier of claim 1 , wherein the amplifying transistor and the cunent minoring transistor comprise gallium nitride (GaN) transistors.

4. The power amplifier of claim 1 , further comprising a second amplifying transistor cascoded relative to the amplifying transistor.

5. The power amplifier of claim 4, wherein the amplifying transistor comprises an output for the power amplifier relative to the second amplifying transistor.

6. The power amplifier of claim 4, wherein the amplifying transistor comprises an input for the power amplifier relative to the second amplifying transistor.

7. The power amplifier of claim 1, further comprising a variable attenuator that adjusts a signal to create a signal on which the input signal is based and wherein the controller circuit is coupled to the variable attenuator.

8. The power amplifier of claim 1 , further comprising a driver amplifier that creates the input signal and wherein the controller circuit is coupled to the driver amplifier.

9. The power amplifier of claim 1, wherein the controller circuit comprises a bipolar technology.

10. The power amplifier of claim 1, further comprising an active bias circuit coupled to the amplifying transistor.

11. A power amplifier comprising: an amplifier comprising: a first amplifying transistor coupled to an input node; a second amplifying transistor cascoded with the first amplifying transistor and coupled to an output node; a cunent minor comprising: a first minoring transistor physically proximate the first amplifying transistor, such that the first minoring transistor is embedded in the first amplifying transistor such that a gate, drain, and source of the first minoring transistor are interleaved with elements of the first amplifying transistor; and a second minoring transistor physically proximate the second amplifying transistor; wherein the cunent minor generates a shared cunent signal; and a controller circuit coupled to the cunent minor and configured to receive the shared cunent signal and produce a control signal to adjust an input signal to the amplifier to compensate for temperature droop.

12. The power amplifier of claim 11, further comprising an ambient temperature sensor comprising a second cunent minor spaced from the amplifier and configured to generate an ambient cunent signal provided to the controller circuit.

13. The power amplifier of claim 12, wherein the controller circuit is configured to use a difference between the ambient cunent signal and the shared current signal to generate the control signal.

14. The power amplifier of claim 13, further comprising a variable attenuator coupled to the controller circuit and the input node.

15. The power amplifier of claim 13, further comprising a driver amplifier coupled to the controller circuit and the input node.

16. The power amplifier of claim 13, further comprising an active bias circuit coupled to the input node and the controller circuit.

17. The power amplifier integrated into a device selected from the group consisting of: a set- top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

18. A method of compensating for thermal droop in a power amplifier comprising: positioning a cunent minoring transistor physically proximate an amplifying transistor, such that the cunent minoring transistor is embedded in the amplifying transistor such that a gate, drain, and source of the cunent minoring transistor are interleaved with elements of the amplifying transistor; positioning a second cunent mirroring transistor distant from the amplifying transistor;generating a difference between currents in the cunent mirroring transistor and the second cunent minoring transistor to generate a control signal; and using the control signal to adjust an input signal for the amplifying transistor to compensate for thermal droop.

19. The method of claim 18, wherein using the control signal comprises using the control signal in an active bias circuit.

20. The method of claim 18, wherein using the control signal comprises using the control signal in a driver amplifier.STATEMENT UNDER ARTICLE 19(1)Applicant herein amends claims 1, 11, and 18.The remaining claims are unchanged.The amendments to claims 1, 11, and 18 are based on paragraph 0094 of the Application as filed.If you have any questions, please do not hesitate to contact me.

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