Photonic chip having a heterogeneous iii-v semiconductor structure on a second semiconductor

Abstract

The invention relates to a photonic chip (10) having a heterogeneous III-V semiconductor structure on a second semiconductor comprising, in a stacking direction (Δ): a waveguide (11) made of a first III-V semiconductor material, referred to as the lll-V waveguide, comprising a first confinement layer (110), an active layer (111) and a second confinement layer (112), a waveguide (12) made of a second semiconductor material, referred to as the SC waveguide, comprising a layer (120) of the second semiconductor material. The first confinement layer (110) comprising a first portion (110a) on top of the active layer (111) and at least one extension (110b) extending laterally beyond the active layer (111), the extension (110b) having a thickness (Eb) in the stacking direction that is greater than that (Ea) of the first portion (110a) so as to define an electrical contact face (116) located before the first portion (110a) in the stacking direction (Δ).

Description

DESCRIPTION Title of the invention: Photonic chip with heterogeneous structure of III-V semiconductor on a second semiconductor

[0001] The invention relates to a photonic chip with a heterogeneous structure of a III-V semiconductor on a second semiconductor allowing efficient transmission, in particular adiabatic, without loss, of an optical mode between a waveguide made of a first III-V semiconductor material and a waveguide made of a second semiconductor material.

[0002] There is interest in integrated photonic circuits on silicon chips using silicon optical guides. Such photonic circuits have the advantage of being achievable with the large-scale manufacturing lines of well-known CMOS technologies. However, silicon is a semiconductor that is not well suited for use as a laser source or optical amplifier, due to some of its physical parameters, particularly its indirect band gap.

[0003] However, III-V semiconductor structures are known for producing efficient optical sources. Heterogeneous structures are therefore developed that integrate III-V semiconductors on silicon wafers. These heterogeneous structures therefore combine the versatility, high density, and scalability of CMOS technology with the optical gain of III-V semiconductor materials.

[0004] Figure 1 illustrates an example of a heterogeneous structure 50 according to the prior art. The structure 50 comprises a first waveguide 51 made of III-V semiconductor material coupled to a second waveguide 52 made of silicon material. The III-V waveguide 51 comprises a first p-doped confinement layer 510 and a second n-doped confinement layer 512, on either side of an active layer 511 containing multiple quantum wells (or MQWs for “Multi Quantum Wells” in English). The first p-doped confinement layer 510 comprises on its external face a highly p-doped layer 508 so as to improve electrical contact with an electrode layer 506. Electrodes 534, 536 allow an electrical connection of the second n-doped confinement layer 512, in particular at a highly n-doped zone of the second n-confinement layer. The second optical guide 52 comprises a silicon layer 520. The guides 51, 52 are separated by a material 55 made of silicon oxide SiO2 and are close enough to allow optical coupling between them.

[0005] Typically, III-V quantum well structures are susceptible to the phenomenon of interval band absorption (IVBA) in which the light signal interacts with the p-doping of the first p-doped confinement layer. This results in optical losses that degrade laser performance. To minimize this effect, the first p-doped confinement layer 510 is relatively thicker than the second n-doped confinement layer 512 in order to distance the heavily p-doped layer 508 from the active layer 511. The first confinement layer 510 may further have a doping gradient from the heavily doped layer 508 to the active layer 511 to further mitigate the IVBA phenomenon. The optical signal produced by the quantum wells of the active layer 511 then interacts primarily with the lightly p-doped areas of the first confinement layer 510, which allows for low or moderate absorption.

[0006] However, for efficient optical mode transfer between the lll-V waveguide 51 and the silicon waveguide 52, a phase matching condition must be met. For this purpose, the lll-V waveguide 51 and the silicon waveguide 52 must have equal effective propagation indices in the area, called the transition zone, where the optical mode transfer must occur. The effective propagation index n e ff is also known as the "mode phase constant". It is defined by the following relationship: [Math 1] where n g is the group index and A is the wavelength of the optical signal guided by the waveguide. The effective propagation index of a waveguide depends on the dimensions of the core of this waveguide and the indices of the materials forming the core and the cladding of this waveguide. It can be determined experimentally or by numerical simulation.

[0007] Photonic chips can be fabricated from a silicon-on-oxide (SOI) substrate. The thickness of the layer in monocrystalline silicon of such an SOI substrate is typically between 220 and 300 nm. In the structure of Figure 1, the lll-V waveguide 51 generally has a thickness between 2 and 3 pm. Such a thickness of lll-V waveguide 51 does not allow to obtain a phase matching condition with a silicon waveguide of thickness between 220 and 300 nm. The optical mode transmission between the lll-V waveguide and the silicon waveguide could then not be done without losses. To overcome this, in Figure 1, the thickness of the silicon layer of the silicon guide 52 is increased compared to the conventional thickness, to reach an E2 value between 400 and 500 nm. In the heterogeneous structure 50 illustrated in FIG. 1, the silicon layer has in particular a thickness E2 of 500 nm which makes it possible to obtain a phase matching condition between the guides 51, 52.However, having a thicker silicon layer than in conventional silicon photonic chips makes the manufacturing process of the heterogeneous structure 50 more complex, because it is not compatible with standard manufacturing processes that define silicon layers with a thickness between 220 and 300 nm.

[0008] A photonic chip comprising a heterogeneous III-V / silicon structure is known from the publication “Membrane buried-heterostructure DFB laser with an optically coupled III-V / Si waveguide,” T. Aihara et al. Optics Express, vol. 27, no. 25, p. 36438, Dec. 2019, doi: 10.1364 / oe.27.036438. This publication describes a heterogeneous structure that does not require the addition of an excess silicon thickness in the silicon waveguide at the transition zone. However, for this, the current injection into the active layer is no longer in a vertical direction, as is the case in the example in Figure 1, but in a horizontal direction. The structure of the photonic chip in this publication is not conventional in the field of photonic components, particularly those intended for optical telecommunications.The electric current flowing between the electrode of the second n-doped confinement layer and the electrode of the first p-doped confinement layer sees a greater electrical resistance than in a vertical structure, such as in the structure of Figure 1 for example.

[0009] A photonic chip is therefore sought comprising a heterogeneous III-V / silicon structure whose architecture remains compatible with the processes of industrial manufacturing of silicon photonic circuits, while limiting optical losses in the III-V structure and losses in the transmission of an optical mode between the III-V waveguide and the silicon waveguide.

[0010] For this purpose, the invention proposes a photonic chip with a heterogeneous structure of a III-V semiconductor on a second semiconductor comprising, in a stacking direction: i. a waveguide made of a first III-V semiconductor material, called a III-V waveguide, comprising a first confinement layer, an active layer and a second confinement layer, ii. a waveguide made of a second semiconductor material, called an SC waveguide, comprising a layer of the second semiconductor material, the III-V waveguide further comprising a first electrode and a second electrode configured to respectively ensure electrical contact with one of said confinement layers, so that the active layer emits a light wave when an electric current flows between said electrodes through the active layer and the confinement layers,the first confinement layer comprising a first portion superimposed on the active layer and at least one extension, extending laterally beyond said active layer, said extension having a thickness in the stacking direction which is greater than that of the first portion, so as to define an electrical contact face located before the first portion in the stacking direction, said first electrode comprising a first contact layer coming against said electrical contact face.,

[0011] By offsetting a portion of the thickness of the first confinement layer to the side relative to the active layer, the influence of this portion on the effective propagation index of the lll-V waveguide is limited. The effective propagation index of the lll-V waveguide can then be lower than the effective propagation index of the lll-V waveguide 51 of the prior art lll-V / silicon heterogeneous structure illustrated in Figure 1. Thus, it is no longer necessary to add an overlayer on the silicon layer of the SC waveguide to balance the effective propagation indices between the lll-V waveguide and the SC waveguide. Furthermore, compared to the prior art lll-V structure in which the current injection into the layer active is horizontal, the photonic chip according to the invention maintains a vertical injection which makes it more compatible with the industrial manufacturing processes of CMOS technologies, in particular SOI technology.

[0012] According to one embodiment, the thickness of the extension defines at least one stair-shaped portion comprising a low landing separated from a high landing by a step height, the low landing comprising an external face of the first portion of the first confinement layer, the high landing comprising the contact face of the first confinement layer, the distance between the foot of the step height and the first portion being between 0 and 2 μm.

[0013] Alternatively, the distance between the foot of the step height and the first portion of the first containment layer is zero.

[0014] According to one embodiment, the thickness of the extension is configured to avoid an intervalence band absorption phenomenon in the III-V waveguide; and the first portion has a thickness configured for a phase matching condition between the III-V waveguide and the SC waveguide.

[0015] According to one embodiment, the extension has a doping profile decreasing from the contact face along said stacking direction; and the first portion of the first confinement layer has a substantially constant doping.

[0016] According to one embodiment, the waveguides extend in a longitudinal direction, said chip comprising a transition zone in which the lll-V waveguide and / or the SC waveguide have a profiling along said longitudinal direction making it possible to transmit an optical mode between the lll-V waveguide and the SC waveguide.

[0017] According to a variant, said extension is at least included in said transition zone.

[0018] According to a variant, outside said transition zone, the first confinement layer consists of the first portion and has a thickness configured to avoid an intervalence band absorption phenomenon in the III-V waveguide.

[0019] According to one embodiment, the second confinement layer extends at least partly laterally beyond the active layer and the first confinement layer. confinement; and the second electrode comprises at least one via extending along the stacking direction, in particular on the side of the first confinement layer and the active layer.

[0020] According to one embodiment, said first confinement layer comprises two extensions each extending from opposite edges of said first portion of the first confinement layer.

[0021] Other characteristics and advantages of the present invention will appear more clearly on reading the description which follows in relation to the following appended figures: [Fig 1]: Figure 1, already described, represents an example of a photonic chip of the prior art; [Fig 2]: Figure 2 represents an example of a photonic chip according to the invention; [Fig 3]: Figure 3 shows top views and sectional views of the chip of Figure 2; [Fig 4]: Figure 4 is an explanatory diagram of an electric current flowing in the chip illustrated in Figure 2; [Fig 5]: Figure 5 illustrates a variant of the photonic chip of Figure 2; [Fig 6]: Figure 6 illustrates another variant of the photonic chip of Figure 2; [Fig 7]: Figure 7 is a schematic bottom view of the photonic chip illustrated in Figure 2; [Fig 8a]: Figure 8a shows successive views of an optical mode propagating in the photonic chip illustrated in Figure 2; [Fig 8b]: Figure 8b shows other successive views of an optical mode propagating in the photonic chip illustrated in Figure 2; [Fig 9]: Figure 9 represents successive steps of an example of a manufacturing process for the photonic chip of Figure 2.

[0022] Figure 2 shows an example of a photonic chip 10 according to an example of the invention. The photonic chip 10 comprises a heterogeneous structure of III-V semiconductor on a second semiconductor. Thus, the photonic chip 10 comprises a waveguide made of III-V semiconductor material, designated in what follows waveguide lll-V 11 , and a waveguide made of a second semiconductor material. In particular, the second semiconductor material is silicon. The waveguide made of second semiconductor material is designated in the following waveguide SC 12. The waveguides 11 , 12 comprise layers forming a stack.

[0023] In a stacking direction A, the III-V waveguide 11 comprises a first confinement layer 110, an active layer 111, a second confinement layer 112. The active layer 111 comprises in particular quantum wells, in particular multiple quantum wells, which make it possible to obtain an optical gain from an electric current flowing between the confinement layers 110, 112. In a manner known per se, the quantum wells then produce a light wave which will be confined in the active part 111. The confinement layers 110, 112 are located respectively on either side of the active layer 111. In particular, the first confinement layer 110 is located on one side of the active layer 111; the second confinement layer 112 is located on the opposite side of the active layer 111.The confinement layers 110, 112 in particular have refractive indices lower than that of the active layer 111, thus making it possible to confine the light wave in the active layer 111 and to guide it. In particular, the confinement layers 110, 112 have dopings of opposite types. For example, the first confinement layer 110 has a p-type doping; and the second confinement layer 112 has an n-type doping. In particular, the first confinement layer 110, the active layer 111, and the second confinement layer 112 form a PIN junction. The III-V material is for example indium phosphide InP.

[0024] The waveguide SC 12 is located after the waveguide III-V 11 in the stacking direction A. The waveguide SC 12 comprises a silicon layer 120. The silicon layer 120 serves in particular as a propagation medium for the light wave in the silicon photonic circuit. In particular, the silicon layer 120 is located opposite the second confinement layer 112 in the stacking direction A.

[0025] The silicon layer 120 is in particular included in a layer of dielectric material 14 serving as a sheath for the waveguide SC 12. The dielectric material is in particular silicon oxide SiO2. In particular, a thin layer of dielectric material 14 separates the second confinement layer 112 of the III-V waveguide 11 from the silicon layer 120 of the SC waveguide 12, so as to allow optical coupling between the III-V waveguide 11 and the SC waveguide 12. The thickness of dielectric material 14 separating the second confinement layer 112 and the silicon layer 120 may be between 5 nm and 200 nm, or even equal to 50 nm. The thickness of dielectric material 14 may be greater by extending the length of an optical transition zone described later.

[0026] Thus, the first confinement layer 110, the active layer 111, the second confinement layer 112 of the III-V waveguide 11, the silicon layer 120 of the SC waveguide 12 form at least in part a stack of layers. Within this stack, the layers extend in particular along parallel planes, which are in particular perpendicular to the stacking direction A.

[0027] The lll-V waveguide 11 and the SC waveguide 12 are therefore in particular located opposite each other along the stacking direction A of the layers so as to allow optical coupling between the two waveguides.

[0028] Still following the stacking direction A, the photonic chip 10 comprises in particular a substrate 16 serving as a support for the photonic chip 10. This substrate 16 is in particular made of silicon. The substrate 16 can serve as a support for other III-V structures or other silicon photonic components, such as for example a phase modulator or a Mach-Zehnder interferometer.

[0029] The III-V waveguide 11 further comprises a first electrode B1 which ensures electrical contact with the first confinement layer 110; and a second electrode B2 which ensures electrical contact with the second confinement layer 112. Thus, the active layer 11 can emit a light wave when a current flows between the electrodes B1, B2 through the confinement layers 110, 112.

[0030] The photonic chip 10 is particular in that, due to the shape of the first confinement layer 110, it does not require an excess thickness of the silicon layer for efficient optical mode transfer between the III-V waveguide 11 and the SC waveguide 12.

[0031] Indeed, the first confinement layer 110 comprises a first portion 110a superimposed on the active layer 111, and an extension 110b which extends laterally beyond the active layer 111. In other words, the extension 110b forms a second portion of the first confinement layer 110, and extends from one side of the first portion 110a of the first confinement layer 110. In particular, the extension 110b extends from the first portion 110a in a transverse direction, in particular perpendicular, to the stacking direction A. The extension 110b has a thickness Eb in the stacking direction A which is greater than the thickness Ea of the first portion 110a. The extension 110b thus defines an electrical contact face 116 located before the first portion 110a in the stacking direction A.Thus, in particular, the following faces or interfaces are located one after the other along the stacking direction A: the contact face 116 of the first stacking layer 110, an upper face 117 of the first portion 110a of the first confinement layer, the interface between the first confinement layer 110 and the active layer 111, the interface between the active layer 111 and the second confinement layer 112, the interface between the III-V waveguide 11 and the SC waveguide 12. The first electrode B1 comprises a first contact layer B10 which comes against the contact face 116 of the first confinement layer 110 for an electrical connection thereof.

[0032] Thanks to the first confinement layer 110 in two parts 110a, 110b, during an optical mode transmission between the lll-V waveguide 11 and the SC waveguide 12, the effective propagation index of the optical mode is sensitive only to the first portion 110a. Unlike the prior art illustrated in FIG. 1, it is therefore not necessary to add an extra thickness to the silicon layer 120 compared to a conventional silicon photonic chip. The thickness Ea of the first portion 110a can be adapted to ensure a phase matching condition between the lll-V waveguide 11 and the SC waveguide 12. In particular, the thickness of the first portion 110a can be small enough to allow a phase matching condition between the lll-V guide 11 and the SC waveguide 12.For example, for a silicon layer thickness 120 of approximately 220 nm, the thickness Ea of the first portion 110a of the first confinement layer 110 may be between 200 and 500 nm. Furthermore, the extension 110b makes it possible to move a heavily doped layer of the first confinement layer 110 away from the active layer 111. The extension 110b can then have a thickness Eb which makes it possible to avoid or greatly limit the phenomenon of intervalence band absorption. In particular, the thickness of the protrusion 110b is sufficiently large to avoid the phenomenon of intervalence band absorption. For example, the thickness Eb of the extension 110b can be between 1 and 3 μm. The thicknesses Ea, Eb are in particular defined according to the stacking direction A. Furthermore, due to its III-V structure which allows vertical current injection into the active layer, the photonic chip 10 is more compatible with CMOS manufacturing technologies than the chip of the prior art which comprises a III-V structure in which the injection is horizontal.

[0033] In particular, the extension 110b extends from an edge of the first portion 110a which is in the extension of an edge of the active layer 111. In other words, seen in the stacking direction A, the extension 110b does not cover the active layer 111, which limits the intervalence band absorption phenomenon. In particular, a staircase-shaped part is defined by the thickness Eb of the extension 110b, in particular by the first portion 110a and the second portion 110b. A low level of the staircase shape comprises the external face 117 of the first portion 110a of the first confinement layer 110. In particular, the external face 117 of the first portion 110a is its opposite face relative to its interface with the active layer 111. A high level of the staircase shape comprises the contact face 116.The upper landing and the lower landing are separated by a step height, which is in particular equal to the difference between the thicknesses Ea, Eb of the first portion 110a and the second portion 110b. Preferably, the distance between the foot of the step height and the first portion 110a is equal to zero, apart from positioning uncertainties. In other words, the step height extends in particular from an edge of the first portion 110a which is in the extension of an edge of the active layer 111. However, the distance between the foot of the step height and the first portion 110a may be greater than or equal to zero, from the edge of the first portion 110a moving away from the active layer 111. The distance between the foot of the step height and the first portion 110a may be between 0 and 2 μm, depending on the size of the photonic chip 10.

[0034] In order to limit the intervalence band absorption phenomenon, the extension 110b of the first confinement layer 110 may have a doping profile which decreases from the contact face 116 along the stacking direction A. In particular, the extension 110b is heavily doped at the contact face 116 to allow good electrical contact with the first contact layer B 10. The doping of the extension 110b can range from 1x10 20 / cm 3 near the contact face 116 at 7x10 17 / cm 3 near the active layer 111. The first portion 110a of the first confinement layer 110 may have a substantially constant doping, in particular substantially equal to the smallest doping value in the extension 110b. For example, the first portion 110a has a doping of 7x10 17 / cm 3 .

[0035] The active layer 111 may be delimited on the sides by a layer of insulating material 118. The layer of insulating material 118 makes it possible to confine the light wave coming from the active layer 111 on the sides. The layer of insulating material 118 extends in particular laterally from an edge of the active layer 111. In particular, the extension 110b of the first confinement layer 110 comes against the layer of insulating material 118. The layer of insulating material 118 extends in particular between the extension 110b of the first confinement layer 110 and the layer of dielectric material 14. The layer of insulating material 118 may be made of a polymer, such as benzocyclobutene (or BCB) for example, or silica SiO2 or even aluminum nitride AIN.The layer of insulating material 118 may be made of a material forming a semi-insulating buried heterostructure (or SIBH for “semi insulating buried heterostructure”), such as semi-insulating indium phosphide, in particular an lnP:Fe material.

[0036] The second confinement layer 112 may extend laterally beyond the active layer 111 and the first confinement layer 110 for electrical contact. In particular, the second electrode B2 of the III-V waveguide comprises a via which extends in the stacking direction A, in particular on the side of the first confinement layer 110. An electrical contact layer B20 is in particular deposited at the bottom of the via on the second confinement layer 112 for electrical contact thereof.

[0037] A passivation layer 113 may cover the III-V / silicon heterogeneous structure. The passivation layer 113 may be made of a polymer, such as benzocyclobutene (or BCB) for example, or silica SiO2 or even aluminum nitride AIN.

[0038] Figure 3 shows a partial top view 1 of the photonic chip 10. To make the representation readable, in view 1, the passivation layer 113, the electrodes B1, B2, the first portion 110a of the first confinement layer 110 and the second confinement layer 112 are not shown. The other views a, b, c, d of Figure 3 show sectional views of the photonic chip 10 taken along the corresponding lines of view 1.

[0039] The lll-V waveguide 11 and the SC waveguide 12 extend in particular in a longitudinal direction corresponding to a direction of propagation of the light waves. In particular, the longitudinal direction is perpendicular to the stacking direction A. In a manner known per se, the photonic chip 10 comprises an optical transition zone 17 in which the SC waveguide 12 or the lll-V waveguide 11 have a profile along the longitudinal direction allowing a transfer or coupling of optical mode from one guide to the other. For example, the cross-section of the SC waveguide 12, in particular of the silicon layer 120, gradually decreases while the cross-section of the lll-V waveguide 11, in particular of the active layer 111, gradually increases.In particular when the insulating layer 118 of the III-V waveguide forms a semi-insulating heterostructure, it itself has a cross-section which gradually increases, as for example shown in views a, b. Then, the cross-section of the active layer 11 gradually increases as for example shown in views c, d. The first confinement layer 110 comprises the extension 110b at least in the transition zone 17, in order to improve the optical mode transfer.

[0040] Beyond the transition zone 17, in particular going to the right in view 1 of FIG. 3, the lll-V waveguide 11 and the SC waveguide 12 have in particular constant cross-sections. In particular, the optical mode is then confined in the lll-V waveguide 11. The lll-V waveguide 11 may have a semiconductor optical amplifier function. An electric current then flows between the electrodes B1, B2 of the lll-V waveguide 11 to amplify the lll-V light wave propagating in the lll-V waveguide 11. The first confinement layer 110 may further comprise the extension 110b beyond the transition zone 17. The path of the electric current i flowing in the lll-V structure is for example illustrated in FIG. 4.

[0041] For a prior art photonic chip having vertical current injection, in which the lll-V waveguide has a length of 600 pm, and the first confinement layer is fully superimposed on the active layer, with a thickness of 2 pm and a width of 2.4 pm, the electrical resistance R1 across the first confinement layer may be about 6 Ω. In the photonic chip 10, the current injection is vertical; but the electric current also flows laterally through the section S at the interface of the first portion 110a and the second portion 110b, which notably limits the current compared to the prior art. For example, when the lll-V waveguide 11 has a length of 600 pm, a thickness Ea of the first portion 110a of 500 nm and a thickness Eb of the extension 110b of 2 pm, the resistance Rs of the section S can be about 5.8 Ω. The total resistance across the first confinement layer 110 can then be 11.8 Ω.However, the photonic chip 10 remains more advantageous than the prior art chip because the silicon layer can have a thickness E of 220 nm. Furthermore, the photonic chip 10 remains more advantageous than a previously described prior art photonic chip in which the current injection into the III-V structure is in a horizontal direction. For a III-V waveguide of length 500 pm, this has a resistance of approximately 25 Ω.

[0042] In a variant illustrated in Figure 5, outside the optical transition zone 17, the photonic chip 20 has a conventional architecture of III-V / silicon heterogeneous structure. The first confinement layer 110 comprises only the first portion and is devoid of the extension 110b. The first confinement layer 110 can then have a thickness and a doping gradient configured to avoid the phenomenon of intervalence band absorption in the III-V waveguide 11. The photonic chip 20 of Figure 5 is otherwise identical to the photonic chip 10 described previously. This variant has an electrical resistance similar to that of the prior art chip described in the previous paragraph, because the electric current flows largely through the part of the III-V waveguide which is of constant section.

[0043] Figure 6 illustrates an example of a photonic chip 30 according to a variant in which the first confinement layer 310 comprises two extensions 310b. The photonic chip 30 is otherwise identical to the photonic chip 10 described in relation to the preceding figures. Each of the extensions 310b is similar to the extension 110b of the photonic chip 10 described in relation to the preceding figures. In this variant, the presence of two extensions 310b makes it possible to reduce by a factor of 2 the contribution of the p-doped part in the total electrical resistance seen by the current injected into the III-V structure.

[0044] Figure 7 shows a partial bottom view of the photonic chip 10, in which only the silicon layer 120 of the waveguide SC 12 and the edges of the assembly formed by the active layer 111 and the layer of insulating material 118 are shown. The photonic chip 10 extends along a plane (X, Z) perpendicular to the stacking direction A. The direction Z corresponds to the longitudinal direction of the photonic chip 10; the direction X corresponds to a transverse direction of the photonic chip 10. Each axis X, Z carries a scale in pm. Similarly to Figure 3, in the transition zone, over a first length L1 the silicon layer 120 is profiled so that its section decreases; over a second length L2, the assembly formed by the active layer 111 and the layer of insulating material 118 is profiled.

[0045] Figures 8a, 8b represent the spatial distribution of the optical mode in cross-sections taken at successive Z positions of Figure 7, during a transmission of an optical mode from the SC waveguide 12 to the lll-V waveguide 11. In these cross-sectional views, the origin of the X axis corresponds to the point of coordinate 4.5 on the X axis of Figure 7. Along the longitudinal Z axis, a progressive transmission of the optical mode is observed from the SC waveguide 12 to the lll-V waveguide 11. The photonic chip 10 notably allows an efficient optical mode transfer between the lll-V waveguide and the SC waveguide, notably a 97% transmission.

[0046] An example of a manufacturing method for the photonic chip 10 will be described in relation to Figure 9. A lll-V structure formed from a p-doped layer 4, an intermediate layer 3 and an n-doped layer 2 is first formed by growth on a lll-V substrate, in particular indium phosphide InP. The assembly is then fixed by bonding to a silicon photonic chip. The lll-V substrate is then removed. Alternatively, a thin layer of lll-V substrate can be bonded to the silicon photonic chip. Growth then takes place from this thin layer of lll-V substrate directly onto the silicon substrate (view a). Then, a dielectric mask M is deposited on the p-doped layer 4 (view b). This mask M makes it possible to define by etching, the active layer 111 in the intermediate layer 3. The n-doped layer then forms the second confinement layer 112. An insulating material is epitaxially grown around the active layer 111 to form the insulating material layer 118 (view c). The mask M is removed. Then, an additional p-doped layer of layer 4 is grown (view d). Prior to growth, an optional layer of quaternary material 5 can be deposited to cover the initial p-doped layer 4. This layer of quaternary material 5 is in particular made of a GalnAsP alloy. It forms a sacrificial layer which facilitates the manufacturing process. It serves in particular as a stop layer for the subsequent etching of the p-doped layer 4. The first confinement layer 110 is then defined by etching (view e).A portion of the insulating material 118 is then removed to define locations where the contact layer B20 is deposited on the second confinement layer 112; and the contact layer B10 is deposited on the contact face 116 of the first confinement layer 110.

[0047] In the waveguide described in relation to the figures, the second semiconductor material is for example silicon, germanium, silicon nitride or lithium niobate or an alloy thereof. The second semiconductor material may be any semiconductor material suitable for the confinement and propagation of an optical mode in the waveguide SC. In particular, such a material has a refractive index sufficiently high to confine an optical mode, in particular a refractive index greater than or equal to 2.

[0048] For example, the second material is an indirect gap semiconductor, which makes it unfavorable for the production of laser components or optical amplification. The second material may be a direct gap material, but whose physical characteristics are unfavorable for the generation of a laser or optical amplification. In both cases, the III-V structure compensates for the shortcomings of the second semiconductor material.

Claims

CLAIMS 1. Photonic chip (10,20,30) with a heterogeneous structure of lll-V semiconductor on a second semiconductor comprising, in a stacking direction (A): i. a waveguide (11) made of a first lll-V semiconductor material, called lll-V waveguide, comprising a first confinement layer (110), an active layer (111) and a second confinement layer (112), ii. a waveguide (12) made of a second semiconductor material, called an SC waveguide, comprising a layer (120) of the second semiconductor material, the III-V waveguide (11) further comprising a first electrode (B1) and a second electrode (B2) configured to respectively ensure electrical contact with one of said confinement layers, so that the active layer (111) emits a light wave when an electric current (i) flows between said electrodes through the active layer (111) and the confinement layers,the first confinement layer (110) comprising a first portion (110a) superimposed on the active layer (111) and at least one extension (110b), extending laterally beyond said active layer (111), said extension (110b) having a thickness (Eb) in the stacking direction (A) which is greater than that (Ea) of the first portion (110a), so as to define an electrical contact face (116) located before the first portion (110a) in the stacking direction (A), said first electrode (B1) comprising a first contact layer (B10) coming against said electrical contact face (116)., 2. Photonic chip (10, 20, 30) according to claim 1, wherein the thickness (Eb) of the extension (110b) defines at least one stair-shaped portion comprising a low landing separated from a high landing by a step height, the low landing comprising an external face (117) of the first portion (110a) of the first confinement layer (110), the high landing comprising the contact face (116) of the first confinement layer (110), the distance between the foot of the step height and the first portion (110a) being between 0 and 2 pm.

3. Photonic chip (10, 20, 30) according to the preceding claim, in which the distance between the foot of the step height and the first portion (110a) of the first confinement layer (110) is equal to zero.

4. Photonic chip (10, 20, 30) according to one of the preceding claims, wherein the thickness (Eb) of the extension (110b) is configured to avoid an intervalence band absorption phenomenon in the lll-V waveguide (11); and the first portion (110a) has a thickness (Ea) configured for a phase matching condition between the lll-V waveguide (11) and the SC waveguide (12).

5. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the extension (110b) has a doping profile decreasing from the contact face (116) along said stacking direction (A); and the first portion (110a) of the first confinement layer (110) has a substantially constant doping.

6. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the waveguides (11, 12) extend in a longitudinal direction, said chip comprising a transition zone (17) in which the III-V waveguide (11) and / or the SC waveguide (12) have a profiling along said longitudinal direction making it possible to transmit an optical mode between the III-V waveguide (11) and the SC waveguide (12).

7. Photonic chip (10, 20, 30) according to the preceding claim, in which said extension (110b) is at least included in said transition zone (17).

8. Photonic chip (20) according to claim 6 or 7, wherein, outside said transition zone (17), the first confinement layer (110) consists of the first portion (110a) and has a thickness (Ea) configured to avoid an intervalence band absorption phenomenon in the III-V waveguide (11).

9. Photonic chip (10, 20, 30) according to one of the preceding claims, in which the second confinement layer (112) extends at least partly laterally beyond the active layer (111) and the first confinement layer (110); and the second electrode (B2) comprises at least one via extending along the stacking direction (A), in particular on the side of the first confinement layer (110) and the active layer (111).

10. Photonic chip (30) according to one of the preceding claims, wherein said first confinement layer (110) comprises two extensions (310b) each extending from opposite edges of said first portion (110a) of the first confinement layer (110).

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